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iommu/amd: Implement IOMMUv2 TLB flushing routines
[deliverable/linux.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <asm/msidef.h>
35 #include <asm/proto.h>
36 #include <asm/iommu.h>
37 #include <asm/gart.h>
38 #include <asm/dma.h>
39
40 #include "amd_iommu_proto.h"
41 #include "amd_iommu_types.h"
42
43 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
44
45 #define LOOP_TIMEOUT 100000
46
47 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
48
49 /* A list of preallocated protection domains */
50 static LIST_HEAD(iommu_pd_list);
51 static DEFINE_SPINLOCK(iommu_pd_list_lock);
52
53 /* List of all available dev_data structures */
54 static LIST_HEAD(dev_data_list);
55 static DEFINE_SPINLOCK(dev_data_list_lock);
56
57 /*
58 * Domain for untranslated devices - only allocated
59 * if iommu=pt passed on kernel cmd line.
60 */
61 static struct protection_domain *pt_domain;
62
63 static struct iommu_ops amd_iommu_ops;
64
65 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
66 int amd_iommu_max_glx_val = -1;
67
68 /*
69 * general struct to manage commands send to an IOMMU
70 */
71 struct iommu_cmd {
72 u32 data[4];
73 };
74
75 static void update_domain(struct protection_domain *domain);
76 static int __init alloc_passthrough_domain(void);
77
78 /****************************************************************************
79 *
80 * Helper functions
81 *
82 ****************************************************************************/
83
84 static struct iommu_dev_data *alloc_dev_data(u16 devid)
85 {
86 struct iommu_dev_data *dev_data;
87 unsigned long flags;
88
89 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
90 if (!dev_data)
91 return NULL;
92
93 dev_data->devid = devid;
94 atomic_set(&dev_data->bind, 0);
95
96 spin_lock_irqsave(&dev_data_list_lock, flags);
97 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
98 spin_unlock_irqrestore(&dev_data_list_lock, flags);
99
100 return dev_data;
101 }
102
103 static void free_dev_data(struct iommu_dev_data *dev_data)
104 {
105 unsigned long flags;
106
107 spin_lock_irqsave(&dev_data_list_lock, flags);
108 list_del(&dev_data->dev_data_list);
109 spin_unlock_irqrestore(&dev_data_list_lock, flags);
110
111 kfree(dev_data);
112 }
113
114 static struct iommu_dev_data *search_dev_data(u16 devid)
115 {
116 struct iommu_dev_data *dev_data;
117 unsigned long flags;
118
119 spin_lock_irqsave(&dev_data_list_lock, flags);
120 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
121 if (dev_data->devid == devid)
122 goto out_unlock;
123 }
124
125 dev_data = NULL;
126
127 out_unlock:
128 spin_unlock_irqrestore(&dev_data_list_lock, flags);
129
130 return dev_data;
131 }
132
133 static struct iommu_dev_data *find_dev_data(u16 devid)
134 {
135 struct iommu_dev_data *dev_data;
136
137 dev_data = search_dev_data(devid);
138
139 if (dev_data == NULL)
140 dev_data = alloc_dev_data(devid);
141
142 return dev_data;
143 }
144
145 static inline u16 get_device_id(struct device *dev)
146 {
147 struct pci_dev *pdev = to_pci_dev(dev);
148
149 return calc_devid(pdev->bus->number, pdev->devfn);
150 }
151
152 static struct iommu_dev_data *get_dev_data(struct device *dev)
153 {
154 return dev->archdata.iommu;
155 }
156
157 static bool pci_iommuv2_capable(struct pci_dev *pdev)
158 {
159 static const int caps[] = {
160 PCI_EXT_CAP_ID_ATS,
161 PCI_PRI_CAP,
162 PCI_PASID_CAP,
163 };
164 int i, pos;
165
166 for (i = 0; i < 3; ++i) {
167 pos = pci_find_ext_capability(pdev, caps[i]);
168 if (pos == 0)
169 return false;
170 }
171
172 return true;
173 }
174
175 /*
176 * In this function the list of preallocated protection domains is traversed to
177 * find the domain for a specific device
178 */
179 static struct dma_ops_domain *find_protection_domain(u16 devid)
180 {
181 struct dma_ops_domain *entry, *ret = NULL;
182 unsigned long flags;
183 u16 alias = amd_iommu_alias_table[devid];
184
185 if (list_empty(&iommu_pd_list))
186 return NULL;
187
188 spin_lock_irqsave(&iommu_pd_list_lock, flags);
189
190 list_for_each_entry(entry, &iommu_pd_list, list) {
191 if (entry->target_dev == devid ||
192 entry->target_dev == alias) {
193 ret = entry;
194 break;
195 }
196 }
197
198 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
199
200 return ret;
201 }
202
203 /*
204 * This function checks if the driver got a valid device from the caller to
205 * avoid dereferencing invalid pointers.
206 */
207 static bool check_device(struct device *dev)
208 {
209 u16 devid;
210
211 if (!dev || !dev->dma_mask)
212 return false;
213
214 /* No device or no PCI device */
215 if (dev->bus != &pci_bus_type)
216 return false;
217
218 devid = get_device_id(dev);
219
220 /* Out of our scope? */
221 if (devid > amd_iommu_last_bdf)
222 return false;
223
224 if (amd_iommu_rlookup_table[devid] == NULL)
225 return false;
226
227 return true;
228 }
229
230 static int iommu_init_device(struct device *dev)
231 {
232 struct pci_dev *pdev = to_pci_dev(dev);
233 struct iommu_dev_data *dev_data;
234 u16 alias;
235
236 if (dev->archdata.iommu)
237 return 0;
238
239 dev_data = find_dev_data(get_device_id(dev));
240 if (!dev_data)
241 return -ENOMEM;
242
243 alias = amd_iommu_alias_table[dev_data->devid];
244 if (alias != dev_data->devid) {
245 struct iommu_dev_data *alias_data;
246
247 alias_data = find_dev_data(alias);
248 if (alias_data == NULL) {
249 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
250 dev_name(dev));
251 free_dev_data(dev_data);
252 return -ENOTSUPP;
253 }
254 dev_data->alias_data = alias_data;
255 }
256
257 if (pci_iommuv2_capable(pdev)) {
258 struct amd_iommu *iommu;
259
260 iommu = amd_iommu_rlookup_table[dev_data->devid];
261 dev_data->iommu_v2 = iommu->is_iommu_v2;
262 }
263
264 dev->archdata.iommu = dev_data;
265
266 return 0;
267 }
268
269 static void iommu_ignore_device(struct device *dev)
270 {
271 u16 devid, alias;
272
273 devid = get_device_id(dev);
274 alias = amd_iommu_alias_table[devid];
275
276 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
277 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
278
279 amd_iommu_rlookup_table[devid] = NULL;
280 amd_iommu_rlookup_table[alias] = NULL;
281 }
282
283 static void iommu_uninit_device(struct device *dev)
284 {
285 /*
286 * Nothing to do here - we keep dev_data around for unplugged devices
287 * and reuse it when the device is re-plugged - not doing so would
288 * introduce a ton of races.
289 */
290 }
291
292 void __init amd_iommu_uninit_devices(void)
293 {
294 struct iommu_dev_data *dev_data, *n;
295 struct pci_dev *pdev = NULL;
296
297 for_each_pci_dev(pdev) {
298
299 if (!check_device(&pdev->dev))
300 continue;
301
302 iommu_uninit_device(&pdev->dev);
303 }
304
305 /* Free all of our dev_data structures */
306 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
307 free_dev_data(dev_data);
308 }
309
310 int __init amd_iommu_init_devices(void)
311 {
312 struct pci_dev *pdev = NULL;
313 int ret = 0;
314
315 for_each_pci_dev(pdev) {
316
317 if (!check_device(&pdev->dev))
318 continue;
319
320 ret = iommu_init_device(&pdev->dev);
321 if (ret == -ENOTSUPP)
322 iommu_ignore_device(&pdev->dev);
323 else if (ret)
324 goto out_free;
325 }
326
327 return 0;
328
329 out_free:
330
331 amd_iommu_uninit_devices();
332
333 return ret;
334 }
335 #ifdef CONFIG_AMD_IOMMU_STATS
336
337 /*
338 * Initialization code for statistics collection
339 */
340
341 DECLARE_STATS_COUNTER(compl_wait);
342 DECLARE_STATS_COUNTER(cnt_map_single);
343 DECLARE_STATS_COUNTER(cnt_unmap_single);
344 DECLARE_STATS_COUNTER(cnt_map_sg);
345 DECLARE_STATS_COUNTER(cnt_unmap_sg);
346 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
347 DECLARE_STATS_COUNTER(cnt_free_coherent);
348 DECLARE_STATS_COUNTER(cross_page);
349 DECLARE_STATS_COUNTER(domain_flush_single);
350 DECLARE_STATS_COUNTER(domain_flush_all);
351 DECLARE_STATS_COUNTER(alloced_io_mem);
352 DECLARE_STATS_COUNTER(total_map_requests);
353
354 static struct dentry *stats_dir;
355 static struct dentry *de_fflush;
356
357 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
358 {
359 if (stats_dir == NULL)
360 return;
361
362 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
363 &cnt->value);
364 }
365
366 static void amd_iommu_stats_init(void)
367 {
368 stats_dir = debugfs_create_dir("amd-iommu", NULL);
369 if (stats_dir == NULL)
370 return;
371
372 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
373 (u32 *)&amd_iommu_unmap_flush);
374
375 amd_iommu_stats_add(&compl_wait);
376 amd_iommu_stats_add(&cnt_map_single);
377 amd_iommu_stats_add(&cnt_unmap_single);
378 amd_iommu_stats_add(&cnt_map_sg);
379 amd_iommu_stats_add(&cnt_unmap_sg);
380 amd_iommu_stats_add(&cnt_alloc_coherent);
381 amd_iommu_stats_add(&cnt_free_coherent);
382 amd_iommu_stats_add(&cross_page);
383 amd_iommu_stats_add(&domain_flush_single);
384 amd_iommu_stats_add(&domain_flush_all);
385 amd_iommu_stats_add(&alloced_io_mem);
386 amd_iommu_stats_add(&total_map_requests);
387 }
388
389 #endif
390
391 /****************************************************************************
392 *
393 * Interrupt handling functions
394 *
395 ****************************************************************************/
396
397 static void dump_dte_entry(u16 devid)
398 {
399 int i;
400
401 for (i = 0; i < 4; ++i)
402 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
403 amd_iommu_dev_table[devid].data[i]);
404 }
405
406 static void dump_command(unsigned long phys_addr)
407 {
408 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
409 int i;
410
411 for (i = 0; i < 4; ++i)
412 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
413 }
414
415 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
416 {
417 u32 *event = __evt;
418 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
419 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
420 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
421 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
422 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
423
424 printk(KERN_ERR "AMD-Vi: Event logged [");
425
426 switch (type) {
427 case EVENT_TYPE_ILL_DEV:
428 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
429 "address=0x%016llx flags=0x%04x]\n",
430 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
431 address, flags);
432 dump_dte_entry(devid);
433 break;
434 case EVENT_TYPE_IO_FAULT:
435 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
436 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
437 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
438 domid, address, flags);
439 break;
440 case EVENT_TYPE_DEV_TAB_ERR:
441 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
442 "address=0x%016llx flags=0x%04x]\n",
443 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
444 address, flags);
445 break;
446 case EVENT_TYPE_PAGE_TAB_ERR:
447 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
448 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
449 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
450 domid, address, flags);
451 break;
452 case EVENT_TYPE_ILL_CMD:
453 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
454 dump_command(address);
455 break;
456 case EVENT_TYPE_CMD_HARD_ERR:
457 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
458 "flags=0x%04x]\n", address, flags);
459 break;
460 case EVENT_TYPE_IOTLB_INV_TO:
461 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
462 "address=0x%016llx]\n",
463 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
464 address);
465 break;
466 case EVENT_TYPE_INV_DEV_REQ:
467 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
468 "address=0x%016llx flags=0x%04x]\n",
469 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
470 address, flags);
471 break;
472 default:
473 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
474 }
475 }
476
477 static void iommu_poll_events(struct amd_iommu *iommu)
478 {
479 u32 head, tail;
480 unsigned long flags;
481
482 spin_lock_irqsave(&iommu->lock, flags);
483
484 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
485 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
486
487 while (head != tail) {
488 iommu_print_event(iommu, iommu->evt_buf + head);
489 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
490 }
491
492 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
493
494 spin_unlock_irqrestore(&iommu->lock, flags);
495 }
496
497 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u32 head)
498 {
499 struct amd_iommu_fault fault;
500 volatile u64 *raw;
501 int i;
502
503 raw = (u64 *)(iommu->ppr_log + head);
504
505 /*
506 * Hardware bug: Interrupt may arrive before the entry is written to
507 * memory. If this happens we need to wait for the entry to arrive.
508 */
509 for (i = 0; i < LOOP_TIMEOUT; ++i) {
510 if (PPR_REQ_TYPE(raw[0]) != 0)
511 break;
512 udelay(1);
513 }
514
515 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
516 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
517 return;
518 }
519
520 fault.address = raw[1];
521 fault.pasid = PPR_PASID(raw[0]);
522 fault.device_id = PPR_DEVID(raw[0]);
523 fault.tag = PPR_TAG(raw[0]);
524 fault.flags = PPR_FLAGS(raw[0]);
525
526 /*
527 * To detect the hardware bug we need to clear the entry
528 * to back to zero.
529 */
530 raw[0] = raw[1] = 0;
531
532 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
533 }
534
535 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
536 {
537 unsigned long flags;
538 u32 head, tail;
539
540 if (iommu->ppr_log == NULL)
541 return;
542
543 spin_lock_irqsave(&iommu->lock, flags);
544
545 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
546 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
547
548 while (head != tail) {
549
550 /* Handle PPR entry */
551 iommu_handle_ppr_entry(iommu, head);
552
553 /* Update and refresh ring-buffer state*/
554 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
555 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
556 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
557 }
558
559 /* enable ppr interrupts again */
560 writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
561
562 spin_unlock_irqrestore(&iommu->lock, flags);
563 }
564
565 irqreturn_t amd_iommu_int_thread(int irq, void *data)
566 {
567 struct amd_iommu *iommu;
568
569 for_each_iommu(iommu) {
570 iommu_poll_events(iommu);
571 iommu_poll_ppr_log(iommu);
572 }
573
574 return IRQ_HANDLED;
575 }
576
577 irqreturn_t amd_iommu_int_handler(int irq, void *data)
578 {
579 return IRQ_WAKE_THREAD;
580 }
581
582 /****************************************************************************
583 *
584 * IOMMU command queuing functions
585 *
586 ****************************************************************************/
587
588 static int wait_on_sem(volatile u64 *sem)
589 {
590 int i = 0;
591
592 while (*sem == 0 && i < LOOP_TIMEOUT) {
593 udelay(1);
594 i += 1;
595 }
596
597 if (i == LOOP_TIMEOUT) {
598 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
599 return -EIO;
600 }
601
602 return 0;
603 }
604
605 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
606 struct iommu_cmd *cmd,
607 u32 tail)
608 {
609 u8 *target;
610
611 target = iommu->cmd_buf + tail;
612 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
613
614 /* Copy command to buffer */
615 memcpy(target, cmd, sizeof(*cmd));
616
617 /* Tell the IOMMU about it */
618 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
619 }
620
621 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
622 {
623 WARN_ON(address & 0x7ULL);
624
625 memset(cmd, 0, sizeof(*cmd));
626 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
627 cmd->data[1] = upper_32_bits(__pa(address));
628 cmd->data[2] = 1;
629 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
630 }
631
632 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
633 {
634 memset(cmd, 0, sizeof(*cmd));
635 cmd->data[0] = devid;
636 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
637 }
638
639 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
640 size_t size, u16 domid, int pde)
641 {
642 u64 pages;
643 int s;
644
645 pages = iommu_num_pages(address, size, PAGE_SIZE);
646 s = 0;
647
648 if (pages > 1) {
649 /*
650 * If we have to flush more than one page, flush all
651 * TLB entries for this domain
652 */
653 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
654 s = 1;
655 }
656
657 address &= PAGE_MASK;
658
659 memset(cmd, 0, sizeof(*cmd));
660 cmd->data[1] |= domid;
661 cmd->data[2] = lower_32_bits(address);
662 cmd->data[3] = upper_32_bits(address);
663 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
664 if (s) /* size bit - we flush more than one 4kb page */
665 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
666 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
667 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
668 }
669
670 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
671 u64 address, size_t size)
672 {
673 u64 pages;
674 int s;
675
676 pages = iommu_num_pages(address, size, PAGE_SIZE);
677 s = 0;
678
679 if (pages > 1) {
680 /*
681 * If we have to flush more than one page, flush all
682 * TLB entries for this domain
683 */
684 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
685 s = 1;
686 }
687
688 address &= PAGE_MASK;
689
690 memset(cmd, 0, sizeof(*cmd));
691 cmd->data[0] = devid;
692 cmd->data[0] |= (qdep & 0xff) << 24;
693 cmd->data[1] = devid;
694 cmd->data[2] = lower_32_bits(address);
695 cmd->data[3] = upper_32_bits(address);
696 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
697 if (s)
698 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
699 }
700
701 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
702 u64 address, bool size)
703 {
704 memset(cmd, 0, sizeof(*cmd));
705
706 address &= ~(0xfffULL);
707
708 cmd->data[0] = pasid & PASID_MASK;
709 cmd->data[1] = domid;
710 cmd->data[2] = lower_32_bits(address);
711 cmd->data[3] = upper_32_bits(address);
712 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
713 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
714 if (size)
715 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
716 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
717 }
718
719 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
720 int qdep, u64 address, bool size)
721 {
722 memset(cmd, 0, sizeof(*cmd));
723
724 address &= ~(0xfffULL);
725
726 cmd->data[0] = devid;
727 cmd->data[0] |= (pasid & 0xff) << 16;
728 cmd->data[0] |= (qdep & 0xff) << 24;
729 cmd->data[1] = devid;
730 cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
731 cmd->data[2] = lower_32_bits(address);
732 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
733 cmd->data[3] = upper_32_bits(address);
734 if (size)
735 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
736 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
737 }
738
739 static void build_inv_all(struct iommu_cmd *cmd)
740 {
741 memset(cmd, 0, sizeof(*cmd));
742 CMD_SET_TYPE(cmd, CMD_INV_ALL);
743 }
744
745 /*
746 * Writes the command to the IOMMUs command buffer and informs the
747 * hardware about the new command.
748 */
749 static int iommu_queue_command_sync(struct amd_iommu *iommu,
750 struct iommu_cmd *cmd,
751 bool sync)
752 {
753 u32 left, tail, head, next_tail;
754 unsigned long flags;
755
756 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
757
758 again:
759 spin_lock_irqsave(&iommu->lock, flags);
760
761 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
762 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
763 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
764 left = (head - next_tail) % iommu->cmd_buf_size;
765
766 if (left <= 2) {
767 struct iommu_cmd sync_cmd;
768 volatile u64 sem = 0;
769 int ret;
770
771 build_completion_wait(&sync_cmd, (u64)&sem);
772 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
773
774 spin_unlock_irqrestore(&iommu->lock, flags);
775
776 if ((ret = wait_on_sem(&sem)) != 0)
777 return ret;
778
779 goto again;
780 }
781
782 copy_cmd_to_buffer(iommu, cmd, tail);
783
784 /* We need to sync now to make sure all commands are processed */
785 iommu->need_sync = sync;
786
787 spin_unlock_irqrestore(&iommu->lock, flags);
788
789 return 0;
790 }
791
792 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
793 {
794 return iommu_queue_command_sync(iommu, cmd, true);
795 }
796
797 /*
798 * This function queues a completion wait command into the command
799 * buffer of an IOMMU
800 */
801 static int iommu_completion_wait(struct amd_iommu *iommu)
802 {
803 struct iommu_cmd cmd;
804 volatile u64 sem = 0;
805 int ret;
806
807 if (!iommu->need_sync)
808 return 0;
809
810 build_completion_wait(&cmd, (u64)&sem);
811
812 ret = iommu_queue_command_sync(iommu, &cmd, false);
813 if (ret)
814 return ret;
815
816 return wait_on_sem(&sem);
817 }
818
819 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
820 {
821 struct iommu_cmd cmd;
822
823 build_inv_dte(&cmd, devid);
824
825 return iommu_queue_command(iommu, &cmd);
826 }
827
828 static void iommu_flush_dte_all(struct amd_iommu *iommu)
829 {
830 u32 devid;
831
832 for (devid = 0; devid <= 0xffff; ++devid)
833 iommu_flush_dte(iommu, devid);
834
835 iommu_completion_wait(iommu);
836 }
837
838 /*
839 * This function uses heavy locking and may disable irqs for some time. But
840 * this is no issue because it is only called during resume.
841 */
842 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
843 {
844 u32 dom_id;
845
846 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
847 struct iommu_cmd cmd;
848 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
849 dom_id, 1);
850 iommu_queue_command(iommu, &cmd);
851 }
852
853 iommu_completion_wait(iommu);
854 }
855
856 static void iommu_flush_all(struct amd_iommu *iommu)
857 {
858 struct iommu_cmd cmd;
859
860 build_inv_all(&cmd);
861
862 iommu_queue_command(iommu, &cmd);
863 iommu_completion_wait(iommu);
864 }
865
866 void iommu_flush_all_caches(struct amd_iommu *iommu)
867 {
868 if (iommu_feature(iommu, FEATURE_IA)) {
869 iommu_flush_all(iommu);
870 } else {
871 iommu_flush_dte_all(iommu);
872 iommu_flush_tlb_all(iommu);
873 }
874 }
875
876 /*
877 * Command send function for flushing on-device TLB
878 */
879 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
880 u64 address, size_t size)
881 {
882 struct amd_iommu *iommu;
883 struct iommu_cmd cmd;
884 int qdep;
885
886 qdep = dev_data->ats.qdep;
887 iommu = amd_iommu_rlookup_table[dev_data->devid];
888
889 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
890
891 return iommu_queue_command(iommu, &cmd);
892 }
893
894 /*
895 * Command send function for invalidating a device table entry
896 */
897 static int device_flush_dte(struct iommu_dev_data *dev_data)
898 {
899 struct amd_iommu *iommu;
900 int ret;
901
902 iommu = amd_iommu_rlookup_table[dev_data->devid];
903
904 ret = iommu_flush_dte(iommu, dev_data->devid);
905 if (ret)
906 return ret;
907
908 if (dev_data->ats.enabled)
909 ret = device_flush_iotlb(dev_data, 0, ~0UL);
910
911 return ret;
912 }
913
914 /*
915 * TLB invalidation function which is called from the mapping functions.
916 * It invalidates a single PTE if the range to flush is within a single
917 * page. Otherwise it flushes the whole TLB of the IOMMU.
918 */
919 static void __domain_flush_pages(struct protection_domain *domain,
920 u64 address, size_t size, int pde)
921 {
922 struct iommu_dev_data *dev_data;
923 struct iommu_cmd cmd;
924 int ret = 0, i;
925
926 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
927
928 for (i = 0; i < amd_iommus_present; ++i) {
929 if (!domain->dev_iommu[i])
930 continue;
931
932 /*
933 * Devices of this domain are behind this IOMMU
934 * We need a TLB flush
935 */
936 ret |= iommu_queue_command(amd_iommus[i], &cmd);
937 }
938
939 list_for_each_entry(dev_data, &domain->dev_list, list) {
940
941 if (!dev_data->ats.enabled)
942 continue;
943
944 ret |= device_flush_iotlb(dev_data, address, size);
945 }
946
947 WARN_ON(ret);
948 }
949
950 static void domain_flush_pages(struct protection_domain *domain,
951 u64 address, size_t size)
952 {
953 __domain_flush_pages(domain, address, size, 0);
954 }
955
956 /* Flush the whole IO/TLB for a given protection domain */
957 static void domain_flush_tlb(struct protection_domain *domain)
958 {
959 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
960 }
961
962 /* Flush the whole IO/TLB for a given protection domain - including PDE */
963 static void domain_flush_tlb_pde(struct protection_domain *domain)
964 {
965 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
966 }
967
968 static void domain_flush_complete(struct protection_domain *domain)
969 {
970 int i;
971
972 for (i = 0; i < amd_iommus_present; ++i) {
973 if (!domain->dev_iommu[i])
974 continue;
975
976 /*
977 * Devices of this domain are behind this IOMMU
978 * We need to wait for completion of all commands.
979 */
980 iommu_completion_wait(amd_iommus[i]);
981 }
982 }
983
984
985 /*
986 * This function flushes the DTEs for all devices in domain
987 */
988 static void domain_flush_devices(struct protection_domain *domain)
989 {
990 struct iommu_dev_data *dev_data;
991
992 list_for_each_entry(dev_data, &domain->dev_list, list)
993 device_flush_dte(dev_data);
994 }
995
996 /****************************************************************************
997 *
998 * The functions below are used the create the page table mappings for
999 * unity mapped regions.
1000 *
1001 ****************************************************************************/
1002
1003 /*
1004 * This function is used to add another level to an IO page table. Adding
1005 * another level increases the size of the address space by 9 bits to a size up
1006 * to 64 bits.
1007 */
1008 static bool increase_address_space(struct protection_domain *domain,
1009 gfp_t gfp)
1010 {
1011 u64 *pte;
1012
1013 if (domain->mode == PAGE_MODE_6_LEVEL)
1014 /* address space already 64 bit large */
1015 return false;
1016
1017 pte = (void *)get_zeroed_page(gfp);
1018 if (!pte)
1019 return false;
1020
1021 *pte = PM_LEVEL_PDE(domain->mode,
1022 virt_to_phys(domain->pt_root));
1023 domain->pt_root = pte;
1024 domain->mode += 1;
1025 domain->updated = true;
1026
1027 return true;
1028 }
1029
1030 static u64 *alloc_pte(struct protection_domain *domain,
1031 unsigned long address,
1032 unsigned long page_size,
1033 u64 **pte_page,
1034 gfp_t gfp)
1035 {
1036 int level, end_lvl;
1037 u64 *pte, *page;
1038
1039 BUG_ON(!is_power_of_2(page_size));
1040
1041 while (address > PM_LEVEL_SIZE(domain->mode))
1042 increase_address_space(domain, gfp);
1043
1044 level = domain->mode - 1;
1045 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1046 address = PAGE_SIZE_ALIGN(address, page_size);
1047 end_lvl = PAGE_SIZE_LEVEL(page_size);
1048
1049 while (level > end_lvl) {
1050 if (!IOMMU_PTE_PRESENT(*pte)) {
1051 page = (u64 *)get_zeroed_page(gfp);
1052 if (!page)
1053 return NULL;
1054 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1055 }
1056
1057 /* No level skipping support yet */
1058 if (PM_PTE_LEVEL(*pte) != level)
1059 return NULL;
1060
1061 level -= 1;
1062
1063 pte = IOMMU_PTE_PAGE(*pte);
1064
1065 if (pte_page && level == end_lvl)
1066 *pte_page = pte;
1067
1068 pte = &pte[PM_LEVEL_INDEX(level, address)];
1069 }
1070
1071 return pte;
1072 }
1073
1074 /*
1075 * This function checks if there is a PTE for a given dma address. If
1076 * there is one, it returns the pointer to it.
1077 */
1078 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
1079 {
1080 int level;
1081 u64 *pte;
1082
1083 if (address > PM_LEVEL_SIZE(domain->mode))
1084 return NULL;
1085
1086 level = domain->mode - 1;
1087 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1088
1089 while (level > 0) {
1090
1091 /* Not Present */
1092 if (!IOMMU_PTE_PRESENT(*pte))
1093 return NULL;
1094
1095 /* Large PTE */
1096 if (PM_PTE_LEVEL(*pte) == 0x07) {
1097 unsigned long pte_mask, __pte;
1098
1099 /*
1100 * If we have a series of large PTEs, make
1101 * sure to return a pointer to the first one.
1102 */
1103 pte_mask = PTE_PAGE_SIZE(*pte);
1104 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1105 __pte = ((unsigned long)pte) & pte_mask;
1106
1107 return (u64 *)__pte;
1108 }
1109
1110 /* No level skipping support yet */
1111 if (PM_PTE_LEVEL(*pte) != level)
1112 return NULL;
1113
1114 level -= 1;
1115
1116 /* Walk to the next level */
1117 pte = IOMMU_PTE_PAGE(*pte);
1118 pte = &pte[PM_LEVEL_INDEX(level, address)];
1119 }
1120
1121 return pte;
1122 }
1123
1124 /*
1125 * Generic mapping functions. It maps a physical address into a DMA
1126 * address space. It allocates the page table pages if necessary.
1127 * In the future it can be extended to a generic mapping function
1128 * supporting all features of AMD IOMMU page tables like level skipping
1129 * and full 64 bit address spaces.
1130 */
1131 static int iommu_map_page(struct protection_domain *dom,
1132 unsigned long bus_addr,
1133 unsigned long phys_addr,
1134 int prot,
1135 unsigned long page_size)
1136 {
1137 u64 __pte, *pte;
1138 int i, count;
1139
1140 if (!(prot & IOMMU_PROT_MASK))
1141 return -EINVAL;
1142
1143 bus_addr = PAGE_ALIGN(bus_addr);
1144 phys_addr = PAGE_ALIGN(phys_addr);
1145 count = PAGE_SIZE_PTE_COUNT(page_size);
1146 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1147
1148 for (i = 0; i < count; ++i)
1149 if (IOMMU_PTE_PRESENT(pte[i]))
1150 return -EBUSY;
1151
1152 if (page_size > PAGE_SIZE) {
1153 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1154 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1155 } else
1156 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1157
1158 if (prot & IOMMU_PROT_IR)
1159 __pte |= IOMMU_PTE_IR;
1160 if (prot & IOMMU_PROT_IW)
1161 __pte |= IOMMU_PTE_IW;
1162
1163 for (i = 0; i < count; ++i)
1164 pte[i] = __pte;
1165
1166 update_domain(dom);
1167
1168 return 0;
1169 }
1170
1171 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1172 unsigned long bus_addr,
1173 unsigned long page_size)
1174 {
1175 unsigned long long unmap_size, unmapped;
1176 u64 *pte;
1177
1178 BUG_ON(!is_power_of_2(page_size));
1179
1180 unmapped = 0;
1181
1182 while (unmapped < page_size) {
1183
1184 pte = fetch_pte(dom, bus_addr);
1185
1186 if (!pte) {
1187 /*
1188 * No PTE for this address
1189 * move forward in 4kb steps
1190 */
1191 unmap_size = PAGE_SIZE;
1192 } else if (PM_PTE_LEVEL(*pte) == 0) {
1193 /* 4kb PTE found for this address */
1194 unmap_size = PAGE_SIZE;
1195 *pte = 0ULL;
1196 } else {
1197 int count, i;
1198
1199 /* Large PTE found which maps this address */
1200 unmap_size = PTE_PAGE_SIZE(*pte);
1201 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1202 for (i = 0; i < count; i++)
1203 pte[i] = 0ULL;
1204 }
1205
1206 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1207 unmapped += unmap_size;
1208 }
1209
1210 BUG_ON(!is_power_of_2(unmapped));
1211
1212 return unmapped;
1213 }
1214
1215 /*
1216 * This function checks if a specific unity mapping entry is needed for
1217 * this specific IOMMU.
1218 */
1219 static int iommu_for_unity_map(struct amd_iommu *iommu,
1220 struct unity_map_entry *entry)
1221 {
1222 u16 bdf, i;
1223
1224 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1225 bdf = amd_iommu_alias_table[i];
1226 if (amd_iommu_rlookup_table[bdf] == iommu)
1227 return 1;
1228 }
1229
1230 return 0;
1231 }
1232
1233 /*
1234 * This function actually applies the mapping to the page table of the
1235 * dma_ops domain.
1236 */
1237 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1238 struct unity_map_entry *e)
1239 {
1240 u64 addr;
1241 int ret;
1242
1243 for (addr = e->address_start; addr < e->address_end;
1244 addr += PAGE_SIZE) {
1245 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1246 PAGE_SIZE);
1247 if (ret)
1248 return ret;
1249 /*
1250 * if unity mapping is in aperture range mark the page
1251 * as allocated in the aperture
1252 */
1253 if (addr < dma_dom->aperture_size)
1254 __set_bit(addr >> PAGE_SHIFT,
1255 dma_dom->aperture[0]->bitmap);
1256 }
1257
1258 return 0;
1259 }
1260
1261 /*
1262 * Init the unity mappings for a specific IOMMU in the system
1263 *
1264 * Basically iterates over all unity mapping entries and applies them to
1265 * the default domain DMA of that IOMMU if necessary.
1266 */
1267 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1268 {
1269 struct unity_map_entry *entry;
1270 int ret;
1271
1272 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1273 if (!iommu_for_unity_map(iommu, entry))
1274 continue;
1275 ret = dma_ops_unity_map(iommu->default_dom, entry);
1276 if (ret)
1277 return ret;
1278 }
1279
1280 return 0;
1281 }
1282
1283 /*
1284 * Inits the unity mappings required for a specific device
1285 */
1286 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1287 u16 devid)
1288 {
1289 struct unity_map_entry *e;
1290 int ret;
1291
1292 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1293 if (!(devid >= e->devid_start && devid <= e->devid_end))
1294 continue;
1295 ret = dma_ops_unity_map(dma_dom, e);
1296 if (ret)
1297 return ret;
1298 }
1299
1300 return 0;
1301 }
1302
1303 /****************************************************************************
1304 *
1305 * The next functions belong to the address allocator for the dma_ops
1306 * interface functions. They work like the allocators in the other IOMMU
1307 * drivers. Its basically a bitmap which marks the allocated pages in
1308 * the aperture. Maybe it could be enhanced in the future to a more
1309 * efficient allocator.
1310 *
1311 ****************************************************************************/
1312
1313 /*
1314 * The address allocator core functions.
1315 *
1316 * called with domain->lock held
1317 */
1318
1319 /*
1320 * Used to reserve address ranges in the aperture (e.g. for exclusion
1321 * ranges.
1322 */
1323 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1324 unsigned long start_page,
1325 unsigned int pages)
1326 {
1327 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1328
1329 if (start_page + pages > last_page)
1330 pages = last_page - start_page;
1331
1332 for (i = start_page; i < start_page + pages; ++i) {
1333 int index = i / APERTURE_RANGE_PAGES;
1334 int page = i % APERTURE_RANGE_PAGES;
1335 __set_bit(page, dom->aperture[index]->bitmap);
1336 }
1337 }
1338
1339 /*
1340 * This function is used to add a new aperture range to an existing
1341 * aperture in case of dma_ops domain allocation or address allocation
1342 * failure.
1343 */
1344 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1345 bool populate, gfp_t gfp)
1346 {
1347 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1348 struct amd_iommu *iommu;
1349 unsigned long i, old_size;
1350
1351 #ifdef CONFIG_IOMMU_STRESS
1352 populate = false;
1353 #endif
1354
1355 if (index >= APERTURE_MAX_RANGES)
1356 return -ENOMEM;
1357
1358 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1359 if (!dma_dom->aperture[index])
1360 return -ENOMEM;
1361
1362 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1363 if (!dma_dom->aperture[index]->bitmap)
1364 goto out_free;
1365
1366 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1367
1368 if (populate) {
1369 unsigned long address = dma_dom->aperture_size;
1370 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1371 u64 *pte, *pte_page;
1372
1373 for (i = 0; i < num_ptes; ++i) {
1374 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1375 &pte_page, gfp);
1376 if (!pte)
1377 goto out_free;
1378
1379 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1380
1381 address += APERTURE_RANGE_SIZE / 64;
1382 }
1383 }
1384
1385 old_size = dma_dom->aperture_size;
1386 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1387
1388 /* Reserve address range used for MSI messages */
1389 if (old_size < MSI_ADDR_BASE_LO &&
1390 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1391 unsigned long spage;
1392 int pages;
1393
1394 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1395 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1396
1397 dma_ops_reserve_addresses(dma_dom, spage, pages);
1398 }
1399
1400 /* Initialize the exclusion range if necessary */
1401 for_each_iommu(iommu) {
1402 if (iommu->exclusion_start &&
1403 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1404 && iommu->exclusion_start < dma_dom->aperture_size) {
1405 unsigned long startpage;
1406 int pages = iommu_num_pages(iommu->exclusion_start,
1407 iommu->exclusion_length,
1408 PAGE_SIZE);
1409 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1410 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1411 }
1412 }
1413
1414 /*
1415 * Check for areas already mapped as present in the new aperture
1416 * range and mark those pages as reserved in the allocator. Such
1417 * mappings may already exist as a result of requested unity
1418 * mappings for devices.
1419 */
1420 for (i = dma_dom->aperture[index]->offset;
1421 i < dma_dom->aperture_size;
1422 i += PAGE_SIZE) {
1423 u64 *pte = fetch_pte(&dma_dom->domain, i);
1424 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1425 continue;
1426
1427 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
1428 }
1429
1430 update_domain(&dma_dom->domain);
1431
1432 return 0;
1433
1434 out_free:
1435 update_domain(&dma_dom->domain);
1436
1437 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1438
1439 kfree(dma_dom->aperture[index]);
1440 dma_dom->aperture[index] = NULL;
1441
1442 return -ENOMEM;
1443 }
1444
1445 static unsigned long dma_ops_area_alloc(struct device *dev,
1446 struct dma_ops_domain *dom,
1447 unsigned int pages,
1448 unsigned long align_mask,
1449 u64 dma_mask,
1450 unsigned long start)
1451 {
1452 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1453 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1454 int i = start >> APERTURE_RANGE_SHIFT;
1455 unsigned long boundary_size;
1456 unsigned long address = -1;
1457 unsigned long limit;
1458
1459 next_bit >>= PAGE_SHIFT;
1460
1461 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1462 PAGE_SIZE) >> PAGE_SHIFT;
1463
1464 for (;i < max_index; ++i) {
1465 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1466
1467 if (dom->aperture[i]->offset >= dma_mask)
1468 break;
1469
1470 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1471 dma_mask >> PAGE_SHIFT);
1472
1473 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1474 limit, next_bit, pages, 0,
1475 boundary_size, align_mask);
1476 if (address != -1) {
1477 address = dom->aperture[i]->offset +
1478 (address << PAGE_SHIFT);
1479 dom->next_address = address + (pages << PAGE_SHIFT);
1480 break;
1481 }
1482
1483 next_bit = 0;
1484 }
1485
1486 return address;
1487 }
1488
1489 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1490 struct dma_ops_domain *dom,
1491 unsigned int pages,
1492 unsigned long align_mask,
1493 u64 dma_mask)
1494 {
1495 unsigned long address;
1496
1497 #ifdef CONFIG_IOMMU_STRESS
1498 dom->next_address = 0;
1499 dom->need_flush = true;
1500 #endif
1501
1502 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1503 dma_mask, dom->next_address);
1504
1505 if (address == -1) {
1506 dom->next_address = 0;
1507 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1508 dma_mask, 0);
1509 dom->need_flush = true;
1510 }
1511
1512 if (unlikely(address == -1))
1513 address = DMA_ERROR_CODE;
1514
1515 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1516
1517 return address;
1518 }
1519
1520 /*
1521 * The address free function.
1522 *
1523 * called with domain->lock held
1524 */
1525 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1526 unsigned long address,
1527 unsigned int pages)
1528 {
1529 unsigned i = address >> APERTURE_RANGE_SHIFT;
1530 struct aperture_range *range = dom->aperture[i];
1531
1532 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1533
1534 #ifdef CONFIG_IOMMU_STRESS
1535 if (i < 4)
1536 return;
1537 #endif
1538
1539 if (address >= dom->next_address)
1540 dom->need_flush = true;
1541
1542 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1543
1544 bitmap_clear(range->bitmap, address, pages);
1545
1546 }
1547
1548 /****************************************************************************
1549 *
1550 * The next functions belong to the domain allocation. A domain is
1551 * allocated for every IOMMU as the default domain. If device isolation
1552 * is enabled, every device get its own domain. The most important thing
1553 * about domains is the page table mapping the DMA address space they
1554 * contain.
1555 *
1556 ****************************************************************************/
1557
1558 /*
1559 * This function adds a protection domain to the global protection domain list
1560 */
1561 static void add_domain_to_list(struct protection_domain *domain)
1562 {
1563 unsigned long flags;
1564
1565 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1566 list_add(&domain->list, &amd_iommu_pd_list);
1567 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1568 }
1569
1570 /*
1571 * This function removes a protection domain to the global
1572 * protection domain list
1573 */
1574 static void del_domain_from_list(struct protection_domain *domain)
1575 {
1576 unsigned long flags;
1577
1578 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1579 list_del(&domain->list);
1580 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1581 }
1582
1583 static u16 domain_id_alloc(void)
1584 {
1585 unsigned long flags;
1586 int id;
1587
1588 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1589 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1590 BUG_ON(id == 0);
1591 if (id > 0 && id < MAX_DOMAIN_ID)
1592 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1593 else
1594 id = 0;
1595 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1596
1597 return id;
1598 }
1599
1600 static void domain_id_free(int id)
1601 {
1602 unsigned long flags;
1603
1604 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1605 if (id > 0 && id < MAX_DOMAIN_ID)
1606 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1607 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1608 }
1609
1610 static void free_pagetable(struct protection_domain *domain)
1611 {
1612 int i, j;
1613 u64 *p1, *p2, *p3;
1614
1615 p1 = domain->pt_root;
1616
1617 if (!p1)
1618 return;
1619
1620 for (i = 0; i < 512; ++i) {
1621 if (!IOMMU_PTE_PRESENT(p1[i]))
1622 continue;
1623
1624 p2 = IOMMU_PTE_PAGE(p1[i]);
1625 for (j = 0; j < 512; ++j) {
1626 if (!IOMMU_PTE_PRESENT(p2[j]))
1627 continue;
1628 p3 = IOMMU_PTE_PAGE(p2[j]);
1629 free_page((unsigned long)p3);
1630 }
1631
1632 free_page((unsigned long)p2);
1633 }
1634
1635 free_page((unsigned long)p1);
1636
1637 domain->pt_root = NULL;
1638 }
1639
1640 static void free_gcr3_table(struct protection_domain *domain)
1641 {
1642 free_page((unsigned long)domain->gcr3_tbl);
1643 }
1644
1645 /*
1646 * Free a domain, only used if something went wrong in the
1647 * allocation path and we need to free an already allocated page table
1648 */
1649 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1650 {
1651 int i;
1652
1653 if (!dom)
1654 return;
1655
1656 del_domain_from_list(&dom->domain);
1657
1658 free_pagetable(&dom->domain);
1659
1660 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1661 if (!dom->aperture[i])
1662 continue;
1663 free_page((unsigned long)dom->aperture[i]->bitmap);
1664 kfree(dom->aperture[i]);
1665 }
1666
1667 kfree(dom);
1668 }
1669
1670 /*
1671 * Allocates a new protection domain usable for the dma_ops functions.
1672 * It also initializes the page table and the address allocator data
1673 * structures required for the dma_ops interface
1674 */
1675 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1676 {
1677 struct dma_ops_domain *dma_dom;
1678
1679 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1680 if (!dma_dom)
1681 return NULL;
1682
1683 spin_lock_init(&dma_dom->domain.lock);
1684
1685 dma_dom->domain.id = domain_id_alloc();
1686 if (dma_dom->domain.id == 0)
1687 goto free_dma_dom;
1688 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1689 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1690 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1691 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1692 dma_dom->domain.priv = dma_dom;
1693 if (!dma_dom->domain.pt_root)
1694 goto free_dma_dom;
1695
1696 dma_dom->need_flush = false;
1697 dma_dom->target_dev = 0xffff;
1698
1699 add_domain_to_list(&dma_dom->domain);
1700
1701 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1702 goto free_dma_dom;
1703
1704 /*
1705 * mark the first page as allocated so we never return 0 as
1706 * a valid dma-address. So we can use 0 as error value
1707 */
1708 dma_dom->aperture[0]->bitmap[0] = 1;
1709 dma_dom->next_address = 0;
1710
1711
1712 return dma_dom;
1713
1714 free_dma_dom:
1715 dma_ops_domain_free(dma_dom);
1716
1717 return NULL;
1718 }
1719
1720 /*
1721 * little helper function to check whether a given protection domain is a
1722 * dma_ops domain
1723 */
1724 static bool dma_ops_domain(struct protection_domain *domain)
1725 {
1726 return domain->flags & PD_DMA_OPS_MASK;
1727 }
1728
1729 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1730 {
1731 u64 pte_root = 0;
1732 u64 flags = 0;
1733
1734 if (domain->mode != PAGE_MODE_NONE)
1735 pte_root = virt_to_phys(domain->pt_root);
1736
1737 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1738 << DEV_ENTRY_MODE_SHIFT;
1739 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1740
1741 flags = amd_iommu_dev_table[devid].data[1];
1742
1743 if (ats)
1744 flags |= DTE_FLAG_IOTLB;
1745
1746 if (domain->flags & PD_IOMMUV2_MASK) {
1747 u64 gcr3 = __pa(domain->gcr3_tbl);
1748 u64 glx = domain->glx;
1749 u64 tmp;
1750
1751 pte_root |= DTE_FLAG_GV;
1752 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1753
1754 /* First mask out possible old values for GCR3 table */
1755 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1756 flags &= ~tmp;
1757
1758 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1759 flags &= ~tmp;
1760
1761 /* Encode GCR3 table into DTE */
1762 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1763 pte_root |= tmp;
1764
1765 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1766 flags |= tmp;
1767
1768 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1769 flags |= tmp;
1770 }
1771
1772 flags &= ~(0xffffUL);
1773 flags |= domain->id;
1774
1775 amd_iommu_dev_table[devid].data[1] = flags;
1776 amd_iommu_dev_table[devid].data[0] = pte_root;
1777 }
1778
1779 static void clear_dte_entry(u16 devid)
1780 {
1781 /* remove entry from the device table seen by the hardware */
1782 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1783 amd_iommu_dev_table[devid].data[1] = 0;
1784
1785 amd_iommu_apply_erratum_63(devid);
1786 }
1787
1788 static void do_attach(struct iommu_dev_data *dev_data,
1789 struct protection_domain *domain)
1790 {
1791 struct amd_iommu *iommu;
1792 bool ats;
1793
1794 iommu = amd_iommu_rlookup_table[dev_data->devid];
1795 ats = dev_data->ats.enabled;
1796
1797 /* Update data structures */
1798 dev_data->domain = domain;
1799 list_add(&dev_data->list, &domain->dev_list);
1800 set_dte_entry(dev_data->devid, domain, ats);
1801
1802 /* Do reference counting */
1803 domain->dev_iommu[iommu->index] += 1;
1804 domain->dev_cnt += 1;
1805
1806 /* Flush the DTE entry */
1807 device_flush_dte(dev_data);
1808 }
1809
1810 static void do_detach(struct iommu_dev_data *dev_data)
1811 {
1812 struct amd_iommu *iommu;
1813
1814 iommu = amd_iommu_rlookup_table[dev_data->devid];
1815
1816 /* decrease reference counters */
1817 dev_data->domain->dev_iommu[iommu->index] -= 1;
1818 dev_data->domain->dev_cnt -= 1;
1819
1820 /* Update data structures */
1821 dev_data->domain = NULL;
1822 list_del(&dev_data->list);
1823 clear_dte_entry(dev_data->devid);
1824
1825 /* Flush the DTE entry */
1826 device_flush_dte(dev_data);
1827 }
1828
1829 /*
1830 * If a device is not yet associated with a domain, this function does
1831 * assigns it visible for the hardware
1832 */
1833 static int __attach_device(struct iommu_dev_data *dev_data,
1834 struct protection_domain *domain)
1835 {
1836 int ret;
1837
1838 /* lock domain */
1839 spin_lock(&domain->lock);
1840
1841 if (dev_data->alias_data != NULL) {
1842 struct iommu_dev_data *alias_data = dev_data->alias_data;
1843
1844 /* Some sanity checks */
1845 ret = -EBUSY;
1846 if (alias_data->domain != NULL &&
1847 alias_data->domain != domain)
1848 goto out_unlock;
1849
1850 if (dev_data->domain != NULL &&
1851 dev_data->domain != domain)
1852 goto out_unlock;
1853
1854 /* Do real assignment */
1855 if (alias_data->domain == NULL)
1856 do_attach(alias_data, domain);
1857
1858 atomic_inc(&alias_data->bind);
1859 }
1860
1861 if (dev_data->domain == NULL)
1862 do_attach(dev_data, domain);
1863
1864 atomic_inc(&dev_data->bind);
1865
1866 ret = 0;
1867
1868 out_unlock:
1869
1870 /* ready */
1871 spin_unlock(&domain->lock);
1872
1873 return ret;
1874 }
1875
1876
1877 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1878 {
1879 pci_disable_ats(pdev);
1880 pci_disable_pri(pdev);
1881 pci_disable_pasid(pdev);
1882 }
1883
1884 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1885 {
1886 int ret;
1887
1888 /* Only allow access to user-accessible pages */
1889 ret = pci_enable_pasid(pdev, 0);
1890 if (ret)
1891 goto out_err;
1892
1893 /* First reset the PRI state of the device */
1894 ret = pci_reset_pri(pdev);
1895 if (ret)
1896 goto out_err;
1897
1898 /* FIXME: Hardcode number of outstanding requests for now */
1899 ret = pci_enable_pri(pdev, 32);
1900 if (ret)
1901 goto out_err;
1902
1903 ret = pci_enable_ats(pdev, PAGE_SHIFT);
1904 if (ret)
1905 goto out_err;
1906
1907 return 0;
1908
1909 out_err:
1910 pci_disable_pri(pdev);
1911 pci_disable_pasid(pdev);
1912
1913 return ret;
1914 }
1915
1916 /*
1917 * If a device is not yet associated with a domain, this function does
1918 * assigns it visible for the hardware
1919 */
1920 static int attach_device(struct device *dev,
1921 struct protection_domain *domain)
1922 {
1923 struct pci_dev *pdev = to_pci_dev(dev);
1924 struct iommu_dev_data *dev_data;
1925 unsigned long flags;
1926 int ret;
1927
1928 dev_data = get_dev_data(dev);
1929
1930 if (domain->flags & PD_IOMMUV2_MASK) {
1931 if (!dev_data->iommu_v2 || !dev_data->passthrough)
1932 return -EINVAL;
1933
1934 if (pdev_iommuv2_enable(pdev) != 0)
1935 return -EINVAL;
1936
1937 dev_data->ats.enabled = true;
1938 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1939 } else if (amd_iommu_iotlb_sup &&
1940 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
1941 dev_data->ats.enabled = true;
1942 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1943 }
1944
1945 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1946 ret = __attach_device(dev_data, domain);
1947 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1948
1949 /*
1950 * We might boot into a crash-kernel here. The crashed kernel
1951 * left the caches in the IOMMU dirty. So we have to flush
1952 * here to evict all dirty stuff.
1953 */
1954 domain_flush_tlb_pde(domain);
1955
1956 return ret;
1957 }
1958
1959 /*
1960 * Removes a device from a protection domain (unlocked)
1961 */
1962 static void __detach_device(struct iommu_dev_data *dev_data)
1963 {
1964 struct protection_domain *domain;
1965 unsigned long flags;
1966
1967 BUG_ON(!dev_data->domain);
1968
1969 domain = dev_data->domain;
1970
1971 spin_lock_irqsave(&domain->lock, flags);
1972
1973 if (dev_data->alias_data != NULL) {
1974 struct iommu_dev_data *alias_data = dev_data->alias_data;
1975
1976 if (atomic_dec_and_test(&alias_data->bind))
1977 do_detach(alias_data);
1978 }
1979
1980 if (atomic_dec_and_test(&dev_data->bind))
1981 do_detach(dev_data);
1982
1983 spin_unlock_irqrestore(&domain->lock, flags);
1984
1985 /*
1986 * If we run in passthrough mode the device must be assigned to the
1987 * passthrough domain if it is detached from any other domain.
1988 * Make sure we can deassign from the pt_domain itself.
1989 */
1990 if (dev_data->passthrough &&
1991 (dev_data->domain == NULL && domain != pt_domain))
1992 __attach_device(dev_data, pt_domain);
1993 }
1994
1995 /*
1996 * Removes a device from a protection domain (with devtable_lock held)
1997 */
1998 static void detach_device(struct device *dev)
1999 {
2000 struct protection_domain *domain;
2001 struct iommu_dev_data *dev_data;
2002 unsigned long flags;
2003
2004 dev_data = get_dev_data(dev);
2005 domain = dev_data->domain;
2006
2007 /* lock device table */
2008 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2009 __detach_device(dev_data);
2010 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2011
2012 if (domain->flags & PD_IOMMUV2_MASK)
2013 pdev_iommuv2_disable(to_pci_dev(dev));
2014 else if (dev_data->ats.enabled)
2015 pci_disable_ats(to_pci_dev(dev));
2016
2017 dev_data->ats.enabled = false;
2018 }
2019
2020 /*
2021 * Find out the protection domain structure for a given PCI device. This
2022 * will give us the pointer to the page table root for example.
2023 */
2024 static struct protection_domain *domain_for_device(struct device *dev)
2025 {
2026 struct iommu_dev_data *dev_data;
2027 struct protection_domain *dom = NULL;
2028 unsigned long flags;
2029
2030 dev_data = get_dev_data(dev);
2031
2032 if (dev_data->domain)
2033 return dev_data->domain;
2034
2035 if (dev_data->alias_data != NULL) {
2036 struct iommu_dev_data *alias_data = dev_data->alias_data;
2037
2038 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2039 if (alias_data->domain != NULL) {
2040 __attach_device(dev_data, alias_data->domain);
2041 dom = alias_data->domain;
2042 }
2043 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2044 }
2045
2046 return dom;
2047 }
2048
2049 static int device_change_notifier(struct notifier_block *nb,
2050 unsigned long action, void *data)
2051 {
2052 struct dma_ops_domain *dma_domain;
2053 struct protection_domain *domain;
2054 struct iommu_dev_data *dev_data;
2055 struct device *dev = data;
2056 struct amd_iommu *iommu;
2057 unsigned long flags;
2058 u16 devid;
2059
2060 if (!check_device(dev))
2061 return 0;
2062
2063 devid = get_device_id(dev);
2064 iommu = amd_iommu_rlookup_table[devid];
2065 dev_data = get_dev_data(dev);
2066
2067 switch (action) {
2068 case BUS_NOTIFY_UNBOUND_DRIVER:
2069
2070 domain = domain_for_device(dev);
2071
2072 if (!domain)
2073 goto out;
2074 if (dev_data->passthrough)
2075 break;
2076 detach_device(dev);
2077 break;
2078 case BUS_NOTIFY_ADD_DEVICE:
2079
2080 iommu_init_device(dev);
2081
2082 domain = domain_for_device(dev);
2083
2084 /* allocate a protection domain if a device is added */
2085 dma_domain = find_protection_domain(devid);
2086 if (dma_domain)
2087 goto out;
2088 dma_domain = dma_ops_domain_alloc();
2089 if (!dma_domain)
2090 goto out;
2091 dma_domain->target_dev = devid;
2092
2093 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2094 list_add_tail(&dma_domain->list, &iommu_pd_list);
2095 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2096
2097 break;
2098 case BUS_NOTIFY_DEL_DEVICE:
2099
2100 iommu_uninit_device(dev);
2101
2102 default:
2103 goto out;
2104 }
2105
2106 iommu_completion_wait(iommu);
2107
2108 out:
2109 return 0;
2110 }
2111
2112 static struct notifier_block device_nb = {
2113 .notifier_call = device_change_notifier,
2114 };
2115
2116 void amd_iommu_init_notifier(void)
2117 {
2118 bus_register_notifier(&pci_bus_type, &device_nb);
2119 }
2120
2121 /*****************************************************************************
2122 *
2123 * The next functions belong to the dma_ops mapping/unmapping code.
2124 *
2125 *****************************************************************************/
2126
2127 /*
2128 * In the dma_ops path we only have the struct device. This function
2129 * finds the corresponding IOMMU, the protection domain and the
2130 * requestor id for a given device.
2131 * If the device is not yet associated with a domain this is also done
2132 * in this function.
2133 */
2134 static struct protection_domain *get_domain(struct device *dev)
2135 {
2136 struct protection_domain *domain;
2137 struct dma_ops_domain *dma_dom;
2138 u16 devid = get_device_id(dev);
2139
2140 if (!check_device(dev))
2141 return ERR_PTR(-EINVAL);
2142
2143 domain = domain_for_device(dev);
2144 if (domain != NULL && !dma_ops_domain(domain))
2145 return ERR_PTR(-EBUSY);
2146
2147 if (domain != NULL)
2148 return domain;
2149
2150 /* Device not bount yet - bind it */
2151 dma_dom = find_protection_domain(devid);
2152 if (!dma_dom)
2153 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2154 attach_device(dev, &dma_dom->domain);
2155 DUMP_printk("Using protection domain %d for device %s\n",
2156 dma_dom->domain.id, dev_name(dev));
2157
2158 return &dma_dom->domain;
2159 }
2160
2161 static void update_device_table(struct protection_domain *domain)
2162 {
2163 struct iommu_dev_data *dev_data;
2164
2165 list_for_each_entry(dev_data, &domain->dev_list, list)
2166 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2167 }
2168
2169 static void update_domain(struct protection_domain *domain)
2170 {
2171 if (!domain->updated)
2172 return;
2173
2174 update_device_table(domain);
2175
2176 domain_flush_devices(domain);
2177 domain_flush_tlb_pde(domain);
2178
2179 domain->updated = false;
2180 }
2181
2182 /*
2183 * This function fetches the PTE for a given address in the aperture
2184 */
2185 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2186 unsigned long address)
2187 {
2188 struct aperture_range *aperture;
2189 u64 *pte, *pte_page;
2190
2191 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2192 if (!aperture)
2193 return NULL;
2194
2195 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2196 if (!pte) {
2197 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2198 GFP_ATOMIC);
2199 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2200 } else
2201 pte += PM_LEVEL_INDEX(0, address);
2202
2203 update_domain(&dom->domain);
2204
2205 return pte;
2206 }
2207
2208 /*
2209 * This is the generic map function. It maps one 4kb page at paddr to
2210 * the given address in the DMA address space for the domain.
2211 */
2212 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2213 unsigned long address,
2214 phys_addr_t paddr,
2215 int direction)
2216 {
2217 u64 *pte, __pte;
2218
2219 WARN_ON(address > dom->aperture_size);
2220
2221 paddr &= PAGE_MASK;
2222
2223 pte = dma_ops_get_pte(dom, address);
2224 if (!pte)
2225 return DMA_ERROR_CODE;
2226
2227 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2228
2229 if (direction == DMA_TO_DEVICE)
2230 __pte |= IOMMU_PTE_IR;
2231 else if (direction == DMA_FROM_DEVICE)
2232 __pte |= IOMMU_PTE_IW;
2233 else if (direction == DMA_BIDIRECTIONAL)
2234 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2235
2236 WARN_ON(*pte);
2237
2238 *pte = __pte;
2239
2240 return (dma_addr_t)address;
2241 }
2242
2243 /*
2244 * The generic unmapping function for on page in the DMA address space.
2245 */
2246 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2247 unsigned long address)
2248 {
2249 struct aperture_range *aperture;
2250 u64 *pte;
2251
2252 if (address >= dom->aperture_size)
2253 return;
2254
2255 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2256 if (!aperture)
2257 return;
2258
2259 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2260 if (!pte)
2261 return;
2262
2263 pte += PM_LEVEL_INDEX(0, address);
2264
2265 WARN_ON(!*pte);
2266
2267 *pte = 0ULL;
2268 }
2269
2270 /*
2271 * This function contains common code for mapping of a physically
2272 * contiguous memory region into DMA address space. It is used by all
2273 * mapping functions provided with this IOMMU driver.
2274 * Must be called with the domain lock held.
2275 */
2276 static dma_addr_t __map_single(struct device *dev,
2277 struct dma_ops_domain *dma_dom,
2278 phys_addr_t paddr,
2279 size_t size,
2280 int dir,
2281 bool align,
2282 u64 dma_mask)
2283 {
2284 dma_addr_t offset = paddr & ~PAGE_MASK;
2285 dma_addr_t address, start, ret;
2286 unsigned int pages;
2287 unsigned long align_mask = 0;
2288 int i;
2289
2290 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2291 paddr &= PAGE_MASK;
2292
2293 INC_STATS_COUNTER(total_map_requests);
2294
2295 if (pages > 1)
2296 INC_STATS_COUNTER(cross_page);
2297
2298 if (align)
2299 align_mask = (1UL << get_order(size)) - 1;
2300
2301 retry:
2302 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2303 dma_mask);
2304 if (unlikely(address == DMA_ERROR_CODE)) {
2305 /*
2306 * setting next_address here will let the address
2307 * allocator only scan the new allocated range in the
2308 * first run. This is a small optimization.
2309 */
2310 dma_dom->next_address = dma_dom->aperture_size;
2311
2312 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2313 goto out;
2314
2315 /*
2316 * aperture was successfully enlarged by 128 MB, try
2317 * allocation again
2318 */
2319 goto retry;
2320 }
2321
2322 start = address;
2323 for (i = 0; i < pages; ++i) {
2324 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2325 if (ret == DMA_ERROR_CODE)
2326 goto out_unmap;
2327
2328 paddr += PAGE_SIZE;
2329 start += PAGE_SIZE;
2330 }
2331 address += offset;
2332
2333 ADD_STATS_COUNTER(alloced_io_mem, size);
2334
2335 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2336 domain_flush_tlb(&dma_dom->domain);
2337 dma_dom->need_flush = false;
2338 } else if (unlikely(amd_iommu_np_cache))
2339 domain_flush_pages(&dma_dom->domain, address, size);
2340
2341 out:
2342 return address;
2343
2344 out_unmap:
2345
2346 for (--i; i >= 0; --i) {
2347 start -= PAGE_SIZE;
2348 dma_ops_domain_unmap(dma_dom, start);
2349 }
2350
2351 dma_ops_free_addresses(dma_dom, address, pages);
2352
2353 return DMA_ERROR_CODE;
2354 }
2355
2356 /*
2357 * Does the reverse of the __map_single function. Must be called with
2358 * the domain lock held too
2359 */
2360 static void __unmap_single(struct dma_ops_domain *dma_dom,
2361 dma_addr_t dma_addr,
2362 size_t size,
2363 int dir)
2364 {
2365 dma_addr_t flush_addr;
2366 dma_addr_t i, start;
2367 unsigned int pages;
2368
2369 if ((dma_addr == DMA_ERROR_CODE) ||
2370 (dma_addr + size > dma_dom->aperture_size))
2371 return;
2372
2373 flush_addr = dma_addr;
2374 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2375 dma_addr &= PAGE_MASK;
2376 start = dma_addr;
2377
2378 for (i = 0; i < pages; ++i) {
2379 dma_ops_domain_unmap(dma_dom, start);
2380 start += PAGE_SIZE;
2381 }
2382
2383 SUB_STATS_COUNTER(alloced_io_mem, size);
2384
2385 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2386
2387 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2388 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2389 dma_dom->need_flush = false;
2390 }
2391 }
2392
2393 /*
2394 * The exported map_single function for dma_ops.
2395 */
2396 static dma_addr_t map_page(struct device *dev, struct page *page,
2397 unsigned long offset, size_t size,
2398 enum dma_data_direction dir,
2399 struct dma_attrs *attrs)
2400 {
2401 unsigned long flags;
2402 struct protection_domain *domain;
2403 dma_addr_t addr;
2404 u64 dma_mask;
2405 phys_addr_t paddr = page_to_phys(page) + offset;
2406
2407 INC_STATS_COUNTER(cnt_map_single);
2408
2409 domain = get_domain(dev);
2410 if (PTR_ERR(domain) == -EINVAL)
2411 return (dma_addr_t)paddr;
2412 else if (IS_ERR(domain))
2413 return DMA_ERROR_CODE;
2414
2415 dma_mask = *dev->dma_mask;
2416
2417 spin_lock_irqsave(&domain->lock, flags);
2418
2419 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2420 dma_mask);
2421 if (addr == DMA_ERROR_CODE)
2422 goto out;
2423
2424 domain_flush_complete(domain);
2425
2426 out:
2427 spin_unlock_irqrestore(&domain->lock, flags);
2428
2429 return addr;
2430 }
2431
2432 /*
2433 * The exported unmap_single function for dma_ops.
2434 */
2435 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2436 enum dma_data_direction dir, struct dma_attrs *attrs)
2437 {
2438 unsigned long flags;
2439 struct protection_domain *domain;
2440
2441 INC_STATS_COUNTER(cnt_unmap_single);
2442
2443 domain = get_domain(dev);
2444 if (IS_ERR(domain))
2445 return;
2446
2447 spin_lock_irqsave(&domain->lock, flags);
2448
2449 __unmap_single(domain->priv, dma_addr, size, dir);
2450
2451 domain_flush_complete(domain);
2452
2453 spin_unlock_irqrestore(&domain->lock, flags);
2454 }
2455
2456 /*
2457 * This is a special map_sg function which is used if we should map a
2458 * device which is not handled by an AMD IOMMU in the system.
2459 */
2460 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2461 int nelems, int dir)
2462 {
2463 struct scatterlist *s;
2464 int i;
2465
2466 for_each_sg(sglist, s, nelems, i) {
2467 s->dma_address = (dma_addr_t)sg_phys(s);
2468 s->dma_length = s->length;
2469 }
2470
2471 return nelems;
2472 }
2473
2474 /*
2475 * The exported map_sg function for dma_ops (handles scatter-gather
2476 * lists).
2477 */
2478 static int map_sg(struct device *dev, struct scatterlist *sglist,
2479 int nelems, enum dma_data_direction dir,
2480 struct dma_attrs *attrs)
2481 {
2482 unsigned long flags;
2483 struct protection_domain *domain;
2484 int i;
2485 struct scatterlist *s;
2486 phys_addr_t paddr;
2487 int mapped_elems = 0;
2488 u64 dma_mask;
2489
2490 INC_STATS_COUNTER(cnt_map_sg);
2491
2492 domain = get_domain(dev);
2493 if (PTR_ERR(domain) == -EINVAL)
2494 return map_sg_no_iommu(dev, sglist, nelems, dir);
2495 else if (IS_ERR(domain))
2496 return 0;
2497
2498 dma_mask = *dev->dma_mask;
2499
2500 spin_lock_irqsave(&domain->lock, flags);
2501
2502 for_each_sg(sglist, s, nelems, i) {
2503 paddr = sg_phys(s);
2504
2505 s->dma_address = __map_single(dev, domain->priv,
2506 paddr, s->length, dir, false,
2507 dma_mask);
2508
2509 if (s->dma_address) {
2510 s->dma_length = s->length;
2511 mapped_elems++;
2512 } else
2513 goto unmap;
2514 }
2515
2516 domain_flush_complete(domain);
2517
2518 out:
2519 spin_unlock_irqrestore(&domain->lock, flags);
2520
2521 return mapped_elems;
2522 unmap:
2523 for_each_sg(sglist, s, mapped_elems, i) {
2524 if (s->dma_address)
2525 __unmap_single(domain->priv, s->dma_address,
2526 s->dma_length, dir);
2527 s->dma_address = s->dma_length = 0;
2528 }
2529
2530 mapped_elems = 0;
2531
2532 goto out;
2533 }
2534
2535 /*
2536 * The exported map_sg function for dma_ops (handles scatter-gather
2537 * lists).
2538 */
2539 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2540 int nelems, enum dma_data_direction dir,
2541 struct dma_attrs *attrs)
2542 {
2543 unsigned long flags;
2544 struct protection_domain *domain;
2545 struct scatterlist *s;
2546 int i;
2547
2548 INC_STATS_COUNTER(cnt_unmap_sg);
2549
2550 domain = get_domain(dev);
2551 if (IS_ERR(domain))
2552 return;
2553
2554 spin_lock_irqsave(&domain->lock, flags);
2555
2556 for_each_sg(sglist, s, nelems, i) {
2557 __unmap_single(domain->priv, s->dma_address,
2558 s->dma_length, dir);
2559 s->dma_address = s->dma_length = 0;
2560 }
2561
2562 domain_flush_complete(domain);
2563
2564 spin_unlock_irqrestore(&domain->lock, flags);
2565 }
2566
2567 /*
2568 * The exported alloc_coherent function for dma_ops.
2569 */
2570 static void *alloc_coherent(struct device *dev, size_t size,
2571 dma_addr_t *dma_addr, gfp_t flag)
2572 {
2573 unsigned long flags;
2574 void *virt_addr;
2575 struct protection_domain *domain;
2576 phys_addr_t paddr;
2577 u64 dma_mask = dev->coherent_dma_mask;
2578
2579 INC_STATS_COUNTER(cnt_alloc_coherent);
2580
2581 domain = get_domain(dev);
2582 if (PTR_ERR(domain) == -EINVAL) {
2583 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2584 *dma_addr = __pa(virt_addr);
2585 return virt_addr;
2586 } else if (IS_ERR(domain))
2587 return NULL;
2588
2589 dma_mask = dev->coherent_dma_mask;
2590 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2591 flag |= __GFP_ZERO;
2592
2593 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2594 if (!virt_addr)
2595 return NULL;
2596
2597 paddr = virt_to_phys(virt_addr);
2598
2599 if (!dma_mask)
2600 dma_mask = *dev->dma_mask;
2601
2602 spin_lock_irqsave(&domain->lock, flags);
2603
2604 *dma_addr = __map_single(dev, domain->priv, paddr,
2605 size, DMA_BIDIRECTIONAL, true, dma_mask);
2606
2607 if (*dma_addr == DMA_ERROR_CODE) {
2608 spin_unlock_irqrestore(&domain->lock, flags);
2609 goto out_free;
2610 }
2611
2612 domain_flush_complete(domain);
2613
2614 spin_unlock_irqrestore(&domain->lock, flags);
2615
2616 return virt_addr;
2617
2618 out_free:
2619
2620 free_pages((unsigned long)virt_addr, get_order(size));
2621
2622 return NULL;
2623 }
2624
2625 /*
2626 * The exported free_coherent function for dma_ops.
2627 */
2628 static void free_coherent(struct device *dev, size_t size,
2629 void *virt_addr, dma_addr_t dma_addr)
2630 {
2631 unsigned long flags;
2632 struct protection_domain *domain;
2633
2634 INC_STATS_COUNTER(cnt_free_coherent);
2635
2636 domain = get_domain(dev);
2637 if (IS_ERR(domain))
2638 goto free_mem;
2639
2640 spin_lock_irqsave(&domain->lock, flags);
2641
2642 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2643
2644 domain_flush_complete(domain);
2645
2646 spin_unlock_irqrestore(&domain->lock, flags);
2647
2648 free_mem:
2649 free_pages((unsigned long)virt_addr, get_order(size));
2650 }
2651
2652 /*
2653 * This function is called by the DMA layer to find out if we can handle a
2654 * particular device. It is part of the dma_ops.
2655 */
2656 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2657 {
2658 return check_device(dev);
2659 }
2660
2661 /*
2662 * The function for pre-allocating protection domains.
2663 *
2664 * If the driver core informs the DMA layer if a driver grabs a device
2665 * we don't need to preallocate the protection domains anymore.
2666 * For now we have to.
2667 */
2668 static void prealloc_protection_domains(void)
2669 {
2670 struct iommu_dev_data *dev_data;
2671 struct dma_ops_domain *dma_dom;
2672 struct pci_dev *dev = NULL;
2673 u16 devid;
2674
2675 for_each_pci_dev(dev) {
2676
2677 /* Do we handle this device? */
2678 if (!check_device(&dev->dev))
2679 continue;
2680
2681 dev_data = get_dev_data(&dev->dev);
2682 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
2683 /* Make sure passthrough domain is allocated */
2684 alloc_passthrough_domain();
2685 dev_data->passthrough = true;
2686 attach_device(&dev->dev, pt_domain);
2687 pr_info("AMD-Vi: Using passthough domain for device %s\n",
2688 dev_name(&dev->dev));
2689 }
2690
2691 /* Is there already any domain for it? */
2692 if (domain_for_device(&dev->dev))
2693 continue;
2694
2695 devid = get_device_id(&dev->dev);
2696
2697 dma_dom = dma_ops_domain_alloc();
2698 if (!dma_dom)
2699 continue;
2700 init_unity_mappings_for_device(dma_dom, devid);
2701 dma_dom->target_dev = devid;
2702
2703 attach_device(&dev->dev, &dma_dom->domain);
2704
2705 list_add_tail(&dma_dom->list, &iommu_pd_list);
2706 }
2707 }
2708
2709 static struct dma_map_ops amd_iommu_dma_ops = {
2710 .alloc_coherent = alloc_coherent,
2711 .free_coherent = free_coherent,
2712 .map_page = map_page,
2713 .unmap_page = unmap_page,
2714 .map_sg = map_sg,
2715 .unmap_sg = unmap_sg,
2716 .dma_supported = amd_iommu_dma_supported,
2717 };
2718
2719 static unsigned device_dma_ops_init(void)
2720 {
2721 struct iommu_dev_data *dev_data;
2722 struct pci_dev *pdev = NULL;
2723 unsigned unhandled = 0;
2724
2725 for_each_pci_dev(pdev) {
2726 if (!check_device(&pdev->dev)) {
2727 unhandled += 1;
2728 continue;
2729 }
2730
2731 dev_data = get_dev_data(&pdev->dev);
2732
2733 if (!dev_data->passthrough)
2734 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
2735 else
2736 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
2737 }
2738
2739 return unhandled;
2740 }
2741
2742 /*
2743 * The function which clues the AMD IOMMU driver into dma_ops.
2744 */
2745
2746 void __init amd_iommu_init_api(void)
2747 {
2748 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2749 }
2750
2751 int __init amd_iommu_init_dma_ops(void)
2752 {
2753 struct amd_iommu *iommu;
2754 int ret, unhandled;
2755
2756 /*
2757 * first allocate a default protection domain for every IOMMU we
2758 * found in the system. Devices not assigned to any other
2759 * protection domain will be assigned to the default one.
2760 */
2761 for_each_iommu(iommu) {
2762 iommu->default_dom = dma_ops_domain_alloc();
2763 if (iommu->default_dom == NULL)
2764 return -ENOMEM;
2765 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2766 ret = iommu_init_unity_mappings(iommu);
2767 if (ret)
2768 goto free_domains;
2769 }
2770
2771 /*
2772 * Pre-allocate the protection domains for each device.
2773 */
2774 prealloc_protection_domains();
2775
2776 iommu_detected = 1;
2777 swiotlb = 0;
2778
2779 /* Make the driver finally visible to the drivers */
2780 unhandled = device_dma_ops_init();
2781 if (unhandled && max_pfn > MAX_DMA32_PFN) {
2782 /* There are unhandled devices - initialize swiotlb for them */
2783 swiotlb = 1;
2784 }
2785
2786 amd_iommu_stats_init();
2787
2788 return 0;
2789
2790 free_domains:
2791
2792 for_each_iommu(iommu) {
2793 if (iommu->default_dom)
2794 dma_ops_domain_free(iommu->default_dom);
2795 }
2796
2797 return ret;
2798 }
2799
2800 /*****************************************************************************
2801 *
2802 * The following functions belong to the exported interface of AMD IOMMU
2803 *
2804 * This interface allows access to lower level functions of the IOMMU
2805 * like protection domain handling and assignement of devices to domains
2806 * which is not possible with the dma_ops interface.
2807 *
2808 *****************************************************************************/
2809
2810 static void cleanup_domain(struct protection_domain *domain)
2811 {
2812 struct iommu_dev_data *dev_data, *next;
2813 unsigned long flags;
2814
2815 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2816
2817 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2818 __detach_device(dev_data);
2819 atomic_set(&dev_data->bind, 0);
2820 }
2821
2822 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2823 }
2824
2825 static void protection_domain_free(struct protection_domain *domain)
2826 {
2827 if (!domain)
2828 return;
2829
2830 del_domain_from_list(domain);
2831
2832 if (domain->id)
2833 domain_id_free(domain->id);
2834
2835 kfree(domain);
2836 }
2837
2838 static struct protection_domain *protection_domain_alloc(void)
2839 {
2840 struct protection_domain *domain;
2841
2842 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2843 if (!domain)
2844 return NULL;
2845
2846 spin_lock_init(&domain->lock);
2847 mutex_init(&domain->api_lock);
2848 domain->id = domain_id_alloc();
2849 if (!domain->id)
2850 goto out_err;
2851 INIT_LIST_HEAD(&domain->dev_list);
2852
2853 add_domain_to_list(domain);
2854
2855 return domain;
2856
2857 out_err:
2858 kfree(domain);
2859
2860 return NULL;
2861 }
2862
2863 static int __init alloc_passthrough_domain(void)
2864 {
2865 if (pt_domain != NULL)
2866 return 0;
2867
2868 /* allocate passthrough domain */
2869 pt_domain = protection_domain_alloc();
2870 if (!pt_domain)
2871 return -ENOMEM;
2872
2873 pt_domain->mode = PAGE_MODE_NONE;
2874
2875 return 0;
2876 }
2877 static int amd_iommu_domain_init(struct iommu_domain *dom)
2878 {
2879 struct protection_domain *domain;
2880
2881 domain = protection_domain_alloc();
2882 if (!domain)
2883 goto out_free;
2884
2885 domain->mode = PAGE_MODE_3_LEVEL;
2886 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2887 if (!domain->pt_root)
2888 goto out_free;
2889
2890 dom->priv = domain;
2891
2892 return 0;
2893
2894 out_free:
2895 protection_domain_free(domain);
2896
2897 return -ENOMEM;
2898 }
2899
2900 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2901 {
2902 struct protection_domain *domain = dom->priv;
2903
2904 if (!domain)
2905 return;
2906
2907 if (domain->dev_cnt > 0)
2908 cleanup_domain(domain);
2909
2910 BUG_ON(domain->dev_cnt != 0);
2911
2912 if (domain->mode != PAGE_MODE_NONE)
2913 free_pagetable(domain);
2914
2915 if (domain->flags & PD_IOMMUV2_MASK)
2916 free_gcr3_table(domain);
2917
2918 protection_domain_free(domain);
2919
2920 dom->priv = NULL;
2921 }
2922
2923 static void amd_iommu_detach_device(struct iommu_domain *dom,
2924 struct device *dev)
2925 {
2926 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2927 struct amd_iommu *iommu;
2928 u16 devid;
2929
2930 if (!check_device(dev))
2931 return;
2932
2933 devid = get_device_id(dev);
2934
2935 if (dev_data->domain != NULL)
2936 detach_device(dev);
2937
2938 iommu = amd_iommu_rlookup_table[devid];
2939 if (!iommu)
2940 return;
2941
2942 iommu_completion_wait(iommu);
2943 }
2944
2945 static int amd_iommu_attach_device(struct iommu_domain *dom,
2946 struct device *dev)
2947 {
2948 struct protection_domain *domain = dom->priv;
2949 struct iommu_dev_data *dev_data;
2950 struct amd_iommu *iommu;
2951 int ret;
2952
2953 if (!check_device(dev))
2954 return -EINVAL;
2955
2956 dev_data = dev->archdata.iommu;
2957
2958 iommu = amd_iommu_rlookup_table[dev_data->devid];
2959 if (!iommu)
2960 return -EINVAL;
2961
2962 if (dev_data->domain)
2963 detach_device(dev);
2964
2965 ret = attach_device(dev, domain);
2966
2967 iommu_completion_wait(iommu);
2968
2969 return ret;
2970 }
2971
2972 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2973 phys_addr_t paddr, int gfp_order, int iommu_prot)
2974 {
2975 unsigned long page_size = 0x1000UL << gfp_order;
2976 struct protection_domain *domain = dom->priv;
2977 int prot = 0;
2978 int ret;
2979
2980 if (domain->mode == PAGE_MODE_NONE)
2981 return -EINVAL;
2982
2983 if (iommu_prot & IOMMU_READ)
2984 prot |= IOMMU_PROT_IR;
2985 if (iommu_prot & IOMMU_WRITE)
2986 prot |= IOMMU_PROT_IW;
2987
2988 mutex_lock(&domain->api_lock);
2989 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
2990 mutex_unlock(&domain->api_lock);
2991
2992 return ret;
2993 }
2994
2995 static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2996 int gfp_order)
2997 {
2998 struct protection_domain *domain = dom->priv;
2999 unsigned long page_size, unmap_size;
3000
3001 if (domain->mode == PAGE_MODE_NONE)
3002 return -EINVAL;
3003
3004 page_size = 0x1000UL << gfp_order;
3005
3006 mutex_lock(&domain->api_lock);
3007 unmap_size = iommu_unmap_page(domain, iova, page_size);
3008 mutex_unlock(&domain->api_lock);
3009
3010 domain_flush_tlb_pde(domain);
3011
3012 return get_order(unmap_size);
3013 }
3014
3015 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3016 unsigned long iova)
3017 {
3018 struct protection_domain *domain = dom->priv;
3019 unsigned long offset_mask;
3020 phys_addr_t paddr;
3021 u64 *pte, __pte;
3022
3023 if (domain->mode == PAGE_MODE_NONE)
3024 return iova;
3025
3026 pte = fetch_pte(domain, iova);
3027
3028 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3029 return 0;
3030
3031 if (PM_PTE_LEVEL(*pte) == 0)
3032 offset_mask = PAGE_SIZE - 1;
3033 else
3034 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3035
3036 __pte = *pte & PM_ADDR_MASK;
3037 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
3038
3039 return paddr;
3040 }
3041
3042 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3043 unsigned long cap)
3044 {
3045 switch (cap) {
3046 case IOMMU_CAP_CACHE_COHERENCY:
3047 return 1;
3048 }
3049
3050 return 0;
3051 }
3052
3053 static struct iommu_ops amd_iommu_ops = {
3054 .domain_init = amd_iommu_domain_init,
3055 .domain_destroy = amd_iommu_domain_destroy,
3056 .attach_dev = amd_iommu_attach_device,
3057 .detach_dev = amd_iommu_detach_device,
3058 .map = amd_iommu_map,
3059 .unmap = amd_iommu_unmap,
3060 .iova_to_phys = amd_iommu_iova_to_phys,
3061 .domain_has_cap = amd_iommu_domain_has_cap,
3062 };
3063
3064 /*****************************************************************************
3065 *
3066 * The next functions do a basic initialization of IOMMU for pass through
3067 * mode
3068 *
3069 * In passthrough mode the IOMMU is initialized and enabled but not used for
3070 * DMA-API translation.
3071 *
3072 *****************************************************************************/
3073
3074 int __init amd_iommu_init_passthrough(void)
3075 {
3076 struct iommu_dev_data *dev_data;
3077 struct pci_dev *dev = NULL;
3078 struct amd_iommu *iommu;
3079 u16 devid;
3080 int ret;
3081
3082 ret = alloc_passthrough_domain();
3083 if (ret)
3084 return ret;
3085
3086 for_each_pci_dev(dev) {
3087 if (!check_device(&dev->dev))
3088 continue;
3089
3090 dev_data = get_dev_data(&dev->dev);
3091 dev_data->passthrough = true;
3092
3093 devid = get_device_id(&dev->dev);
3094
3095 iommu = amd_iommu_rlookup_table[devid];
3096 if (!iommu)
3097 continue;
3098
3099 attach_device(&dev->dev, pt_domain);
3100 }
3101
3102 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3103
3104 return 0;
3105 }
3106
3107 /* IOMMUv2 specific functions */
3108 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3109 {
3110 return atomic_notifier_chain_register(&ppr_notifier, nb);
3111 }
3112 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3113
3114 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3115 {
3116 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3117 }
3118 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3119
3120 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3121 {
3122 struct protection_domain *domain = dom->priv;
3123 unsigned long flags;
3124
3125 spin_lock_irqsave(&domain->lock, flags);
3126
3127 /* Update data structure */
3128 domain->mode = PAGE_MODE_NONE;
3129 domain->updated = true;
3130
3131 /* Make changes visible to IOMMUs */
3132 update_domain(domain);
3133
3134 /* Page-table is not visible to IOMMU anymore, so free it */
3135 free_pagetable(domain);
3136
3137 spin_unlock_irqrestore(&domain->lock, flags);
3138 }
3139 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3140
3141 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3142 {
3143 struct protection_domain *domain = dom->priv;
3144 unsigned long flags;
3145 int levels, ret;
3146
3147 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3148 return -EINVAL;
3149
3150 /* Number of GCR3 table levels required */
3151 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3152 levels += 1;
3153
3154 if (levels > amd_iommu_max_glx_val)
3155 return -EINVAL;
3156
3157 spin_lock_irqsave(&domain->lock, flags);
3158
3159 /*
3160 * Save us all sanity checks whether devices already in the
3161 * domain support IOMMUv2. Just force that the domain has no
3162 * devices attached when it is switched into IOMMUv2 mode.
3163 */
3164 ret = -EBUSY;
3165 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3166 goto out;
3167
3168 ret = -ENOMEM;
3169 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3170 if (domain->gcr3_tbl == NULL)
3171 goto out;
3172
3173 domain->glx = levels;
3174 domain->flags |= PD_IOMMUV2_MASK;
3175 domain->updated = true;
3176
3177 update_domain(domain);
3178
3179 ret = 0;
3180
3181 out:
3182 spin_unlock_irqrestore(&domain->lock, flags);
3183
3184 return ret;
3185 }
3186 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3187
3188 static int __flush_pasid(struct protection_domain *domain, int pasid,
3189 u64 address, bool size)
3190 {
3191 struct iommu_dev_data *dev_data;
3192 struct iommu_cmd cmd;
3193 int i, ret;
3194
3195 if (!(domain->flags & PD_IOMMUV2_MASK))
3196 return -EINVAL;
3197
3198 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3199
3200 /*
3201 * IOMMU TLB needs to be flushed before Device TLB to
3202 * prevent device TLB refill from IOMMU TLB
3203 */
3204 for (i = 0; i < amd_iommus_present; ++i) {
3205 if (domain->dev_iommu[i] == 0)
3206 continue;
3207
3208 ret = iommu_queue_command(amd_iommus[i], &cmd);
3209 if (ret != 0)
3210 goto out;
3211 }
3212
3213 /* Wait until IOMMU TLB flushes are complete */
3214 domain_flush_complete(domain);
3215
3216 /* Now flush device TLBs */
3217 list_for_each_entry(dev_data, &domain->dev_list, list) {
3218 struct amd_iommu *iommu;
3219 int qdep;
3220
3221 BUG_ON(!dev_data->ats.enabled);
3222
3223 qdep = dev_data->ats.qdep;
3224 iommu = amd_iommu_rlookup_table[dev_data->devid];
3225
3226 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3227 qdep, address, size);
3228
3229 ret = iommu_queue_command(iommu, &cmd);
3230 if (ret != 0)
3231 goto out;
3232 }
3233
3234 /* Wait until all device TLBs are flushed */
3235 domain_flush_complete(domain);
3236
3237 ret = 0;
3238
3239 out:
3240
3241 return ret;
3242 }
3243
3244 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3245 u64 address)
3246 {
3247 return __flush_pasid(domain, pasid, address, false);
3248 }
3249
3250 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3251 u64 address)
3252 {
3253 struct protection_domain *domain = dom->priv;
3254 unsigned long flags;
3255 int ret;
3256
3257 spin_lock_irqsave(&domain->lock, flags);
3258 ret = __amd_iommu_flush_page(domain, pasid, address);
3259 spin_unlock_irqrestore(&domain->lock, flags);
3260
3261 return ret;
3262 }
3263 EXPORT_SYMBOL(amd_iommu_flush_page);
3264
3265 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3266 {
3267 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3268 true);
3269 }
3270
3271 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3272 {
3273 struct protection_domain *domain = dom->priv;
3274 unsigned long flags;
3275 int ret;
3276
3277 spin_lock_irqsave(&domain->lock, flags);
3278 ret = __amd_iommu_flush_tlb(domain, pasid);
3279 spin_unlock_irqrestore(&domain->lock, flags);
3280
3281 return ret;
3282 }
3283 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3284
Linux kernel - Deliverables
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