2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/pci-ats.h>
25 #include <linux/bitmap.h>
26 #include <linux/slab.h>
27 #include <linux/debugfs.h>
28 #include <linux/scatterlist.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/iommu-helper.h>
31 #include <linux/iommu.h>
32 #include <linux/delay.h>
33 #include <linux/amd-iommu.h>
34 #include <linux/notifier.h>
35 #include <linux/export.h>
36 #include <linux/irq.h>
37 #include <linux/msi.h>
38 #include <linux/dma-contiguous.h>
39 #include <linux/irqdomain.h>
40 #include <linux/percpu.h>
41 #include <asm/irq_remapping.h>
42 #include <asm/io_apic.h>
44 #include <asm/hw_irq.h>
45 #include <asm/msidef.h>
46 #include <asm/proto.h>
47 #include <asm/iommu.h>
51 #include "amd_iommu_proto.h"
52 #include "amd_iommu_types.h"
53 #include "irq_remapping.h"
55 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
57 #define LOOP_TIMEOUT 100000
60 * This bitmap is used to advertise the page sizes our hardware support
61 * to the IOMMU core, which will then use this information to split
62 * physically contiguous memory regions it is mapping into page sizes
65 * 512GB Pages are not supported due to a hardware bug
67 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
69 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
71 /* List of all available dev_data structures */
72 static LIST_HEAD(dev_data_list
);
73 static DEFINE_SPINLOCK(dev_data_list_lock
);
75 LIST_HEAD(ioapic_map
);
77 LIST_HEAD(acpihid_map
);
80 * Domain for untranslated devices - only allocated
81 * if iommu=pt passed on kernel cmd line.
83 static const struct iommu_ops amd_iommu_ops
;
85 static ATOMIC_NOTIFIER_HEAD(ppr_notifier
);
86 int amd_iommu_max_glx_val
= -1;
88 static struct dma_map_ops amd_iommu_dma_ops
;
91 * This struct contains device specific data for the IOMMU
93 struct iommu_dev_data
{
94 struct list_head list
; /* For domain->dev_list */
95 struct list_head dev_data_list
; /* For global dev_data_list */
96 struct protection_domain
*domain
; /* Domain the device is bound to */
97 u16 devid
; /* PCI Device ID */
98 u16 alias
; /* Alias Device ID */
99 bool iommu_v2
; /* Device can make use of IOMMUv2 */
100 bool passthrough
; /* Device is identity mapped */
104 } ats
; /* ATS state */
105 bool pri_tlp
; /* PASID TLB required for
107 u32 errata
; /* Bitmap for errata to apply */
111 * general struct to manage commands send to an IOMMU
117 struct kmem_cache
*amd_iommu_irq_cache
;
119 static void update_domain(struct protection_domain
*domain
);
120 static int protection_domain_init(struct protection_domain
*domain
);
121 static void detach_device(struct device
*dev
);
124 * For dynamic growth the aperture size is split into ranges of 128MB of
125 * DMA address space each. This struct represents one such range.
127 struct aperture_range
{
129 spinlock_t bitmap_lock
;
131 /* address allocation bitmap */
132 unsigned long *bitmap
;
133 unsigned long offset
;
134 unsigned long next_bit
;
137 * Array of PTE pages for the aperture. In this array we save all the
138 * leaf pages of the domain page table used for the aperture. This way
139 * we don't need to walk the page table to find a specific PTE. We can
140 * just calculate its address in constant time.
146 * Data container for a dma_ops specific protection domain
148 struct dma_ops_domain
{
149 /* generic protection domain information */
150 struct protection_domain domain
;
152 /* size of the aperture for the mappings */
153 unsigned long aperture_size
;
155 /* aperture index we start searching for free addresses */
156 u32 __percpu
*next_index
;
158 /* address space relevant data */
159 struct aperture_range
*aperture
[APERTURE_MAX_RANGES
];
162 /****************************************************************************
166 ****************************************************************************/
168 static inline int match_hid_uid(struct device
*dev
,
169 struct acpihid_map_entry
*entry
)
171 const char *hid
, *uid
;
173 hid
= acpi_device_hid(ACPI_COMPANION(dev
));
174 uid
= acpi_device_uid(ACPI_COMPANION(dev
));
180 return strcmp(hid
, entry
->hid
);
183 return strcmp(hid
, entry
->hid
);
185 return (strcmp(hid
, entry
->hid
) || strcmp(uid
, entry
->uid
));
188 static inline u16
get_pci_device_id(struct device
*dev
)
190 struct pci_dev
*pdev
= to_pci_dev(dev
);
192 return PCI_DEVID(pdev
->bus
->number
, pdev
->devfn
);
195 static inline int get_acpihid_device_id(struct device
*dev
,
196 struct acpihid_map_entry
**entry
)
198 struct acpihid_map_entry
*p
;
200 list_for_each_entry(p
, &acpihid_map
, list
) {
201 if (!match_hid_uid(dev
, p
)) {
210 static inline int get_device_id(struct device
*dev
)
215 devid
= get_pci_device_id(dev
);
217 devid
= get_acpihid_device_id(dev
, NULL
);
222 static struct protection_domain
*to_pdomain(struct iommu_domain
*dom
)
224 return container_of(dom
, struct protection_domain
, domain
);
227 static struct iommu_dev_data
*alloc_dev_data(u16 devid
)
229 struct iommu_dev_data
*dev_data
;
232 dev_data
= kzalloc(sizeof(*dev_data
), GFP_KERNEL
);
236 dev_data
->devid
= devid
;
238 spin_lock_irqsave(&dev_data_list_lock
, flags
);
239 list_add_tail(&dev_data
->dev_data_list
, &dev_data_list
);
240 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
245 static struct iommu_dev_data
*search_dev_data(u16 devid
)
247 struct iommu_dev_data
*dev_data
;
250 spin_lock_irqsave(&dev_data_list_lock
, flags
);
251 list_for_each_entry(dev_data
, &dev_data_list
, dev_data_list
) {
252 if (dev_data
->devid
== devid
)
259 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
264 static int __last_alias(struct pci_dev
*pdev
, u16 alias
, void *data
)
266 *(u16
*)data
= alias
;
270 static u16
get_alias(struct device
*dev
)
272 struct pci_dev
*pdev
= to_pci_dev(dev
);
273 u16 devid
, ivrs_alias
, pci_alias
;
275 /* The callers make sure that get_device_id() does not fail here */
276 devid
= get_device_id(dev
);
277 ivrs_alias
= amd_iommu_alias_table
[devid
];
278 pci_for_each_dma_alias(pdev
, __last_alias
, &pci_alias
);
280 if (ivrs_alias
== pci_alias
)
286 * The IVRS is fairly reliable in telling us about aliases, but it
287 * can't know about every screwy device. If we don't have an IVRS
288 * reported alias, use the PCI reported alias. In that case we may
289 * still need to initialize the rlookup and dev_table entries if the
290 * alias is to a non-existent device.
292 if (ivrs_alias
== devid
) {
293 if (!amd_iommu_rlookup_table
[pci_alias
]) {
294 amd_iommu_rlookup_table
[pci_alias
] =
295 amd_iommu_rlookup_table
[devid
];
296 memcpy(amd_iommu_dev_table
[pci_alias
].data
,
297 amd_iommu_dev_table
[devid
].data
,
298 sizeof(amd_iommu_dev_table
[pci_alias
].data
));
304 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
305 "for device %s[%04x:%04x], kernel reported alias "
306 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias
), PCI_SLOT(ivrs_alias
),
307 PCI_FUNC(ivrs_alias
), dev_name(dev
), pdev
->vendor
, pdev
->device
,
308 PCI_BUS_NUM(pci_alias
), PCI_SLOT(pci_alias
),
309 PCI_FUNC(pci_alias
));
312 * If we don't have a PCI DMA alias and the IVRS alias is on the same
313 * bus, then the IVRS table may know about a quirk that we don't.
315 if (pci_alias
== devid
&&
316 PCI_BUS_NUM(ivrs_alias
) == pdev
->bus
->number
) {
317 pci_add_dma_alias(pdev
, ivrs_alias
& 0xff);
318 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
319 PCI_SLOT(ivrs_alias
), PCI_FUNC(ivrs_alias
),
326 static struct iommu_dev_data
*find_dev_data(u16 devid
)
328 struct iommu_dev_data
*dev_data
;
330 dev_data
= search_dev_data(devid
);
332 if (dev_data
== NULL
)
333 dev_data
= alloc_dev_data(devid
);
338 static struct iommu_dev_data
*get_dev_data(struct device
*dev
)
340 return dev
->archdata
.iommu
;
344 * Find or create an IOMMU group for a acpihid device.
346 static struct iommu_group
*acpihid_device_group(struct device
*dev
)
348 struct acpihid_map_entry
*p
, *entry
= NULL
;
351 devid
= get_acpihid_device_id(dev
, &entry
);
353 return ERR_PTR(devid
);
355 list_for_each_entry(p
, &acpihid_map
, list
) {
356 if ((devid
== p
->devid
) && p
->group
)
357 entry
->group
= p
->group
;
361 entry
->group
= generic_device_group(dev
);
366 static bool pci_iommuv2_capable(struct pci_dev
*pdev
)
368 static const int caps
[] = {
371 PCI_EXT_CAP_ID_PASID
,
375 for (i
= 0; i
< 3; ++i
) {
376 pos
= pci_find_ext_capability(pdev
, caps
[i
]);
384 static bool pdev_pri_erratum(struct pci_dev
*pdev
, u32 erratum
)
386 struct iommu_dev_data
*dev_data
;
388 dev_data
= get_dev_data(&pdev
->dev
);
390 return dev_data
->errata
& (1 << erratum
) ? true : false;
394 * This function actually applies the mapping to the page table of the
397 static void alloc_unity_mapping(struct dma_ops_domain
*dma_dom
,
398 struct unity_map_entry
*e
)
402 for (addr
= e
->address_start
; addr
< e
->address_end
;
404 if (addr
< dma_dom
->aperture_size
)
405 __set_bit(addr
>> PAGE_SHIFT
,
406 dma_dom
->aperture
[0]->bitmap
);
411 * Inits the unity mappings required for a specific device
413 static void init_unity_mappings_for_device(struct device
*dev
,
414 struct dma_ops_domain
*dma_dom
)
416 struct unity_map_entry
*e
;
419 devid
= get_device_id(dev
);
423 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
424 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
426 alloc_unity_mapping(dma_dom
, e
);
431 * This function checks if the driver got a valid device from the caller to
432 * avoid dereferencing invalid pointers.
434 static bool check_device(struct device
*dev
)
438 if (!dev
|| !dev
->dma_mask
)
441 devid
= get_device_id(dev
);
445 /* Out of our scope? */
446 if (devid
> amd_iommu_last_bdf
)
449 if (amd_iommu_rlookup_table
[devid
] == NULL
)
455 static void init_iommu_group(struct device
*dev
)
457 struct dma_ops_domain
*dma_domain
;
458 struct iommu_domain
*domain
;
459 struct iommu_group
*group
;
461 group
= iommu_group_get_for_dev(dev
);
465 domain
= iommu_group_default_domain(group
);
469 dma_domain
= to_pdomain(domain
)->priv
;
471 init_unity_mappings_for_device(dev
, dma_domain
);
473 iommu_group_put(group
);
476 static int iommu_init_device(struct device
*dev
)
478 struct iommu_dev_data
*dev_data
;
481 if (dev
->archdata
.iommu
)
484 devid
= get_device_id(dev
);
488 dev_data
= find_dev_data(devid
);
492 dev_data
->alias
= get_alias(dev
);
494 if (dev_is_pci(dev
) && pci_iommuv2_capable(to_pci_dev(dev
))) {
495 struct amd_iommu
*iommu
;
497 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
498 dev_data
->iommu_v2
= iommu
->is_iommu_v2
;
501 dev
->archdata
.iommu
= dev_data
;
503 iommu_device_link(amd_iommu_rlookup_table
[dev_data
->devid
]->iommu_dev
,
509 static void iommu_ignore_device(struct device
*dev
)
514 devid
= get_device_id(dev
);
518 alias
= get_alias(dev
);
520 memset(&amd_iommu_dev_table
[devid
], 0, sizeof(struct dev_table_entry
));
521 memset(&amd_iommu_dev_table
[alias
], 0, sizeof(struct dev_table_entry
));
523 amd_iommu_rlookup_table
[devid
] = NULL
;
524 amd_iommu_rlookup_table
[alias
] = NULL
;
527 static void iommu_uninit_device(struct device
*dev
)
530 struct iommu_dev_data
*dev_data
;
532 devid
= get_device_id(dev
);
536 dev_data
= search_dev_data(devid
);
540 if (dev_data
->domain
)
543 iommu_device_unlink(amd_iommu_rlookup_table
[dev_data
->devid
]->iommu_dev
,
546 iommu_group_remove_device(dev
);
549 dev
->archdata
.dma_ops
= NULL
;
552 * We keep dev_data around for unplugged devices and reuse it when the
553 * device is re-plugged - not doing so would introduce a ton of races.
557 /****************************************************************************
559 * Interrupt handling functions
561 ****************************************************************************/
563 static void dump_dte_entry(u16 devid
)
567 for (i
= 0; i
< 4; ++i
)
568 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i
,
569 amd_iommu_dev_table
[devid
].data
[i
]);
572 static void dump_command(unsigned long phys_addr
)
574 struct iommu_cmd
*cmd
= phys_to_virt(phys_addr
);
577 for (i
= 0; i
< 4; ++i
)
578 pr_err("AMD-Vi: CMD[%d]: %08x\n", i
, cmd
->data
[i
]);
581 static void iommu_print_event(struct amd_iommu
*iommu
, void *__evt
)
583 int type
, devid
, domid
, flags
;
584 volatile u32
*event
= __evt
;
589 type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
590 devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
591 domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
592 flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
593 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
596 /* Did we hit the erratum? */
597 if (++count
== LOOP_TIMEOUT
) {
598 pr_err("AMD-Vi: No event written to event log\n");
605 printk(KERN_ERR
"AMD-Vi: Event logged [");
608 case EVENT_TYPE_ILL_DEV
:
609 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
610 "address=0x%016llx flags=0x%04x]\n",
611 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
613 dump_dte_entry(devid
);
615 case EVENT_TYPE_IO_FAULT
:
616 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
617 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
618 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
619 domid
, address
, flags
);
621 case EVENT_TYPE_DEV_TAB_ERR
:
622 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
623 "address=0x%016llx flags=0x%04x]\n",
624 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
627 case EVENT_TYPE_PAGE_TAB_ERR
:
628 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
629 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
630 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
631 domid
, address
, flags
);
633 case EVENT_TYPE_ILL_CMD
:
634 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
635 dump_command(address
);
637 case EVENT_TYPE_CMD_HARD_ERR
:
638 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
639 "flags=0x%04x]\n", address
, flags
);
641 case EVENT_TYPE_IOTLB_INV_TO
:
642 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
643 "address=0x%016llx]\n",
644 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
647 case EVENT_TYPE_INV_DEV_REQ
:
648 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
649 "address=0x%016llx flags=0x%04x]\n",
650 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
654 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
657 memset(__evt
, 0, 4 * sizeof(u32
));
660 static void iommu_poll_events(struct amd_iommu
*iommu
)
664 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
665 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
667 while (head
!= tail
) {
668 iommu_print_event(iommu
, iommu
->evt_buf
+ head
);
669 head
= (head
+ EVENT_ENTRY_SIZE
) % EVT_BUFFER_SIZE
;
672 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
675 static void iommu_handle_ppr_entry(struct amd_iommu
*iommu
, u64
*raw
)
677 struct amd_iommu_fault fault
;
679 if (PPR_REQ_TYPE(raw
[0]) != PPR_REQ_FAULT
) {
680 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
684 fault
.address
= raw
[1];
685 fault
.pasid
= PPR_PASID(raw
[0]);
686 fault
.device_id
= PPR_DEVID(raw
[0]);
687 fault
.tag
= PPR_TAG(raw
[0]);
688 fault
.flags
= PPR_FLAGS(raw
[0]);
690 atomic_notifier_call_chain(&ppr_notifier
, 0, &fault
);
693 static void iommu_poll_ppr_log(struct amd_iommu
*iommu
)
697 if (iommu
->ppr_log
== NULL
)
700 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
701 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
703 while (head
!= tail
) {
708 raw
= (u64
*)(iommu
->ppr_log
+ head
);
711 * Hardware bug: Interrupt may arrive before the entry is
712 * written to memory. If this happens we need to wait for the
715 for (i
= 0; i
< LOOP_TIMEOUT
; ++i
) {
716 if (PPR_REQ_TYPE(raw
[0]) != 0)
721 /* Avoid memcpy function-call overhead */
726 * To detect the hardware bug we need to clear the entry
729 raw
[0] = raw
[1] = 0UL;
731 /* Update head pointer of hardware ring-buffer */
732 head
= (head
+ PPR_ENTRY_SIZE
) % PPR_LOG_SIZE
;
733 writel(head
, iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
735 /* Handle PPR entry */
736 iommu_handle_ppr_entry(iommu
, entry
);
738 /* Refresh ring-buffer information */
739 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
740 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
744 irqreturn_t
amd_iommu_int_thread(int irq
, void *data
)
746 struct amd_iommu
*iommu
= (struct amd_iommu
*) data
;
747 u32 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
749 while (status
& (MMIO_STATUS_EVT_INT_MASK
| MMIO_STATUS_PPR_INT_MASK
)) {
750 /* Enable EVT and PPR interrupts again */
751 writel((MMIO_STATUS_EVT_INT_MASK
| MMIO_STATUS_PPR_INT_MASK
),
752 iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
754 if (status
& MMIO_STATUS_EVT_INT_MASK
) {
755 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
756 iommu_poll_events(iommu
);
759 if (status
& MMIO_STATUS_PPR_INT_MASK
) {
760 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
761 iommu_poll_ppr_log(iommu
);
765 * Hardware bug: ERBT1312
766 * When re-enabling interrupt (by writing 1
767 * to clear the bit), the hardware might also try to set
768 * the interrupt bit in the event status register.
769 * In this scenario, the bit will be set, and disable
770 * subsequent interrupts.
772 * Workaround: The IOMMU driver should read back the
773 * status register and check if the interrupt bits are cleared.
774 * If not, driver will need to go through the interrupt handler
775 * again and re-clear the bits
777 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
782 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
784 return IRQ_WAKE_THREAD
;
787 /****************************************************************************
789 * IOMMU command queuing functions
791 ****************************************************************************/
793 static int wait_on_sem(volatile u64
*sem
)
797 while (*sem
== 0 && i
< LOOP_TIMEOUT
) {
802 if (i
== LOOP_TIMEOUT
) {
803 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
810 static void copy_cmd_to_buffer(struct amd_iommu
*iommu
,
811 struct iommu_cmd
*cmd
,
816 target
= iommu
->cmd_buf
+ tail
;
817 tail
= (tail
+ sizeof(*cmd
)) % CMD_BUFFER_SIZE
;
819 /* Copy command to buffer */
820 memcpy(target
, cmd
, sizeof(*cmd
));
822 /* Tell the IOMMU about it */
823 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
826 static void build_completion_wait(struct iommu_cmd
*cmd
, u64 address
)
828 WARN_ON(address
& 0x7ULL
);
830 memset(cmd
, 0, sizeof(*cmd
));
831 cmd
->data
[0] = lower_32_bits(__pa(address
)) | CMD_COMPL_WAIT_STORE_MASK
;
832 cmd
->data
[1] = upper_32_bits(__pa(address
));
834 CMD_SET_TYPE(cmd
, CMD_COMPL_WAIT
);
837 static void build_inv_dte(struct iommu_cmd
*cmd
, u16 devid
)
839 memset(cmd
, 0, sizeof(*cmd
));
840 cmd
->data
[0] = devid
;
841 CMD_SET_TYPE(cmd
, CMD_INV_DEV_ENTRY
);
844 static void build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
845 size_t size
, u16 domid
, int pde
)
850 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
855 * If we have to flush more than one page, flush all
856 * TLB entries for this domain
858 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
862 address
&= PAGE_MASK
;
864 memset(cmd
, 0, sizeof(*cmd
));
865 cmd
->data
[1] |= domid
;
866 cmd
->data
[2] = lower_32_bits(address
);
867 cmd
->data
[3] = upper_32_bits(address
);
868 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
869 if (s
) /* size bit - we flush more than one 4kb page */
870 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
871 if (pde
) /* PDE bit - we want to flush everything, not only the PTEs */
872 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
875 static void build_inv_iotlb_pages(struct iommu_cmd
*cmd
, u16 devid
, int qdep
,
876 u64 address
, size_t size
)
881 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
886 * If we have to flush more than one page, flush all
887 * TLB entries for this domain
889 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
893 address
&= PAGE_MASK
;
895 memset(cmd
, 0, sizeof(*cmd
));
896 cmd
->data
[0] = devid
;
897 cmd
->data
[0] |= (qdep
& 0xff) << 24;
898 cmd
->data
[1] = devid
;
899 cmd
->data
[2] = lower_32_bits(address
);
900 cmd
->data
[3] = upper_32_bits(address
);
901 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
903 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
906 static void build_inv_iommu_pasid(struct iommu_cmd
*cmd
, u16 domid
, int pasid
,
907 u64 address
, bool size
)
909 memset(cmd
, 0, sizeof(*cmd
));
911 address
&= ~(0xfffULL
);
913 cmd
->data
[0] = pasid
;
914 cmd
->data
[1] = domid
;
915 cmd
->data
[2] = lower_32_bits(address
);
916 cmd
->data
[3] = upper_32_bits(address
);
917 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
918 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
920 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
921 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
924 static void build_inv_iotlb_pasid(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
925 int qdep
, u64 address
, bool size
)
927 memset(cmd
, 0, sizeof(*cmd
));
929 address
&= ~(0xfffULL
);
931 cmd
->data
[0] = devid
;
932 cmd
->data
[0] |= ((pasid
>> 8) & 0xff) << 16;
933 cmd
->data
[0] |= (qdep
& 0xff) << 24;
934 cmd
->data
[1] = devid
;
935 cmd
->data
[1] |= (pasid
& 0xff) << 16;
936 cmd
->data
[2] = lower_32_bits(address
);
937 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
938 cmd
->data
[3] = upper_32_bits(address
);
940 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
941 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
944 static void build_complete_ppr(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
945 int status
, int tag
, bool gn
)
947 memset(cmd
, 0, sizeof(*cmd
));
949 cmd
->data
[0] = devid
;
951 cmd
->data
[1] = pasid
;
952 cmd
->data
[2] = CMD_INV_IOMMU_PAGES_GN_MASK
;
954 cmd
->data
[3] = tag
& 0x1ff;
955 cmd
->data
[3] |= (status
& PPR_STATUS_MASK
) << PPR_STATUS_SHIFT
;
957 CMD_SET_TYPE(cmd
, CMD_COMPLETE_PPR
);
960 static void build_inv_all(struct iommu_cmd
*cmd
)
962 memset(cmd
, 0, sizeof(*cmd
));
963 CMD_SET_TYPE(cmd
, CMD_INV_ALL
);
966 static void build_inv_irt(struct iommu_cmd
*cmd
, u16 devid
)
968 memset(cmd
, 0, sizeof(*cmd
));
969 cmd
->data
[0] = devid
;
970 CMD_SET_TYPE(cmd
, CMD_INV_IRT
);
974 * Writes the command to the IOMMUs command buffer and informs the
975 * hardware about the new command.
977 static int iommu_queue_command_sync(struct amd_iommu
*iommu
,
978 struct iommu_cmd
*cmd
,
981 u32 left
, tail
, head
, next_tail
;
985 spin_lock_irqsave(&iommu
->lock
, flags
);
987 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
988 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
989 next_tail
= (tail
+ sizeof(*cmd
)) % CMD_BUFFER_SIZE
;
990 left
= (head
- next_tail
) % CMD_BUFFER_SIZE
;
993 struct iommu_cmd sync_cmd
;
994 volatile u64 sem
= 0;
997 build_completion_wait(&sync_cmd
, (u64
)&sem
);
998 copy_cmd_to_buffer(iommu
, &sync_cmd
, tail
);
1000 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1002 if ((ret
= wait_on_sem(&sem
)) != 0)
1008 copy_cmd_to_buffer(iommu
, cmd
, tail
);
1010 /* We need to sync now to make sure all commands are processed */
1011 iommu
->need_sync
= sync
;
1013 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1018 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
1020 return iommu_queue_command_sync(iommu
, cmd
, true);
1024 * This function queues a completion wait command into the command
1025 * buffer of an IOMMU
1027 static int iommu_completion_wait(struct amd_iommu
*iommu
)
1029 struct iommu_cmd cmd
;
1030 volatile u64 sem
= 0;
1033 if (!iommu
->need_sync
)
1036 build_completion_wait(&cmd
, (u64
)&sem
);
1038 ret
= iommu_queue_command_sync(iommu
, &cmd
, false);
1042 return wait_on_sem(&sem
);
1045 static int iommu_flush_dte(struct amd_iommu
*iommu
, u16 devid
)
1047 struct iommu_cmd cmd
;
1049 build_inv_dte(&cmd
, devid
);
1051 return iommu_queue_command(iommu
, &cmd
);
1054 static void iommu_flush_dte_all(struct amd_iommu
*iommu
)
1058 for (devid
= 0; devid
<= 0xffff; ++devid
)
1059 iommu_flush_dte(iommu
, devid
);
1061 iommu_completion_wait(iommu
);
1065 * This function uses heavy locking and may disable irqs for some time. But
1066 * this is no issue because it is only called during resume.
1068 static void iommu_flush_tlb_all(struct amd_iommu
*iommu
)
1072 for (dom_id
= 0; dom_id
<= 0xffff; ++dom_id
) {
1073 struct iommu_cmd cmd
;
1074 build_inv_iommu_pages(&cmd
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
1076 iommu_queue_command(iommu
, &cmd
);
1079 iommu_completion_wait(iommu
);
1082 static void iommu_flush_all(struct amd_iommu
*iommu
)
1084 struct iommu_cmd cmd
;
1086 build_inv_all(&cmd
);
1088 iommu_queue_command(iommu
, &cmd
);
1089 iommu_completion_wait(iommu
);
1092 static void iommu_flush_irt(struct amd_iommu
*iommu
, u16 devid
)
1094 struct iommu_cmd cmd
;
1096 build_inv_irt(&cmd
, devid
);
1098 iommu_queue_command(iommu
, &cmd
);
1101 static void iommu_flush_irt_all(struct amd_iommu
*iommu
)
1105 for (devid
= 0; devid
<= MAX_DEV_TABLE_ENTRIES
; devid
++)
1106 iommu_flush_irt(iommu
, devid
);
1108 iommu_completion_wait(iommu
);
1111 void iommu_flush_all_caches(struct amd_iommu
*iommu
)
1113 if (iommu_feature(iommu
, FEATURE_IA
)) {
1114 iommu_flush_all(iommu
);
1116 iommu_flush_dte_all(iommu
);
1117 iommu_flush_irt_all(iommu
);
1118 iommu_flush_tlb_all(iommu
);
1123 * Command send function for flushing on-device TLB
1125 static int device_flush_iotlb(struct iommu_dev_data
*dev_data
,
1126 u64 address
, size_t size
)
1128 struct amd_iommu
*iommu
;
1129 struct iommu_cmd cmd
;
1132 qdep
= dev_data
->ats
.qdep
;
1133 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1135 build_inv_iotlb_pages(&cmd
, dev_data
->devid
, qdep
, address
, size
);
1137 return iommu_queue_command(iommu
, &cmd
);
1141 * Command send function for invalidating a device table entry
1143 static int device_flush_dte(struct iommu_dev_data
*dev_data
)
1145 struct amd_iommu
*iommu
;
1149 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1150 alias
= dev_data
->alias
;
1152 ret
= iommu_flush_dte(iommu
, dev_data
->devid
);
1153 if (!ret
&& alias
!= dev_data
->devid
)
1154 ret
= iommu_flush_dte(iommu
, alias
);
1158 if (dev_data
->ats
.enabled
)
1159 ret
= device_flush_iotlb(dev_data
, 0, ~0UL);
1165 * TLB invalidation function which is called from the mapping functions.
1166 * It invalidates a single PTE if the range to flush is within a single
1167 * page. Otherwise it flushes the whole TLB of the IOMMU.
1169 static void __domain_flush_pages(struct protection_domain
*domain
,
1170 u64 address
, size_t size
, int pde
)
1172 struct iommu_dev_data
*dev_data
;
1173 struct iommu_cmd cmd
;
1176 build_inv_iommu_pages(&cmd
, address
, size
, domain
->id
, pde
);
1178 for (i
= 0; i
< amd_iommus_present
; ++i
) {
1179 if (!domain
->dev_iommu
[i
])
1183 * Devices of this domain are behind this IOMMU
1184 * We need a TLB flush
1186 ret
|= iommu_queue_command(amd_iommus
[i
], &cmd
);
1189 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
1191 if (!dev_data
->ats
.enabled
)
1194 ret
|= device_flush_iotlb(dev_data
, address
, size
);
1200 static void domain_flush_pages(struct protection_domain
*domain
,
1201 u64 address
, size_t size
)
1203 __domain_flush_pages(domain
, address
, size
, 0);
1206 /* Flush the whole IO/TLB for a given protection domain */
1207 static void domain_flush_tlb(struct protection_domain
*domain
)
1209 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 0);
1212 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1213 static void domain_flush_tlb_pde(struct protection_domain
*domain
)
1215 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 1);
1218 static void domain_flush_complete(struct protection_domain
*domain
)
1222 for (i
= 0; i
< amd_iommus_present
; ++i
) {
1223 if (!domain
->dev_iommu
[i
])
1227 * Devices of this domain are behind this IOMMU
1228 * We need to wait for completion of all commands.
1230 iommu_completion_wait(amd_iommus
[i
]);
1236 * This function flushes the DTEs for all devices in domain
1238 static void domain_flush_devices(struct protection_domain
*domain
)
1240 struct iommu_dev_data
*dev_data
;
1242 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
1243 device_flush_dte(dev_data
);
1246 /****************************************************************************
1248 * The functions below are used the create the page table mappings for
1249 * unity mapped regions.
1251 ****************************************************************************/
1254 * This function is used to add another level to an IO page table. Adding
1255 * another level increases the size of the address space by 9 bits to a size up
1258 static bool increase_address_space(struct protection_domain
*domain
,
1263 if (domain
->mode
== PAGE_MODE_6_LEVEL
)
1264 /* address space already 64 bit large */
1267 pte
= (void *)get_zeroed_page(gfp
);
1271 *pte
= PM_LEVEL_PDE(domain
->mode
,
1272 virt_to_phys(domain
->pt_root
));
1273 domain
->pt_root
= pte
;
1275 domain
->updated
= true;
1280 static u64
*alloc_pte(struct protection_domain
*domain
,
1281 unsigned long address
,
1282 unsigned long page_size
,
1289 BUG_ON(!is_power_of_2(page_size
));
1291 while (address
> PM_LEVEL_SIZE(domain
->mode
))
1292 increase_address_space(domain
, gfp
);
1294 level
= domain
->mode
- 1;
1295 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1296 address
= PAGE_SIZE_ALIGN(address
, page_size
);
1297 end_lvl
= PAGE_SIZE_LEVEL(page_size
);
1299 while (level
> end_lvl
) {
1304 if (!IOMMU_PTE_PRESENT(__pte
)) {
1305 page
= (u64
*)get_zeroed_page(gfp
);
1309 __npte
= PM_LEVEL_PDE(level
, virt_to_phys(page
));
1311 if (cmpxchg64(pte
, __pte
, __npte
)) {
1312 free_page((unsigned long)page
);
1317 /* No level skipping support yet */
1318 if (PM_PTE_LEVEL(*pte
) != level
)
1323 pte
= IOMMU_PTE_PAGE(*pte
);
1325 if (pte_page
&& level
== end_lvl
)
1328 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1335 * This function checks if there is a PTE for a given dma address. If
1336 * there is one, it returns the pointer to it.
1338 static u64
*fetch_pte(struct protection_domain
*domain
,
1339 unsigned long address
,
1340 unsigned long *page_size
)
1345 if (address
> PM_LEVEL_SIZE(domain
->mode
))
1348 level
= domain
->mode
- 1;
1349 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1350 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1355 if (!IOMMU_PTE_PRESENT(*pte
))
1359 if (PM_PTE_LEVEL(*pte
) == 7 ||
1360 PM_PTE_LEVEL(*pte
) == 0)
1363 /* No level skipping support yet */
1364 if (PM_PTE_LEVEL(*pte
) != level
)
1369 /* Walk to the next level */
1370 pte
= IOMMU_PTE_PAGE(*pte
);
1371 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1372 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1375 if (PM_PTE_LEVEL(*pte
) == 0x07) {
1376 unsigned long pte_mask
;
1379 * If we have a series of large PTEs, make
1380 * sure to return a pointer to the first one.
1382 *page_size
= pte_mask
= PTE_PAGE_SIZE(*pte
);
1383 pte_mask
= ~((PAGE_SIZE_PTE_COUNT(pte_mask
) << 3) - 1);
1384 pte
= (u64
*)(((unsigned long)pte
) & pte_mask
);
1391 * Generic mapping functions. It maps a physical address into a DMA
1392 * address space. It allocates the page table pages if necessary.
1393 * In the future it can be extended to a generic mapping function
1394 * supporting all features of AMD IOMMU page tables like level skipping
1395 * and full 64 bit address spaces.
1397 static int iommu_map_page(struct protection_domain
*dom
,
1398 unsigned long bus_addr
,
1399 unsigned long phys_addr
,
1401 unsigned long page_size
)
1406 BUG_ON(!IS_ALIGNED(bus_addr
, page_size
));
1407 BUG_ON(!IS_ALIGNED(phys_addr
, page_size
));
1409 if (!(prot
& IOMMU_PROT_MASK
))
1412 count
= PAGE_SIZE_PTE_COUNT(page_size
);
1413 pte
= alloc_pte(dom
, bus_addr
, page_size
, NULL
, GFP_KERNEL
);
1418 for (i
= 0; i
< count
; ++i
)
1419 if (IOMMU_PTE_PRESENT(pte
[i
]))
1423 __pte
= PAGE_SIZE_PTE(phys_addr
, page_size
);
1424 __pte
|= PM_LEVEL_ENC(7) | IOMMU_PTE_P
| IOMMU_PTE_FC
;
1426 __pte
= phys_addr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1428 if (prot
& IOMMU_PROT_IR
)
1429 __pte
|= IOMMU_PTE_IR
;
1430 if (prot
& IOMMU_PROT_IW
)
1431 __pte
|= IOMMU_PTE_IW
;
1433 for (i
= 0; i
< count
; ++i
)
1441 static unsigned long iommu_unmap_page(struct protection_domain
*dom
,
1442 unsigned long bus_addr
,
1443 unsigned long page_size
)
1445 unsigned long long unmapped
;
1446 unsigned long unmap_size
;
1449 BUG_ON(!is_power_of_2(page_size
));
1453 while (unmapped
< page_size
) {
1455 pte
= fetch_pte(dom
, bus_addr
, &unmap_size
);
1460 count
= PAGE_SIZE_PTE_COUNT(unmap_size
);
1461 for (i
= 0; i
< count
; i
++)
1465 bus_addr
= (bus_addr
& ~(unmap_size
- 1)) + unmap_size
;
1466 unmapped
+= unmap_size
;
1469 BUG_ON(unmapped
&& !is_power_of_2(unmapped
));
1474 /****************************************************************************
1476 * The next functions belong to the address allocator for the dma_ops
1477 * interface functions. They work like the allocators in the other IOMMU
1478 * drivers. Its basically a bitmap which marks the allocated pages in
1479 * the aperture. Maybe it could be enhanced in the future to a more
1480 * efficient allocator.
1482 ****************************************************************************/
1485 * The address allocator core functions.
1487 * called with domain->lock held
1491 * Used to reserve address ranges in the aperture (e.g. for exclusion
1494 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
1495 unsigned long start_page
,
1498 unsigned int i
, last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
1500 if (start_page
+ pages
> last_page
)
1501 pages
= last_page
- start_page
;
1503 for (i
= start_page
; i
< start_page
+ pages
; ++i
) {
1504 int index
= i
/ APERTURE_RANGE_PAGES
;
1505 int page
= i
% APERTURE_RANGE_PAGES
;
1506 __set_bit(page
, dom
->aperture
[index
]->bitmap
);
1511 * This function is used to add a new aperture range to an existing
1512 * aperture in case of dma_ops domain allocation or address allocation
1515 static int alloc_new_range(struct dma_ops_domain
*dma_dom
,
1516 bool populate
, gfp_t gfp
)
1518 int index
= dma_dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1519 unsigned long i
, old_size
, pte_pgsize
;
1520 struct aperture_range
*range
;
1521 struct amd_iommu
*iommu
;
1522 unsigned long flags
;
1524 #ifdef CONFIG_IOMMU_STRESS
1528 if (index
>= APERTURE_MAX_RANGES
)
1531 range
= kzalloc(sizeof(struct aperture_range
), gfp
);
1535 range
->bitmap
= (void *)get_zeroed_page(gfp
);
1539 range
->offset
= dma_dom
->aperture_size
;
1541 spin_lock_init(&range
->bitmap_lock
);
1544 unsigned long address
= dma_dom
->aperture_size
;
1545 int i
, num_ptes
= APERTURE_RANGE_PAGES
/ 512;
1546 u64
*pte
, *pte_page
;
1548 for (i
= 0; i
< num_ptes
; ++i
) {
1549 pte
= alloc_pte(&dma_dom
->domain
, address
, PAGE_SIZE
,
1554 range
->pte_pages
[i
] = pte_page
;
1556 address
+= APERTURE_RANGE_SIZE
/ 64;
1560 spin_lock_irqsave(&dma_dom
->domain
.lock
, flags
);
1562 /* First take the bitmap_lock and then publish the range */
1563 spin_lock(&range
->bitmap_lock
);
1565 old_size
= dma_dom
->aperture_size
;
1566 dma_dom
->aperture
[index
] = range
;
1567 dma_dom
->aperture_size
+= APERTURE_RANGE_SIZE
;
1569 /* Reserve address range used for MSI messages */
1570 if (old_size
< MSI_ADDR_BASE_LO
&&
1571 dma_dom
->aperture_size
> MSI_ADDR_BASE_LO
) {
1572 unsigned long spage
;
1575 pages
= iommu_num_pages(MSI_ADDR_BASE_LO
, 0x10000, PAGE_SIZE
);
1576 spage
= MSI_ADDR_BASE_LO
>> PAGE_SHIFT
;
1578 dma_ops_reserve_addresses(dma_dom
, spage
, pages
);
1581 /* Initialize the exclusion range if necessary */
1582 for_each_iommu(iommu
) {
1583 if (iommu
->exclusion_start
&&
1584 iommu
->exclusion_start
>= dma_dom
->aperture
[index
]->offset
1585 && iommu
->exclusion_start
< dma_dom
->aperture_size
) {
1586 unsigned long startpage
;
1587 int pages
= iommu_num_pages(iommu
->exclusion_start
,
1588 iommu
->exclusion_length
,
1590 startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
1591 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
1596 * Check for areas already mapped as present in the new aperture
1597 * range and mark those pages as reserved in the allocator. Such
1598 * mappings may already exist as a result of requested unity
1599 * mappings for devices.
1601 for (i
= dma_dom
->aperture
[index
]->offset
;
1602 i
< dma_dom
->aperture_size
;
1604 u64
*pte
= fetch_pte(&dma_dom
->domain
, i
, &pte_pgsize
);
1605 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
1608 dma_ops_reserve_addresses(dma_dom
, i
>> PAGE_SHIFT
,
1612 update_domain(&dma_dom
->domain
);
1614 spin_unlock(&range
->bitmap_lock
);
1616 spin_unlock_irqrestore(&dma_dom
->domain
.lock
, flags
);
1621 update_domain(&dma_dom
->domain
);
1623 free_page((unsigned long)range
->bitmap
);
1630 static dma_addr_t
dma_ops_aperture_alloc(struct dma_ops_domain
*dom
,
1631 struct aperture_range
*range
,
1632 unsigned long pages
,
1633 unsigned long dma_mask
,
1634 unsigned long boundary_size
,
1635 unsigned long align_mask
,
1638 unsigned long offset
, limit
, flags
;
1642 offset
= range
->offset
>> PAGE_SHIFT
;
1643 limit
= iommu_device_max_index(APERTURE_RANGE_PAGES
, offset
,
1644 dma_mask
>> PAGE_SHIFT
);
1647 if (!spin_trylock_irqsave(&range
->bitmap_lock
, flags
))
1650 spin_lock_irqsave(&range
->bitmap_lock
, flags
);
1653 address
= iommu_area_alloc(range
->bitmap
, limit
, range
->next_bit
,
1654 pages
, offset
, boundary_size
, align_mask
);
1655 if (address
== -1) {
1656 /* Nothing found, retry one time */
1657 address
= iommu_area_alloc(range
->bitmap
, limit
,
1658 0, pages
, offset
, boundary_size
,
1664 range
->next_bit
= address
+ pages
;
1666 spin_unlock_irqrestore(&range
->bitmap_lock
, flags
);
1669 domain_flush_tlb(&dom
->domain
);
1670 domain_flush_complete(&dom
->domain
);
1676 static unsigned long dma_ops_area_alloc(struct device
*dev
,
1677 struct dma_ops_domain
*dom
,
1679 unsigned long align_mask
,
1682 unsigned long boundary_size
, mask
;
1683 unsigned long address
= -1;
1689 mask
= dma_get_seg_boundary(dev
);
1692 start
= this_cpu_read(*dom
->next_index
);
1694 /* Sanity check - is it really necessary? */
1695 if (unlikely(start
> APERTURE_MAX_RANGES
)) {
1697 this_cpu_write(*dom
->next_index
, 0);
1700 boundary_size
= mask
+ 1 ? ALIGN(mask
+ 1, PAGE_SIZE
) >> PAGE_SHIFT
:
1701 1UL << (BITS_PER_LONG
- PAGE_SHIFT
);
1703 for (i
= 0; i
< APERTURE_MAX_RANGES
; ++i
) {
1704 struct aperture_range
*range
;
1707 index
= (start
+ i
) % APERTURE_MAX_RANGES
;
1709 range
= dom
->aperture
[index
];
1711 if (!range
|| range
->offset
>= dma_mask
)
1714 address
= dma_ops_aperture_alloc(dom
, range
, pages
,
1715 dma_mask
, boundary_size
,
1717 if (address
!= -1) {
1718 address
= range
->offset
+ (address
<< PAGE_SHIFT
);
1719 this_cpu_write(*dom
->next_index
, index
);
1724 if (address
== -1 && first
) {
1734 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
1735 struct dma_ops_domain
*dom
,
1737 unsigned long align_mask
,
1740 unsigned long address
= -1;
1742 while (address
== -1) {
1743 address
= dma_ops_area_alloc(dev
, dom
, pages
,
1744 align_mask
, dma_mask
);
1746 if (address
== -1 && alloc_new_range(dom
, false, GFP_ATOMIC
))
1750 if (unlikely(address
== -1))
1751 address
= DMA_ERROR_CODE
;
1753 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
1759 * The address free function.
1761 * called with domain->lock held
1763 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
1764 unsigned long address
,
1767 unsigned i
= address
>> APERTURE_RANGE_SHIFT
;
1768 struct aperture_range
*range
= dom
->aperture
[i
];
1769 unsigned long flags
;
1771 BUG_ON(i
>= APERTURE_MAX_RANGES
|| range
== NULL
);
1773 #ifdef CONFIG_IOMMU_STRESS
1778 if (amd_iommu_unmap_flush
) {
1779 domain_flush_tlb(&dom
->domain
);
1780 domain_flush_complete(&dom
->domain
);
1783 address
= (address
% APERTURE_RANGE_SIZE
) >> PAGE_SHIFT
;
1785 spin_lock_irqsave(&range
->bitmap_lock
, flags
);
1786 if (address
+ pages
> range
->next_bit
)
1787 range
->next_bit
= address
+ pages
;
1788 bitmap_clear(range
->bitmap
, address
, pages
);
1789 spin_unlock_irqrestore(&range
->bitmap_lock
, flags
);
1793 /****************************************************************************
1795 * The next functions belong to the domain allocation. A domain is
1796 * allocated for every IOMMU as the default domain. If device isolation
1797 * is enabled, every device get its own domain. The most important thing
1798 * about domains is the page table mapping the DMA address space they
1801 ****************************************************************************/
1804 * This function adds a protection domain to the global protection domain list
1806 static void add_domain_to_list(struct protection_domain
*domain
)
1808 unsigned long flags
;
1810 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1811 list_add(&domain
->list
, &amd_iommu_pd_list
);
1812 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1816 * This function removes a protection domain to the global
1817 * protection domain list
1819 static void del_domain_from_list(struct protection_domain
*domain
)
1821 unsigned long flags
;
1823 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1824 list_del(&domain
->list
);
1825 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1828 static u16
domain_id_alloc(void)
1830 unsigned long flags
;
1833 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1834 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
1836 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1837 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
1840 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1845 static void domain_id_free(int id
)
1847 unsigned long flags
;
1849 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1850 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1851 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
1852 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1855 #define DEFINE_FREE_PT_FN(LVL, FN) \
1856 static void free_pt_##LVL (unsigned long __pt) \
1864 for (i = 0; i < 512; ++i) { \
1865 /* PTE present? */ \
1866 if (!IOMMU_PTE_PRESENT(pt[i])) \
1870 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1871 PM_PTE_LEVEL(pt[i]) == 7) \
1874 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1877 free_page((unsigned long)pt); \
1880 DEFINE_FREE_PT_FN(l2
, free_page
)
1881 DEFINE_FREE_PT_FN(l3
, free_pt_l2
)
1882 DEFINE_FREE_PT_FN(l4
, free_pt_l3
)
1883 DEFINE_FREE_PT_FN(l5
, free_pt_l4
)
1884 DEFINE_FREE_PT_FN(l6
, free_pt_l5
)
1886 static void free_pagetable(struct protection_domain
*domain
)
1888 unsigned long root
= (unsigned long)domain
->pt_root
;
1890 switch (domain
->mode
) {
1891 case PAGE_MODE_NONE
:
1893 case PAGE_MODE_1_LEVEL
:
1896 case PAGE_MODE_2_LEVEL
:
1899 case PAGE_MODE_3_LEVEL
:
1902 case PAGE_MODE_4_LEVEL
:
1905 case PAGE_MODE_5_LEVEL
:
1908 case PAGE_MODE_6_LEVEL
:
1916 static void free_gcr3_tbl_level1(u64
*tbl
)
1921 for (i
= 0; i
< 512; ++i
) {
1922 if (!(tbl
[i
] & GCR3_VALID
))
1925 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1927 free_page((unsigned long)ptr
);
1931 static void free_gcr3_tbl_level2(u64
*tbl
)
1936 for (i
= 0; i
< 512; ++i
) {
1937 if (!(tbl
[i
] & GCR3_VALID
))
1940 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1942 free_gcr3_tbl_level1(ptr
);
1946 static void free_gcr3_table(struct protection_domain
*domain
)
1948 if (domain
->glx
== 2)
1949 free_gcr3_tbl_level2(domain
->gcr3_tbl
);
1950 else if (domain
->glx
== 1)
1951 free_gcr3_tbl_level1(domain
->gcr3_tbl
);
1953 BUG_ON(domain
->glx
!= 0);
1955 free_page((unsigned long)domain
->gcr3_tbl
);
1959 * Free a domain, only used if something went wrong in the
1960 * allocation path and we need to free an already allocated page table
1962 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
1969 free_percpu(dom
->next_index
);
1971 del_domain_from_list(&dom
->domain
);
1973 free_pagetable(&dom
->domain
);
1975 for (i
= 0; i
< APERTURE_MAX_RANGES
; ++i
) {
1976 if (!dom
->aperture
[i
])
1978 free_page((unsigned long)dom
->aperture
[i
]->bitmap
);
1979 kfree(dom
->aperture
[i
]);
1985 static int dma_ops_domain_alloc_apertures(struct dma_ops_domain
*dma_dom
,
1988 int ret
, i
, apertures
;
1990 apertures
= dma_dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1993 for (i
= apertures
; i
< max_apertures
; ++i
) {
1994 ret
= alloc_new_range(dma_dom
, false, GFP_KERNEL
);
2003 * Allocates a new protection domain usable for the dma_ops functions.
2004 * It also initializes the page table and the address allocator data
2005 * structures required for the dma_ops interface
2007 static struct dma_ops_domain
*dma_ops_domain_alloc(void)
2009 struct dma_ops_domain
*dma_dom
;
2012 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
2016 if (protection_domain_init(&dma_dom
->domain
))
2019 dma_dom
->next_index
= alloc_percpu(u32
);
2020 if (!dma_dom
->next_index
)
2023 dma_dom
->domain
.mode
= PAGE_MODE_2_LEVEL
;
2024 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
2025 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
2026 dma_dom
->domain
.priv
= dma_dom
;
2027 if (!dma_dom
->domain
.pt_root
)
2030 add_domain_to_list(&dma_dom
->domain
);
2032 if (alloc_new_range(dma_dom
, true, GFP_KERNEL
))
2036 * mark the first page as allocated so we never return 0 as
2037 * a valid dma-address. So we can use 0 as error value
2039 dma_dom
->aperture
[0]->bitmap
[0] = 1;
2041 for_each_possible_cpu(cpu
)
2042 *per_cpu_ptr(dma_dom
->next_index
, cpu
) = 0;
2047 dma_ops_domain_free(dma_dom
);
2053 * little helper function to check whether a given protection domain is a
2056 static bool dma_ops_domain(struct protection_domain
*domain
)
2058 return domain
->flags
& PD_DMA_OPS_MASK
;
2061 static void set_dte_entry(u16 devid
, struct protection_domain
*domain
, bool ats
)
2066 if (domain
->mode
!= PAGE_MODE_NONE
)
2067 pte_root
= virt_to_phys(domain
->pt_root
);
2069 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
2070 << DEV_ENTRY_MODE_SHIFT
;
2071 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
2073 flags
= amd_iommu_dev_table
[devid
].data
[1];
2076 flags
|= DTE_FLAG_IOTLB
;
2078 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2079 u64 gcr3
= __pa(domain
->gcr3_tbl
);
2080 u64 glx
= domain
->glx
;
2083 pte_root
|= DTE_FLAG_GV
;
2084 pte_root
|= (glx
& DTE_GLX_MASK
) << DTE_GLX_SHIFT
;
2086 /* First mask out possible old values for GCR3 table */
2087 tmp
= DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B
;
2090 tmp
= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C
;
2093 /* Encode GCR3 table into DTE */
2094 tmp
= DTE_GCR3_VAL_A(gcr3
) << DTE_GCR3_SHIFT_A
;
2097 tmp
= DTE_GCR3_VAL_B(gcr3
) << DTE_GCR3_SHIFT_B
;
2100 tmp
= DTE_GCR3_VAL_C(gcr3
) << DTE_GCR3_SHIFT_C
;
2104 flags
&= ~(0xffffUL
);
2105 flags
|= domain
->id
;
2107 amd_iommu_dev_table
[devid
].data
[1] = flags
;
2108 amd_iommu_dev_table
[devid
].data
[0] = pte_root
;
2111 static void clear_dte_entry(u16 devid
)
2113 /* remove entry from the device table seen by the hardware */
2114 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
2115 amd_iommu_dev_table
[devid
].data
[1] &= DTE_FLAG_MASK
;
2117 amd_iommu_apply_erratum_63(devid
);
2120 static void do_attach(struct iommu_dev_data
*dev_data
,
2121 struct protection_domain
*domain
)
2123 struct amd_iommu
*iommu
;
2127 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
2128 alias
= dev_data
->alias
;
2129 ats
= dev_data
->ats
.enabled
;
2131 /* Update data structures */
2132 dev_data
->domain
= domain
;
2133 list_add(&dev_data
->list
, &domain
->dev_list
);
2135 /* Do reference counting */
2136 domain
->dev_iommu
[iommu
->index
] += 1;
2137 domain
->dev_cnt
+= 1;
2139 /* Update device table */
2140 set_dte_entry(dev_data
->devid
, domain
, ats
);
2141 if (alias
!= dev_data
->devid
)
2142 set_dte_entry(alias
, domain
, ats
);
2144 device_flush_dte(dev_data
);
2147 static void do_detach(struct iommu_dev_data
*dev_data
)
2149 struct amd_iommu
*iommu
;
2153 * First check if the device is still attached. It might already
2154 * be detached from its domain because the generic
2155 * iommu_detach_group code detached it and we try again here in
2156 * our alias handling.
2158 if (!dev_data
->domain
)
2161 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
2162 alias
= dev_data
->alias
;
2164 /* decrease reference counters */
2165 dev_data
->domain
->dev_iommu
[iommu
->index
] -= 1;
2166 dev_data
->domain
->dev_cnt
-= 1;
2168 /* Update data structures */
2169 dev_data
->domain
= NULL
;
2170 list_del(&dev_data
->list
);
2171 clear_dte_entry(dev_data
->devid
);
2172 if (alias
!= dev_data
->devid
)
2173 clear_dte_entry(alias
);
2175 /* Flush the DTE entry */
2176 device_flush_dte(dev_data
);
2180 * If a device is not yet associated with a domain, this function does
2181 * assigns it visible for the hardware
2183 static int __attach_device(struct iommu_dev_data
*dev_data
,
2184 struct protection_domain
*domain
)
2189 * Must be called with IRQs disabled. Warn here to detect early
2192 WARN_ON(!irqs_disabled());
2195 spin_lock(&domain
->lock
);
2198 if (dev_data
->domain
!= NULL
)
2201 /* Attach alias group root */
2202 do_attach(dev_data
, domain
);
2209 spin_unlock(&domain
->lock
);
2215 static void pdev_iommuv2_disable(struct pci_dev
*pdev
)
2217 pci_disable_ats(pdev
);
2218 pci_disable_pri(pdev
);
2219 pci_disable_pasid(pdev
);
2222 /* FIXME: Change generic reset-function to do the same */
2223 static int pri_reset_while_enabled(struct pci_dev
*pdev
)
2228 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2232 pci_read_config_word(pdev
, pos
+ PCI_PRI_CTRL
, &control
);
2233 control
|= PCI_PRI_CTRL_RESET
;
2234 pci_write_config_word(pdev
, pos
+ PCI_PRI_CTRL
, control
);
2239 static int pdev_iommuv2_enable(struct pci_dev
*pdev
)
2244 /* FIXME: Hardcode number of outstanding requests for now */
2246 if (pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE
))
2248 reset_enable
= pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_ENABLE_RESET
);
2250 /* Only allow access to user-accessible pages */
2251 ret
= pci_enable_pasid(pdev
, 0);
2255 /* First reset the PRI state of the device */
2256 ret
= pci_reset_pri(pdev
);
2261 ret
= pci_enable_pri(pdev
, reqs
);
2266 ret
= pri_reset_while_enabled(pdev
);
2271 ret
= pci_enable_ats(pdev
, PAGE_SHIFT
);
2278 pci_disable_pri(pdev
);
2279 pci_disable_pasid(pdev
);
2284 /* FIXME: Move this to PCI code */
2285 #define PCI_PRI_TLP_OFF (1 << 15)
2287 static bool pci_pri_tlp_required(struct pci_dev
*pdev
)
2292 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2296 pci_read_config_word(pdev
, pos
+ PCI_PRI_STATUS
, &status
);
2298 return (status
& PCI_PRI_TLP_OFF
) ? true : false;
2302 * If a device is not yet associated with a domain, this function
2303 * assigns it visible for the hardware
2305 static int attach_device(struct device
*dev
,
2306 struct protection_domain
*domain
)
2308 struct pci_dev
*pdev
;
2309 struct iommu_dev_data
*dev_data
;
2310 unsigned long flags
;
2313 dev_data
= get_dev_data(dev
);
2315 if (!dev_is_pci(dev
))
2316 goto skip_ats_check
;
2318 pdev
= to_pci_dev(dev
);
2319 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2320 if (!dev_data
->passthrough
)
2323 if (dev_data
->iommu_v2
) {
2324 if (pdev_iommuv2_enable(pdev
) != 0)
2327 dev_data
->ats
.enabled
= true;
2328 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2329 dev_data
->pri_tlp
= pci_pri_tlp_required(pdev
);
2331 } else if (amd_iommu_iotlb_sup
&&
2332 pci_enable_ats(pdev
, PAGE_SHIFT
) == 0) {
2333 dev_data
->ats
.enabled
= true;
2334 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2338 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2339 ret
= __attach_device(dev_data
, domain
);
2340 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2343 * We might boot into a crash-kernel here. The crashed kernel
2344 * left the caches in the IOMMU dirty. So we have to flush
2345 * here to evict all dirty stuff.
2347 domain_flush_tlb_pde(domain
);
2353 * Removes a device from a protection domain (unlocked)
2355 static void __detach_device(struct iommu_dev_data
*dev_data
)
2357 struct protection_domain
*domain
;
2360 * Must be called with IRQs disabled. Warn here to detect early
2363 WARN_ON(!irqs_disabled());
2365 if (WARN_ON(!dev_data
->domain
))
2368 domain
= dev_data
->domain
;
2370 spin_lock(&domain
->lock
);
2372 do_detach(dev_data
);
2374 spin_unlock(&domain
->lock
);
2378 * Removes a device from a protection domain (with devtable_lock held)
2380 static void detach_device(struct device
*dev
)
2382 struct protection_domain
*domain
;
2383 struct iommu_dev_data
*dev_data
;
2384 unsigned long flags
;
2386 dev_data
= get_dev_data(dev
);
2387 domain
= dev_data
->domain
;
2389 /* lock device table */
2390 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2391 __detach_device(dev_data
);
2392 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2394 if (!dev_is_pci(dev
))
2397 if (domain
->flags
& PD_IOMMUV2_MASK
&& dev_data
->iommu_v2
)
2398 pdev_iommuv2_disable(to_pci_dev(dev
));
2399 else if (dev_data
->ats
.enabled
)
2400 pci_disable_ats(to_pci_dev(dev
));
2402 dev_data
->ats
.enabled
= false;
2405 static int amd_iommu_add_device(struct device
*dev
)
2407 struct iommu_dev_data
*dev_data
;
2408 struct iommu_domain
*domain
;
2409 struct amd_iommu
*iommu
;
2412 if (!check_device(dev
) || get_dev_data(dev
))
2415 devid
= get_device_id(dev
);
2419 iommu
= amd_iommu_rlookup_table
[devid
];
2421 ret
= iommu_init_device(dev
);
2423 if (ret
!= -ENOTSUPP
)
2424 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2427 iommu_ignore_device(dev
);
2428 dev
->archdata
.dma_ops
= &nommu_dma_ops
;
2431 init_iommu_group(dev
);
2433 dev_data
= get_dev_data(dev
);
2437 if (iommu_pass_through
|| dev_data
->iommu_v2
)
2438 iommu_request_dm_for_dev(dev
);
2440 /* Domains are initialized for this device - have a look what we ended up with */
2441 domain
= iommu_get_domain_for_dev(dev
);
2442 if (domain
->type
== IOMMU_DOMAIN_IDENTITY
)
2443 dev_data
->passthrough
= true;
2445 dev
->archdata
.dma_ops
= &amd_iommu_dma_ops
;
2448 iommu_completion_wait(iommu
);
2453 static void amd_iommu_remove_device(struct device
*dev
)
2455 struct amd_iommu
*iommu
;
2458 if (!check_device(dev
))
2461 devid
= get_device_id(dev
);
2465 iommu
= amd_iommu_rlookup_table
[devid
];
2467 iommu_uninit_device(dev
);
2468 iommu_completion_wait(iommu
);
2471 static struct iommu_group
*amd_iommu_device_group(struct device
*dev
)
2473 if (dev_is_pci(dev
))
2474 return pci_device_group(dev
);
2476 return acpihid_device_group(dev
);
2479 /*****************************************************************************
2481 * The next functions belong to the dma_ops mapping/unmapping code.
2483 *****************************************************************************/
2486 * In the dma_ops path we only have the struct device. This function
2487 * finds the corresponding IOMMU, the protection domain and the
2488 * requestor id for a given device.
2489 * If the device is not yet associated with a domain this is also done
2492 static struct protection_domain
*get_domain(struct device
*dev
)
2494 struct protection_domain
*domain
;
2495 struct iommu_domain
*io_domain
;
2497 if (!check_device(dev
))
2498 return ERR_PTR(-EINVAL
);
2500 io_domain
= iommu_get_domain_for_dev(dev
);
2504 domain
= to_pdomain(io_domain
);
2505 if (!dma_ops_domain(domain
))
2506 return ERR_PTR(-EBUSY
);
2511 static void update_device_table(struct protection_domain
*domain
)
2513 struct iommu_dev_data
*dev_data
;
2515 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
2516 set_dte_entry(dev_data
->devid
, domain
, dev_data
->ats
.enabled
);
2519 static void update_domain(struct protection_domain
*domain
)
2521 if (!domain
->updated
)
2524 update_device_table(domain
);
2526 domain_flush_devices(domain
);
2527 domain_flush_tlb_pde(domain
);
2529 domain
->updated
= false;
2533 * This function fetches the PTE for a given address in the aperture
2535 static u64
* dma_ops_get_pte(struct dma_ops_domain
*dom
,
2536 unsigned long address
)
2538 struct aperture_range
*aperture
;
2539 u64
*pte
, *pte_page
;
2541 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
2545 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
2547 pte
= alloc_pte(&dom
->domain
, address
, PAGE_SIZE
, &pte_page
,
2549 aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)] = pte_page
;
2551 pte
+= PM_LEVEL_INDEX(0, address
);
2553 update_domain(&dom
->domain
);
2559 * This is the generic map function. It maps one 4kb page at paddr to
2560 * the given address in the DMA address space for the domain.
2562 static dma_addr_t
dma_ops_domain_map(struct dma_ops_domain
*dom
,
2563 unsigned long address
,
2569 WARN_ON(address
> dom
->aperture_size
);
2573 pte
= dma_ops_get_pte(dom
, address
);
2575 return DMA_ERROR_CODE
;
2577 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
2579 if (direction
== DMA_TO_DEVICE
)
2580 __pte
|= IOMMU_PTE_IR
;
2581 else if (direction
== DMA_FROM_DEVICE
)
2582 __pte
|= IOMMU_PTE_IW
;
2583 else if (direction
== DMA_BIDIRECTIONAL
)
2584 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
2590 return (dma_addr_t
)address
;
2594 * The generic unmapping function for on page in the DMA address space.
2596 static void dma_ops_domain_unmap(struct dma_ops_domain
*dom
,
2597 unsigned long address
)
2599 struct aperture_range
*aperture
;
2602 if (address
>= dom
->aperture_size
)
2605 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
2609 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
2613 pte
+= PM_LEVEL_INDEX(0, address
);
2615 WARN_ON_ONCE(!*pte
);
2621 * This function contains common code for mapping of a physically
2622 * contiguous memory region into DMA address space. It is used by all
2623 * mapping functions provided with this IOMMU driver.
2624 * Must be called with the domain lock held.
2626 static dma_addr_t
__map_single(struct device
*dev
,
2627 struct dma_ops_domain
*dma_dom
,
2634 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
2635 dma_addr_t address
, start
, ret
;
2637 unsigned long align_mask
= 0;
2640 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
2644 align_mask
= (1UL << get_order(size
)) - 1;
2646 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
, align_mask
,
2649 if (address
== DMA_ERROR_CODE
)
2653 for (i
= 0; i
< pages
; ++i
) {
2654 ret
= dma_ops_domain_map(dma_dom
, start
, paddr
, dir
);
2655 if (ret
== DMA_ERROR_CODE
)
2663 if (unlikely(amd_iommu_np_cache
)) {
2664 domain_flush_pages(&dma_dom
->domain
, address
, size
);
2665 domain_flush_complete(&dma_dom
->domain
);
2673 for (--i
; i
>= 0; --i
) {
2675 dma_ops_domain_unmap(dma_dom
, start
);
2678 dma_ops_free_addresses(dma_dom
, address
, pages
);
2680 return DMA_ERROR_CODE
;
2684 * Does the reverse of the __map_single function. Must be called with
2685 * the domain lock held too
2687 static void __unmap_single(struct dma_ops_domain
*dma_dom
,
2688 dma_addr_t dma_addr
,
2692 dma_addr_t flush_addr
;
2693 dma_addr_t i
, start
;
2696 if ((dma_addr
== DMA_ERROR_CODE
) ||
2697 (dma_addr
+ size
> dma_dom
->aperture_size
))
2700 flush_addr
= dma_addr
;
2701 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
2702 dma_addr
&= PAGE_MASK
;
2705 for (i
= 0; i
< pages
; ++i
) {
2706 dma_ops_domain_unmap(dma_dom
, start
);
2710 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
2714 * The exported map_single function for dma_ops.
2716 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
2717 unsigned long offset
, size_t size
,
2718 enum dma_data_direction dir
,
2719 struct dma_attrs
*attrs
)
2721 phys_addr_t paddr
= page_to_phys(page
) + offset
;
2722 struct protection_domain
*domain
;
2725 domain
= get_domain(dev
);
2726 if (PTR_ERR(domain
) == -EINVAL
)
2727 return (dma_addr_t
)paddr
;
2728 else if (IS_ERR(domain
))
2729 return DMA_ERROR_CODE
;
2731 dma_mask
= *dev
->dma_mask
;
2733 return __map_single(dev
, domain
->priv
, paddr
, size
, dir
, false,
2738 * The exported unmap_single function for dma_ops.
2740 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
2741 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
2743 struct protection_domain
*domain
;
2745 domain
= get_domain(dev
);
2749 __unmap_single(domain
->priv
, dma_addr
, size
, dir
);
2753 * The exported map_sg function for dma_ops (handles scatter-gather
2756 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
2757 int nelems
, enum dma_data_direction dir
,
2758 struct dma_attrs
*attrs
)
2760 struct protection_domain
*domain
;
2762 struct scatterlist
*s
;
2764 int mapped_elems
= 0;
2767 domain
= get_domain(dev
);
2771 dma_mask
= *dev
->dma_mask
;
2773 for_each_sg(sglist
, s
, nelems
, i
) {
2776 s
->dma_address
= __map_single(dev
, domain
->priv
,
2777 paddr
, s
->length
, dir
, false,
2780 if (s
->dma_address
) {
2781 s
->dma_length
= s
->length
;
2787 return mapped_elems
;
2790 for_each_sg(sglist
, s
, mapped_elems
, i
) {
2792 __unmap_single(domain
->priv
, s
->dma_address
,
2793 s
->dma_length
, dir
);
2794 s
->dma_address
= s
->dma_length
= 0;
2801 * The exported map_sg function for dma_ops (handles scatter-gather
2804 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
2805 int nelems
, enum dma_data_direction dir
,
2806 struct dma_attrs
*attrs
)
2808 struct protection_domain
*domain
;
2809 struct scatterlist
*s
;
2812 domain
= get_domain(dev
);
2816 for_each_sg(sglist
, s
, nelems
, i
) {
2817 __unmap_single(domain
->priv
, s
->dma_address
,
2818 s
->dma_length
, dir
);
2819 s
->dma_address
= s
->dma_length
= 0;
2824 * The exported alloc_coherent function for dma_ops.
2826 static void *alloc_coherent(struct device
*dev
, size_t size
,
2827 dma_addr_t
*dma_addr
, gfp_t flag
,
2828 struct dma_attrs
*attrs
)
2830 u64 dma_mask
= dev
->coherent_dma_mask
;
2831 struct protection_domain
*domain
;
2834 domain
= get_domain(dev
);
2835 if (PTR_ERR(domain
) == -EINVAL
) {
2836 page
= alloc_pages(flag
, get_order(size
));
2837 *dma_addr
= page_to_phys(page
);
2838 return page_address(page
);
2839 } else if (IS_ERR(domain
))
2842 size
= PAGE_ALIGN(size
);
2843 dma_mask
= dev
->coherent_dma_mask
;
2844 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
2847 page
= alloc_pages(flag
| __GFP_NOWARN
, get_order(size
));
2849 if (!gfpflags_allow_blocking(flag
))
2852 page
= dma_alloc_from_contiguous(dev
, size
>> PAGE_SHIFT
,
2859 dma_mask
= *dev
->dma_mask
;
2861 *dma_addr
= __map_single(dev
, domain
->priv
, page_to_phys(page
),
2862 size
, DMA_BIDIRECTIONAL
, true, dma_mask
);
2864 if (*dma_addr
== DMA_ERROR_CODE
)
2867 return page_address(page
);
2871 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2872 __free_pages(page
, get_order(size
));
2878 * The exported free_coherent function for dma_ops.
2880 static void free_coherent(struct device
*dev
, size_t size
,
2881 void *virt_addr
, dma_addr_t dma_addr
,
2882 struct dma_attrs
*attrs
)
2884 struct protection_domain
*domain
;
2887 page
= virt_to_page(virt_addr
);
2888 size
= PAGE_ALIGN(size
);
2890 domain
= get_domain(dev
);
2894 __unmap_single(domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
2897 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2898 __free_pages(page
, get_order(size
));
2902 * This function is called by the DMA layer to find out if we can handle a
2903 * particular device. It is part of the dma_ops.
2905 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
2907 return check_device(dev
);
2910 static int set_dma_mask(struct device
*dev
, u64 mask
)
2912 struct protection_domain
*domain
;
2913 int max_apertures
= 1;
2915 domain
= get_domain(dev
);
2917 return PTR_ERR(domain
);
2919 if (mask
== DMA_BIT_MASK(64))
2921 else if (mask
> DMA_BIT_MASK(32))
2925 * To prevent lock contention it doesn't make sense to allocate more
2926 * apertures than online cpus
2928 if (max_apertures
> num_online_cpus())
2929 max_apertures
= num_online_cpus();
2931 if (dma_ops_domain_alloc_apertures(domain
->priv
, max_apertures
))
2932 dev_err(dev
, "Can't allocate %d iommu apertures\n",
2938 static struct dma_map_ops amd_iommu_dma_ops
= {
2939 .alloc
= alloc_coherent
,
2940 .free
= free_coherent
,
2941 .map_page
= map_page
,
2942 .unmap_page
= unmap_page
,
2944 .unmap_sg
= unmap_sg
,
2945 .dma_supported
= amd_iommu_dma_supported
,
2946 .set_dma_mask
= set_dma_mask
,
2949 int __init
amd_iommu_init_api(void)
2953 err
= bus_set_iommu(&pci_bus_type
, &amd_iommu_ops
);
2956 #ifdef CONFIG_ARM_AMBA
2957 err
= bus_set_iommu(&amba_bustype
, &amd_iommu_ops
);
2964 int __init
amd_iommu_init_dma_ops(void)
2966 swiotlb
= iommu_pass_through
? 1 : 0;
2970 * In case we don't initialize SWIOTLB (actually the common case
2971 * when AMD IOMMU is enabled), make sure there are global
2972 * dma_ops set as a fall-back for devices not handled by this
2973 * driver (for example non-PCI devices).
2976 dma_ops
= &nommu_dma_ops
;
2978 if (amd_iommu_unmap_flush
)
2979 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2981 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2986 /*****************************************************************************
2988 * The following functions belong to the exported interface of AMD IOMMU
2990 * This interface allows access to lower level functions of the IOMMU
2991 * like protection domain handling and assignement of devices to domains
2992 * which is not possible with the dma_ops interface.
2994 *****************************************************************************/
2996 static void cleanup_domain(struct protection_domain
*domain
)
2998 struct iommu_dev_data
*entry
;
2999 unsigned long flags
;
3001 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
3003 while (!list_empty(&domain
->dev_list
)) {
3004 entry
= list_first_entry(&domain
->dev_list
,
3005 struct iommu_dev_data
, list
);
3006 __detach_device(entry
);
3009 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
3012 static void protection_domain_free(struct protection_domain
*domain
)
3017 del_domain_from_list(domain
);
3020 domain_id_free(domain
->id
);
3025 static int protection_domain_init(struct protection_domain
*domain
)
3027 spin_lock_init(&domain
->lock
);
3028 mutex_init(&domain
->api_lock
);
3029 domain
->id
= domain_id_alloc();
3032 INIT_LIST_HEAD(&domain
->dev_list
);
3037 static struct protection_domain
*protection_domain_alloc(void)
3039 struct protection_domain
*domain
;
3041 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
3045 if (protection_domain_init(domain
))
3048 add_domain_to_list(domain
);
3058 static struct iommu_domain
*amd_iommu_domain_alloc(unsigned type
)
3060 struct protection_domain
*pdomain
;
3061 struct dma_ops_domain
*dma_domain
;
3064 case IOMMU_DOMAIN_UNMANAGED
:
3065 pdomain
= protection_domain_alloc();
3069 pdomain
->mode
= PAGE_MODE_3_LEVEL
;
3070 pdomain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
3071 if (!pdomain
->pt_root
) {
3072 protection_domain_free(pdomain
);
3076 pdomain
->domain
.geometry
.aperture_start
= 0;
3077 pdomain
->domain
.geometry
.aperture_end
= ~0ULL;
3078 pdomain
->domain
.geometry
.force_aperture
= true;
3081 case IOMMU_DOMAIN_DMA
:
3082 dma_domain
= dma_ops_domain_alloc();
3084 pr_err("AMD-Vi: Failed to allocate\n");
3087 pdomain
= &dma_domain
->domain
;
3089 case IOMMU_DOMAIN_IDENTITY
:
3090 pdomain
= protection_domain_alloc();
3094 pdomain
->mode
= PAGE_MODE_NONE
;
3100 return &pdomain
->domain
;
3103 static void amd_iommu_domain_free(struct iommu_domain
*dom
)
3105 struct protection_domain
*domain
;
3110 domain
= to_pdomain(dom
);
3112 if (domain
->dev_cnt
> 0)
3113 cleanup_domain(domain
);
3115 BUG_ON(domain
->dev_cnt
!= 0);
3117 if (domain
->mode
!= PAGE_MODE_NONE
)
3118 free_pagetable(domain
);
3120 if (domain
->flags
& PD_IOMMUV2_MASK
)
3121 free_gcr3_table(domain
);
3123 protection_domain_free(domain
);
3126 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
3129 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
3130 struct amd_iommu
*iommu
;
3133 if (!check_device(dev
))
3136 devid
= get_device_id(dev
);
3140 if (dev_data
->domain
!= NULL
)
3143 iommu
= amd_iommu_rlookup_table
[devid
];
3147 iommu_completion_wait(iommu
);
3150 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
3153 struct protection_domain
*domain
= to_pdomain(dom
);
3154 struct iommu_dev_data
*dev_data
;
3155 struct amd_iommu
*iommu
;
3158 if (!check_device(dev
))
3161 dev_data
= dev
->archdata
.iommu
;
3163 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3167 if (dev_data
->domain
)
3170 ret
= attach_device(dev
, domain
);
3172 iommu_completion_wait(iommu
);
3177 static int amd_iommu_map(struct iommu_domain
*dom
, unsigned long iova
,
3178 phys_addr_t paddr
, size_t page_size
, int iommu_prot
)
3180 struct protection_domain
*domain
= to_pdomain(dom
);
3184 if (domain
->mode
== PAGE_MODE_NONE
)
3187 if (iommu_prot
& IOMMU_READ
)
3188 prot
|= IOMMU_PROT_IR
;
3189 if (iommu_prot
& IOMMU_WRITE
)
3190 prot
|= IOMMU_PROT_IW
;
3192 mutex_lock(&domain
->api_lock
);
3193 ret
= iommu_map_page(domain
, iova
, paddr
, prot
, page_size
);
3194 mutex_unlock(&domain
->api_lock
);
3199 static size_t amd_iommu_unmap(struct iommu_domain
*dom
, unsigned long iova
,
3202 struct protection_domain
*domain
= to_pdomain(dom
);
3205 if (domain
->mode
== PAGE_MODE_NONE
)
3208 mutex_lock(&domain
->api_lock
);
3209 unmap_size
= iommu_unmap_page(domain
, iova
, page_size
);
3210 mutex_unlock(&domain
->api_lock
);
3212 domain_flush_tlb_pde(domain
);
3217 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
3220 struct protection_domain
*domain
= to_pdomain(dom
);
3221 unsigned long offset_mask
, pte_pgsize
;
3224 if (domain
->mode
== PAGE_MODE_NONE
)
3227 pte
= fetch_pte(domain
, iova
, &pte_pgsize
);
3229 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
3232 offset_mask
= pte_pgsize
- 1;
3233 __pte
= *pte
& PM_ADDR_MASK
;
3235 return (__pte
& ~offset_mask
) | (iova
& offset_mask
);
3238 static bool amd_iommu_capable(enum iommu_cap cap
)
3241 case IOMMU_CAP_CACHE_COHERENCY
:
3243 case IOMMU_CAP_INTR_REMAP
:
3244 return (irq_remapping_enabled
== 1);
3245 case IOMMU_CAP_NOEXEC
:
3252 static void amd_iommu_get_dm_regions(struct device
*dev
,
3253 struct list_head
*head
)
3255 struct unity_map_entry
*entry
;
3258 devid
= get_device_id(dev
);
3262 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
3263 struct iommu_dm_region
*region
;
3265 if (devid
< entry
->devid_start
|| devid
> entry
->devid_end
)
3268 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
3270 pr_err("Out of memory allocating dm-regions for %s\n",
3275 region
->start
= entry
->address_start
;
3276 region
->length
= entry
->address_end
- entry
->address_start
;
3277 if (entry
->prot
& IOMMU_PROT_IR
)
3278 region
->prot
|= IOMMU_READ
;
3279 if (entry
->prot
& IOMMU_PROT_IW
)
3280 region
->prot
|= IOMMU_WRITE
;
3282 list_add_tail(®ion
->list
, head
);
3286 static void amd_iommu_put_dm_regions(struct device
*dev
,
3287 struct list_head
*head
)
3289 struct iommu_dm_region
*entry
, *next
;
3291 list_for_each_entry_safe(entry
, next
, head
, list
)
3295 static const struct iommu_ops amd_iommu_ops
= {
3296 .capable
= amd_iommu_capable
,
3297 .domain_alloc
= amd_iommu_domain_alloc
,
3298 .domain_free
= amd_iommu_domain_free
,
3299 .attach_dev
= amd_iommu_attach_device
,
3300 .detach_dev
= amd_iommu_detach_device
,
3301 .map
= amd_iommu_map
,
3302 .unmap
= amd_iommu_unmap
,
3303 .map_sg
= default_iommu_map_sg
,
3304 .iova_to_phys
= amd_iommu_iova_to_phys
,
3305 .add_device
= amd_iommu_add_device
,
3306 .remove_device
= amd_iommu_remove_device
,
3307 .device_group
= amd_iommu_device_group
,
3308 .get_dm_regions
= amd_iommu_get_dm_regions
,
3309 .put_dm_regions
= amd_iommu_put_dm_regions
,
3310 .pgsize_bitmap
= AMD_IOMMU_PGSIZES
,
3313 /*****************************************************************************
3315 * The next functions do a basic initialization of IOMMU for pass through
3318 * In passthrough mode the IOMMU is initialized and enabled but not used for
3319 * DMA-API translation.
3321 *****************************************************************************/
3323 /* IOMMUv2 specific functions */
3324 int amd_iommu_register_ppr_notifier(struct notifier_block
*nb
)
3326 return atomic_notifier_chain_register(&ppr_notifier
, nb
);
3328 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier
);
3330 int amd_iommu_unregister_ppr_notifier(struct notifier_block
*nb
)
3332 return atomic_notifier_chain_unregister(&ppr_notifier
, nb
);
3334 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier
);
3336 void amd_iommu_domain_direct_map(struct iommu_domain
*dom
)
3338 struct protection_domain
*domain
= to_pdomain(dom
);
3339 unsigned long flags
;
3341 spin_lock_irqsave(&domain
->lock
, flags
);
3343 /* Update data structure */
3344 domain
->mode
= PAGE_MODE_NONE
;
3345 domain
->updated
= true;
3347 /* Make changes visible to IOMMUs */
3348 update_domain(domain
);
3350 /* Page-table is not visible to IOMMU anymore, so free it */
3351 free_pagetable(domain
);
3353 spin_unlock_irqrestore(&domain
->lock
, flags
);
3355 EXPORT_SYMBOL(amd_iommu_domain_direct_map
);
3357 int amd_iommu_domain_enable_v2(struct iommu_domain
*dom
, int pasids
)
3359 struct protection_domain
*domain
= to_pdomain(dom
);
3360 unsigned long flags
;
3363 if (pasids
<= 0 || pasids
> (PASID_MASK
+ 1))
3366 /* Number of GCR3 table levels required */
3367 for (levels
= 0; (pasids
- 1) & ~0x1ff; pasids
>>= 9)
3370 if (levels
> amd_iommu_max_glx_val
)
3373 spin_lock_irqsave(&domain
->lock
, flags
);
3376 * Save us all sanity checks whether devices already in the
3377 * domain support IOMMUv2. Just force that the domain has no
3378 * devices attached when it is switched into IOMMUv2 mode.
3381 if (domain
->dev_cnt
> 0 || domain
->flags
& PD_IOMMUV2_MASK
)
3385 domain
->gcr3_tbl
= (void *)get_zeroed_page(GFP_ATOMIC
);
3386 if (domain
->gcr3_tbl
== NULL
)
3389 domain
->glx
= levels
;
3390 domain
->flags
|= PD_IOMMUV2_MASK
;
3391 domain
->updated
= true;
3393 update_domain(domain
);
3398 spin_unlock_irqrestore(&domain
->lock
, flags
);
3402 EXPORT_SYMBOL(amd_iommu_domain_enable_v2
);
3404 static int __flush_pasid(struct protection_domain
*domain
, int pasid
,
3405 u64 address
, bool size
)
3407 struct iommu_dev_data
*dev_data
;
3408 struct iommu_cmd cmd
;
3411 if (!(domain
->flags
& PD_IOMMUV2_MASK
))
3414 build_inv_iommu_pasid(&cmd
, domain
->id
, pasid
, address
, size
);
3417 * IOMMU TLB needs to be flushed before Device TLB to
3418 * prevent device TLB refill from IOMMU TLB
3420 for (i
= 0; i
< amd_iommus_present
; ++i
) {
3421 if (domain
->dev_iommu
[i
] == 0)
3424 ret
= iommu_queue_command(amd_iommus
[i
], &cmd
);
3429 /* Wait until IOMMU TLB flushes are complete */
3430 domain_flush_complete(domain
);
3432 /* Now flush device TLBs */
3433 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
3434 struct amd_iommu
*iommu
;
3438 There might be non-IOMMUv2 capable devices in an IOMMUv2
3441 if (!dev_data
->ats
.enabled
)
3444 qdep
= dev_data
->ats
.qdep
;
3445 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3447 build_inv_iotlb_pasid(&cmd
, dev_data
->devid
, pasid
,
3448 qdep
, address
, size
);
3450 ret
= iommu_queue_command(iommu
, &cmd
);
3455 /* Wait until all device TLBs are flushed */
3456 domain_flush_complete(domain
);
3465 static int __amd_iommu_flush_page(struct protection_domain
*domain
, int pasid
,
3468 return __flush_pasid(domain
, pasid
, address
, false);
3471 int amd_iommu_flush_page(struct iommu_domain
*dom
, int pasid
,
3474 struct protection_domain
*domain
= to_pdomain(dom
);
3475 unsigned long flags
;
3478 spin_lock_irqsave(&domain
->lock
, flags
);
3479 ret
= __amd_iommu_flush_page(domain
, pasid
, address
);
3480 spin_unlock_irqrestore(&domain
->lock
, flags
);
3484 EXPORT_SYMBOL(amd_iommu_flush_page
);
3486 static int __amd_iommu_flush_tlb(struct protection_domain
*domain
, int pasid
)
3488 return __flush_pasid(domain
, pasid
, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
3492 int amd_iommu_flush_tlb(struct iommu_domain
*dom
, int pasid
)
3494 struct protection_domain
*domain
= to_pdomain(dom
);
3495 unsigned long flags
;
3498 spin_lock_irqsave(&domain
->lock
, flags
);
3499 ret
= __amd_iommu_flush_tlb(domain
, pasid
);
3500 spin_unlock_irqrestore(&domain
->lock
, flags
);
3504 EXPORT_SYMBOL(amd_iommu_flush_tlb
);
3506 static u64
*__get_gcr3_pte(u64
*root
, int level
, int pasid
, bool alloc
)
3513 index
= (pasid
>> (9 * level
)) & 0x1ff;
3519 if (!(*pte
& GCR3_VALID
)) {
3523 root
= (void *)get_zeroed_page(GFP_ATOMIC
);
3527 *pte
= __pa(root
) | GCR3_VALID
;
3530 root
= __va(*pte
& PAGE_MASK
);
3538 static int __set_gcr3(struct protection_domain
*domain
, int pasid
,
3543 if (domain
->mode
!= PAGE_MODE_NONE
)
3546 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, true);
3550 *pte
= (cr3
& PAGE_MASK
) | GCR3_VALID
;
3552 return __amd_iommu_flush_tlb(domain
, pasid
);
3555 static int __clear_gcr3(struct protection_domain
*domain
, int pasid
)
3559 if (domain
->mode
!= PAGE_MODE_NONE
)
3562 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, false);
3568 return __amd_iommu_flush_tlb(domain
, pasid
);
3571 int amd_iommu_domain_set_gcr3(struct iommu_domain
*dom
, int pasid
,
3574 struct protection_domain
*domain
= to_pdomain(dom
);
3575 unsigned long flags
;
3578 spin_lock_irqsave(&domain
->lock
, flags
);
3579 ret
= __set_gcr3(domain
, pasid
, cr3
);
3580 spin_unlock_irqrestore(&domain
->lock
, flags
);
3584 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3
);
3586 int amd_iommu_domain_clear_gcr3(struct iommu_domain
*dom
, int pasid
)
3588 struct protection_domain
*domain
= to_pdomain(dom
);
3589 unsigned long flags
;
3592 spin_lock_irqsave(&domain
->lock
, flags
);
3593 ret
= __clear_gcr3(domain
, pasid
);
3594 spin_unlock_irqrestore(&domain
->lock
, flags
);
3598 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3
);
3600 int amd_iommu_complete_ppr(struct pci_dev
*pdev
, int pasid
,
3601 int status
, int tag
)
3603 struct iommu_dev_data
*dev_data
;
3604 struct amd_iommu
*iommu
;
3605 struct iommu_cmd cmd
;
3607 dev_data
= get_dev_data(&pdev
->dev
);
3608 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3610 build_complete_ppr(&cmd
, dev_data
->devid
, pasid
, status
,
3611 tag
, dev_data
->pri_tlp
);
3613 return iommu_queue_command(iommu
, &cmd
);
3615 EXPORT_SYMBOL(amd_iommu_complete_ppr
);
3617 struct iommu_domain
*amd_iommu_get_v2_domain(struct pci_dev
*pdev
)
3619 struct protection_domain
*pdomain
;
3621 pdomain
= get_domain(&pdev
->dev
);
3622 if (IS_ERR(pdomain
))
3625 /* Only return IOMMUv2 domains */
3626 if (!(pdomain
->flags
& PD_IOMMUV2_MASK
))
3629 return &pdomain
->domain
;
3631 EXPORT_SYMBOL(amd_iommu_get_v2_domain
);
3633 void amd_iommu_enable_device_erratum(struct pci_dev
*pdev
, u32 erratum
)
3635 struct iommu_dev_data
*dev_data
;
3637 if (!amd_iommu_v2_supported())
3640 dev_data
= get_dev_data(&pdev
->dev
);
3641 dev_data
->errata
|= (1 << erratum
);
3643 EXPORT_SYMBOL(amd_iommu_enable_device_erratum
);
3645 int amd_iommu_device_info(struct pci_dev
*pdev
,
3646 struct amd_iommu_device_info
*info
)
3651 if (pdev
== NULL
|| info
== NULL
)
3654 if (!amd_iommu_v2_supported())
3657 memset(info
, 0, sizeof(*info
));
3659 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ATS
);
3661 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_ATS_SUP
;
3663 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
3665 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRI_SUP
;
3667 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PASID
);
3671 max_pasids
= 1 << (9 * (amd_iommu_max_glx_val
+ 1));
3672 max_pasids
= min(max_pasids
, (1 << 20));
3674 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PASID_SUP
;
3675 info
->max_pasids
= min(pci_max_pasids(pdev
), max_pasids
);
3677 features
= pci_pasid_features(pdev
);
3678 if (features
& PCI_PASID_CAP_EXEC
)
3679 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP
;
3680 if (features
& PCI_PASID_CAP_PRIV
)
3681 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP
;
3686 EXPORT_SYMBOL(amd_iommu_device_info
);
3688 #ifdef CONFIG_IRQ_REMAP
3690 /*****************************************************************************
3692 * Interrupt Remapping Implementation
3694 *****************************************************************************/
3712 u16 devid
; /* Device ID for IRTE table */
3713 u16 index
; /* Index into IRTE table*/
3716 struct amd_ir_data
{
3717 struct irq_2_irte irq_2_irte
;
3718 union irte irte_entry
;
3720 struct msi_msg msi_entry
;
3724 static struct irq_chip amd_ir_chip
;
3726 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3727 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3728 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3729 #define DTE_IRQ_REMAP_ENABLE 1ULL
3731 static void set_dte_irq_entry(u16 devid
, struct irq_remap_table
*table
)
3735 dte
= amd_iommu_dev_table
[devid
].data
[2];
3736 dte
&= ~DTE_IRQ_PHYS_ADDR_MASK
;
3737 dte
|= virt_to_phys(table
->table
);
3738 dte
|= DTE_IRQ_REMAP_INTCTL
;
3739 dte
|= DTE_IRQ_TABLE_LEN
;
3740 dte
|= DTE_IRQ_REMAP_ENABLE
;
3742 amd_iommu_dev_table
[devid
].data
[2] = dte
;
3745 #define IRTE_ALLOCATED (~1U)
3747 static struct irq_remap_table
*get_irq_table(u16 devid
, bool ioapic
)
3749 struct irq_remap_table
*table
= NULL
;
3750 struct amd_iommu
*iommu
;
3751 unsigned long flags
;
3754 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
3756 iommu
= amd_iommu_rlookup_table
[devid
];
3760 table
= irq_lookup_table
[devid
];
3764 alias
= amd_iommu_alias_table
[devid
];
3765 table
= irq_lookup_table
[alias
];
3767 irq_lookup_table
[devid
] = table
;
3768 set_dte_irq_entry(devid
, table
);
3769 iommu_flush_dte(iommu
, devid
);
3773 /* Nothing there yet, allocate new irq remapping table */
3774 table
= kzalloc(sizeof(*table
), GFP_ATOMIC
);
3778 /* Initialize table spin-lock */
3779 spin_lock_init(&table
->lock
);
3782 /* Keep the first 32 indexes free for IOAPIC interrupts */
3783 table
->min_index
= 32;
3785 table
->table
= kmem_cache_alloc(amd_iommu_irq_cache
, GFP_ATOMIC
);
3786 if (!table
->table
) {
3792 memset(table
->table
, 0, MAX_IRQS_PER_TABLE
* sizeof(u32
));
3797 for (i
= 0; i
< 32; ++i
)
3798 table
->table
[i
] = IRTE_ALLOCATED
;
3801 irq_lookup_table
[devid
] = table
;
3802 set_dte_irq_entry(devid
, table
);
3803 iommu_flush_dte(iommu
, devid
);
3804 if (devid
!= alias
) {
3805 irq_lookup_table
[alias
] = table
;
3806 set_dte_irq_entry(alias
, table
);
3807 iommu_flush_dte(iommu
, alias
);
3811 iommu_completion_wait(iommu
);
3814 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
3819 static int alloc_irq_index(u16 devid
, int count
)
3821 struct irq_remap_table
*table
;
3822 unsigned long flags
;
3825 table
= get_irq_table(devid
, false);
3829 spin_lock_irqsave(&table
->lock
, flags
);
3831 /* Scan table for free entries */
3832 for (c
= 0, index
= table
->min_index
;
3833 index
< MAX_IRQS_PER_TABLE
;
3835 if (table
->table
[index
] == 0)
3842 table
->table
[index
- c
+ 1] = IRTE_ALLOCATED
;
3852 spin_unlock_irqrestore(&table
->lock
, flags
);
3857 static int modify_irte(u16 devid
, int index
, union irte irte
)
3859 struct irq_remap_table
*table
;
3860 struct amd_iommu
*iommu
;
3861 unsigned long flags
;
3863 iommu
= amd_iommu_rlookup_table
[devid
];
3867 table
= get_irq_table(devid
, false);
3871 spin_lock_irqsave(&table
->lock
, flags
);
3872 table
->table
[index
] = irte
.val
;
3873 spin_unlock_irqrestore(&table
->lock
, flags
);
3875 iommu_flush_irt(iommu
, devid
);
3876 iommu_completion_wait(iommu
);
3881 static void free_irte(u16 devid
, int index
)
3883 struct irq_remap_table
*table
;
3884 struct amd_iommu
*iommu
;
3885 unsigned long flags
;
3887 iommu
= amd_iommu_rlookup_table
[devid
];
3891 table
= get_irq_table(devid
, false);
3895 spin_lock_irqsave(&table
->lock
, flags
);
3896 table
->table
[index
] = 0;
3897 spin_unlock_irqrestore(&table
->lock
, flags
);
3899 iommu_flush_irt(iommu
, devid
);
3900 iommu_completion_wait(iommu
);
3903 static int get_devid(struct irq_alloc_info
*info
)
3907 switch (info
->type
) {
3908 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
3909 devid
= get_ioapic_devid(info
->ioapic_id
);
3911 case X86_IRQ_ALLOC_TYPE_HPET
:
3912 devid
= get_hpet_devid(info
->hpet_id
);
3914 case X86_IRQ_ALLOC_TYPE_MSI
:
3915 case X86_IRQ_ALLOC_TYPE_MSIX
:
3916 devid
= get_device_id(&info
->msi_dev
->dev
);
3926 static struct irq_domain
*get_ir_irq_domain(struct irq_alloc_info
*info
)
3928 struct amd_iommu
*iommu
;
3934 devid
= get_devid(info
);
3936 iommu
= amd_iommu_rlookup_table
[devid
];
3938 return iommu
->ir_domain
;
3944 static struct irq_domain
*get_irq_domain(struct irq_alloc_info
*info
)
3946 struct amd_iommu
*iommu
;
3952 switch (info
->type
) {
3953 case X86_IRQ_ALLOC_TYPE_MSI
:
3954 case X86_IRQ_ALLOC_TYPE_MSIX
:
3955 devid
= get_device_id(&info
->msi_dev
->dev
);
3959 iommu
= amd_iommu_rlookup_table
[devid
];
3961 return iommu
->msi_domain
;
3970 struct irq_remap_ops amd_iommu_irq_ops
= {
3971 .prepare
= amd_iommu_prepare
,
3972 .enable
= amd_iommu_enable
,
3973 .disable
= amd_iommu_disable
,
3974 .reenable
= amd_iommu_reenable
,
3975 .enable_faulting
= amd_iommu_enable_faulting
,
3976 .get_ir_irq_domain
= get_ir_irq_domain
,
3977 .get_irq_domain
= get_irq_domain
,
3980 static void irq_remapping_prepare_irte(struct amd_ir_data
*data
,
3981 struct irq_cfg
*irq_cfg
,
3982 struct irq_alloc_info
*info
,
3983 int devid
, int index
, int sub_handle
)
3985 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
3986 struct msi_msg
*msg
= &data
->msi_entry
;
3987 union irte
*irte
= &data
->irte_entry
;
3988 struct IO_APIC_route_entry
*entry
;
3990 data
->irq_2_irte
.devid
= devid
;
3991 data
->irq_2_irte
.index
= index
+ sub_handle
;
3993 /* Setup IRTE for IOMMU */
3995 irte
->fields
.vector
= irq_cfg
->vector
;
3996 irte
->fields
.int_type
= apic
->irq_delivery_mode
;
3997 irte
->fields
.destination
= irq_cfg
->dest_apicid
;
3998 irte
->fields
.dm
= apic
->irq_dest_mode
;
3999 irte
->fields
.valid
= 1;
4001 switch (info
->type
) {
4002 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
4003 /* Setup IOAPIC entry */
4004 entry
= info
->ioapic_entry
;
4005 info
->ioapic_entry
= NULL
;
4006 memset(entry
, 0, sizeof(*entry
));
4007 entry
->vector
= index
;
4009 entry
->trigger
= info
->ioapic_trigger
;
4010 entry
->polarity
= info
->ioapic_polarity
;
4011 /* Mask level triggered irqs. */
4012 if (info
->ioapic_trigger
)
4016 case X86_IRQ_ALLOC_TYPE_HPET
:
4017 case X86_IRQ_ALLOC_TYPE_MSI
:
4018 case X86_IRQ_ALLOC_TYPE_MSIX
:
4019 msg
->address_hi
= MSI_ADDR_BASE_HI
;
4020 msg
->address_lo
= MSI_ADDR_BASE_LO
;
4021 msg
->data
= irte_info
->index
;
4030 static int irq_remapping_alloc(struct irq_domain
*domain
, unsigned int virq
,
4031 unsigned int nr_irqs
, void *arg
)
4033 struct irq_alloc_info
*info
= arg
;
4034 struct irq_data
*irq_data
;
4035 struct amd_ir_data
*data
;
4036 struct irq_cfg
*cfg
;
4042 if (nr_irqs
> 1 && info
->type
!= X86_IRQ_ALLOC_TYPE_MSI
&&
4043 info
->type
!= X86_IRQ_ALLOC_TYPE_MSIX
)
4047 * With IRQ remapping enabled, don't need contiguous CPU vectors
4048 * to support multiple MSI interrupts.
4050 if (info
->type
== X86_IRQ_ALLOC_TYPE_MSI
)
4051 info
->flags
&= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS
;
4053 devid
= get_devid(info
);
4057 ret
= irq_domain_alloc_irqs_parent(domain
, virq
, nr_irqs
, arg
);
4061 if (info
->type
== X86_IRQ_ALLOC_TYPE_IOAPIC
) {
4062 if (get_irq_table(devid
, true))
4063 index
= info
->ioapic_pin
;
4067 index
= alloc_irq_index(devid
, nr_irqs
);
4070 pr_warn("Failed to allocate IRTE\n");
4071 goto out_free_parent
;
4074 for (i
= 0; i
< nr_irqs
; i
++) {
4075 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4076 cfg
= irqd_cfg(irq_data
);
4077 if (!irq_data
|| !cfg
) {
4083 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
4087 irq_data
->hwirq
= (devid
<< 16) + i
;
4088 irq_data
->chip_data
= data
;
4089 irq_data
->chip
= &amd_ir_chip
;
4090 irq_remapping_prepare_irte(data
, cfg
, info
, devid
, index
, i
);
4091 irq_set_status_flags(virq
+ i
, IRQ_MOVE_PCNTXT
);
4097 for (i
--; i
>= 0; i
--) {
4098 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4100 kfree(irq_data
->chip_data
);
4102 for (i
= 0; i
< nr_irqs
; i
++)
4103 free_irte(devid
, index
+ i
);
4105 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4109 static void irq_remapping_free(struct irq_domain
*domain
, unsigned int virq
,
4110 unsigned int nr_irqs
)
4112 struct irq_2_irte
*irte_info
;
4113 struct irq_data
*irq_data
;
4114 struct amd_ir_data
*data
;
4117 for (i
= 0; i
< nr_irqs
; i
++) {
4118 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4119 if (irq_data
&& irq_data
->chip_data
) {
4120 data
= irq_data
->chip_data
;
4121 irte_info
= &data
->irq_2_irte
;
4122 free_irte(irte_info
->devid
, irte_info
->index
);
4126 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4129 static void irq_remapping_activate(struct irq_domain
*domain
,
4130 struct irq_data
*irq_data
)
4132 struct amd_ir_data
*data
= irq_data
->chip_data
;
4133 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4135 modify_irte(irte_info
->devid
, irte_info
->index
, data
->irte_entry
);
4138 static void irq_remapping_deactivate(struct irq_domain
*domain
,
4139 struct irq_data
*irq_data
)
4141 struct amd_ir_data
*data
= irq_data
->chip_data
;
4142 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4146 modify_irte(irte_info
->devid
, irte_info
->index
, data
->irte_entry
);
4149 static struct irq_domain_ops amd_ir_domain_ops
= {
4150 .alloc
= irq_remapping_alloc
,
4151 .free
= irq_remapping_free
,
4152 .activate
= irq_remapping_activate
,
4153 .deactivate
= irq_remapping_deactivate
,
4156 static int amd_ir_set_affinity(struct irq_data
*data
,
4157 const struct cpumask
*mask
, bool force
)
4159 struct amd_ir_data
*ir_data
= data
->chip_data
;
4160 struct irq_2_irte
*irte_info
= &ir_data
->irq_2_irte
;
4161 struct irq_cfg
*cfg
= irqd_cfg(data
);
4162 struct irq_data
*parent
= data
->parent_data
;
4165 ret
= parent
->chip
->irq_set_affinity(parent
, mask
, force
);
4166 if (ret
< 0 || ret
== IRQ_SET_MASK_OK_DONE
)
4170 * Atomically updates the IRTE with the new destination, vector
4171 * and flushes the interrupt entry cache.
4173 ir_data
->irte_entry
.fields
.vector
= cfg
->vector
;
4174 ir_data
->irte_entry
.fields
.destination
= cfg
->dest_apicid
;
4175 modify_irte(irte_info
->devid
, irte_info
->index
, ir_data
->irte_entry
);
4178 * After this point, all the interrupts will start arriving
4179 * at the new destination. So, time to cleanup the previous
4180 * vector allocation.
4182 send_cleanup_vector(cfg
);
4184 return IRQ_SET_MASK_OK_DONE
;
4187 static void ir_compose_msi_msg(struct irq_data
*irq_data
, struct msi_msg
*msg
)
4189 struct amd_ir_data
*ir_data
= irq_data
->chip_data
;
4191 *msg
= ir_data
->msi_entry
;
4194 static struct irq_chip amd_ir_chip
= {
4195 .irq_ack
= ir_ack_apic_edge
,
4196 .irq_set_affinity
= amd_ir_set_affinity
,
4197 .irq_compose_msi_msg
= ir_compose_msi_msg
,
4200 int amd_iommu_create_irq_domain(struct amd_iommu
*iommu
)
4202 iommu
->ir_domain
= irq_domain_add_tree(NULL
, &amd_ir_domain_ops
, iommu
);
4203 if (!iommu
->ir_domain
)
4206 iommu
->ir_domain
->parent
= arch_get_ir_parent_domain();
4207 iommu
->msi_domain
= arch_create_msi_irq_domain(iommu
->ir_domain
);