2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <linux/dma-contiguous.h>
37 #include <asm/irq_remapping.h>
38 #include <asm/io_apic.h>
40 #include <asm/hw_irq.h>
41 #include <asm/msidef.h>
42 #include <asm/proto.h>
43 #include <asm/iommu.h>
47 #include "amd_iommu_proto.h"
48 #include "amd_iommu_types.h"
49 #include "irq_remapping.h"
51 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
53 #define LOOP_TIMEOUT 100000
56 * This bitmap is used to advertise the page sizes our hardware support
57 * to the IOMMU core, which will then use this information to split
58 * physically contiguous memory regions it is mapping into page sizes
61 * 512GB Pages are not supported due to a hardware bug
63 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
65 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
67 /* A list of preallocated protection domains */
68 static LIST_HEAD(iommu_pd_list
);
69 static DEFINE_SPINLOCK(iommu_pd_list_lock
);
71 /* List of all available dev_data structures */
72 static LIST_HEAD(dev_data_list
);
73 static DEFINE_SPINLOCK(dev_data_list_lock
);
75 LIST_HEAD(ioapic_map
);
79 * Domain for untranslated devices - only allocated
80 * if iommu=pt passed on kernel cmd line.
82 static struct protection_domain
*pt_domain
;
84 static const struct iommu_ops amd_iommu_ops
;
86 static ATOMIC_NOTIFIER_HEAD(ppr_notifier
);
87 int amd_iommu_max_glx_val
= -1;
89 static struct dma_map_ops amd_iommu_dma_ops
;
92 * This struct contains device specific data for the IOMMU
94 struct iommu_dev_data
{
95 struct list_head list
; /* For domain->dev_list */
96 struct list_head dev_data_list
; /* For global dev_data_list */
97 struct list_head alias_list
; /* Link alias-groups together */
98 struct iommu_dev_data
*alias_data
;/* The alias dev_data */
99 struct protection_domain
*domain
; /* Domain the device is bound to */
100 u16 devid
; /* PCI Device ID */
101 bool iommu_v2
; /* Device can make use of IOMMUv2 */
102 bool passthrough
; /* Default for device is pt_domain */
106 } ats
; /* ATS state */
107 bool pri_tlp
; /* PASID TLB required for
109 u32 errata
; /* Bitmap for errata to apply */
113 * general struct to manage commands send to an IOMMU
119 struct kmem_cache
*amd_iommu_irq_cache
;
121 static void update_domain(struct protection_domain
*domain
);
122 static int __init
alloc_passthrough_domain(void);
124 /****************************************************************************
128 ****************************************************************************/
130 static struct protection_domain
*to_pdomain(struct iommu_domain
*dom
)
132 return container_of(dom
, struct protection_domain
, domain
);
135 static struct iommu_dev_data
*alloc_dev_data(u16 devid
)
137 struct iommu_dev_data
*dev_data
;
140 dev_data
= kzalloc(sizeof(*dev_data
), GFP_KERNEL
);
144 INIT_LIST_HEAD(&dev_data
->alias_list
);
146 dev_data
->devid
= devid
;
148 spin_lock_irqsave(&dev_data_list_lock
, flags
);
149 list_add_tail(&dev_data
->dev_data_list
, &dev_data_list
);
150 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
155 static void free_dev_data(struct iommu_dev_data
*dev_data
)
159 spin_lock_irqsave(&dev_data_list_lock
, flags
);
160 list_del(&dev_data
->dev_data_list
);
161 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
166 static struct iommu_dev_data
*search_dev_data(u16 devid
)
168 struct iommu_dev_data
*dev_data
;
171 spin_lock_irqsave(&dev_data_list_lock
, flags
);
172 list_for_each_entry(dev_data
, &dev_data_list
, dev_data_list
) {
173 if (dev_data
->devid
== devid
)
180 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
185 static struct iommu_dev_data
*find_dev_data(u16 devid
)
187 struct iommu_dev_data
*dev_data
;
189 dev_data
= search_dev_data(devid
);
191 if (dev_data
== NULL
)
192 dev_data
= alloc_dev_data(devid
);
197 static inline u16
get_device_id(struct device
*dev
)
199 struct pci_dev
*pdev
= to_pci_dev(dev
);
201 return PCI_DEVID(pdev
->bus
->number
, pdev
->devfn
);
204 static struct iommu_dev_data
*get_dev_data(struct device
*dev
)
206 return dev
->archdata
.iommu
;
209 static bool pci_iommuv2_capable(struct pci_dev
*pdev
)
211 static const int caps
[] = {
214 PCI_EXT_CAP_ID_PASID
,
218 for (i
= 0; i
< 3; ++i
) {
219 pos
= pci_find_ext_capability(pdev
, caps
[i
]);
227 static bool pdev_pri_erratum(struct pci_dev
*pdev
, u32 erratum
)
229 struct iommu_dev_data
*dev_data
;
231 dev_data
= get_dev_data(&pdev
->dev
);
233 return dev_data
->errata
& (1 << erratum
) ? true : false;
237 * In this function the list of preallocated protection domains is traversed to
238 * find the domain for a specific device
240 static struct dma_ops_domain
*find_protection_domain(u16 devid
)
242 struct dma_ops_domain
*entry
, *ret
= NULL
;
244 u16 alias
= amd_iommu_alias_table
[devid
];
246 if (list_empty(&iommu_pd_list
))
249 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
251 list_for_each_entry(entry
, &iommu_pd_list
, list
) {
252 if (entry
->target_dev
== devid
||
253 entry
->target_dev
== alias
) {
259 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
265 * This function checks if the driver got a valid device from the caller to
266 * avoid dereferencing invalid pointers.
268 static bool check_device(struct device
*dev
)
272 if (!dev
|| !dev
->dma_mask
)
276 if (!dev_is_pci(dev
))
279 devid
= get_device_id(dev
);
281 /* Out of our scope? */
282 if (devid
> amd_iommu_last_bdf
)
285 if (amd_iommu_rlookup_table
[devid
] == NULL
)
291 static void init_iommu_group(struct device
*dev
)
293 struct iommu_group
*group
;
295 group
= iommu_group_get_for_dev(dev
);
297 iommu_group_put(group
);
300 static int __last_alias(struct pci_dev
*pdev
, u16 alias
, void *data
)
302 *(u16
*)data
= alias
;
306 static u16
get_alias(struct device
*dev
)
308 struct pci_dev
*pdev
= to_pci_dev(dev
);
309 u16 devid
, ivrs_alias
, pci_alias
;
311 devid
= get_device_id(dev
);
312 ivrs_alias
= amd_iommu_alias_table
[devid
];
313 pci_for_each_dma_alias(pdev
, __last_alias
, &pci_alias
);
315 if (ivrs_alias
== pci_alias
)
321 * The IVRS is fairly reliable in telling us about aliases, but it
322 * can't know about every screwy device. If we don't have an IVRS
323 * reported alias, use the PCI reported alias. In that case we may
324 * still need to initialize the rlookup and dev_table entries if the
325 * alias is to a non-existent device.
327 if (ivrs_alias
== devid
) {
328 if (!amd_iommu_rlookup_table
[pci_alias
]) {
329 amd_iommu_rlookup_table
[pci_alias
] =
330 amd_iommu_rlookup_table
[devid
];
331 memcpy(amd_iommu_dev_table
[pci_alias
].data
,
332 amd_iommu_dev_table
[devid
].data
,
333 sizeof(amd_iommu_dev_table
[pci_alias
].data
));
339 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
340 "for device %s[%04x:%04x], kernel reported alias "
341 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias
), PCI_SLOT(ivrs_alias
),
342 PCI_FUNC(ivrs_alias
), dev_name(dev
), pdev
->vendor
, pdev
->device
,
343 PCI_BUS_NUM(pci_alias
), PCI_SLOT(pci_alias
),
344 PCI_FUNC(pci_alias
));
347 * If we don't have a PCI DMA alias and the IVRS alias is on the same
348 * bus, then the IVRS table may know about a quirk that we don't.
350 if (pci_alias
== devid
&&
351 PCI_BUS_NUM(ivrs_alias
) == pdev
->bus
->number
) {
352 pdev
->dev_flags
|= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN
;
353 pdev
->dma_alias_devfn
= ivrs_alias
& 0xff;
354 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
355 PCI_SLOT(ivrs_alias
), PCI_FUNC(ivrs_alias
),
362 static int iommu_init_device(struct device
*dev
)
364 struct pci_dev
*pdev
= to_pci_dev(dev
);
365 struct iommu_dev_data
*dev_data
;
368 if (dev
->archdata
.iommu
)
371 dev_data
= find_dev_data(get_device_id(dev
));
375 alias
= get_alias(dev
);
377 if (alias
!= dev_data
->devid
) {
378 struct iommu_dev_data
*alias_data
;
380 alias_data
= find_dev_data(alias
);
381 if (alias_data
== NULL
) {
382 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
384 free_dev_data(dev_data
);
387 dev_data
->alias_data
= alias_data
;
389 /* Add device to the alias_list */
390 list_add(&dev_data
->alias_list
, &alias_data
->alias_list
);
393 if (pci_iommuv2_capable(pdev
)) {
394 struct amd_iommu
*iommu
;
396 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
397 dev_data
->iommu_v2
= iommu
->is_iommu_v2
;
400 dev
->archdata
.iommu
= dev_data
;
402 iommu_device_link(amd_iommu_rlookup_table
[dev_data
->devid
]->iommu_dev
,
408 static void iommu_ignore_device(struct device
*dev
)
412 devid
= get_device_id(dev
);
413 alias
= amd_iommu_alias_table
[devid
];
415 memset(&amd_iommu_dev_table
[devid
], 0, sizeof(struct dev_table_entry
));
416 memset(&amd_iommu_dev_table
[alias
], 0, sizeof(struct dev_table_entry
));
418 amd_iommu_rlookup_table
[devid
] = NULL
;
419 amd_iommu_rlookup_table
[alias
] = NULL
;
422 static void iommu_uninit_device(struct device
*dev
)
424 struct iommu_dev_data
*dev_data
= search_dev_data(get_device_id(dev
));
429 iommu_device_unlink(amd_iommu_rlookup_table
[dev_data
->devid
]->iommu_dev
,
432 iommu_group_remove_device(dev
);
434 /* Unlink from alias, it may change if another device is re-plugged */
435 dev_data
->alias_data
= NULL
;
438 * We keep dev_data around for unplugged devices and reuse it when the
439 * device is re-plugged - not doing so would introduce a ton of races.
443 void __init
amd_iommu_uninit_devices(void)
445 struct iommu_dev_data
*dev_data
, *n
;
446 struct pci_dev
*pdev
= NULL
;
448 for_each_pci_dev(pdev
) {
450 if (!check_device(&pdev
->dev
))
453 iommu_uninit_device(&pdev
->dev
);
456 /* Free all of our dev_data structures */
457 list_for_each_entry_safe(dev_data
, n
, &dev_data_list
, dev_data_list
)
458 free_dev_data(dev_data
);
461 int __init
amd_iommu_init_devices(void)
463 struct pci_dev
*pdev
= NULL
;
466 for_each_pci_dev(pdev
) {
468 if (!check_device(&pdev
->dev
))
471 ret
= iommu_init_device(&pdev
->dev
);
472 if (ret
== -ENOTSUPP
)
473 iommu_ignore_device(&pdev
->dev
);
479 * Initialize IOMMU groups only after iommu_init_device() has
480 * had a chance to populate any IVRS defined aliases.
482 for_each_pci_dev(pdev
) {
483 if (check_device(&pdev
->dev
))
484 init_iommu_group(&pdev
->dev
);
491 amd_iommu_uninit_devices();
495 #ifdef CONFIG_AMD_IOMMU_STATS
498 * Initialization code for statistics collection
501 DECLARE_STATS_COUNTER(compl_wait
);
502 DECLARE_STATS_COUNTER(cnt_map_single
);
503 DECLARE_STATS_COUNTER(cnt_unmap_single
);
504 DECLARE_STATS_COUNTER(cnt_map_sg
);
505 DECLARE_STATS_COUNTER(cnt_unmap_sg
);
506 DECLARE_STATS_COUNTER(cnt_alloc_coherent
);
507 DECLARE_STATS_COUNTER(cnt_free_coherent
);
508 DECLARE_STATS_COUNTER(cross_page
);
509 DECLARE_STATS_COUNTER(domain_flush_single
);
510 DECLARE_STATS_COUNTER(domain_flush_all
);
511 DECLARE_STATS_COUNTER(alloced_io_mem
);
512 DECLARE_STATS_COUNTER(total_map_requests
);
513 DECLARE_STATS_COUNTER(complete_ppr
);
514 DECLARE_STATS_COUNTER(invalidate_iotlb
);
515 DECLARE_STATS_COUNTER(invalidate_iotlb_all
);
516 DECLARE_STATS_COUNTER(pri_requests
);
518 static struct dentry
*stats_dir
;
519 static struct dentry
*de_fflush
;
521 static void amd_iommu_stats_add(struct __iommu_counter
*cnt
)
523 if (stats_dir
== NULL
)
526 cnt
->dent
= debugfs_create_u64(cnt
->name
, 0444, stats_dir
,
530 static void amd_iommu_stats_init(void)
532 stats_dir
= debugfs_create_dir("amd-iommu", NULL
);
533 if (stats_dir
== NULL
)
536 de_fflush
= debugfs_create_bool("fullflush", 0444, stats_dir
,
537 &amd_iommu_unmap_flush
);
539 amd_iommu_stats_add(&compl_wait
);
540 amd_iommu_stats_add(&cnt_map_single
);
541 amd_iommu_stats_add(&cnt_unmap_single
);
542 amd_iommu_stats_add(&cnt_map_sg
);
543 amd_iommu_stats_add(&cnt_unmap_sg
);
544 amd_iommu_stats_add(&cnt_alloc_coherent
);
545 amd_iommu_stats_add(&cnt_free_coherent
);
546 amd_iommu_stats_add(&cross_page
);
547 amd_iommu_stats_add(&domain_flush_single
);
548 amd_iommu_stats_add(&domain_flush_all
);
549 amd_iommu_stats_add(&alloced_io_mem
);
550 amd_iommu_stats_add(&total_map_requests
);
551 amd_iommu_stats_add(&complete_ppr
);
552 amd_iommu_stats_add(&invalidate_iotlb
);
553 amd_iommu_stats_add(&invalidate_iotlb_all
);
554 amd_iommu_stats_add(&pri_requests
);
559 /****************************************************************************
561 * Interrupt handling functions
563 ****************************************************************************/
565 static void dump_dte_entry(u16 devid
)
569 for (i
= 0; i
< 4; ++i
)
570 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i
,
571 amd_iommu_dev_table
[devid
].data
[i
]);
574 static void dump_command(unsigned long phys_addr
)
576 struct iommu_cmd
*cmd
= phys_to_virt(phys_addr
);
579 for (i
= 0; i
< 4; ++i
)
580 pr_err("AMD-Vi: CMD[%d]: %08x\n", i
, cmd
->data
[i
]);
583 static void iommu_print_event(struct amd_iommu
*iommu
, void *__evt
)
585 int type
, devid
, domid
, flags
;
586 volatile u32
*event
= __evt
;
591 type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
592 devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
593 domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
594 flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
595 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
598 /* Did we hit the erratum? */
599 if (++count
== LOOP_TIMEOUT
) {
600 pr_err("AMD-Vi: No event written to event log\n");
607 printk(KERN_ERR
"AMD-Vi: Event logged [");
610 case EVENT_TYPE_ILL_DEV
:
611 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
612 "address=0x%016llx flags=0x%04x]\n",
613 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
615 dump_dte_entry(devid
);
617 case EVENT_TYPE_IO_FAULT
:
618 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
619 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
620 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
621 domid
, address
, flags
);
623 case EVENT_TYPE_DEV_TAB_ERR
:
624 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
625 "address=0x%016llx flags=0x%04x]\n",
626 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
629 case EVENT_TYPE_PAGE_TAB_ERR
:
630 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
631 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
632 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
633 domid
, address
, flags
);
635 case EVENT_TYPE_ILL_CMD
:
636 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
637 dump_command(address
);
639 case EVENT_TYPE_CMD_HARD_ERR
:
640 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
641 "flags=0x%04x]\n", address
, flags
);
643 case EVENT_TYPE_IOTLB_INV_TO
:
644 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
645 "address=0x%016llx]\n",
646 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
649 case EVENT_TYPE_INV_DEV_REQ
:
650 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
651 "address=0x%016llx flags=0x%04x]\n",
652 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
656 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
659 memset(__evt
, 0, 4 * sizeof(u32
));
662 static void iommu_poll_events(struct amd_iommu
*iommu
)
666 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
667 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
669 while (head
!= tail
) {
670 iommu_print_event(iommu
, iommu
->evt_buf
+ head
);
671 head
= (head
+ EVENT_ENTRY_SIZE
) % iommu
->evt_buf_size
;
674 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
677 static void iommu_handle_ppr_entry(struct amd_iommu
*iommu
, u64
*raw
)
679 struct amd_iommu_fault fault
;
681 INC_STATS_COUNTER(pri_requests
);
683 if (PPR_REQ_TYPE(raw
[0]) != PPR_REQ_FAULT
) {
684 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
688 fault
.address
= raw
[1];
689 fault
.pasid
= PPR_PASID(raw
[0]);
690 fault
.device_id
= PPR_DEVID(raw
[0]);
691 fault
.tag
= PPR_TAG(raw
[0]);
692 fault
.flags
= PPR_FLAGS(raw
[0]);
694 atomic_notifier_call_chain(&ppr_notifier
, 0, &fault
);
697 static void iommu_poll_ppr_log(struct amd_iommu
*iommu
)
701 if (iommu
->ppr_log
== NULL
)
704 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
705 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
707 while (head
!= tail
) {
712 raw
= (u64
*)(iommu
->ppr_log
+ head
);
715 * Hardware bug: Interrupt may arrive before the entry is
716 * written to memory. If this happens we need to wait for the
719 for (i
= 0; i
< LOOP_TIMEOUT
; ++i
) {
720 if (PPR_REQ_TYPE(raw
[0]) != 0)
725 /* Avoid memcpy function-call overhead */
730 * To detect the hardware bug we need to clear the entry
733 raw
[0] = raw
[1] = 0UL;
735 /* Update head pointer of hardware ring-buffer */
736 head
= (head
+ PPR_ENTRY_SIZE
) % PPR_LOG_SIZE
;
737 writel(head
, iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
739 /* Handle PPR entry */
740 iommu_handle_ppr_entry(iommu
, entry
);
742 /* Refresh ring-buffer information */
743 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
744 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
748 irqreturn_t
amd_iommu_int_thread(int irq
, void *data
)
750 struct amd_iommu
*iommu
= (struct amd_iommu
*) data
;
751 u32 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
753 while (status
& (MMIO_STATUS_EVT_INT_MASK
| MMIO_STATUS_PPR_INT_MASK
)) {
754 /* Enable EVT and PPR interrupts again */
755 writel((MMIO_STATUS_EVT_INT_MASK
| MMIO_STATUS_PPR_INT_MASK
),
756 iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
758 if (status
& MMIO_STATUS_EVT_INT_MASK
) {
759 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
760 iommu_poll_events(iommu
);
763 if (status
& MMIO_STATUS_PPR_INT_MASK
) {
764 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
765 iommu_poll_ppr_log(iommu
);
769 * Hardware bug: ERBT1312
770 * When re-enabling interrupt (by writing 1
771 * to clear the bit), the hardware might also try to set
772 * the interrupt bit in the event status register.
773 * In this scenario, the bit will be set, and disable
774 * subsequent interrupts.
776 * Workaround: The IOMMU driver should read back the
777 * status register and check if the interrupt bits are cleared.
778 * If not, driver will need to go through the interrupt handler
779 * again and re-clear the bits
781 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
786 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
788 return IRQ_WAKE_THREAD
;
791 /****************************************************************************
793 * IOMMU command queuing functions
795 ****************************************************************************/
797 static int wait_on_sem(volatile u64
*sem
)
801 while (*sem
== 0 && i
< LOOP_TIMEOUT
) {
806 if (i
== LOOP_TIMEOUT
) {
807 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
814 static void copy_cmd_to_buffer(struct amd_iommu
*iommu
,
815 struct iommu_cmd
*cmd
,
820 target
= iommu
->cmd_buf
+ tail
;
821 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
823 /* Copy command to buffer */
824 memcpy(target
, cmd
, sizeof(*cmd
));
826 /* Tell the IOMMU about it */
827 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
830 static void build_completion_wait(struct iommu_cmd
*cmd
, u64 address
)
832 WARN_ON(address
& 0x7ULL
);
834 memset(cmd
, 0, sizeof(*cmd
));
835 cmd
->data
[0] = lower_32_bits(__pa(address
)) | CMD_COMPL_WAIT_STORE_MASK
;
836 cmd
->data
[1] = upper_32_bits(__pa(address
));
838 CMD_SET_TYPE(cmd
, CMD_COMPL_WAIT
);
841 static void build_inv_dte(struct iommu_cmd
*cmd
, u16 devid
)
843 memset(cmd
, 0, sizeof(*cmd
));
844 cmd
->data
[0] = devid
;
845 CMD_SET_TYPE(cmd
, CMD_INV_DEV_ENTRY
);
848 static void build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
849 size_t size
, u16 domid
, int pde
)
854 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
859 * If we have to flush more than one page, flush all
860 * TLB entries for this domain
862 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
866 address
&= PAGE_MASK
;
868 memset(cmd
, 0, sizeof(*cmd
));
869 cmd
->data
[1] |= domid
;
870 cmd
->data
[2] = lower_32_bits(address
);
871 cmd
->data
[3] = upper_32_bits(address
);
872 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
873 if (s
) /* size bit - we flush more than one 4kb page */
874 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
875 if (pde
) /* PDE bit - we want to flush everything, not only the PTEs */
876 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
879 static void build_inv_iotlb_pages(struct iommu_cmd
*cmd
, u16 devid
, int qdep
,
880 u64 address
, size_t size
)
885 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
890 * If we have to flush more than one page, flush all
891 * TLB entries for this domain
893 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
897 address
&= PAGE_MASK
;
899 memset(cmd
, 0, sizeof(*cmd
));
900 cmd
->data
[0] = devid
;
901 cmd
->data
[0] |= (qdep
& 0xff) << 24;
902 cmd
->data
[1] = devid
;
903 cmd
->data
[2] = lower_32_bits(address
);
904 cmd
->data
[3] = upper_32_bits(address
);
905 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
907 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
910 static void build_inv_iommu_pasid(struct iommu_cmd
*cmd
, u16 domid
, int pasid
,
911 u64 address
, bool size
)
913 memset(cmd
, 0, sizeof(*cmd
));
915 address
&= ~(0xfffULL
);
917 cmd
->data
[0] = pasid
;
918 cmd
->data
[1] = domid
;
919 cmd
->data
[2] = lower_32_bits(address
);
920 cmd
->data
[3] = upper_32_bits(address
);
921 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
922 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
924 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
925 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
928 static void build_inv_iotlb_pasid(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
929 int qdep
, u64 address
, bool size
)
931 memset(cmd
, 0, sizeof(*cmd
));
933 address
&= ~(0xfffULL
);
935 cmd
->data
[0] = devid
;
936 cmd
->data
[0] |= ((pasid
>> 8) & 0xff) << 16;
937 cmd
->data
[0] |= (qdep
& 0xff) << 24;
938 cmd
->data
[1] = devid
;
939 cmd
->data
[1] |= (pasid
& 0xff) << 16;
940 cmd
->data
[2] = lower_32_bits(address
);
941 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
942 cmd
->data
[3] = upper_32_bits(address
);
944 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
945 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
948 static void build_complete_ppr(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
949 int status
, int tag
, bool gn
)
951 memset(cmd
, 0, sizeof(*cmd
));
953 cmd
->data
[0] = devid
;
955 cmd
->data
[1] = pasid
;
956 cmd
->data
[2] = CMD_INV_IOMMU_PAGES_GN_MASK
;
958 cmd
->data
[3] = tag
& 0x1ff;
959 cmd
->data
[3] |= (status
& PPR_STATUS_MASK
) << PPR_STATUS_SHIFT
;
961 CMD_SET_TYPE(cmd
, CMD_COMPLETE_PPR
);
964 static void build_inv_all(struct iommu_cmd
*cmd
)
966 memset(cmd
, 0, sizeof(*cmd
));
967 CMD_SET_TYPE(cmd
, CMD_INV_ALL
);
970 static void build_inv_irt(struct iommu_cmd
*cmd
, u16 devid
)
972 memset(cmd
, 0, sizeof(*cmd
));
973 cmd
->data
[0] = devid
;
974 CMD_SET_TYPE(cmd
, CMD_INV_IRT
);
978 * Writes the command to the IOMMUs command buffer and informs the
979 * hardware about the new command.
981 static int iommu_queue_command_sync(struct amd_iommu
*iommu
,
982 struct iommu_cmd
*cmd
,
985 u32 left
, tail
, head
, next_tail
;
988 WARN_ON(iommu
->cmd_buf_size
& CMD_BUFFER_UNINITIALIZED
);
991 spin_lock_irqsave(&iommu
->lock
, flags
);
993 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
994 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
995 next_tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
996 left
= (head
- next_tail
) % iommu
->cmd_buf_size
;
999 struct iommu_cmd sync_cmd
;
1000 volatile u64 sem
= 0;
1003 build_completion_wait(&sync_cmd
, (u64
)&sem
);
1004 copy_cmd_to_buffer(iommu
, &sync_cmd
, tail
);
1006 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1008 if ((ret
= wait_on_sem(&sem
)) != 0)
1014 copy_cmd_to_buffer(iommu
, cmd
, tail
);
1016 /* We need to sync now to make sure all commands are processed */
1017 iommu
->need_sync
= sync
;
1019 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1024 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
1026 return iommu_queue_command_sync(iommu
, cmd
, true);
1030 * This function queues a completion wait command into the command
1031 * buffer of an IOMMU
1033 static int iommu_completion_wait(struct amd_iommu
*iommu
)
1035 struct iommu_cmd cmd
;
1036 volatile u64 sem
= 0;
1039 if (!iommu
->need_sync
)
1042 build_completion_wait(&cmd
, (u64
)&sem
);
1044 ret
= iommu_queue_command_sync(iommu
, &cmd
, false);
1048 return wait_on_sem(&sem
);
1051 static int iommu_flush_dte(struct amd_iommu
*iommu
, u16 devid
)
1053 struct iommu_cmd cmd
;
1055 build_inv_dte(&cmd
, devid
);
1057 return iommu_queue_command(iommu
, &cmd
);
1060 static void iommu_flush_dte_all(struct amd_iommu
*iommu
)
1064 for (devid
= 0; devid
<= 0xffff; ++devid
)
1065 iommu_flush_dte(iommu
, devid
);
1067 iommu_completion_wait(iommu
);
1071 * This function uses heavy locking and may disable irqs for some time. But
1072 * this is no issue because it is only called during resume.
1074 static void iommu_flush_tlb_all(struct amd_iommu
*iommu
)
1078 for (dom_id
= 0; dom_id
<= 0xffff; ++dom_id
) {
1079 struct iommu_cmd cmd
;
1080 build_inv_iommu_pages(&cmd
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
1082 iommu_queue_command(iommu
, &cmd
);
1085 iommu_completion_wait(iommu
);
1088 static void iommu_flush_all(struct amd_iommu
*iommu
)
1090 struct iommu_cmd cmd
;
1092 build_inv_all(&cmd
);
1094 iommu_queue_command(iommu
, &cmd
);
1095 iommu_completion_wait(iommu
);
1098 static void iommu_flush_irt(struct amd_iommu
*iommu
, u16 devid
)
1100 struct iommu_cmd cmd
;
1102 build_inv_irt(&cmd
, devid
);
1104 iommu_queue_command(iommu
, &cmd
);
1107 static void iommu_flush_irt_all(struct amd_iommu
*iommu
)
1111 for (devid
= 0; devid
<= MAX_DEV_TABLE_ENTRIES
; devid
++)
1112 iommu_flush_irt(iommu
, devid
);
1114 iommu_completion_wait(iommu
);
1117 void iommu_flush_all_caches(struct amd_iommu
*iommu
)
1119 if (iommu_feature(iommu
, FEATURE_IA
)) {
1120 iommu_flush_all(iommu
);
1122 iommu_flush_dte_all(iommu
);
1123 iommu_flush_irt_all(iommu
);
1124 iommu_flush_tlb_all(iommu
);
1129 * Command send function for flushing on-device TLB
1131 static int device_flush_iotlb(struct iommu_dev_data
*dev_data
,
1132 u64 address
, size_t size
)
1134 struct amd_iommu
*iommu
;
1135 struct iommu_cmd cmd
;
1138 qdep
= dev_data
->ats
.qdep
;
1139 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1141 build_inv_iotlb_pages(&cmd
, dev_data
->devid
, qdep
, address
, size
);
1143 return iommu_queue_command(iommu
, &cmd
);
1147 * Command send function for invalidating a device table entry
1149 static int device_flush_dte(struct iommu_dev_data
*dev_data
)
1151 struct amd_iommu
*iommu
;
1154 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1156 ret
= iommu_flush_dte(iommu
, dev_data
->devid
);
1160 if (dev_data
->ats
.enabled
)
1161 ret
= device_flush_iotlb(dev_data
, 0, ~0UL);
1167 * TLB invalidation function which is called from the mapping functions.
1168 * It invalidates a single PTE if the range to flush is within a single
1169 * page. Otherwise it flushes the whole TLB of the IOMMU.
1171 static void __domain_flush_pages(struct protection_domain
*domain
,
1172 u64 address
, size_t size
, int pde
)
1174 struct iommu_dev_data
*dev_data
;
1175 struct iommu_cmd cmd
;
1178 build_inv_iommu_pages(&cmd
, address
, size
, domain
->id
, pde
);
1180 for (i
= 0; i
< amd_iommus_present
; ++i
) {
1181 if (!domain
->dev_iommu
[i
])
1185 * Devices of this domain are behind this IOMMU
1186 * We need a TLB flush
1188 ret
|= iommu_queue_command(amd_iommus
[i
], &cmd
);
1191 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
1193 if (!dev_data
->ats
.enabled
)
1196 ret
|= device_flush_iotlb(dev_data
, address
, size
);
1202 static void domain_flush_pages(struct protection_domain
*domain
,
1203 u64 address
, size_t size
)
1205 __domain_flush_pages(domain
, address
, size
, 0);
1208 /* Flush the whole IO/TLB for a given protection domain */
1209 static void domain_flush_tlb(struct protection_domain
*domain
)
1211 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 0);
1214 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1215 static void domain_flush_tlb_pde(struct protection_domain
*domain
)
1217 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 1);
1220 static void domain_flush_complete(struct protection_domain
*domain
)
1224 for (i
= 0; i
< amd_iommus_present
; ++i
) {
1225 if (!domain
->dev_iommu
[i
])
1229 * Devices of this domain are behind this IOMMU
1230 * We need to wait for completion of all commands.
1232 iommu_completion_wait(amd_iommus
[i
]);
1238 * This function flushes the DTEs for all devices in domain
1240 static void domain_flush_devices(struct protection_domain
*domain
)
1242 struct iommu_dev_data
*dev_data
;
1244 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
1245 device_flush_dte(dev_data
);
1248 /****************************************************************************
1250 * The functions below are used the create the page table mappings for
1251 * unity mapped regions.
1253 ****************************************************************************/
1256 * This function is used to add another level to an IO page table. Adding
1257 * another level increases the size of the address space by 9 bits to a size up
1260 static bool increase_address_space(struct protection_domain
*domain
,
1265 if (domain
->mode
== PAGE_MODE_6_LEVEL
)
1266 /* address space already 64 bit large */
1269 pte
= (void *)get_zeroed_page(gfp
);
1273 *pte
= PM_LEVEL_PDE(domain
->mode
,
1274 virt_to_phys(domain
->pt_root
));
1275 domain
->pt_root
= pte
;
1277 domain
->updated
= true;
1282 static u64
*alloc_pte(struct protection_domain
*domain
,
1283 unsigned long address
,
1284 unsigned long page_size
,
1291 BUG_ON(!is_power_of_2(page_size
));
1293 while (address
> PM_LEVEL_SIZE(domain
->mode
))
1294 increase_address_space(domain
, gfp
);
1296 level
= domain
->mode
- 1;
1297 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1298 address
= PAGE_SIZE_ALIGN(address
, page_size
);
1299 end_lvl
= PAGE_SIZE_LEVEL(page_size
);
1301 while (level
> end_lvl
) {
1302 if (!IOMMU_PTE_PRESENT(*pte
)) {
1303 page
= (u64
*)get_zeroed_page(gfp
);
1306 *pte
= PM_LEVEL_PDE(level
, virt_to_phys(page
));
1309 /* No level skipping support yet */
1310 if (PM_PTE_LEVEL(*pte
) != level
)
1315 pte
= IOMMU_PTE_PAGE(*pte
);
1317 if (pte_page
&& level
== end_lvl
)
1320 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1327 * This function checks if there is a PTE for a given dma address. If
1328 * there is one, it returns the pointer to it.
1330 static u64
*fetch_pte(struct protection_domain
*domain
,
1331 unsigned long address
,
1332 unsigned long *page_size
)
1337 if (address
> PM_LEVEL_SIZE(domain
->mode
))
1340 level
= domain
->mode
- 1;
1341 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1342 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1347 if (!IOMMU_PTE_PRESENT(*pte
))
1351 if (PM_PTE_LEVEL(*pte
) == 7 ||
1352 PM_PTE_LEVEL(*pte
) == 0)
1355 /* No level skipping support yet */
1356 if (PM_PTE_LEVEL(*pte
) != level
)
1361 /* Walk to the next level */
1362 pte
= IOMMU_PTE_PAGE(*pte
);
1363 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1364 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1367 if (PM_PTE_LEVEL(*pte
) == 0x07) {
1368 unsigned long pte_mask
;
1371 * If we have a series of large PTEs, make
1372 * sure to return a pointer to the first one.
1374 *page_size
= pte_mask
= PTE_PAGE_SIZE(*pte
);
1375 pte_mask
= ~((PAGE_SIZE_PTE_COUNT(pte_mask
) << 3) - 1);
1376 pte
= (u64
*)(((unsigned long)pte
) & pte_mask
);
1383 * Generic mapping functions. It maps a physical address into a DMA
1384 * address space. It allocates the page table pages if necessary.
1385 * In the future it can be extended to a generic mapping function
1386 * supporting all features of AMD IOMMU page tables like level skipping
1387 * and full 64 bit address spaces.
1389 static int iommu_map_page(struct protection_domain
*dom
,
1390 unsigned long bus_addr
,
1391 unsigned long phys_addr
,
1393 unsigned long page_size
)
1398 BUG_ON(!IS_ALIGNED(bus_addr
, page_size
));
1399 BUG_ON(!IS_ALIGNED(phys_addr
, page_size
));
1401 if (!(prot
& IOMMU_PROT_MASK
))
1404 count
= PAGE_SIZE_PTE_COUNT(page_size
);
1405 pte
= alloc_pte(dom
, bus_addr
, page_size
, NULL
, GFP_KERNEL
);
1410 for (i
= 0; i
< count
; ++i
)
1411 if (IOMMU_PTE_PRESENT(pte
[i
]))
1415 __pte
= PAGE_SIZE_PTE(phys_addr
, page_size
);
1416 __pte
|= PM_LEVEL_ENC(7) | IOMMU_PTE_P
| IOMMU_PTE_FC
;
1418 __pte
= phys_addr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1420 if (prot
& IOMMU_PROT_IR
)
1421 __pte
|= IOMMU_PTE_IR
;
1422 if (prot
& IOMMU_PROT_IW
)
1423 __pte
|= IOMMU_PTE_IW
;
1425 for (i
= 0; i
< count
; ++i
)
1433 static unsigned long iommu_unmap_page(struct protection_domain
*dom
,
1434 unsigned long bus_addr
,
1435 unsigned long page_size
)
1437 unsigned long long unmapped
;
1438 unsigned long unmap_size
;
1441 BUG_ON(!is_power_of_2(page_size
));
1445 while (unmapped
< page_size
) {
1447 pte
= fetch_pte(dom
, bus_addr
, &unmap_size
);
1452 count
= PAGE_SIZE_PTE_COUNT(unmap_size
);
1453 for (i
= 0; i
< count
; i
++)
1457 bus_addr
= (bus_addr
& ~(unmap_size
- 1)) + unmap_size
;
1458 unmapped
+= unmap_size
;
1461 BUG_ON(unmapped
&& !is_power_of_2(unmapped
));
1467 * This function checks if a specific unity mapping entry is needed for
1468 * this specific IOMMU.
1470 static int iommu_for_unity_map(struct amd_iommu
*iommu
,
1471 struct unity_map_entry
*entry
)
1475 for (i
= entry
->devid_start
; i
<= entry
->devid_end
; ++i
) {
1476 bdf
= amd_iommu_alias_table
[i
];
1477 if (amd_iommu_rlookup_table
[bdf
] == iommu
)
1485 * This function actually applies the mapping to the page table of the
1488 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
1489 struct unity_map_entry
*e
)
1494 for (addr
= e
->address_start
; addr
< e
->address_end
;
1495 addr
+= PAGE_SIZE
) {
1496 ret
= iommu_map_page(&dma_dom
->domain
, addr
, addr
, e
->prot
,
1501 * if unity mapping is in aperture range mark the page
1502 * as allocated in the aperture
1504 if (addr
< dma_dom
->aperture_size
)
1505 __set_bit(addr
>> PAGE_SHIFT
,
1506 dma_dom
->aperture
[0]->bitmap
);
1513 * Init the unity mappings for a specific IOMMU in the system
1515 * Basically iterates over all unity mapping entries and applies them to
1516 * the default domain DMA of that IOMMU if necessary.
1518 static int iommu_init_unity_mappings(struct amd_iommu
*iommu
)
1520 struct unity_map_entry
*entry
;
1523 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
1524 if (!iommu_for_unity_map(iommu
, entry
))
1526 ret
= dma_ops_unity_map(iommu
->default_dom
, entry
);
1535 * Inits the unity mappings required for a specific device
1537 static int init_unity_mappings_for_device(struct dma_ops_domain
*dma_dom
,
1540 struct unity_map_entry
*e
;
1543 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
1544 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
1546 ret
= dma_ops_unity_map(dma_dom
, e
);
1554 /****************************************************************************
1556 * The next functions belong to the address allocator for the dma_ops
1557 * interface functions. They work like the allocators in the other IOMMU
1558 * drivers. Its basically a bitmap which marks the allocated pages in
1559 * the aperture. Maybe it could be enhanced in the future to a more
1560 * efficient allocator.
1562 ****************************************************************************/
1565 * The address allocator core functions.
1567 * called with domain->lock held
1571 * Used to reserve address ranges in the aperture (e.g. for exclusion
1574 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
1575 unsigned long start_page
,
1578 unsigned int i
, last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
1580 if (start_page
+ pages
> last_page
)
1581 pages
= last_page
- start_page
;
1583 for (i
= start_page
; i
< start_page
+ pages
; ++i
) {
1584 int index
= i
/ APERTURE_RANGE_PAGES
;
1585 int page
= i
% APERTURE_RANGE_PAGES
;
1586 __set_bit(page
, dom
->aperture
[index
]->bitmap
);
1591 * This function is used to add a new aperture range to an existing
1592 * aperture in case of dma_ops domain allocation or address allocation
1595 static int alloc_new_range(struct dma_ops_domain
*dma_dom
,
1596 bool populate
, gfp_t gfp
)
1598 int index
= dma_dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1599 struct amd_iommu
*iommu
;
1600 unsigned long i
, old_size
, pte_pgsize
;
1602 #ifdef CONFIG_IOMMU_STRESS
1606 if (index
>= APERTURE_MAX_RANGES
)
1609 dma_dom
->aperture
[index
] = kzalloc(sizeof(struct aperture_range
), gfp
);
1610 if (!dma_dom
->aperture
[index
])
1613 dma_dom
->aperture
[index
]->bitmap
= (void *)get_zeroed_page(gfp
);
1614 if (!dma_dom
->aperture
[index
]->bitmap
)
1617 dma_dom
->aperture
[index
]->offset
= dma_dom
->aperture_size
;
1620 unsigned long address
= dma_dom
->aperture_size
;
1621 int i
, num_ptes
= APERTURE_RANGE_PAGES
/ 512;
1622 u64
*pte
, *pte_page
;
1624 for (i
= 0; i
< num_ptes
; ++i
) {
1625 pte
= alloc_pte(&dma_dom
->domain
, address
, PAGE_SIZE
,
1630 dma_dom
->aperture
[index
]->pte_pages
[i
] = pte_page
;
1632 address
+= APERTURE_RANGE_SIZE
/ 64;
1636 old_size
= dma_dom
->aperture_size
;
1637 dma_dom
->aperture_size
+= APERTURE_RANGE_SIZE
;
1639 /* Reserve address range used for MSI messages */
1640 if (old_size
< MSI_ADDR_BASE_LO
&&
1641 dma_dom
->aperture_size
> MSI_ADDR_BASE_LO
) {
1642 unsigned long spage
;
1645 pages
= iommu_num_pages(MSI_ADDR_BASE_LO
, 0x10000, PAGE_SIZE
);
1646 spage
= MSI_ADDR_BASE_LO
>> PAGE_SHIFT
;
1648 dma_ops_reserve_addresses(dma_dom
, spage
, pages
);
1651 /* Initialize the exclusion range if necessary */
1652 for_each_iommu(iommu
) {
1653 if (iommu
->exclusion_start
&&
1654 iommu
->exclusion_start
>= dma_dom
->aperture
[index
]->offset
1655 && iommu
->exclusion_start
< dma_dom
->aperture_size
) {
1656 unsigned long startpage
;
1657 int pages
= iommu_num_pages(iommu
->exclusion_start
,
1658 iommu
->exclusion_length
,
1660 startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
1661 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
1666 * Check for areas already mapped as present in the new aperture
1667 * range and mark those pages as reserved in the allocator. Such
1668 * mappings may already exist as a result of requested unity
1669 * mappings for devices.
1671 for (i
= dma_dom
->aperture
[index
]->offset
;
1672 i
< dma_dom
->aperture_size
;
1674 u64
*pte
= fetch_pte(&dma_dom
->domain
, i
, &pte_pgsize
);
1675 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
1678 dma_ops_reserve_addresses(dma_dom
, i
>> PAGE_SHIFT
,
1682 update_domain(&dma_dom
->domain
);
1687 update_domain(&dma_dom
->domain
);
1689 free_page((unsigned long)dma_dom
->aperture
[index
]->bitmap
);
1691 kfree(dma_dom
->aperture
[index
]);
1692 dma_dom
->aperture
[index
] = NULL
;
1697 static unsigned long dma_ops_area_alloc(struct device
*dev
,
1698 struct dma_ops_domain
*dom
,
1700 unsigned long align_mask
,
1702 unsigned long start
)
1704 unsigned long next_bit
= dom
->next_address
% APERTURE_RANGE_SIZE
;
1705 int max_index
= dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1706 int i
= start
>> APERTURE_RANGE_SHIFT
;
1707 unsigned long boundary_size
;
1708 unsigned long address
= -1;
1709 unsigned long limit
;
1711 next_bit
>>= PAGE_SHIFT
;
1713 boundary_size
= ALIGN(dma_get_seg_boundary(dev
) + 1,
1714 PAGE_SIZE
) >> PAGE_SHIFT
;
1716 for (;i
< max_index
; ++i
) {
1717 unsigned long offset
= dom
->aperture
[i
]->offset
>> PAGE_SHIFT
;
1719 if (dom
->aperture
[i
]->offset
>= dma_mask
)
1722 limit
= iommu_device_max_index(APERTURE_RANGE_PAGES
, offset
,
1723 dma_mask
>> PAGE_SHIFT
);
1725 address
= iommu_area_alloc(dom
->aperture
[i
]->bitmap
,
1726 limit
, next_bit
, pages
, 0,
1727 boundary_size
, align_mask
);
1728 if (address
!= -1) {
1729 address
= dom
->aperture
[i
]->offset
+
1730 (address
<< PAGE_SHIFT
);
1731 dom
->next_address
= address
+ (pages
<< PAGE_SHIFT
);
1741 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
1742 struct dma_ops_domain
*dom
,
1744 unsigned long align_mask
,
1747 unsigned long address
;
1749 #ifdef CONFIG_IOMMU_STRESS
1750 dom
->next_address
= 0;
1751 dom
->need_flush
= true;
1754 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1755 dma_mask
, dom
->next_address
);
1757 if (address
== -1) {
1758 dom
->next_address
= 0;
1759 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1761 dom
->need_flush
= true;
1764 if (unlikely(address
== -1))
1765 address
= DMA_ERROR_CODE
;
1767 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
1773 * The address free function.
1775 * called with domain->lock held
1777 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
1778 unsigned long address
,
1781 unsigned i
= address
>> APERTURE_RANGE_SHIFT
;
1782 struct aperture_range
*range
= dom
->aperture
[i
];
1784 BUG_ON(i
>= APERTURE_MAX_RANGES
|| range
== NULL
);
1786 #ifdef CONFIG_IOMMU_STRESS
1791 if (address
>= dom
->next_address
)
1792 dom
->need_flush
= true;
1794 address
= (address
% APERTURE_RANGE_SIZE
) >> PAGE_SHIFT
;
1796 bitmap_clear(range
->bitmap
, address
, pages
);
1800 /****************************************************************************
1802 * The next functions belong to the domain allocation. A domain is
1803 * allocated for every IOMMU as the default domain. If device isolation
1804 * is enabled, every device get its own domain. The most important thing
1805 * about domains is the page table mapping the DMA address space they
1808 ****************************************************************************/
1811 * This function adds a protection domain to the global protection domain list
1813 static void add_domain_to_list(struct protection_domain
*domain
)
1815 unsigned long flags
;
1817 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1818 list_add(&domain
->list
, &amd_iommu_pd_list
);
1819 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1823 * This function removes a protection domain to the global
1824 * protection domain list
1826 static void del_domain_from_list(struct protection_domain
*domain
)
1828 unsigned long flags
;
1830 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1831 list_del(&domain
->list
);
1832 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1835 static u16
domain_id_alloc(void)
1837 unsigned long flags
;
1840 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1841 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
1843 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1844 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
1847 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1852 static void domain_id_free(int id
)
1854 unsigned long flags
;
1856 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1857 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1858 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
1859 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1862 #define DEFINE_FREE_PT_FN(LVL, FN) \
1863 static void free_pt_##LVL (unsigned long __pt) \
1871 for (i = 0; i < 512; ++i) { \
1872 if (!IOMMU_PTE_PRESENT(pt[i])) \
1875 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1878 free_page((unsigned long)pt); \
1881 DEFINE_FREE_PT_FN(l2
, free_page
)
1882 DEFINE_FREE_PT_FN(l3
, free_pt_l2
)
1883 DEFINE_FREE_PT_FN(l4
, free_pt_l3
)
1884 DEFINE_FREE_PT_FN(l5
, free_pt_l4
)
1885 DEFINE_FREE_PT_FN(l6
, free_pt_l5
)
1887 static void free_pagetable(struct protection_domain
*domain
)
1889 unsigned long root
= (unsigned long)domain
->pt_root
;
1891 switch (domain
->mode
) {
1892 case PAGE_MODE_NONE
:
1894 case PAGE_MODE_1_LEVEL
:
1897 case PAGE_MODE_2_LEVEL
:
1900 case PAGE_MODE_3_LEVEL
:
1903 case PAGE_MODE_4_LEVEL
:
1906 case PAGE_MODE_5_LEVEL
:
1909 case PAGE_MODE_6_LEVEL
:
1917 static void free_gcr3_tbl_level1(u64
*tbl
)
1922 for (i
= 0; i
< 512; ++i
) {
1923 if (!(tbl
[i
] & GCR3_VALID
))
1926 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1928 free_page((unsigned long)ptr
);
1932 static void free_gcr3_tbl_level2(u64
*tbl
)
1937 for (i
= 0; i
< 512; ++i
) {
1938 if (!(tbl
[i
] & GCR3_VALID
))
1941 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1943 free_gcr3_tbl_level1(ptr
);
1947 static void free_gcr3_table(struct protection_domain
*domain
)
1949 if (domain
->glx
== 2)
1950 free_gcr3_tbl_level2(domain
->gcr3_tbl
);
1951 else if (domain
->glx
== 1)
1952 free_gcr3_tbl_level1(domain
->gcr3_tbl
);
1953 else if (domain
->glx
!= 0)
1956 free_page((unsigned long)domain
->gcr3_tbl
);
1960 * Free a domain, only used if something went wrong in the
1961 * allocation path and we need to free an already allocated page table
1963 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
1970 del_domain_from_list(&dom
->domain
);
1972 free_pagetable(&dom
->domain
);
1974 for (i
= 0; i
< APERTURE_MAX_RANGES
; ++i
) {
1975 if (!dom
->aperture
[i
])
1977 free_page((unsigned long)dom
->aperture
[i
]->bitmap
);
1978 kfree(dom
->aperture
[i
]);
1985 * Allocates a new protection domain usable for the dma_ops functions.
1986 * It also initializes the page table and the address allocator data
1987 * structures required for the dma_ops interface
1989 static struct dma_ops_domain
*dma_ops_domain_alloc(void)
1991 struct dma_ops_domain
*dma_dom
;
1993 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
1997 spin_lock_init(&dma_dom
->domain
.lock
);
1999 dma_dom
->domain
.id
= domain_id_alloc();
2000 if (dma_dom
->domain
.id
== 0)
2002 INIT_LIST_HEAD(&dma_dom
->domain
.dev_list
);
2003 dma_dom
->domain
.mode
= PAGE_MODE_2_LEVEL
;
2004 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
2005 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
2006 dma_dom
->domain
.priv
= dma_dom
;
2007 if (!dma_dom
->domain
.pt_root
)
2010 dma_dom
->need_flush
= false;
2011 dma_dom
->target_dev
= 0xffff;
2013 add_domain_to_list(&dma_dom
->domain
);
2015 if (alloc_new_range(dma_dom
, true, GFP_KERNEL
))
2019 * mark the first page as allocated so we never return 0 as
2020 * a valid dma-address. So we can use 0 as error value
2022 dma_dom
->aperture
[0]->bitmap
[0] = 1;
2023 dma_dom
->next_address
= 0;
2029 dma_ops_domain_free(dma_dom
);
2035 * little helper function to check whether a given protection domain is a
2038 static bool dma_ops_domain(struct protection_domain
*domain
)
2040 return domain
->flags
& PD_DMA_OPS_MASK
;
2043 static void set_dte_entry(u16 devid
, struct protection_domain
*domain
, bool ats
)
2048 if (domain
->mode
!= PAGE_MODE_NONE
)
2049 pte_root
= virt_to_phys(domain
->pt_root
);
2051 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
2052 << DEV_ENTRY_MODE_SHIFT
;
2053 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
2055 flags
= amd_iommu_dev_table
[devid
].data
[1];
2058 flags
|= DTE_FLAG_IOTLB
;
2060 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2061 u64 gcr3
= __pa(domain
->gcr3_tbl
);
2062 u64 glx
= domain
->glx
;
2065 pte_root
|= DTE_FLAG_GV
;
2066 pte_root
|= (glx
& DTE_GLX_MASK
) << DTE_GLX_SHIFT
;
2068 /* First mask out possible old values for GCR3 table */
2069 tmp
= DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B
;
2072 tmp
= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C
;
2075 /* Encode GCR3 table into DTE */
2076 tmp
= DTE_GCR3_VAL_A(gcr3
) << DTE_GCR3_SHIFT_A
;
2079 tmp
= DTE_GCR3_VAL_B(gcr3
) << DTE_GCR3_SHIFT_B
;
2082 tmp
= DTE_GCR3_VAL_C(gcr3
) << DTE_GCR3_SHIFT_C
;
2086 flags
&= ~(0xffffUL
);
2087 flags
|= domain
->id
;
2089 amd_iommu_dev_table
[devid
].data
[1] = flags
;
2090 amd_iommu_dev_table
[devid
].data
[0] = pte_root
;
2093 static void clear_dte_entry(u16 devid
)
2095 /* remove entry from the device table seen by the hardware */
2096 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
2097 amd_iommu_dev_table
[devid
].data
[1] = 0;
2099 amd_iommu_apply_erratum_63(devid
);
2102 static void do_attach(struct iommu_dev_data
*dev_data
,
2103 struct protection_domain
*domain
)
2105 struct amd_iommu
*iommu
;
2108 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
2109 ats
= dev_data
->ats
.enabled
;
2111 /* Update data structures */
2112 dev_data
->domain
= domain
;
2113 list_add(&dev_data
->list
, &domain
->dev_list
);
2114 set_dte_entry(dev_data
->devid
, domain
, ats
);
2116 /* Do reference counting */
2117 domain
->dev_iommu
[iommu
->index
] += 1;
2118 domain
->dev_cnt
+= 1;
2120 /* Flush the DTE entry */
2121 device_flush_dte(dev_data
);
2124 static void do_detach(struct iommu_dev_data
*dev_data
)
2126 struct amd_iommu
*iommu
;
2128 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
2130 /* decrease reference counters */
2131 dev_data
->domain
->dev_iommu
[iommu
->index
] -= 1;
2132 dev_data
->domain
->dev_cnt
-= 1;
2134 /* Update data structures */
2135 dev_data
->domain
= NULL
;
2136 list_del(&dev_data
->list
);
2137 clear_dte_entry(dev_data
->devid
);
2139 /* Flush the DTE entry */
2140 device_flush_dte(dev_data
);
2144 * If a device is not yet associated with a domain, this function does
2145 * assigns it visible for the hardware
2147 static int __attach_device(struct iommu_dev_data
*dev_data
,
2148 struct protection_domain
*domain
)
2150 struct iommu_dev_data
*head
, *entry
;
2154 spin_lock(&domain
->lock
);
2158 if (head
->alias_data
!= NULL
)
2159 head
= head
->alias_data
;
2161 /* Now we have the root of the alias group, if any */
2164 if (head
->domain
!= NULL
)
2167 /* Attach alias group root */
2168 do_attach(head
, domain
);
2170 /* Attach other devices in the alias group */
2171 list_for_each_entry(entry
, &head
->alias_list
, alias_list
)
2172 do_attach(entry
, domain
);
2179 spin_unlock(&domain
->lock
);
2185 static void pdev_iommuv2_disable(struct pci_dev
*pdev
)
2187 pci_disable_ats(pdev
);
2188 pci_disable_pri(pdev
);
2189 pci_disable_pasid(pdev
);
2192 /* FIXME: Change generic reset-function to do the same */
2193 static int pri_reset_while_enabled(struct pci_dev
*pdev
)
2198 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2202 pci_read_config_word(pdev
, pos
+ PCI_PRI_CTRL
, &control
);
2203 control
|= PCI_PRI_CTRL_RESET
;
2204 pci_write_config_word(pdev
, pos
+ PCI_PRI_CTRL
, control
);
2209 static int pdev_iommuv2_enable(struct pci_dev
*pdev
)
2214 /* FIXME: Hardcode number of outstanding requests for now */
2216 if (pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE
))
2218 reset_enable
= pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_ENABLE_RESET
);
2220 /* Only allow access to user-accessible pages */
2221 ret
= pci_enable_pasid(pdev
, 0);
2225 /* First reset the PRI state of the device */
2226 ret
= pci_reset_pri(pdev
);
2231 ret
= pci_enable_pri(pdev
, reqs
);
2236 ret
= pri_reset_while_enabled(pdev
);
2241 ret
= pci_enable_ats(pdev
, PAGE_SHIFT
);
2248 pci_disable_pri(pdev
);
2249 pci_disable_pasid(pdev
);
2254 /* FIXME: Move this to PCI code */
2255 #define PCI_PRI_TLP_OFF (1 << 15)
2257 static bool pci_pri_tlp_required(struct pci_dev
*pdev
)
2262 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2266 pci_read_config_word(pdev
, pos
+ PCI_PRI_STATUS
, &status
);
2268 return (status
& PCI_PRI_TLP_OFF
) ? true : false;
2272 * If a device is not yet associated with a domain, this function
2273 * assigns it visible for the hardware
2275 static int attach_device(struct device
*dev
,
2276 struct protection_domain
*domain
)
2278 struct pci_dev
*pdev
= to_pci_dev(dev
);
2279 struct iommu_dev_data
*dev_data
;
2280 unsigned long flags
;
2283 dev_data
= get_dev_data(dev
);
2285 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2286 if (!dev_data
->iommu_v2
|| !dev_data
->passthrough
)
2289 if (pdev_iommuv2_enable(pdev
) != 0)
2292 dev_data
->ats
.enabled
= true;
2293 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2294 dev_data
->pri_tlp
= pci_pri_tlp_required(pdev
);
2295 } else if (amd_iommu_iotlb_sup
&&
2296 pci_enable_ats(pdev
, PAGE_SHIFT
) == 0) {
2297 dev_data
->ats
.enabled
= true;
2298 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2301 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2302 ret
= __attach_device(dev_data
, domain
);
2303 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2306 * We might boot into a crash-kernel here. The crashed kernel
2307 * left the caches in the IOMMU dirty. So we have to flush
2308 * here to evict all dirty stuff.
2310 domain_flush_tlb_pde(domain
);
2316 * Removes a device from a protection domain (unlocked)
2318 static void __detach_device(struct iommu_dev_data
*dev_data
)
2320 struct iommu_dev_data
*head
, *entry
;
2321 struct protection_domain
*domain
;
2322 unsigned long flags
;
2324 BUG_ON(!dev_data
->domain
);
2326 domain
= dev_data
->domain
;
2328 spin_lock_irqsave(&domain
->lock
, flags
);
2331 if (head
->alias_data
!= NULL
)
2332 head
= head
->alias_data
;
2334 list_for_each_entry(entry
, &head
->alias_list
, alias_list
)
2339 spin_unlock_irqrestore(&domain
->lock
, flags
);
2342 * If we run in passthrough mode the device must be assigned to the
2343 * passthrough domain if it is detached from any other domain.
2344 * Make sure we can deassign from the pt_domain itself.
2346 if (dev_data
->passthrough
&&
2347 (dev_data
->domain
== NULL
&& domain
!= pt_domain
))
2348 __attach_device(dev_data
, pt_domain
);
2352 * Removes a device from a protection domain (with devtable_lock held)
2354 static void detach_device(struct device
*dev
)
2356 struct protection_domain
*domain
;
2357 struct iommu_dev_data
*dev_data
;
2358 unsigned long flags
;
2360 dev_data
= get_dev_data(dev
);
2361 domain
= dev_data
->domain
;
2363 /* lock device table */
2364 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2365 __detach_device(dev_data
);
2366 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2368 if (domain
->flags
& PD_IOMMUV2_MASK
)
2369 pdev_iommuv2_disable(to_pci_dev(dev
));
2370 else if (dev_data
->ats
.enabled
)
2371 pci_disable_ats(to_pci_dev(dev
));
2373 dev_data
->ats
.enabled
= false;
2377 * Find out the protection domain structure for a given PCI device. This
2378 * will give us the pointer to the page table root for example.
2380 static struct protection_domain
*domain_for_device(struct device
*dev
)
2382 struct iommu_dev_data
*dev_data
;
2383 struct protection_domain
*dom
= NULL
;
2384 unsigned long flags
;
2386 dev_data
= get_dev_data(dev
);
2388 if (dev_data
->domain
)
2389 return dev_data
->domain
;
2391 if (dev_data
->alias_data
!= NULL
) {
2392 struct iommu_dev_data
*alias_data
= dev_data
->alias_data
;
2394 read_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2395 if (alias_data
->domain
!= NULL
) {
2396 __attach_device(dev_data
, alias_data
->domain
);
2397 dom
= alias_data
->domain
;
2399 read_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2405 static int device_change_notifier(struct notifier_block
*nb
,
2406 unsigned long action
, void *data
)
2408 struct dma_ops_domain
*dma_domain
;
2409 struct protection_domain
*domain
;
2410 struct iommu_dev_data
*dev_data
;
2411 struct device
*dev
= data
;
2412 struct amd_iommu
*iommu
;
2413 unsigned long flags
;
2416 if (!check_device(dev
))
2419 devid
= get_device_id(dev
);
2420 iommu
= amd_iommu_rlookup_table
[devid
];
2421 dev_data
= get_dev_data(dev
);
2424 case BUS_NOTIFY_ADD_DEVICE
:
2426 iommu_init_device(dev
);
2427 init_iommu_group(dev
);
2430 * dev_data is still NULL and
2431 * got initialized in iommu_init_device
2433 dev_data
= get_dev_data(dev
);
2435 if (iommu_pass_through
|| dev_data
->iommu_v2
) {
2436 dev_data
->passthrough
= true;
2437 attach_device(dev
, pt_domain
);
2441 domain
= domain_for_device(dev
);
2443 /* allocate a protection domain if a device is added */
2444 dma_domain
= find_protection_domain(devid
);
2446 dma_domain
= dma_ops_domain_alloc();
2449 dma_domain
->target_dev
= devid
;
2451 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
2452 list_add_tail(&dma_domain
->list
, &iommu_pd_list
);
2453 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
2456 dev
->archdata
.dma_ops
= &amd_iommu_dma_ops
;
2459 case BUS_NOTIFY_REMOVED_DEVICE
:
2461 iommu_uninit_device(dev
);
2467 iommu_completion_wait(iommu
);
2473 static struct notifier_block device_nb
= {
2474 .notifier_call
= device_change_notifier
,
2477 void amd_iommu_init_notifier(void)
2479 bus_register_notifier(&pci_bus_type
, &device_nb
);
2482 /*****************************************************************************
2484 * The next functions belong to the dma_ops mapping/unmapping code.
2486 *****************************************************************************/
2489 * In the dma_ops path we only have the struct device. This function
2490 * finds the corresponding IOMMU, the protection domain and the
2491 * requestor id for a given device.
2492 * If the device is not yet associated with a domain this is also done
2495 static struct protection_domain
*get_domain(struct device
*dev
)
2497 struct protection_domain
*domain
;
2498 struct dma_ops_domain
*dma_dom
;
2499 u16 devid
= get_device_id(dev
);
2501 if (!check_device(dev
))
2502 return ERR_PTR(-EINVAL
);
2504 domain
= domain_for_device(dev
);
2505 if (domain
!= NULL
&& !dma_ops_domain(domain
))
2506 return ERR_PTR(-EBUSY
);
2511 /* Device not bound yet - bind it */
2512 dma_dom
= find_protection_domain(devid
);
2514 dma_dom
= amd_iommu_rlookup_table
[devid
]->default_dom
;
2515 attach_device(dev
, &dma_dom
->domain
);
2516 DUMP_printk("Using protection domain %d for device %s\n",
2517 dma_dom
->domain
.id
, dev_name(dev
));
2519 return &dma_dom
->domain
;
2522 static void update_device_table(struct protection_domain
*domain
)
2524 struct iommu_dev_data
*dev_data
;
2526 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
2527 set_dte_entry(dev_data
->devid
, domain
, dev_data
->ats
.enabled
);
2530 static void update_domain(struct protection_domain
*domain
)
2532 if (!domain
->updated
)
2535 update_device_table(domain
);
2537 domain_flush_devices(domain
);
2538 domain_flush_tlb_pde(domain
);
2540 domain
->updated
= false;
2544 * This function fetches the PTE for a given address in the aperture
2546 static u64
* dma_ops_get_pte(struct dma_ops_domain
*dom
,
2547 unsigned long address
)
2549 struct aperture_range
*aperture
;
2550 u64
*pte
, *pte_page
;
2552 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
2556 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
2558 pte
= alloc_pte(&dom
->domain
, address
, PAGE_SIZE
, &pte_page
,
2560 aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)] = pte_page
;
2562 pte
+= PM_LEVEL_INDEX(0, address
);
2564 update_domain(&dom
->domain
);
2570 * This is the generic map function. It maps one 4kb page at paddr to
2571 * the given address in the DMA address space for the domain.
2573 static dma_addr_t
dma_ops_domain_map(struct dma_ops_domain
*dom
,
2574 unsigned long address
,
2580 WARN_ON(address
> dom
->aperture_size
);
2584 pte
= dma_ops_get_pte(dom
, address
);
2586 return DMA_ERROR_CODE
;
2588 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
2590 if (direction
== DMA_TO_DEVICE
)
2591 __pte
|= IOMMU_PTE_IR
;
2592 else if (direction
== DMA_FROM_DEVICE
)
2593 __pte
|= IOMMU_PTE_IW
;
2594 else if (direction
== DMA_BIDIRECTIONAL
)
2595 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
2601 return (dma_addr_t
)address
;
2605 * The generic unmapping function for on page in the DMA address space.
2607 static void dma_ops_domain_unmap(struct dma_ops_domain
*dom
,
2608 unsigned long address
)
2610 struct aperture_range
*aperture
;
2613 if (address
>= dom
->aperture_size
)
2616 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
2620 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
2624 pte
+= PM_LEVEL_INDEX(0, address
);
2632 * This function contains common code for mapping of a physically
2633 * contiguous memory region into DMA address space. It is used by all
2634 * mapping functions provided with this IOMMU driver.
2635 * Must be called with the domain lock held.
2637 static dma_addr_t
__map_single(struct device
*dev
,
2638 struct dma_ops_domain
*dma_dom
,
2645 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
2646 dma_addr_t address
, start
, ret
;
2648 unsigned long align_mask
= 0;
2651 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
2654 INC_STATS_COUNTER(total_map_requests
);
2657 INC_STATS_COUNTER(cross_page
);
2660 align_mask
= (1UL << get_order(size
)) - 1;
2663 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
, align_mask
,
2665 if (unlikely(address
== DMA_ERROR_CODE
)) {
2667 * setting next_address here will let the address
2668 * allocator only scan the new allocated range in the
2669 * first run. This is a small optimization.
2671 dma_dom
->next_address
= dma_dom
->aperture_size
;
2673 if (alloc_new_range(dma_dom
, false, GFP_ATOMIC
))
2677 * aperture was successfully enlarged by 128 MB, try
2684 for (i
= 0; i
< pages
; ++i
) {
2685 ret
= dma_ops_domain_map(dma_dom
, start
, paddr
, dir
);
2686 if (ret
== DMA_ERROR_CODE
)
2694 ADD_STATS_COUNTER(alloced_io_mem
, size
);
2696 if (unlikely(dma_dom
->need_flush
&& !amd_iommu_unmap_flush
)) {
2697 domain_flush_tlb(&dma_dom
->domain
);
2698 dma_dom
->need_flush
= false;
2699 } else if (unlikely(amd_iommu_np_cache
))
2700 domain_flush_pages(&dma_dom
->domain
, address
, size
);
2707 for (--i
; i
>= 0; --i
) {
2709 dma_ops_domain_unmap(dma_dom
, start
);
2712 dma_ops_free_addresses(dma_dom
, address
, pages
);
2714 return DMA_ERROR_CODE
;
2718 * Does the reverse of the __map_single function. Must be called with
2719 * the domain lock held too
2721 static void __unmap_single(struct dma_ops_domain
*dma_dom
,
2722 dma_addr_t dma_addr
,
2726 dma_addr_t flush_addr
;
2727 dma_addr_t i
, start
;
2730 if ((dma_addr
== DMA_ERROR_CODE
) ||
2731 (dma_addr
+ size
> dma_dom
->aperture_size
))
2734 flush_addr
= dma_addr
;
2735 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
2736 dma_addr
&= PAGE_MASK
;
2739 for (i
= 0; i
< pages
; ++i
) {
2740 dma_ops_domain_unmap(dma_dom
, start
);
2744 SUB_STATS_COUNTER(alloced_io_mem
, size
);
2746 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
2748 if (amd_iommu_unmap_flush
|| dma_dom
->need_flush
) {
2749 domain_flush_pages(&dma_dom
->domain
, flush_addr
, size
);
2750 dma_dom
->need_flush
= false;
2755 * The exported map_single function for dma_ops.
2757 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
2758 unsigned long offset
, size_t size
,
2759 enum dma_data_direction dir
,
2760 struct dma_attrs
*attrs
)
2762 unsigned long flags
;
2763 struct protection_domain
*domain
;
2766 phys_addr_t paddr
= page_to_phys(page
) + offset
;
2768 INC_STATS_COUNTER(cnt_map_single
);
2770 domain
= get_domain(dev
);
2771 if (PTR_ERR(domain
) == -EINVAL
)
2772 return (dma_addr_t
)paddr
;
2773 else if (IS_ERR(domain
))
2774 return DMA_ERROR_CODE
;
2776 dma_mask
= *dev
->dma_mask
;
2778 spin_lock_irqsave(&domain
->lock
, flags
);
2780 addr
= __map_single(dev
, domain
->priv
, paddr
, size
, dir
, false,
2782 if (addr
== DMA_ERROR_CODE
)
2785 domain_flush_complete(domain
);
2788 spin_unlock_irqrestore(&domain
->lock
, flags
);
2794 * The exported unmap_single function for dma_ops.
2796 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
2797 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
2799 unsigned long flags
;
2800 struct protection_domain
*domain
;
2802 INC_STATS_COUNTER(cnt_unmap_single
);
2804 domain
= get_domain(dev
);
2808 spin_lock_irqsave(&domain
->lock
, flags
);
2810 __unmap_single(domain
->priv
, dma_addr
, size
, dir
);
2812 domain_flush_complete(domain
);
2814 spin_unlock_irqrestore(&domain
->lock
, flags
);
2818 * The exported map_sg function for dma_ops (handles scatter-gather
2821 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
2822 int nelems
, enum dma_data_direction dir
,
2823 struct dma_attrs
*attrs
)
2825 unsigned long flags
;
2826 struct protection_domain
*domain
;
2828 struct scatterlist
*s
;
2830 int mapped_elems
= 0;
2833 INC_STATS_COUNTER(cnt_map_sg
);
2835 domain
= get_domain(dev
);
2839 dma_mask
= *dev
->dma_mask
;
2841 spin_lock_irqsave(&domain
->lock
, flags
);
2843 for_each_sg(sglist
, s
, nelems
, i
) {
2846 s
->dma_address
= __map_single(dev
, domain
->priv
,
2847 paddr
, s
->length
, dir
, false,
2850 if (s
->dma_address
) {
2851 s
->dma_length
= s
->length
;
2857 domain_flush_complete(domain
);
2860 spin_unlock_irqrestore(&domain
->lock
, flags
);
2862 return mapped_elems
;
2864 for_each_sg(sglist
, s
, mapped_elems
, i
) {
2866 __unmap_single(domain
->priv
, s
->dma_address
,
2867 s
->dma_length
, dir
);
2868 s
->dma_address
= s
->dma_length
= 0;
2877 * The exported map_sg function for dma_ops (handles scatter-gather
2880 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
2881 int nelems
, enum dma_data_direction dir
,
2882 struct dma_attrs
*attrs
)
2884 unsigned long flags
;
2885 struct protection_domain
*domain
;
2886 struct scatterlist
*s
;
2889 INC_STATS_COUNTER(cnt_unmap_sg
);
2891 domain
= get_domain(dev
);
2895 spin_lock_irqsave(&domain
->lock
, flags
);
2897 for_each_sg(sglist
, s
, nelems
, i
) {
2898 __unmap_single(domain
->priv
, s
->dma_address
,
2899 s
->dma_length
, dir
);
2900 s
->dma_address
= s
->dma_length
= 0;
2903 domain_flush_complete(domain
);
2905 spin_unlock_irqrestore(&domain
->lock
, flags
);
2909 * The exported alloc_coherent function for dma_ops.
2911 static void *alloc_coherent(struct device
*dev
, size_t size
,
2912 dma_addr_t
*dma_addr
, gfp_t flag
,
2913 struct dma_attrs
*attrs
)
2915 u64 dma_mask
= dev
->coherent_dma_mask
;
2916 struct protection_domain
*domain
;
2917 unsigned long flags
;
2920 INC_STATS_COUNTER(cnt_alloc_coherent
);
2922 domain
= get_domain(dev
);
2923 if (PTR_ERR(domain
) == -EINVAL
) {
2924 page
= alloc_pages(flag
, get_order(size
));
2925 *dma_addr
= page_to_phys(page
);
2926 return page_address(page
);
2927 } else if (IS_ERR(domain
))
2930 size
= PAGE_ALIGN(size
);
2931 dma_mask
= dev
->coherent_dma_mask
;
2932 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
2935 page
= alloc_pages(flag
| __GFP_NOWARN
, get_order(size
));
2937 if (!(flag
& __GFP_WAIT
))
2940 page
= dma_alloc_from_contiguous(dev
, size
>> PAGE_SHIFT
,
2947 dma_mask
= *dev
->dma_mask
;
2949 spin_lock_irqsave(&domain
->lock
, flags
);
2951 *dma_addr
= __map_single(dev
, domain
->priv
, page_to_phys(page
),
2952 size
, DMA_BIDIRECTIONAL
, true, dma_mask
);
2954 if (*dma_addr
== DMA_ERROR_CODE
) {
2955 spin_unlock_irqrestore(&domain
->lock
, flags
);
2959 domain_flush_complete(domain
);
2961 spin_unlock_irqrestore(&domain
->lock
, flags
);
2963 return page_address(page
);
2967 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2968 __free_pages(page
, get_order(size
));
2974 * The exported free_coherent function for dma_ops.
2976 static void free_coherent(struct device
*dev
, size_t size
,
2977 void *virt_addr
, dma_addr_t dma_addr
,
2978 struct dma_attrs
*attrs
)
2980 struct protection_domain
*domain
;
2981 unsigned long flags
;
2984 INC_STATS_COUNTER(cnt_free_coherent
);
2986 page
= virt_to_page(virt_addr
);
2987 size
= PAGE_ALIGN(size
);
2989 domain
= get_domain(dev
);
2993 spin_lock_irqsave(&domain
->lock
, flags
);
2995 __unmap_single(domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
2997 domain_flush_complete(domain
);
2999 spin_unlock_irqrestore(&domain
->lock
, flags
);
3002 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
3003 __free_pages(page
, get_order(size
));
3007 * This function is called by the DMA layer to find out if we can handle a
3008 * particular device. It is part of the dma_ops.
3010 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
3012 return check_device(dev
);
3016 * The function for pre-allocating protection domains.
3018 * If the driver core informs the DMA layer if a driver grabs a device
3019 * we don't need to preallocate the protection domains anymore.
3020 * For now we have to.
3022 static void __init
prealloc_protection_domains(void)
3024 struct iommu_dev_data
*dev_data
;
3025 struct dma_ops_domain
*dma_dom
;
3026 struct pci_dev
*dev
= NULL
;
3029 for_each_pci_dev(dev
) {
3031 /* Do we handle this device? */
3032 if (!check_device(&dev
->dev
))
3035 dev_data
= get_dev_data(&dev
->dev
);
3036 if (!amd_iommu_force_isolation
&& dev_data
->iommu_v2
) {
3037 /* Make sure passthrough domain is allocated */
3038 alloc_passthrough_domain();
3039 dev_data
->passthrough
= true;
3040 attach_device(&dev
->dev
, pt_domain
);
3041 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
3042 dev_name(&dev
->dev
));
3045 /* Is there already any domain for it? */
3046 if (domain_for_device(&dev
->dev
))
3049 devid
= get_device_id(&dev
->dev
);
3051 dma_dom
= dma_ops_domain_alloc();
3054 init_unity_mappings_for_device(dma_dom
, devid
);
3055 dma_dom
->target_dev
= devid
;
3057 attach_device(&dev
->dev
, &dma_dom
->domain
);
3059 list_add_tail(&dma_dom
->list
, &iommu_pd_list
);
3063 static struct dma_map_ops amd_iommu_dma_ops
= {
3064 .alloc
= alloc_coherent
,
3065 .free
= free_coherent
,
3066 .map_page
= map_page
,
3067 .unmap_page
= unmap_page
,
3069 .unmap_sg
= unmap_sg
,
3070 .dma_supported
= amd_iommu_dma_supported
,
3073 static unsigned device_dma_ops_init(void)
3075 struct iommu_dev_data
*dev_data
;
3076 struct pci_dev
*pdev
= NULL
;
3077 unsigned unhandled
= 0;
3079 for_each_pci_dev(pdev
) {
3080 if (!check_device(&pdev
->dev
)) {
3082 iommu_ignore_device(&pdev
->dev
);
3088 dev_data
= get_dev_data(&pdev
->dev
);
3090 if (!dev_data
->passthrough
)
3091 pdev
->dev
.archdata
.dma_ops
= &amd_iommu_dma_ops
;
3093 pdev
->dev
.archdata
.dma_ops
= &nommu_dma_ops
;
3100 * The function which clues the AMD IOMMU driver into dma_ops.
3103 void __init
amd_iommu_init_api(void)
3105 bus_set_iommu(&pci_bus_type
, &amd_iommu_ops
);
3108 int __init
amd_iommu_init_dma_ops(void)
3110 struct amd_iommu
*iommu
;
3114 * first allocate a default protection domain for every IOMMU we
3115 * found in the system. Devices not assigned to any other
3116 * protection domain will be assigned to the default one.
3118 for_each_iommu(iommu
) {
3119 iommu
->default_dom
= dma_ops_domain_alloc();
3120 if (iommu
->default_dom
== NULL
)
3122 iommu
->default_dom
->domain
.flags
|= PD_DEFAULT_MASK
;
3123 ret
= iommu_init_unity_mappings(iommu
);
3129 * Pre-allocate the protection domains for each device.
3131 prealloc_protection_domains();
3136 /* Make the driver finally visible to the drivers */
3137 unhandled
= device_dma_ops_init();
3138 if (unhandled
&& max_pfn
> MAX_DMA32_PFN
) {
3139 /* There are unhandled devices - initialize swiotlb for them */
3143 amd_iommu_stats_init();
3145 if (amd_iommu_unmap_flush
)
3146 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3148 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3154 for_each_iommu(iommu
) {
3155 dma_ops_domain_free(iommu
->default_dom
);
3161 /*****************************************************************************
3163 * The following functions belong to the exported interface of AMD IOMMU
3165 * This interface allows access to lower level functions of the IOMMU
3166 * like protection domain handling and assignement of devices to domains
3167 * which is not possible with the dma_ops interface.
3169 *****************************************************************************/
3171 static void cleanup_domain(struct protection_domain
*domain
)
3173 struct iommu_dev_data
*entry
;
3174 unsigned long flags
;
3176 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
3178 while (!list_empty(&domain
->dev_list
)) {
3179 entry
= list_first_entry(&domain
->dev_list
,
3180 struct iommu_dev_data
, list
);
3181 __detach_device(entry
);
3184 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
3187 static void protection_domain_free(struct protection_domain
*domain
)
3192 del_domain_from_list(domain
);
3195 domain_id_free(domain
->id
);
3200 static struct protection_domain
*protection_domain_alloc(void)
3202 struct protection_domain
*domain
;
3204 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
3208 spin_lock_init(&domain
->lock
);
3209 mutex_init(&domain
->api_lock
);
3210 domain
->id
= domain_id_alloc();
3213 INIT_LIST_HEAD(&domain
->dev_list
);
3215 add_domain_to_list(domain
);
3225 static int __init
alloc_passthrough_domain(void)
3227 if (pt_domain
!= NULL
)
3230 /* allocate passthrough domain */
3231 pt_domain
= protection_domain_alloc();
3235 pt_domain
->mode
= PAGE_MODE_NONE
;
3240 static struct iommu_domain
*amd_iommu_domain_alloc(unsigned type
)
3242 struct protection_domain
*pdomain
;
3244 /* We only support unmanaged domains for now */
3245 if (type
!= IOMMU_DOMAIN_UNMANAGED
)
3248 pdomain
= protection_domain_alloc();
3252 pdomain
->mode
= PAGE_MODE_3_LEVEL
;
3253 pdomain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
3254 if (!pdomain
->pt_root
)
3257 pdomain
->domain
.geometry
.aperture_start
= 0;
3258 pdomain
->domain
.geometry
.aperture_end
= ~0ULL;
3259 pdomain
->domain
.geometry
.force_aperture
= true;
3261 return &pdomain
->domain
;
3264 protection_domain_free(pdomain
);
3269 static void amd_iommu_domain_free(struct iommu_domain
*dom
)
3271 struct protection_domain
*domain
;
3276 domain
= to_pdomain(dom
);
3278 if (domain
->dev_cnt
> 0)
3279 cleanup_domain(domain
);
3281 BUG_ON(domain
->dev_cnt
!= 0);
3283 if (domain
->mode
!= PAGE_MODE_NONE
)
3284 free_pagetable(domain
);
3286 if (domain
->flags
& PD_IOMMUV2_MASK
)
3287 free_gcr3_table(domain
);
3289 protection_domain_free(domain
);
3292 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
3295 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
3296 struct amd_iommu
*iommu
;
3299 if (!check_device(dev
))
3302 devid
= get_device_id(dev
);
3304 if (dev_data
->domain
!= NULL
)
3307 iommu
= amd_iommu_rlookup_table
[devid
];
3311 iommu_completion_wait(iommu
);
3314 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
3317 struct protection_domain
*domain
= to_pdomain(dom
);
3318 struct iommu_dev_data
*dev_data
;
3319 struct amd_iommu
*iommu
;
3322 if (!check_device(dev
))
3325 dev_data
= dev
->archdata
.iommu
;
3327 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3331 if (dev_data
->domain
)
3334 ret
= attach_device(dev
, domain
);
3336 iommu_completion_wait(iommu
);
3341 static int amd_iommu_map(struct iommu_domain
*dom
, unsigned long iova
,
3342 phys_addr_t paddr
, size_t page_size
, int iommu_prot
)
3344 struct protection_domain
*domain
= to_pdomain(dom
);
3348 if (domain
->mode
== PAGE_MODE_NONE
)
3351 if (iommu_prot
& IOMMU_READ
)
3352 prot
|= IOMMU_PROT_IR
;
3353 if (iommu_prot
& IOMMU_WRITE
)
3354 prot
|= IOMMU_PROT_IW
;
3356 mutex_lock(&domain
->api_lock
);
3357 ret
= iommu_map_page(domain
, iova
, paddr
, prot
, page_size
);
3358 mutex_unlock(&domain
->api_lock
);
3363 static size_t amd_iommu_unmap(struct iommu_domain
*dom
, unsigned long iova
,
3366 struct protection_domain
*domain
= to_pdomain(dom
);
3369 if (domain
->mode
== PAGE_MODE_NONE
)
3372 mutex_lock(&domain
->api_lock
);
3373 unmap_size
= iommu_unmap_page(domain
, iova
, page_size
);
3374 mutex_unlock(&domain
->api_lock
);
3376 domain_flush_tlb_pde(domain
);
3381 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
3384 struct protection_domain
*domain
= to_pdomain(dom
);
3385 unsigned long offset_mask
, pte_pgsize
;
3388 if (domain
->mode
== PAGE_MODE_NONE
)
3391 pte
= fetch_pte(domain
, iova
, &pte_pgsize
);
3393 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
3396 offset_mask
= pte_pgsize
- 1;
3397 __pte
= *pte
& PM_ADDR_MASK
;
3399 return (__pte
& ~offset_mask
) | (iova
& offset_mask
);
3402 static bool amd_iommu_capable(enum iommu_cap cap
)
3405 case IOMMU_CAP_CACHE_COHERENCY
:
3407 case IOMMU_CAP_INTR_REMAP
:
3408 return (irq_remapping_enabled
== 1);
3409 case IOMMU_CAP_NOEXEC
:
3416 static const struct iommu_ops amd_iommu_ops
= {
3417 .capable
= amd_iommu_capable
,
3418 .domain_alloc
= amd_iommu_domain_alloc
,
3419 .domain_free
= amd_iommu_domain_free
,
3420 .attach_dev
= amd_iommu_attach_device
,
3421 .detach_dev
= amd_iommu_detach_device
,
3422 .map
= amd_iommu_map
,
3423 .unmap
= amd_iommu_unmap
,
3424 .map_sg
= default_iommu_map_sg
,
3425 .iova_to_phys
= amd_iommu_iova_to_phys
,
3426 .pgsize_bitmap
= AMD_IOMMU_PGSIZES
,
3429 /*****************************************************************************
3431 * The next functions do a basic initialization of IOMMU for pass through
3434 * In passthrough mode the IOMMU is initialized and enabled but not used for
3435 * DMA-API translation.
3437 *****************************************************************************/
3439 int __init
amd_iommu_init_passthrough(void)
3441 struct iommu_dev_data
*dev_data
;
3442 struct pci_dev
*dev
= NULL
;
3445 ret
= alloc_passthrough_domain();
3449 for_each_pci_dev(dev
) {
3450 if (!check_device(&dev
->dev
))
3453 dev_data
= get_dev_data(&dev
->dev
);
3454 dev_data
->passthrough
= true;
3456 attach_device(&dev
->dev
, pt_domain
);
3459 amd_iommu_stats_init();
3461 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3466 /* IOMMUv2 specific functions */
3467 int amd_iommu_register_ppr_notifier(struct notifier_block
*nb
)
3469 return atomic_notifier_chain_register(&ppr_notifier
, nb
);
3471 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier
);
3473 int amd_iommu_unregister_ppr_notifier(struct notifier_block
*nb
)
3475 return atomic_notifier_chain_unregister(&ppr_notifier
, nb
);
3477 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier
);
3479 void amd_iommu_domain_direct_map(struct iommu_domain
*dom
)
3481 struct protection_domain
*domain
= to_pdomain(dom
);
3482 unsigned long flags
;
3484 spin_lock_irqsave(&domain
->lock
, flags
);
3486 /* Update data structure */
3487 domain
->mode
= PAGE_MODE_NONE
;
3488 domain
->updated
= true;
3490 /* Make changes visible to IOMMUs */
3491 update_domain(domain
);
3493 /* Page-table is not visible to IOMMU anymore, so free it */
3494 free_pagetable(domain
);
3496 spin_unlock_irqrestore(&domain
->lock
, flags
);
3498 EXPORT_SYMBOL(amd_iommu_domain_direct_map
);
3500 int amd_iommu_domain_enable_v2(struct iommu_domain
*dom
, int pasids
)
3502 struct protection_domain
*domain
= to_pdomain(dom
);
3503 unsigned long flags
;
3506 if (pasids
<= 0 || pasids
> (PASID_MASK
+ 1))
3509 /* Number of GCR3 table levels required */
3510 for (levels
= 0; (pasids
- 1) & ~0x1ff; pasids
>>= 9)
3513 if (levels
> amd_iommu_max_glx_val
)
3516 spin_lock_irqsave(&domain
->lock
, flags
);
3519 * Save us all sanity checks whether devices already in the
3520 * domain support IOMMUv2. Just force that the domain has no
3521 * devices attached when it is switched into IOMMUv2 mode.
3524 if (domain
->dev_cnt
> 0 || domain
->flags
& PD_IOMMUV2_MASK
)
3528 domain
->gcr3_tbl
= (void *)get_zeroed_page(GFP_ATOMIC
);
3529 if (domain
->gcr3_tbl
== NULL
)
3532 domain
->glx
= levels
;
3533 domain
->flags
|= PD_IOMMUV2_MASK
;
3534 domain
->updated
= true;
3536 update_domain(domain
);
3541 spin_unlock_irqrestore(&domain
->lock
, flags
);
3545 EXPORT_SYMBOL(amd_iommu_domain_enable_v2
);
3547 static int __flush_pasid(struct protection_domain
*domain
, int pasid
,
3548 u64 address
, bool size
)
3550 struct iommu_dev_data
*dev_data
;
3551 struct iommu_cmd cmd
;
3554 if (!(domain
->flags
& PD_IOMMUV2_MASK
))
3557 build_inv_iommu_pasid(&cmd
, domain
->id
, pasid
, address
, size
);
3560 * IOMMU TLB needs to be flushed before Device TLB to
3561 * prevent device TLB refill from IOMMU TLB
3563 for (i
= 0; i
< amd_iommus_present
; ++i
) {
3564 if (domain
->dev_iommu
[i
] == 0)
3567 ret
= iommu_queue_command(amd_iommus
[i
], &cmd
);
3572 /* Wait until IOMMU TLB flushes are complete */
3573 domain_flush_complete(domain
);
3575 /* Now flush device TLBs */
3576 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
3577 struct amd_iommu
*iommu
;
3580 BUG_ON(!dev_data
->ats
.enabled
);
3582 qdep
= dev_data
->ats
.qdep
;
3583 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3585 build_inv_iotlb_pasid(&cmd
, dev_data
->devid
, pasid
,
3586 qdep
, address
, size
);
3588 ret
= iommu_queue_command(iommu
, &cmd
);
3593 /* Wait until all device TLBs are flushed */
3594 domain_flush_complete(domain
);
3603 static int __amd_iommu_flush_page(struct protection_domain
*domain
, int pasid
,
3606 INC_STATS_COUNTER(invalidate_iotlb
);
3608 return __flush_pasid(domain
, pasid
, address
, false);
3611 int amd_iommu_flush_page(struct iommu_domain
*dom
, int pasid
,
3614 struct protection_domain
*domain
= to_pdomain(dom
);
3615 unsigned long flags
;
3618 spin_lock_irqsave(&domain
->lock
, flags
);
3619 ret
= __amd_iommu_flush_page(domain
, pasid
, address
);
3620 spin_unlock_irqrestore(&domain
->lock
, flags
);
3624 EXPORT_SYMBOL(amd_iommu_flush_page
);
3626 static int __amd_iommu_flush_tlb(struct protection_domain
*domain
, int pasid
)
3628 INC_STATS_COUNTER(invalidate_iotlb_all
);
3630 return __flush_pasid(domain
, pasid
, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
3634 int amd_iommu_flush_tlb(struct iommu_domain
*dom
, int pasid
)
3636 struct protection_domain
*domain
= to_pdomain(dom
);
3637 unsigned long flags
;
3640 spin_lock_irqsave(&domain
->lock
, flags
);
3641 ret
= __amd_iommu_flush_tlb(domain
, pasid
);
3642 spin_unlock_irqrestore(&domain
->lock
, flags
);
3646 EXPORT_SYMBOL(amd_iommu_flush_tlb
);
3648 static u64
*__get_gcr3_pte(u64
*root
, int level
, int pasid
, bool alloc
)
3655 index
= (pasid
>> (9 * level
)) & 0x1ff;
3661 if (!(*pte
& GCR3_VALID
)) {
3665 root
= (void *)get_zeroed_page(GFP_ATOMIC
);
3669 *pte
= __pa(root
) | GCR3_VALID
;
3672 root
= __va(*pte
& PAGE_MASK
);
3680 static int __set_gcr3(struct protection_domain
*domain
, int pasid
,
3685 if (domain
->mode
!= PAGE_MODE_NONE
)
3688 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, true);
3692 *pte
= (cr3
& PAGE_MASK
) | GCR3_VALID
;
3694 return __amd_iommu_flush_tlb(domain
, pasid
);
3697 static int __clear_gcr3(struct protection_domain
*domain
, int pasid
)
3701 if (domain
->mode
!= PAGE_MODE_NONE
)
3704 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, false);
3710 return __amd_iommu_flush_tlb(domain
, pasid
);
3713 int amd_iommu_domain_set_gcr3(struct iommu_domain
*dom
, int pasid
,
3716 struct protection_domain
*domain
= to_pdomain(dom
);
3717 unsigned long flags
;
3720 spin_lock_irqsave(&domain
->lock
, flags
);
3721 ret
= __set_gcr3(domain
, pasid
, cr3
);
3722 spin_unlock_irqrestore(&domain
->lock
, flags
);
3726 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3
);
3728 int amd_iommu_domain_clear_gcr3(struct iommu_domain
*dom
, int pasid
)
3730 struct protection_domain
*domain
= to_pdomain(dom
);
3731 unsigned long flags
;
3734 spin_lock_irqsave(&domain
->lock
, flags
);
3735 ret
= __clear_gcr3(domain
, pasid
);
3736 spin_unlock_irqrestore(&domain
->lock
, flags
);
3740 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3
);
3742 int amd_iommu_complete_ppr(struct pci_dev
*pdev
, int pasid
,
3743 int status
, int tag
)
3745 struct iommu_dev_data
*dev_data
;
3746 struct amd_iommu
*iommu
;
3747 struct iommu_cmd cmd
;
3749 INC_STATS_COUNTER(complete_ppr
);
3751 dev_data
= get_dev_data(&pdev
->dev
);
3752 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3754 build_complete_ppr(&cmd
, dev_data
->devid
, pasid
, status
,
3755 tag
, dev_data
->pri_tlp
);
3757 return iommu_queue_command(iommu
, &cmd
);
3759 EXPORT_SYMBOL(amd_iommu_complete_ppr
);
3761 struct iommu_domain
*amd_iommu_get_v2_domain(struct pci_dev
*pdev
)
3763 struct protection_domain
*pdomain
;
3765 pdomain
= get_domain(&pdev
->dev
);
3766 if (IS_ERR(pdomain
))
3769 /* Only return IOMMUv2 domains */
3770 if (!(pdomain
->flags
& PD_IOMMUV2_MASK
))
3773 return &pdomain
->domain
;
3775 EXPORT_SYMBOL(amd_iommu_get_v2_domain
);
3777 void amd_iommu_enable_device_erratum(struct pci_dev
*pdev
, u32 erratum
)
3779 struct iommu_dev_data
*dev_data
;
3781 if (!amd_iommu_v2_supported())
3784 dev_data
= get_dev_data(&pdev
->dev
);
3785 dev_data
->errata
|= (1 << erratum
);
3787 EXPORT_SYMBOL(amd_iommu_enable_device_erratum
);
3789 int amd_iommu_device_info(struct pci_dev
*pdev
,
3790 struct amd_iommu_device_info
*info
)
3795 if (pdev
== NULL
|| info
== NULL
)
3798 if (!amd_iommu_v2_supported())
3801 memset(info
, 0, sizeof(*info
));
3803 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ATS
);
3805 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_ATS_SUP
;
3807 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
3809 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRI_SUP
;
3811 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PASID
);
3815 max_pasids
= 1 << (9 * (amd_iommu_max_glx_val
+ 1));
3816 max_pasids
= min(max_pasids
, (1 << 20));
3818 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PASID_SUP
;
3819 info
->max_pasids
= min(pci_max_pasids(pdev
), max_pasids
);
3821 features
= pci_pasid_features(pdev
);
3822 if (features
& PCI_PASID_CAP_EXEC
)
3823 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP
;
3824 if (features
& PCI_PASID_CAP_PRIV
)
3825 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP
;
3830 EXPORT_SYMBOL(amd_iommu_device_info
);
3832 #ifdef CONFIG_IRQ_REMAP
3834 /*****************************************************************************
3836 * Interrupt Remapping Implementation
3838 *****************************************************************************/
3855 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3856 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3857 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3858 #define DTE_IRQ_REMAP_ENABLE 1ULL
3860 static void set_dte_irq_entry(u16 devid
, struct irq_remap_table
*table
)
3864 dte
= amd_iommu_dev_table
[devid
].data
[2];
3865 dte
&= ~DTE_IRQ_PHYS_ADDR_MASK
;
3866 dte
|= virt_to_phys(table
->table
);
3867 dte
|= DTE_IRQ_REMAP_INTCTL
;
3868 dte
|= DTE_IRQ_TABLE_LEN
;
3869 dte
|= DTE_IRQ_REMAP_ENABLE
;
3871 amd_iommu_dev_table
[devid
].data
[2] = dte
;
3874 #define IRTE_ALLOCATED (~1U)
3876 static struct irq_remap_table
*get_irq_table(u16 devid
, bool ioapic
)
3878 struct irq_remap_table
*table
= NULL
;
3879 struct amd_iommu
*iommu
;
3880 unsigned long flags
;
3883 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
3885 iommu
= amd_iommu_rlookup_table
[devid
];
3889 table
= irq_lookup_table
[devid
];
3893 alias
= amd_iommu_alias_table
[devid
];
3894 table
= irq_lookup_table
[alias
];
3896 irq_lookup_table
[devid
] = table
;
3897 set_dte_irq_entry(devid
, table
);
3898 iommu_flush_dte(iommu
, devid
);
3902 /* Nothing there yet, allocate new irq remapping table */
3903 table
= kzalloc(sizeof(*table
), GFP_ATOMIC
);
3907 /* Initialize table spin-lock */
3908 spin_lock_init(&table
->lock
);
3911 /* Keep the first 32 indexes free for IOAPIC interrupts */
3912 table
->min_index
= 32;
3914 table
->table
= kmem_cache_alloc(amd_iommu_irq_cache
, GFP_ATOMIC
);
3915 if (!table
->table
) {
3921 memset(table
->table
, 0, MAX_IRQS_PER_TABLE
* sizeof(u32
));
3926 for (i
= 0; i
< 32; ++i
)
3927 table
->table
[i
] = IRTE_ALLOCATED
;
3930 irq_lookup_table
[devid
] = table
;
3931 set_dte_irq_entry(devid
, table
);
3932 iommu_flush_dte(iommu
, devid
);
3933 if (devid
!= alias
) {
3934 irq_lookup_table
[alias
] = table
;
3935 set_dte_irq_entry(alias
, table
);
3936 iommu_flush_dte(iommu
, alias
);
3940 iommu_completion_wait(iommu
);
3943 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
3948 static int alloc_irq_index(struct irq_cfg
*cfg
, u16 devid
, int count
)
3950 struct irq_remap_table
*table
;
3951 unsigned long flags
;
3954 table
= get_irq_table(devid
, false);
3958 spin_lock_irqsave(&table
->lock
, flags
);
3960 /* Scan table for free entries */
3961 for (c
= 0, index
= table
->min_index
;
3962 index
< MAX_IRQS_PER_TABLE
;
3964 if (table
->table
[index
] == 0)
3970 struct irq_2_irte
*irte_info
;
3973 table
->table
[index
- c
+ 1] = IRTE_ALLOCATED
;
3978 irte_info
= &cfg
->irq_2_irte
;
3979 irte_info
->devid
= devid
;
3980 irte_info
->index
= index
;
3989 spin_unlock_irqrestore(&table
->lock
, flags
);
3994 static int get_irte(u16 devid
, int index
, union irte
*irte
)
3996 struct irq_remap_table
*table
;
3997 unsigned long flags
;
3999 table
= get_irq_table(devid
, false);
4003 spin_lock_irqsave(&table
->lock
, flags
);
4004 irte
->val
= table
->table
[index
];
4005 spin_unlock_irqrestore(&table
->lock
, flags
);
4010 static int modify_irte(u16 devid
, int index
, union irte irte
)
4012 struct irq_remap_table
*table
;
4013 struct amd_iommu
*iommu
;
4014 unsigned long flags
;
4016 iommu
= amd_iommu_rlookup_table
[devid
];
4020 table
= get_irq_table(devid
, false);
4024 spin_lock_irqsave(&table
->lock
, flags
);
4025 table
->table
[index
] = irte
.val
;
4026 spin_unlock_irqrestore(&table
->lock
, flags
);
4028 iommu_flush_irt(iommu
, devid
);
4029 iommu_completion_wait(iommu
);
4034 static void free_irte(u16 devid
, int index
)
4036 struct irq_remap_table
*table
;
4037 struct amd_iommu
*iommu
;
4038 unsigned long flags
;
4040 iommu
= amd_iommu_rlookup_table
[devid
];
4044 table
= get_irq_table(devid
, false);
4048 spin_lock_irqsave(&table
->lock
, flags
);
4049 table
->table
[index
] = 0;
4050 spin_unlock_irqrestore(&table
->lock
, flags
);
4052 iommu_flush_irt(iommu
, devid
);
4053 iommu_completion_wait(iommu
);
4056 static int setup_ioapic_entry(int irq
, struct IO_APIC_route_entry
*entry
,
4057 unsigned int destination
, int vector
,
4058 struct io_apic_irq_attr
*attr
)
4060 struct irq_remap_table
*table
;
4061 struct irq_2_irte
*irte_info
;
4062 struct irq_cfg
*cfg
;
4073 irte_info
= &cfg
->irq_2_irte
;
4074 ioapic_id
= mpc_ioapic_id(attr
->ioapic
);
4075 devid
= get_ioapic_devid(ioapic_id
);
4080 table
= get_irq_table(devid
, true);
4084 index
= attr
->ioapic_pin
;
4086 /* Setup IRQ remapping info */
4088 irte_info
->devid
= devid
;
4089 irte_info
->index
= index
;
4091 /* Setup IRTE for IOMMU */
4093 irte
.fields
.vector
= vector
;
4094 irte
.fields
.int_type
= apic
->irq_delivery_mode
;
4095 irte
.fields
.destination
= destination
;
4096 irte
.fields
.dm
= apic
->irq_dest_mode
;
4097 irte
.fields
.valid
= 1;
4099 ret
= modify_irte(devid
, index
, irte
);
4103 /* Setup IOAPIC entry */
4104 memset(entry
, 0, sizeof(*entry
));
4106 entry
->vector
= index
;
4108 entry
->trigger
= attr
->trigger
;
4109 entry
->polarity
= attr
->polarity
;
4112 * Mask level triggered irqs.
4120 static int set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
4123 struct irq_2_irte
*irte_info
;
4124 unsigned int dest
, irq
;
4125 struct irq_cfg
*cfg
;
4129 if (!config_enabled(CONFIG_SMP
))
4132 cfg
= irqd_cfg(data
);
4134 irte_info
= &cfg
->irq_2_irte
;
4136 if (!cpumask_intersects(mask
, cpu_online_mask
))
4139 if (get_irte(irte_info
->devid
, irte_info
->index
, &irte
))
4142 if (assign_irq_vector(irq
, cfg
, mask
))
4145 err
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
, &dest
);
4147 if (assign_irq_vector(irq
, cfg
, data
->affinity
))
4148 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq
);
4152 irte
.fields
.vector
= cfg
->vector
;
4153 irte
.fields
.destination
= dest
;
4155 modify_irte(irte_info
->devid
, irte_info
->index
, irte
);
4157 if (cfg
->move_in_progress
)
4158 send_cleanup_vector(cfg
);
4160 cpumask_copy(data
->affinity
, mask
);
4165 static int free_irq(int irq
)
4167 struct irq_2_irte
*irte_info
;
4168 struct irq_cfg
*cfg
;
4174 irte_info
= &cfg
->irq_2_irte
;
4176 free_irte(irte_info
->devid
, irte_info
->index
);
4181 static void compose_msi_msg(struct pci_dev
*pdev
,
4182 unsigned int irq
, unsigned int dest
,
4183 struct msi_msg
*msg
, u8 hpet_id
)
4185 struct irq_2_irte
*irte_info
;
4186 struct irq_cfg
*cfg
;
4193 irte_info
= &cfg
->irq_2_irte
;
4196 irte
.fields
.vector
= cfg
->vector
;
4197 irte
.fields
.int_type
= apic
->irq_delivery_mode
;
4198 irte
.fields
.destination
= dest
;
4199 irte
.fields
.dm
= apic
->irq_dest_mode
;
4200 irte
.fields
.valid
= 1;
4202 modify_irte(irte_info
->devid
, irte_info
->index
, irte
);
4204 msg
->address_hi
= MSI_ADDR_BASE_HI
;
4205 msg
->address_lo
= MSI_ADDR_BASE_LO
;
4206 msg
->data
= irte_info
->index
;
4209 static int msi_alloc_irq(struct pci_dev
*pdev
, int irq
, int nvec
)
4211 struct irq_cfg
*cfg
;
4222 devid
= get_device_id(&pdev
->dev
);
4223 index
= alloc_irq_index(cfg
, devid
, nvec
);
4225 return index
< 0 ? MAX_IRQS_PER_TABLE
: index
;
4228 static int msi_setup_irq(struct pci_dev
*pdev
, unsigned int irq
,
4229 int index
, int offset
)
4231 struct irq_2_irte
*irte_info
;
4232 struct irq_cfg
*cfg
;
4242 if (index
>= MAX_IRQS_PER_TABLE
)
4245 devid
= get_device_id(&pdev
->dev
);
4246 irte_info
= &cfg
->irq_2_irte
;
4249 irte_info
->devid
= devid
;
4250 irte_info
->index
= index
+ offset
;
4255 static int alloc_hpet_msi(unsigned int irq
, unsigned int id
)
4257 struct irq_2_irte
*irte_info
;
4258 struct irq_cfg
*cfg
;
4265 irte_info
= &cfg
->irq_2_irte
;
4266 devid
= get_hpet_devid(id
);
4270 index
= alloc_irq_index(cfg
, devid
, 1);
4275 irte_info
->devid
= devid
;
4276 irte_info
->index
= index
;
4281 struct irq_remap_ops amd_iommu_irq_ops
= {
4282 .prepare
= amd_iommu_prepare
,
4283 .enable
= amd_iommu_enable
,
4284 .disable
= amd_iommu_disable
,
4285 .reenable
= amd_iommu_reenable
,
4286 .enable_faulting
= amd_iommu_enable_faulting
,
4287 .setup_ioapic_entry
= setup_ioapic_entry
,
4288 .set_affinity
= set_affinity
,
4289 .free_irq
= free_irq
,
4290 .compose_msi_msg
= compose_msi_msg
,
4291 .msi_alloc_irq
= msi_alloc_irq
,
4292 .msi_setup_irq
= msi_setup_irq
,
4293 .alloc_hpet_msi
= alloc_hpet_msi
,