2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <linux/dma-contiguous.h>
37 #include <linux/irqdomain.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/io_apic.h>
41 #include <asm/hw_irq.h>
42 #include <asm/msidef.h>
43 #include <asm/proto.h>
44 #include <asm/iommu.h>
48 #include "amd_iommu_proto.h"
49 #include "amd_iommu_types.h"
50 #include "irq_remapping.h"
52 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
54 #define LOOP_TIMEOUT 100000
57 * This bitmap is used to advertise the page sizes our hardware support
58 * to the IOMMU core, which will then use this information to split
59 * physically contiguous memory regions it is mapping into page sizes
62 * 512GB Pages are not supported due to a hardware bug
64 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
66 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
68 /* List of all available dev_data structures */
69 static LIST_HEAD(dev_data_list
);
70 static DEFINE_SPINLOCK(dev_data_list_lock
);
72 LIST_HEAD(ioapic_map
);
76 * Domain for untranslated devices - only allocated
77 * if iommu=pt passed on kernel cmd line.
79 static struct protection_domain
*pt_domain
;
81 static const struct iommu_ops amd_iommu_ops
;
83 static ATOMIC_NOTIFIER_HEAD(ppr_notifier
);
84 int amd_iommu_max_glx_val
= -1;
86 static struct dma_map_ops amd_iommu_dma_ops
;
89 * This struct contains device specific data for the IOMMU
91 struct iommu_dev_data
{
92 struct list_head list
; /* For domain->dev_list */
93 struct list_head dev_data_list
; /* For global dev_data_list */
94 struct list_head alias_list
; /* Link alias-groups together */
95 struct iommu_dev_data
*alias_data
;/* The alias dev_data */
96 struct protection_domain
*domain
; /* Domain the device is bound to */
97 u16 devid
; /* PCI Device ID */
98 bool iommu_v2
; /* Device can make use of IOMMUv2 */
99 bool passthrough
; /* Default for device is pt_domain */
103 } ats
; /* ATS state */
104 bool pri_tlp
; /* PASID TLB required for
106 u32 errata
; /* Bitmap for errata to apply */
110 * general struct to manage commands send to an IOMMU
116 struct kmem_cache
*amd_iommu_irq_cache
;
118 static void update_domain(struct protection_domain
*domain
);
119 static int alloc_passthrough_domain(void);
121 /****************************************************************************
125 ****************************************************************************/
127 static struct protection_domain
*to_pdomain(struct iommu_domain
*dom
)
129 return container_of(dom
, struct protection_domain
, domain
);
132 static struct iommu_dev_data
*alloc_dev_data(u16 devid
)
134 struct iommu_dev_data
*dev_data
;
137 dev_data
= kzalloc(sizeof(*dev_data
), GFP_KERNEL
);
141 INIT_LIST_HEAD(&dev_data
->alias_list
);
143 dev_data
->devid
= devid
;
145 spin_lock_irqsave(&dev_data_list_lock
, flags
);
146 list_add_tail(&dev_data
->dev_data_list
, &dev_data_list
);
147 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
152 static void free_dev_data(struct iommu_dev_data
*dev_data
)
156 spin_lock_irqsave(&dev_data_list_lock
, flags
);
157 list_del(&dev_data
->dev_data_list
);
158 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
163 static struct iommu_dev_data
*search_dev_data(u16 devid
)
165 struct iommu_dev_data
*dev_data
;
168 spin_lock_irqsave(&dev_data_list_lock
, flags
);
169 list_for_each_entry(dev_data
, &dev_data_list
, dev_data_list
) {
170 if (dev_data
->devid
== devid
)
177 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
182 static struct iommu_dev_data
*find_dev_data(u16 devid
)
184 struct iommu_dev_data
*dev_data
;
186 dev_data
= search_dev_data(devid
);
188 if (dev_data
== NULL
)
189 dev_data
= alloc_dev_data(devid
);
194 static inline u16
get_device_id(struct device
*dev
)
196 struct pci_dev
*pdev
= to_pci_dev(dev
);
198 return PCI_DEVID(pdev
->bus
->number
, pdev
->devfn
);
201 static struct iommu_dev_data
*get_dev_data(struct device
*dev
)
203 return dev
->archdata
.iommu
;
206 static bool pci_iommuv2_capable(struct pci_dev
*pdev
)
208 static const int caps
[] = {
211 PCI_EXT_CAP_ID_PASID
,
215 for (i
= 0; i
< 3; ++i
) {
216 pos
= pci_find_ext_capability(pdev
, caps
[i
]);
224 static bool pdev_pri_erratum(struct pci_dev
*pdev
, u32 erratum
)
226 struct iommu_dev_data
*dev_data
;
228 dev_data
= get_dev_data(&pdev
->dev
);
230 return dev_data
->errata
& (1 << erratum
) ? true : false;
234 * This function actually applies the mapping to the page table of the
237 static void alloc_unity_mapping(struct dma_ops_domain
*dma_dom
,
238 struct unity_map_entry
*e
)
242 for (addr
= e
->address_start
; addr
< e
->address_end
;
244 if (addr
< dma_dom
->aperture_size
)
245 __set_bit(addr
>> PAGE_SHIFT
,
246 dma_dom
->aperture
[0]->bitmap
);
251 * Inits the unity mappings required for a specific device
253 static void init_unity_mappings_for_device(struct device
*dev
,
254 struct dma_ops_domain
*dma_dom
)
256 struct unity_map_entry
*e
;
259 devid
= get_device_id(dev
);
261 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
262 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
264 alloc_unity_mapping(dma_dom
, e
);
269 * This function checks if the driver got a valid device from the caller to
270 * avoid dereferencing invalid pointers.
272 static bool check_device(struct device
*dev
)
276 if (!dev
|| !dev
->dma_mask
)
280 if (!dev_is_pci(dev
))
283 devid
= get_device_id(dev
);
285 /* Out of our scope? */
286 if (devid
> amd_iommu_last_bdf
)
289 if (amd_iommu_rlookup_table
[devid
] == NULL
)
295 static void init_iommu_group(struct device
*dev
)
297 struct dma_ops_domain
*dma_domain
;
298 struct iommu_domain
*domain
;
299 struct iommu_group
*group
;
301 group
= iommu_group_get_for_dev(dev
);
305 domain
= iommu_group_default_domain(group
);
309 dma_domain
= to_pdomain(domain
)->priv
;
311 init_unity_mappings_for_device(dev
, dma_domain
);
313 iommu_group_put(group
);
316 static int __last_alias(struct pci_dev
*pdev
, u16 alias
, void *data
)
318 *(u16
*)data
= alias
;
322 static u16
get_alias(struct device
*dev
)
324 struct pci_dev
*pdev
= to_pci_dev(dev
);
325 u16 devid
, ivrs_alias
, pci_alias
;
327 devid
= get_device_id(dev
);
328 ivrs_alias
= amd_iommu_alias_table
[devid
];
329 pci_for_each_dma_alias(pdev
, __last_alias
, &pci_alias
);
331 if (ivrs_alias
== pci_alias
)
337 * The IVRS is fairly reliable in telling us about aliases, but it
338 * can't know about every screwy device. If we don't have an IVRS
339 * reported alias, use the PCI reported alias. In that case we may
340 * still need to initialize the rlookup and dev_table entries if the
341 * alias is to a non-existent device.
343 if (ivrs_alias
== devid
) {
344 if (!amd_iommu_rlookup_table
[pci_alias
]) {
345 amd_iommu_rlookup_table
[pci_alias
] =
346 amd_iommu_rlookup_table
[devid
];
347 memcpy(amd_iommu_dev_table
[pci_alias
].data
,
348 amd_iommu_dev_table
[devid
].data
,
349 sizeof(amd_iommu_dev_table
[pci_alias
].data
));
355 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
356 "for device %s[%04x:%04x], kernel reported alias "
357 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias
), PCI_SLOT(ivrs_alias
),
358 PCI_FUNC(ivrs_alias
), dev_name(dev
), pdev
->vendor
, pdev
->device
,
359 PCI_BUS_NUM(pci_alias
), PCI_SLOT(pci_alias
),
360 PCI_FUNC(pci_alias
));
363 * If we don't have a PCI DMA alias and the IVRS alias is on the same
364 * bus, then the IVRS table may know about a quirk that we don't.
366 if (pci_alias
== devid
&&
367 PCI_BUS_NUM(ivrs_alias
) == pdev
->bus
->number
) {
368 pdev
->dev_flags
|= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN
;
369 pdev
->dma_alias_devfn
= ivrs_alias
& 0xff;
370 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
371 PCI_SLOT(ivrs_alias
), PCI_FUNC(ivrs_alias
),
378 static int iommu_init_device(struct device
*dev
)
380 struct pci_dev
*pdev
= to_pci_dev(dev
);
381 struct iommu_dev_data
*dev_data
;
384 if (dev
->archdata
.iommu
)
387 dev_data
= find_dev_data(get_device_id(dev
));
391 alias
= get_alias(dev
);
393 if (alias
!= dev_data
->devid
) {
394 struct iommu_dev_data
*alias_data
;
396 alias_data
= find_dev_data(alias
);
397 if (alias_data
== NULL
) {
398 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
400 free_dev_data(dev_data
);
403 dev_data
->alias_data
= alias_data
;
405 /* Add device to the alias_list */
406 list_add(&dev_data
->alias_list
, &alias_data
->alias_list
);
409 if (pci_iommuv2_capable(pdev
)) {
410 struct amd_iommu
*iommu
;
412 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
413 dev_data
->iommu_v2
= iommu
->is_iommu_v2
;
416 dev
->archdata
.iommu
= dev_data
;
418 iommu_device_link(amd_iommu_rlookup_table
[dev_data
->devid
]->iommu_dev
,
424 static void iommu_ignore_device(struct device
*dev
)
428 devid
= get_device_id(dev
);
429 alias
= amd_iommu_alias_table
[devid
];
431 memset(&amd_iommu_dev_table
[devid
], 0, sizeof(struct dev_table_entry
));
432 memset(&amd_iommu_dev_table
[alias
], 0, sizeof(struct dev_table_entry
));
434 amd_iommu_rlookup_table
[devid
] = NULL
;
435 amd_iommu_rlookup_table
[alias
] = NULL
;
438 static void iommu_uninit_device(struct device
*dev
)
440 struct iommu_dev_data
*dev_data
= search_dev_data(get_device_id(dev
));
445 iommu_device_unlink(amd_iommu_rlookup_table
[dev_data
->devid
]->iommu_dev
,
448 iommu_group_remove_device(dev
);
450 /* Unlink from alias, it may change if another device is re-plugged */
451 dev_data
->alias_data
= NULL
;
454 dev
->archdata
.dma_ops
= NULL
;
457 * We keep dev_data around for unplugged devices and reuse it when the
458 * device is re-plugged - not doing so would introduce a ton of races.
462 #ifdef CONFIG_AMD_IOMMU_STATS
465 * Initialization code for statistics collection
468 DECLARE_STATS_COUNTER(compl_wait
);
469 DECLARE_STATS_COUNTER(cnt_map_single
);
470 DECLARE_STATS_COUNTER(cnt_unmap_single
);
471 DECLARE_STATS_COUNTER(cnt_map_sg
);
472 DECLARE_STATS_COUNTER(cnt_unmap_sg
);
473 DECLARE_STATS_COUNTER(cnt_alloc_coherent
);
474 DECLARE_STATS_COUNTER(cnt_free_coherent
);
475 DECLARE_STATS_COUNTER(cross_page
);
476 DECLARE_STATS_COUNTER(domain_flush_single
);
477 DECLARE_STATS_COUNTER(domain_flush_all
);
478 DECLARE_STATS_COUNTER(alloced_io_mem
);
479 DECLARE_STATS_COUNTER(total_map_requests
);
480 DECLARE_STATS_COUNTER(complete_ppr
);
481 DECLARE_STATS_COUNTER(invalidate_iotlb
);
482 DECLARE_STATS_COUNTER(invalidate_iotlb_all
);
483 DECLARE_STATS_COUNTER(pri_requests
);
485 static struct dentry
*stats_dir
;
486 static struct dentry
*de_fflush
;
488 static void amd_iommu_stats_add(struct __iommu_counter
*cnt
)
490 if (stats_dir
== NULL
)
493 cnt
->dent
= debugfs_create_u64(cnt
->name
, 0444, stats_dir
,
497 static void amd_iommu_stats_init(void)
499 stats_dir
= debugfs_create_dir("amd-iommu", NULL
);
500 if (stats_dir
== NULL
)
503 de_fflush
= debugfs_create_bool("fullflush", 0444, stats_dir
,
504 &amd_iommu_unmap_flush
);
506 amd_iommu_stats_add(&compl_wait
);
507 amd_iommu_stats_add(&cnt_map_single
);
508 amd_iommu_stats_add(&cnt_unmap_single
);
509 amd_iommu_stats_add(&cnt_map_sg
);
510 amd_iommu_stats_add(&cnt_unmap_sg
);
511 amd_iommu_stats_add(&cnt_alloc_coherent
);
512 amd_iommu_stats_add(&cnt_free_coherent
);
513 amd_iommu_stats_add(&cross_page
);
514 amd_iommu_stats_add(&domain_flush_single
);
515 amd_iommu_stats_add(&domain_flush_all
);
516 amd_iommu_stats_add(&alloced_io_mem
);
517 amd_iommu_stats_add(&total_map_requests
);
518 amd_iommu_stats_add(&complete_ppr
);
519 amd_iommu_stats_add(&invalidate_iotlb
);
520 amd_iommu_stats_add(&invalidate_iotlb_all
);
521 amd_iommu_stats_add(&pri_requests
);
526 /****************************************************************************
528 * Interrupt handling functions
530 ****************************************************************************/
532 static void dump_dte_entry(u16 devid
)
536 for (i
= 0; i
< 4; ++i
)
537 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i
,
538 amd_iommu_dev_table
[devid
].data
[i
]);
541 static void dump_command(unsigned long phys_addr
)
543 struct iommu_cmd
*cmd
= phys_to_virt(phys_addr
);
546 for (i
= 0; i
< 4; ++i
)
547 pr_err("AMD-Vi: CMD[%d]: %08x\n", i
, cmd
->data
[i
]);
550 static void iommu_print_event(struct amd_iommu
*iommu
, void *__evt
)
552 int type
, devid
, domid
, flags
;
553 volatile u32
*event
= __evt
;
558 type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
559 devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
560 domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
561 flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
562 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
565 /* Did we hit the erratum? */
566 if (++count
== LOOP_TIMEOUT
) {
567 pr_err("AMD-Vi: No event written to event log\n");
574 printk(KERN_ERR
"AMD-Vi: Event logged [");
577 case EVENT_TYPE_ILL_DEV
:
578 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
579 "address=0x%016llx flags=0x%04x]\n",
580 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
582 dump_dte_entry(devid
);
584 case EVENT_TYPE_IO_FAULT
:
585 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
586 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
587 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
588 domid
, address
, flags
);
590 case EVENT_TYPE_DEV_TAB_ERR
:
591 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
592 "address=0x%016llx flags=0x%04x]\n",
593 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
596 case EVENT_TYPE_PAGE_TAB_ERR
:
597 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
598 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
599 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
600 domid
, address
, flags
);
602 case EVENT_TYPE_ILL_CMD
:
603 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
604 dump_command(address
);
606 case EVENT_TYPE_CMD_HARD_ERR
:
607 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
608 "flags=0x%04x]\n", address
, flags
);
610 case EVENT_TYPE_IOTLB_INV_TO
:
611 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
612 "address=0x%016llx]\n",
613 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
616 case EVENT_TYPE_INV_DEV_REQ
:
617 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
618 "address=0x%016llx flags=0x%04x]\n",
619 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
623 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
626 memset(__evt
, 0, 4 * sizeof(u32
));
629 static void iommu_poll_events(struct amd_iommu
*iommu
)
633 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
634 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
636 while (head
!= tail
) {
637 iommu_print_event(iommu
, iommu
->evt_buf
+ head
);
638 head
= (head
+ EVENT_ENTRY_SIZE
) % iommu
->evt_buf_size
;
641 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
644 static void iommu_handle_ppr_entry(struct amd_iommu
*iommu
, u64
*raw
)
646 struct amd_iommu_fault fault
;
648 INC_STATS_COUNTER(pri_requests
);
650 if (PPR_REQ_TYPE(raw
[0]) != PPR_REQ_FAULT
) {
651 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
655 fault
.address
= raw
[1];
656 fault
.pasid
= PPR_PASID(raw
[0]);
657 fault
.device_id
= PPR_DEVID(raw
[0]);
658 fault
.tag
= PPR_TAG(raw
[0]);
659 fault
.flags
= PPR_FLAGS(raw
[0]);
661 atomic_notifier_call_chain(&ppr_notifier
, 0, &fault
);
664 static void iommu_poll_ppr_log(struct amd_iommu
*iommu
)
668 if (iommu
->ppr_log
== NULL
)
671 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
672 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
674 while (head
!= tail
) {
679 raw
= (u64
*)(iommu
->ppr_log
+ head
);
682 * Hardware bug: Interrupt may arrive before the entry is
683 * written to memory. If this happens we need to wait for the
686 for (i
= 0; i
< LOOP_TIMEOUT
; ++i
) {
687 if (PPR_REQ_TYPE(raw
[0]) != 0)
692 /* Avoid memcpy function-call overhead */
697 * To detect the hardware bug we need to clear the entry
700 raw
[0] = raw
[1] = 0UL;
702 /* Update head pointer of hardware ring-buffer */
703 head
= (head
+ PPR_ENTRY_SIZE
) % PPR_LOG_SIZE
;
704 writel(head
, iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
706 /* Handle PPR entry */
707 iommu_handle_ppr_entry(iommu
, entry
);
709 /* Refresh ring-buffer information */
710 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
711 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
715 irqreturn_t
amd_iommu_int_thread(int irq
, void *data
)
717 struct amd_iommu
*iommu
= (struct amd_iommu
*) data
;
718 u32 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
720 while (status
& (MMIO_STATUS_EVT_INT_MASK
| MMIO_STATUS_PPR_INT_MASK
)) {
721 /* Enable EVT and PPR interrupts again */
722 writel((MMIO_STATUS_EVT_INT_MASK
| MMIO_STATUS_PPR_INT_MASK
),
723 iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
725 if (status
& MMIO_STATUS_EVT_INT_MASK
) {
726 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
727 iommu_poll_events(iommu
);
730 if (status
& MMIO_STATUS_PPR_INT_MASK
) {
731 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
732 iommu_poll_ppr_log(iommu
);
736 * Hardware bug: ERBT1312
737 * When re-enabling interrupt (by writing 1
738 * to clear the bit), the hardware might also try to set
739 * the interrupt bit in the event status register.
740 * In this scenario, the bit will be set, and disable
741 * subsequent interrupts.
743 * Workaround: The IOMMU driver should read back the
744 * status register and check if the interrupt bits are cleared.
745 * If not, driver will need to go through the interrupt handler
746 * again and re-clear the bits
748 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
753 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
755 return IRQ_WAKE_THREAD
;
758 /****************************************************************************
760 * IOMMU command queuing functions
762 ****************************************************************************/
764 static int wait_on_sem(volatile u64
*sem
)
768 while (*sem
== 0 && i
< LOOP_TIMEOUT
) {
773 if (i
== LOOP_TIMEOUT
) {
774 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
781 static void copy_cmd_to_buffer(struct amd_iommu
*iommu
,
782 struct iommu_cmd
*cmd
,
787 target
= iommu
->cmd_buf
+ tail
;
788 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
790 /* Copy command to buffer */
791 memcpy(target
, cmd
, sizeof(*cmd
));
793 /* Tell the IOMMU about it */
794 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
797 static void build_completion_wait(struct iommu_cmd
*cmd
, u64 address
)
799 WARN_ON(address
& 0x7ULL
);
801 memset(cmd
, 0, sizeof(*cmd
));
802 cmd
->data
[0] = lower_32_bits(__pa(address
)) | CMD_COMPL_WAIT_STORE_MASK
;
803 cmd
->data
[1] = upper_32_bits(__pa(address
));
805 CMD_SET_TYPE(cmd
, CMD_COMPL_WAIT
);
808 static void build_inv_dte(struct iommu_cmd
*cmd
, u16 devid
)
810 memset(cmd
, 0, sizeof(*cmd
));
811 cmd
->data
[0] = devid
;
812 CMD_SET_TYPE(cmd
, CMD_INV_DEV_ENTRY
);
815 static void build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
816 size_t size
, u16 domid
, int pde
)
821 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
826 * If we have to flush more than one page, flush all
827 * TLB entries for this domain
829 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
833 address
&= PAGE_MASK
;
835 memset(cmd
, 0, sizeof(*cmd
));
836 cmd
->data
[1] |= domid
;
837 cmd
->data
[2] = lower_32_bits(address
);
838 cmd
->data
[3] = upper_32_bits(address
);
839 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
840 if (s
) /* size bit - we flush more than one 4kb page */
841 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
842 if (pde
) /* PDE bit - we want to flush everything, not only the PTEs */
843 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
846 static void build_inv_iotlb_pages(struct iommu_cmd
*cmd
, u16 devid
, int qdep
,
847 u64 address
, size_t size
)
852 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
857 * If we have to flush more than one page, flush all
858 * TLB entries for this domain
860 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
864 address
&= PAGE_MASK
;
866 memset(cmd
, 0, sizeof(*cmd
));
867 cmd
->data
[0] = devid
;
868 cmd
->data
[0] |= (qdep
& 0xff) << 24;
869 cmd
->data
[1] = devid
;
870 cmd
->data
[2] = lower_32_bits(address
);
871 cmd
->data
[3] = upper_32_bits(address
);
872 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
874 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
877 static void build_inv_iommu_pasid(struct iommu_cmd
*cmd
, u16 domid
, int pasid
,
878 u64 address
, bool size
)
880 memset(cmd
, 0, sizeof(*cmd
));
882 address
&= ~(0xfffULL
);
884 cmd
->data
[0] = pasid
;
885 cmd
->data
[1] = domid
;
886 cmd
->data
[2] = lower_32_bits(address
);
887 cmd
->data
[3] = upper_32_bits(address
);
888 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
889 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
891 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
892 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
895 static void build_inv_iotlb_pasid(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
896 int qdep
, u64 address
, bool size
)
898 memset(cmd
, 0, sizeof(*cmd
));
900 address
&= ~(0xfffULL
);
902 cmd
->data
[0] = devid
;
903 cmd
->data
[0] |= ((pasid
>> 8) & 0xff) << 16;
904 cmd
->data
[0] |= (qdep
& 0xff) << 24;
905 cmd
->data
[1] = devid
;
906 cmd
->data
[1] |= (pasid
& 0xff) << 16;
907 cmd
->data
[2] = lower_32_bits(address
);
908 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
909 cmd
->data
[3] = upper_32_bits(address
);
911 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
912 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
915 static void build_complete_ppr(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
916 int status
, int tag
, bool gn
)
918 memset(cmd
, 0, sizeof(*cmd
));
920 cmd
->data
[0] = devid
;
922 cmd
->data
[1] = pasid
;
923 cmd
->data
[2] = CMD_INV_IOMMU_PAGES_GN_MASK
;
925 cmd
->data
[3] = tag
& 0x1ff;
926 cmd
->data
[3] |= (status
& PPR_STATUS_MASK
) << PPR_STATUS_SHIFT
;
928 CMD_SET_TYPE(cmd
, CMD_COMPLETE_PPR
);
931 static void build_inv_all(struct iommu_cmd
*cmd
)
933 memset(cmd
, 0, sizeof(*cmd
));
934 CMD_SET_TYPE(cmd
, CMD_INV_ALL
);
937 static void build_inv_irt(struct iommu_cmd
*cmd
, u16 devid
)
939 memset(cmd
, 0, sizeof(*cmd
));
940 cmd
->data
[0] = devid
;
941 CMD_SET_TYPE(cmd
, CMD_INV_IRT
);
945 * Writes the command to the IOMMUs command buffer and informs the
946 * hardware about the new command.
948 static int iommu_queue_command_sync(struct amd_iommu
*iommu
,
949 struct iommu_cmd
*cmd
,
952 u32 left
, tail
, head
, next_tail
;
955 WARN_ON(iommu
->cmd_buf_size
& CMD_BUFFER_UNINITIALIZED
);
958 spin_lock_irqsave(&iommu
->lock
, flags
);
960 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
961 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
962 next_tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
963 left
= (head
- next_tail
) % iommu
->cmd_buf_size
;
966 struct iommu_cmd sync_cmd
;
967 volatile u64 sem
= 0;
970 build_completion_wait(&sync_cmd
, (u64
)&sem
);
971 copy_cmd_to_buffer(iommu
, &sync_cmd
, tail
);
973 spin_unlock_irqrestore(&iommu
->lock
, flags
);
975 if ((ret
= wait_on_sem(&sem
)) != 0)
981 copy_cmd_to_buffer(iommu
, cmd
, tail
);
983 /* We need to sync now to make sure all commands are processed */
984 iommu
->need_sync
= sync
;
986 spin_unlock_irqrestore(&iommu
->lock
, flags
);
991 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
993 return iommu_queue_command_sync(iommu
, cmd
, true);
997 * This function queues a completion wait command into the command
1000 static int iommu_completion_wait(struct amd_iommu
*iommu
)
1002 struct iommu_cmd cmd
;
1003 volatile u64 sem
= 0;
1006 if (!iommu
->need_sync
)
1009 build_completion_wait(&cmd
, (u64
)&sem
);
1011 ret
= iommu_queue_command_sync(iommu
, &cmd
, false);
1015 return wait_on_sem(&sem
);
1018 static int iommu_flush_dte(struct amd_iommu
*iommu
, u16 devid
)
1020 struct iommu_cmd cmd
;
1022 build_inv_dte(&cmd
, devid
);
1024 return iommu_queue_command(iommu
, &cmd
);
1027 static void iommu_flush_dte_all(struct amd_iommu
*iommu
)
1031 for (devid
= 0; devid
<= 0xffff; ++devid
)
1032 iommu_flush_dte(iommu
, devid
);
1034 iommu_completion_wait(iommu
);
1038 * This function uses heavy locking and may disable irqs for some time. But
1039 * this is no issue because it is only called during resume.
1041 static void iommu_flush_tlb_all(struct amd_iommu
*iommu
)
1045 for (dom_id
= 0; dom_id
<= 0xffff; ++dom_id
) {
1046 struct iommu_cmd cmd
;
1047 build_inv_iommu_pages(&cmd
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
1049 iommu_queue_command(iommu
, &cmd
);
1052 iommu_completion_wait(iommu
);
1055 static void iommu_flush_all(struct amd_iommu
*iommu
)
1057 struct iommu_cmd cmd
;
1059 build_inv_all(&cmd
);
1061 iommu_queue_command(iommu
, &cmd
);
1062 iommu_completion_wait(iommu
);
1065 static void iommu_flush_irt(struct amd_iommu
*iommu
, u16 devid
)
1067 struct iommu_cmd cmd
;
1069 build_inv_irt(&cmd
, devid
);
1071 iommu_queue_command(iommu
, &cmd
);
1074 static void iommu_flush_irt_all(struct amd_iommu
*iommu
)
1078 for (devid
= 0; devid
<= MAX_DEV_TABLE_ENTRIES
; devid
++)
1079 iommu_flush_irt(iommu
, devid
);
1081 iommu_completion_wait(iommu
);
1084 void iommu_flush_all_caches(struct amd_iommu
*iommu
)
1086 if (iommu_feature(iommu
, FEATURE_IA
)) {
1087 iommu_flush_all(iommu
);
1089 iommu_flush_dte_all(iommu
);
1090 iommu_flush_irt_all(iommu
);
1091 iommu_flush_tlb_all(iommu
);
1096 * Command send function for flushing on-device TLB
1098 static int device_flush_iotlb(struct iommu_dev_data
*dev_data
,
1099 u64 address
, size_t size
)
1101 struct amd_iommu
*iommu
;
1102 struct iommu_cmd cmd
;
1105 qdep
= dev_data
->ats
.qdep
;
1106 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1108 build_inv_iotlb_pages(&cmd
, dev_data
->devid
, qdep
, address
, size
);
1110 return iommu_queue_command(iommu
, &cmd
);
1114 * Command send function for invalidating a device table entry
1116 static int device_flush_dte(struct iommu_dev_data
*dev_data
)
1118 struct amd_iommu
*iommu
;
1121 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1123 ret
= iommu_flush_dte(iommu
, dev_data
->devid
);
1127 if (dev_data
->ats
.enabled
)
1128 ret
= device_flush_iotlb(dev_data
, 0, ~0UL);
1134 * TLB invalidation function which is called from the mapping functions.
1135 * It invalidates a single PTE if the range to flush is within a single
1136 * page. Otherwise it flushes the whole TLB of the IOMMU.
1138 static void __domain_flush_pages(struct protection_domain
*domain
,
1139 u64 address
, size_t size
, int pde
)
1141 struct iommu_dev_data
*dev_data
;
1142 struct iommu_cmd cmd
;
1145 build_inv_iommu_pages(&cmd
, address
, size
, domain
->id
, pde
);
1147 for (i
= 0; i
< amd_iommus_present
; ++i
) {
1148 if (!domain
->dev_iommu
[i
])
1152 * Devices of this domain are behind this IOMMU
1153 * We need a TLB flush
1155 ret
|= iommu_queue_command(amd_iommus
[i
], &cmd
);
1158 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
1160 if (!dev_data
->ats
.enabled
)
1163 ret
|= device_flush_iotlb(dev_data
, address
, size
);
1169 static void domain_flush_pages(struct protection_domain
*domain
,
1170 u64 address
, size_t size
)
1172 __domain_flush_pages(domain
, address
, size
, 0);
1175 /* Flush the whole IO/TLB for a given protection domain */
1176 static void domain_flush_tlb(struct protection_domain
*domain
)
1178 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 0);
1181 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1182 static void domain_flush_tlb_pde(struct protection_domain
*domain
)
1184 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 1);
1187 static void domain_flush_complete(struct protection_domain
*domain
)
1191 for (i
= 0; i
< amd_iommus_present
; ++i
) {
1192 if (!domain
->dev_iommu
[i
])
1196 * Devices of this domain are behind this IOMMU
1197 * We need to wait for completion of all commands.
1199 iommu_completion_wait(amd_iommus
[i
]);
1205 * This function flushes the DTEs for all devices in domain
1207 static void domain_flush_devices(struct protection_domain
*domain
)
1209 struct iommu_dev_data
*dev_data
;
1211 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
1212 device_flush_dte(dev_data
);
1215 /****************************************************************************
1217 * The functions below are used the create the page table mappings for
1218 * unity mapped regions.
1220 ****************************************************************************/
1223 * This function is used to add another level to an IO page table. Adding
1224 * another level increases the size of the address space by 9 bits to a size up
1227 static bool increase_address_space(struct protection_domain
*domain
,
1232 if (domain
->mode
== PAGE_MODE_6_LEVEL
)
1233 /* address space already 64 bit large */
1236 pte
= (void *)get_zeroed_page(gfp
);
1240 *pte
= PM_LEVEL_PDE(domain
->mode
,
1241 virt_to_phys(domain
->pt_root
));
1242 domain
->pt_root
= pte
;
1244 domain
->updated
= true;
1249 static u64
*alloc_pte(struct protection_domain
*domain
,
1250 unsigned long address
,
1251 unsigned long page_size
,
1258 BUG_ON(!is_power_of_2(page_size
));
1260 while (address
> PM_LEVEL_SIZE(domain
->mode
))
1261 increase_address_space(domain
, gfp
);
1263 level
= domain
->mode
- 1;
1264 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1265 address
= PAGE_SIZE_ALIGN(address
, page_size
);
1266 end_lvl
= PAGE_SIZE_LEVEL(page_size
);
1268 while (level
> end_lvl
) {
1269 if (!IOMMU_PTE_PRESENT(*pte
)) {
1270 page
= (u64
*)get_zeroed_page(gfp
);
1273 *pte
= PM_LEVEL_PDE(level
, virt_to_phys(page
));
1276 /* No level skipping support yet */
1277 if (PM_PTE_LEVEL(*pte
) != level
)
1282 pte
= IOMMU_PTE_PAGE(*pte
);
1284 if (pte_page
&& level
== end_lvl
)
1287 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1294 * This function checks if there is a PTE for a given dma address. If
1295 * there is one, it returns the pointer to it.
1297 static u64
*fetch_pte(struct protection_domain
*domain
,
1298 unsigned long address
,
1299 unsigned long *page_size
)
1304 if (address
> PM_LEVEL_SIZE(domain
->mode
))
1307 level
= domain
->mode
- 1;
1308 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1309 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1314 if (!IOMMU_PTE_PRESENT(*pte
))
1318 if (PM_PTE_LEVEL(*pte
) == 7 ||
1319 PM_PTE_LEVEL(*pte
) == 0)
1322 /* No level skipping support yet */
1323 if (PM_PTE_LEVEL(*pte
) != level
)
1328 /* Walk to the next level */
1329 pte
= IOMMU_PTE_PAGE(*pte
);
1330 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1331 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1334 if (PM_PTE_LEVEL(*pte
) == 0x07) {
1335 unsigned long pte_mask
;
1338 * If we have a series of large PTEs, make
1339 * sure to return a pointer to the first one.
1341 *page_size
= pte_mask
= PTE_PAGE_SIZE(*pte
);
1342 pte_mask
= ~((PAGE_SIZE_PTE_COUNT(pte_mask
) << 3) - 1);
1343 pte
= (u64
*)(((unsigned long)pte
) & pte_mask
);
1350 * Generic mapping functions. It maps a physical address into a DMA
1351 * address space. It allocates the page table pages if necessary.
1352 * In the future it can be extended to a generic mapping function
1353 * supporting all features of AMD IOMMU page tables like level skipping
1354 * and full 64 bit address spaces.
1356 static int iommu_map_page(struct protection_domain
*dom
,
1357 unsigned long bus_addr
,
1358 unsigned long phys_addr
,
1360 unsigned long page_size
)
1365 BUG_ON(!IS_ALIGNED(bus_addr
, page_size
));
1366 BUG_ON(!IS_ALIGNED(phys_addr
, page_size
));
1368 if (!(prot
& IOMMU_PROT_MASK
))
1371 count
= PAGE_SIZE_PTE_COUNT(page_size
);
1372 pte
= alloc_pte(dom
, bus_addr
, page_size
, NULL
, GFP_KERNEL
);
1377 for (i
= 0; i
< count
; ++i
)
1378 if (IOMMU_PTE_PRESENT(pte
[i
]))
1382 __pte
= PAGE_SIZE_PTE(phys_addr
, page_size
);
1383 __pte
|= PM_LEVEL_ENC(7) | IOMMU_PTE_P
| IOMMU_PTE_FC
;
1385 __pte
= phys_addr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1387 if (prot
& IOMMU_PROT_IR
)
1388 __pte
|= IOMMU_PTE_IR
;
1389 if (prot
& IOMMU_PROT_IW
)
1390 __pte
|= IOMMU_PTE_IW
;
1392 for (i
= 0; i
< count
; ++i
)
1400 static unsigned long iommu_unmap_page(struct protection_domain
*dom
,
1401 unsigned long bus_addr
,
1402 unsigned long page_size
)
1404 unsigned long long unmapped
;
1405 unsigned long unmap_size
;
1408 BUG_ON(!is_power_of_2(page_size
));
1412 while (unmapped
< page_size
) {
1414 pte
= fetch_pte(dom
, bus_addr
, &unmap_size
);
1419 count
= PAGE_SIZE_PTE_COUNT(unmap_size
);
1420 for (i
= 0; i
< count
; i
++)
1424 bus_addr
= (bus_addr
& ~(unmap_size
- 1)) + unmap_size
;
1425 unmapped
+= unmap_size
;
1428 BUG_ON(unmapped
&& !is_power_of_2(unmapped
));
1433 /****************************************************************************
1435 * The next functions belong to the address allocator for the dma_ops
1436 * interface functions. They work like the allocators in the other IOMMU
1437 * drivers. Its basically a bitmap which marks the allocated pages in
1438 * the aperture. Maybe it could be enhanced in the future to a more
1439 * efficient allocator.
1441 ****************************************************************************/
1444 * The address allocator core functions.
1446 * called with domain->lock held
1450 * Used to reserve address ranges in the aperture (e.g. for exclusion
1453 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
1454 unsigned long start_page
,
1457 unsigned int i
, last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
1459 if (start_page
+ pages
> last_page
)
1460 pages
= last_page
- start_page
;
1462 for (i
= start_page
; i
< start_page
+ pages
; ++i
) {
1463 int index
= i
/ APERTURE_RANGE_PAGES
;
1464 int page
= i
% APERTURE_RANGE_PAGES
;
1465 __set_bit(page
, dom
->aperture
[index
]->bitmap
);
1470 * This function is used to add a new aperture range to an existing
1471 * aperture in case of dma_ops domain allocation or address allocation
1474 static int alloc_new_range(struct dma_ops_domain
*dma_dom
,
1475 bool populate
, gfp_t gfp
)
1477 int index
= dma_dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1478 struct amd_iommu
*iommu
;
1479 unsigned long i
, old_size
, pte_pgsize
;
1481 #ifdef CONFIG_IOMMU_STRESS
1485 if (index
>= APERTURE_MAX_RANGES
)
1488 dma_dom
->aperture
[index
] = kzalloc(sizeof(struct aperture_range
), gfp
);
1489 if (!dma_dom
->aperture
[index
])
1492 dma_dom
->aperture
[index
]->bitmap
= (void *)get_zeroed_page(gfp
);
1493 if (!dma_dom
->aperture
[index
]->bitmap
)
1496 dma_dom
->aperture
[index
]->offset
= dma_dom
->aperture_size
;
1499 unsigned long address
= dma_dom
->aperture_size
;
1500 int i
, num_ptes
= APERTURE_RANGE_PAGES
/ 512;
1501 u64
*pte
, *pte_page
;
1503 for (i
= 0; i
< num_ptes
; ++i
) {
1504 pte
= alloc_pte(&dma_dom
->domain
, address
, PAGE_SIZE
,
1509 dma_dom
->aperture
[index
]->pte_pages
[i
] = pte_page
;
1511 address
+= APERTURE_RANGE_SIZE
/ 64;
1515 old_size
= dma_dom
->aperture_size
;
1516 dma_dom
->aperture_size
+= APERTURE_RANGE_SIZE
;
1518 /* Reserve address range used for MSI messages */
1519 if (old_size
< MSI_ADDR_BASE_LO
&&
1520 dma_dom
->aperture_size
> MSI_ADDR_BASE_LO
) {
1521 unsigned long spage
;
1524 pages
= iommu_num_pages(MSI_ADDR_BASE_LO
, 0x10000, PAGE_SIZE
);
1525 spage
= MSI_ADDR_BASE_LO
>> PAGE_SHIFT
;
1527 dma_ops_reserve_addresses(dma_dom
, spage
, pages
);
1530 /* Initialize the exclusion range if necessary */
1531 for_each_iommu(iommu
) {
1532 if (iommu
->exclusion_start
&&
1533 iommu
->exclusion_start
>= dma_dom
->aperture
[index
]->offset
1534 && iommu
->exclusion_start
< dma_dom
->aperture_size
) {
1535 unsigned long startpage
;
1536 int pages
= iommu_num_pages(iommu
->exclusion_start
,
1537 iommu
->exclusion_length
,
1539 startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
1540 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
1545 * Check for areas already mapped as present in the new aperture
1546 * range and mark those pages as reserved in the allocator. Such
1547 * mappings may already exist as a result of requested unity
1548 * mappings for devices.
1550 for (i
= dma_dom
->aperture
[index
]->offset
;
1551 i
< dma_dom
->aperture_size
;
1553 u64
*pte
= fetch_pte(&dma_dom
->domain
, i
, &pte_pgsize
);
1554 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
1557 dma_ops_reserve_addresses(dma_dom
, i
>> PAGE_SHIFT
,
1561 update_domain(&dma_dom
->domain
);
1566 update_domain(&dma_dom
->domain
);
1568 free_page((unsigned long)dma_dom
->aperture
[index
]->bitmap
);
1570 kfree(dma_dom
->aperture
[index
]);
1571 dma_dom
->aperture
[index
] = NULL
;
1576 static unsigned long dma_ops_area_alloc(struct device
*dev
,
1577 struct dma_ops_domain
*dom
,
1579 unsigned long align_mask
,
1581 unsigned long start
)
1583 unsigned long next_bit
= dom
->next_address
% APERTURE_RANGE_SIZE
;
1584 int max_index
= dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1585 int i
= start
>> APERTURE_RANGE_SHIFT
;
1586 unsigned long boundary_size
, mask
;
1587 unsigned long address
= -1;
1588 unsigned long limit
;
1590 next_bit
>>= PAGE_SHIFT
;
1592 mask
= dma_get_seg_boundary(dev
);
1594 boundary_size
= mask
+ 1 ? ALIGN(mask
+ 1, PAGE_SIZE
) >> PAGE_SHIFT
:
1595 1UL << (BITS_PER_LONG
- PAGE_SHIFT
);
1597 for (;i
< max_index
; ++i
) {
1598 unsigned long offset
= dom
->aperture
[i
]->offset
>> PAGE_SHIFT
;
1600 if (dom
->aperture
[i
]->offset
>= dma_mask
)
1603 limit
= iommu_device_max_index(APERTURE_RANGE_PAGES
, offset
,
1604 dma_mask
>> PAGE_SHIFT
);
1606 address
= iommu_area_alloc(dom
->aperture
[i
]->bitmap
,
1607 limit
, next_bit
, pages
, 0,
1608 boundary_size
, align_mask
);
1609 if (address
!= -1) {
1610 address
= dom
->aperture
[i
]->offset
+
1611 (address
<< PAGE_SHIFT
);
1612 dom
->next_address
= address
+ (pages
<< PAGE_SHIFT
);
1622 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
1623 struct dma_ops_domain
*dom
,
1625 unsigned long align_mask
,
1628 unsigned long address
;
1630 #ifdef CONFIG_IOMMU_STRESS
1631 dom
->next_address
= 0;
1632 dom
->need_flush
= true;
1635 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1636 dma_mask
, dom
->next_address
);
1638 if (address
== -1) {
1639 dom
->next_address
= 0;
1640 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1642 dom
->need_flush
= true;
1645 if (unlikely(address
== -1))
1646 address
= DMA_ERROR_CODE
;
1648 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
1654 * The address free function.
1656 * called with domain->lock held
1658 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
1659 unsigned long address
,
1662 unsigned i
= address
>> APERTURE_RANGE_SHIFT
;
1663 struct aperture_range
*range
= dom
->aperture
[i
];
1665 BUG_ON(i
>= APERTURE_MAX_RANGES
|| range
== NULL
);
1667 #ifdef CONFIG_IOMMU_STRESS
1672 if (address
>= dom
->next_address
)
1673 dom
->need_flush
= true;
1675 address
= (address
% APERTURE_RANGE_SIZE
) >> PAGE_SHIFT
;
1677 bitmap_clear(range
->bitmap
, address
, pages
);
1681 /****************************************************************************
1683 * The next functions belong to the domain allocation. A domain is
1684 * allocated for every IOMMU as the default domain. If device isolation
1685 * is enabled, every device get its own domain. The most important thing
1686 * about domains is the page table mapping the DMA address space they
1689 ****************************************************************************/
1692 * This function adds a protection domain to the global protection domain list
1694 static void add_domain_to_list(struct protection_domain
*domain
)
1696 unsigned long flags
;
1698 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1699 list_add(&domain
->list
, &amd_iommu_pd_list
);
1700 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1704 * This function removes a protection domain to the global
1705 * protection domain list
1707 static void del_domain_from_list(struct protection_domain
*domain
)
1709 unsigned long flags
;
1711 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1712 list_del(&domain
->list
);
1713 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1716 static u16
domain_id_alloc(void)
1718 unsigned long flags
;
1721 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1722 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
1724 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1725 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
1728 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1733 static void domain_id_free(int id
)
1735 unsigned long flags
;
1737 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1738 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1739 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
1740 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1743 #define DEFINE_FREE_PT_FN(LVL, FN) \
1744 static void free_pt_##LVL (unsigned long __pt) \
1752 for (i = 0; i < 512; ++i) { \
1753 /* PTE present? */ \
1754 if (!IOMMU_PTE_PRESENT(pt[i])) \
1758 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1759 PM_PTE_LEVEL(pt[i]) == 7) \
1762 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1765 free_page((unsigned long)pt); \
1768 DEFINE_FREE_PT_FN(l2
, free_page
)
1769 DEFINE_FREE_PT_FN(l3
, free_pt_l2
)
1770 DEFINE_FREE_PT_FN(l4
, free_pt_l3
)
1771 DEFINE_FREE_PT_FN(l5
, free_pt_l4
)
1772 DEFINE_FREE_PT_FN(l6
, free_pt_l5
)
1774 static void free_pagetable(struct protection_domain
*domain
)
1776 unsigned long root
= (unsigned long)domain
->pt_root
;
1778 switch (domain
->mode
) {
1779 case PAGE_MODE_NONE
:
1781 case PAGE_MODE_1_LEVEL
:
1784 case PAGE_MODE_2_LEVEL
:
1787 case PAGE_MODE_3_LEVEL
:
1790 case PAGE_MODE_4_LEVEL
:
1793 case PAGE_MODE_5_LEVEL
:
1796 case PAGE_MODE_6_LEVEL
:
1804 static void free_gcr3_tbl_level1(u64
*tbl
)
1809 for (i
= 0; i
< 512; ++i
) {
1810 if (!(tbl
[i
] & GCR3_VALID
))
1813 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1815 free_page((unsigned long)ptr
);
1819 static void free_gcr3_tbl_level2(u64
*tbl
)
1824 for (i
= 0; i
< 512; ++i
) {
1825 if (!(tbl
[i
] & GCR3_VALID
))
1828 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1830 free_gcr3_tbl_level1(ptr
);
1834 static void free_gcr3_table(struct protection_domain
*domain
)
1836 if (domain
->glx
== 2)
1837 free_gcr3_tbl_level2(domain
->gcr3_tbl
);
1838 else if (domain
->glx
== 1)
1839 free_gcr3_tbl_level1(domain
->gcr3_tbl
);
1840 else if (domain
->glx
!= 0)
1843 free_page((unsigned long)domain
->gcr3_tbl
);
1847 * Free a domain, only used if something went wrong in the
1848 * allocation path and we need to free an already allocated page table
1850 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
1857 del_domain_from_list(&dom
->domain
);
1859 free_pagetable(&dom
->domain
);
1861 for (i
= 0; i
< APERTURE_MAX_RANGES
; ++i
) {
1862 if (!dom
->aperture
[i
])
1864 free_page((unsigned long)dom
->aperture
[i
]->bitmap
);
1865 kfree(dom
->aperture
[i
]);
1872 * Allocates a new protection domain usable for the dma_ops functions.
1873 * It also initializes the page table and the address allocator data
1874 * structures required for the dma_ops interface
1876 static struct dma_ops_domain
*dma_ops_domain_alloc(void)
1878 struct dma_ops_domain
*dma_dom
;
1880 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
1884 spin_lock_init(&dma_dom
->domain
.lock
);
1886 dma_dom
->domain
.id
= domain_id_alloc();
1887 if (dma_dom
->domain
.id
== 0)
1889 INIT_LIST_HEAD(&dma_dom
->domain
.dev_list
);
1890 dma_dom
->domain
.mode
= PAGE_MODE_2_LEVEL
;
1891 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
1892 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
1893 dma_dom
->domain
.priv
= dma_dom
;
1894 if (!dma_dom
->domain
.pt_root
)
1897 dma_dom
->need_flush
= false;
1899 add_domain_to_list(&dma_dom
->domain
);
1901 if (alloc_new_range(dma_dom
, true, GFP_KERNEL
))
1905 * mark the first page as allocated so we never return 0 as
1906 * a valid dma-address. So we can use 0 as error value
1908 dma_dom
->aperture
[0]->bitmap
[0] = 1;
1909 dma_dom
->next_address
= 0;
1915 dma_ops_domain_free(dma_dom
);
1921 * little helper function to check whether a given protection domain is a
1924 static bool dma_ops_domain(struct protection_domain
*domain
)
1926 return domain
->flags
& PD_DMA_OPS_MASK
;
1929 static void set_dte_entry(u16 devid
, struct protection_domain
*domain
, bool ats
)
1934 if (domain
->mode
!= PAGE_MODE_NONE
)
1935 pte_root
= virt_to_phys(domain
->pt_root
);
1937 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
1938 << DEV_ENTRY_MODE_SHIFT
;
1939 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
1941 flags
= amd_iommu_dev_table
[devid
].data
[1];
1944 flags
|= DTE_FLAG_IOTLB
;
1946 if (domain
->flags
& PD_IOMMUV2_MASK
) {
1947 u64 gcr3
= __pa(domain
->gcr3_tbl
);
1948 u64 glx
= domain
->glx
;
1951 pte_root
|= DTE_FLAG_GV
;
1952 pte_root
|= (glx
& DTE_GLX_MASK
) << DTE_GLX_SHIFT
;
1954 /* First mask out possible old values for GCR3 table */
1955 tmp
= DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B
;
1958 tmp
= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C
;
1961 /* Encode GCR3 table into DTE */
1962 tmp
= DTE_GCR3_VAL_A(gcr3
) << DTE_GCR3_SHIFT_A
;
1965 tmp
= DTE_GCR3_VAL_B(gcr3
) << DTE_GCR3_SHIFT_B
;
1968 tmp
= DTE_GCR3_VAL_C(gcr3
) << DTE_GCR3_SHIFT_C
;
1972 flags
&= ~(0xffffUL
);
1973 flags
|= domain
->id
;
1975 amd_iommu_dev_table
[devid
].data
[1] = flags
;
1976 amd_iommu_dev_table
[devid
].data
[0] = pte_root
;
1979 static void clear_dte_entry(u16 devid
)
1981 /* remove entry from the device table seen by the hardware */
1982 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
1983 amd_iommu_dev_table
[devid
].data
[1] = 0;
1985 amd_iommu_apply_erratum_63(devid
);
1988 static void do_attach(struct iommu_dev_data
*dev_data
,
1989 struct protection_domain
*domain
)
1991 struct amd_iommu
*iommu
;
1994 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1995 ats
= dev_data
->ats
.enabled
;
1997 /* Update data structures */
1998 dev_data
->domain
= domain
;
1999 list_add(&dev_data
->list
, &domain
->dev_list
);
2000 set_dte_entry(dev_data
->devid
, domain
, ats
);
2002 /* Do reference counting */
2003 domain
->dev_iommu
[iommu
->index
] += 1;
2004 domain
->dev_cnt
+= 1;
2006 /* Flush the DTE entry */
2007 device_flush_dte(dev_data
);
2010 static void do_detach(struct iommu_dev_data
*dev_data
)
2012 struct amd_iommu
*iommu
;
2014 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
2016 /* decrease reference counters */
2017 dev_data
->domain
->dev_iommu
[iommu
->index
] -= 1;
2018 dev_data
->domain
->dev_cnt
-= 1;
2020 /* Update data structures */
2021 dev_data
->domain
= NULL
;
2022 list_del(&dev_data
->list
);
2023 clear_dte_entry(dev_data
->devid
);
2025 /* Flush the DTE entry */
2026 device_flush_dte(dev_data
);
2030 * If a device is not yet associated with a domain, this function does
2031 * assigns it visible for the hardware
2033 static int __attach_device(struct iommu_dev_data
*dev_data
,
2034 struct protection_domain
*domain
)
2036 struct iommu_dev_data
*head
, *entry
;
2040 spin_lock(&domain
->lock
);
2044 if (head
->alias_data
!= NULL
)
2045 head
= head
->alias_data
;
2047 /* Now we have the root of the alias group, if any */
2050 if (head
->domain
!= NULL
)
2053 /* Attach alias group root */
2054 do_attach(head
, domain
);
2056 /* Attach other devices in the alias group */
2057 list_for_each_entry(entry
, &head
->alias_list
, alias_list
)
2058 do_attach(entry
, domain
);
2065 spin_unlock(&domain
->lock
);
2071 static void pdev_iommuv2_disable(struct pci_dev
*pdev
)
2073 pci_disable_ats(pdev
);
2074 pci_disable_pri(pdev
);
2075 pci_disable_pasid(pdev
);
2078 /* FIXME: Change generic reset-function to do the same */
2079 static int pri_reset_while_enabled(struct pci_dev
*pdev
)
2084 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2088 pci_read_config_word(pdev
, pos
+ PCI_PRI_CTRL
, &control
);
2089 control
|= PCI_PRI_CTRL_RESET
;
2090 pci_write_config_word(pdev
, pos
+ PCI_PRI_CTRL
, control
);
2095 static int pdev_iommuv2_enable(struct pci_dev
*pdev
)
2100 /* FIXME: Hardcode number of outstanding requests for now */
2102 if (pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE
))
2104 reset_enable
= pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_ENABLE_RESET
);
2106 /* Only allow access to user-accessible pages */
2107 ret
= pci_enable_pasid(pdev
, 0);
2111 /* First reset the PRI state of the device */
2112 ret
= pci_reset_pri(pdev
);
2117 ret
= pci_enable_pri(pdev
, reqs
);
2122 ret
= pri_reset_while_enabled(pdev
);
2127 ret
= pci_enable_ats(pdev
, PAGE_SHIFT
);
2134 pci_disable_pri(pdev
);
2135 pci_disable_pasid(pdev
);
2140 /* FIXME: Move this to PCI code */
2141 #define PCI_PRI_TLP_OFF (1 << 15)
2143 static bool pci_pri_tlp_required(struct pci_dev
*pdev
)
2148 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2152 pci_read_config_word(pdev
, pos
+ PCI_PRI_STATUS
, &status
);
2154 return (status
& PCI_PRI_TLP_OFF
) ? true : false;
2158 * If a device is not yet associated with a domain, this function
2159 * assigns it visible for the hardware
2161 static int attach_device(struct device
*dev
,
2162 struct protection_domain
*domain
)
2164 struct pci_dev
*pdev
= to_pci_dev(dev
);
2165 struct iommu_dev_data
*dev_data
;
2166 unsigned long flags
;
2169 dev_data
= get_dev_data(dev
);
2171 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2172 if (!dev_data
->iommu_v2
|| !dev_data
->passthrough
)
2175 if (pdev_iommuv2_enable(pdev
) != 0)
2178 dev_data
->ats
.enabled
= true;
2179 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2180 dev_data
->pri_tlp
= pci_pri_tlp_required(pdev
);
2181 } else if (amd_iommu_iotlb_sup
&&
2182 pci_enable_ats(pdev
, PAGE_SHIFT
) == 0) {
2183 dev_data
->ats
.enabled
= true;
2184 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2187 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2188 ret
= __attach_device(dev_data
, domain
);
2189 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2192 * We might boot into a crash-kernel here. The crashed kernel
2193 * left the caches in the IOMMU dirty. So we have to flush
2194 * here to evict all dirty stuff.
2196 domain_flush_tlb_pde(domain
);
2202 * Removes a device from a protection domain (unlocked)
2204 static void __detach_device(struct iommu_dev_data
*dev_data
)
2206 struct iommu_dev_data
*head
, *entry
;
2207 struct protection_domain
*domain
;
2208 unsigned long flags
;
2210 BUG_ON(!dev_data
->domain
);
2212 domain
= dev_data
->domain
;
2214 spin_lock_irqsave(&domain
->lock
, flags
);
2217 if (head
->alias_data
!= NULL
)
2218 head
= head
->alias_data
;
2220 list_for_each_entry(entry
, &head
->alias_list
, alias_list
)
2225 spin_unlock_irqrestore(&domain
->lock
, flags
);
2228 * If we run in passthrough mode the device must be assigned to the
2229 * passthrough domain if it is detached from any other domain.
2230 * Make sure we can deassign from the pt_domain itself.
2232 if (dev_data
->passthrough
&&
2233 (dev_data
->domain
== NULL
&& domain
!= pt_domain
))
2234 __attach_device(dev_data
, pt_domain
);
2238 * Removes a device from a protection domain (with devtable_lock held)
2240 static void detach_device(struct device
*dev
)
2242 struct protection_domain
*domain
;
2243 struct iommu_dev_data
*dev_data
;
2244 unsigned long flags
;
2246 dev_data
= get_dev_data(dev
);
2247 domain
= dev_data
->domain
;
2249 /* lock device table */
2250 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2251 __detach_device(dev_data
);
2252 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2254 if (domain
->flags
& PD_IOMMUV2_MASK
)
2255 pdev_iommuv2_disable(to_pci_dev(dev
));
2256 else if (dev_data
->ats
.enabled
)
2257 pci_disable_ats(to_pci_dev(dev
));
2259 dev_data
->ats
.enabled
= false;
2262 static int amd_iommu_add_device(struct device
*dev
)
2264 struct iommu_dev_data
*dev_data
;
2265 struct iommu_domain
*domain
;
2266 struct amd_iommu
*iommu
;
2270 if (!check_device(dev
) || get_dev_data(dev
))
2273 devid
= get_device_id(dev
);
2274 iommu
= amd_iommu_rlookup_table
[devid
];
2276 ret
= iommu_init_device(dev
);
2278 if (ret
!= -ENOTSUPP
)
2279 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2282 iommu_ignore_device(dev
);
2283 dev
->archdata
.dma_ops
= &nommu_dma_ops
;
2286 init_iommu_group(dev
);
2288 dev_data
= get_dev_data(dev
);
2292 if (dev_data
->iommu_v2
)
2293 iommu_request_dm_for_dev(dev
);
2295 /* Domains are initialized for this device - have a look what we ended up with */
2296 domain
= iommu_get_domain_for_dev(dev
);
2297 if (domain
->type
== IOMMU_DOMAIN_IDENTITY
) {
2298 dev_data
->passthrough
= true;
2299 dev
->archdata
.dma_ops
= &nommu_dma_ops
;
2301 dev
->archdata
.dma_ops
= &amd_iommu_dma_ops
;
2305 iommu_completion_wait(iommu
);
2310 static void amd_iommu_remove_device(struct device
*dev
)
2312 struct amd_iommu
*iommu
;
2315 if (!check_device(dev
))
2318 devid
= get_device_id(dev
);
2319 iommu
= amd_iommu_rlookup_table
[devid
];
2321 iommu_uninit_device(dev
);
2322 iommu_completion_wait(iommu
);
2325 /*****************************************************************************
2327 * The next functions belong to the dma_ops mapping/unmapping code.
2329 *****************************************************************************/
2332 * In the dma_ops path we only have the struct device. This function
2333 * finds the corresponding IOMMU, the protection domain and the
2334 * requestor id for a given device.
2335 * If the device is not yet associated with a domain this is also done
2338 static struct protection_domain
*get_domain(struct device
*dev
)
2340 struct protection_domain
*domain
;
2341 struct iommu_domain
*io_domain
;
2343 if (!check_device(dev
))
2344 return ERR_PTR(-EINVAL
);
2346 io_domain
= iommu_get_domain_for_dev(dev
);
2350 domain
= to_pdomain(io_domain
);
2351 if (!dma_ops_domain(domain
))
2352 return ERR_PTR(-EBUSY
);
2357 static void update_device_table(struct protection_domain
*domain
)
2359 struct iommu_dev_data
*dev_data
;
2361 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
2362 set_dte_entry(dev_data
->devid
, domain
, dev_data
->ats
.enabled
);
2365 static void update_domain(struct protection_domain
*domain
)
2367 if (!domain
->updated
)
2370 update_device_table(domain
);
2372 domain_flush_devices(domain
);
2373 domain_flush_tlb_pde(domain
);
2375 domain
->updated
= false;
2379 * This function fetches the PTE for a given address in the aperture
2381 static u64
* dma_ops_get_pte(struct dma_ops_domain
*dom
,
2382 unsigned long address
)
2384 struct aperture_range
*aperture
;
2385 u64
*pte
, *pte_page
;
2387 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
2391 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
2393 pte
= alloc_pte(&dom
->domain
, address
, PAGE_SIZE
, &pte_page
,
2395 aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)] = pte_page
;
2397 pte
+= PM_LEVEL_INDEX(0, address
);
2399 update_domain(&dom
->domain
);
2405 * This is the generic map function. It maps one 4kb page at paddr to
2406 * the given address in the DMA address space for the domain.
2408 static dma_addr_t
dma_ops_domain_map(struct dma_ops_domain
*dom
,
2409 unsigned long address
,
2415 WARN_ON(address
> dom
->aperture_size
);
2419 pte
= dma_ops_get_pte(dom
, address
);
2421 return DMA_ERROR_CODE
;
2423 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
2425 if (direction
== DMA_TO_DEVICE
)
2426 __pte
|= IOMMU_PTE_IR
;
2427 else if (direction
== DMA_FROM_DEVICE
)
2428 __pte
|= IOMMU_PTE_IW
;
2429 else if (direction
== DMA_BIDIRECTIONAL
)
2430 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
2436 return (dma_addr_t
)address
;
2440 * The generic unmapping function for on page in the DMA address space.
2442 static void dma_ops_domain_unmap(struct dma_ops_domain
*dom
,
2443 unsigned long address
)
2445 struct aperture_range
*aperture
;
2448 if (address
>= dom
->aperture_size
)
2451 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
2455 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
2459 pte
+= PM_LEVEL_INDEX(0, address
);
2467 * This function contains common code for mapping of a physically
2468 * contiguous memory region into DMA address space. It is used by all
2469 * mapping functions provided with this IOMMU driver.
2470 * Must be called with the domain lock held.
2472 static dma_addr_t
__map_single(struct device
*dev
,
2473 struct dma_ops_domain
*dma_dom
,
2480 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
2481 dma_addr_t address
, start
, ret
;
2483 unsigned long align_mask
= 0;
2486 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
2489 INC_STATS_COUNTER(total_map_requests
);
2492 INC_STATS_COUNTER(cross_page
);
2495 align_mask
= (1UL << get_order(size
)) - 1;
2498 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
, align_mask
,
2500 if (unlikely(address
== DMA_ERROR_CODE
)) {
2502 * setting next_address here will let the address
2503 * allocator only scan the new allocated range in the
2504 * first run. This is a small optimization.
2506 dma_dom
->next_address
= dma_dom
->aperture_size
;
2508 if (alloc_new_range(dma_dom
, false, GFP_ATOMIC
))
2512 * aperture was successfully enlarged by 128 MB, try
2519 for (i
= 0; i
< pages
; ++i
) {
2520 ret
= dma_ops_domain_map(dma_dom
, start
, paddr
, dir
);
2521 if (ret
== DMA_ERROR_CODE
)
2529 ADD_STATS_COUNTER(alloced_io_mem
, size
);
2531 if (unlikely(dma_dom
->need_flush
&& !amd_iommu_unmap_flush
)) {
2532 domain_flush_tlb(&dma_dom
->domain
);
2533 dma_dom
->need_flush
= false;
2534 } else if (unlikely(amd_iommu_np_cache
))
2535 domain_flush_pages(&dma_dom
->domain
, address
, size
);
2542 for (--i
; i
>= 0; --i
) {
2544 dma_ops_domain_unmap(dma_dom
, start
);
2547 dma_ops_free_addresses(dma_dom
, address
, pages
);
2549 return DMA_ERROR_CODE
;
2553 * Does the reverse of the __map_single function. Must be called with
2554 * the domain lock held too
2556 static void __unmap_single(struct dma_ops_domain
*dma_dom
,
2557 dma_addr_t dma_addr
,
2561 dma_addr_t flush_addr
;
2562 dma_addr_t i
, start
;
2565 if ((dma_addr
== DMA_ERROR_CODE
) ||
2566 (dma_addr
+ size
> dma_dom
->aperture_size
))
2569 flush_addr
= dma_addr
;
2570 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
2571 dma_addr
&= PAGE_MASK
;
2574 for (i
= 0; i
< pages
; ++i
) {
2575 dma_ops_domain_unmap(dma_dom
, start
);
2579 SUB_STATS_COUNTER(alloced_io_mem
, size
);
2581 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
2583 if (amd_iommu_unmap_flush
|| dma_dom
->need_flush
) {
2584 domain_flush_pages(&dma_dom
->domain
, flush_addr
, size
);
2585 dma_dom
->need_flush
= false;
2590 * The exported map_single function for dma_ops.
2592 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
2593 unsigned long offset
, size_t size
,
2594 enum dma_data_direction dir
,
2595 struct dma_attrs
*attrs
)
2597 unsigned long flags
;
2598 struct protection_domain
*domain
;
2601 phys_addr_t paddr
= page_to_phys(page
) + offset
;
2603 INC_STATS_COUNTER(cnt_map_single
);
2605 domain
= get_domain(dev
);
2606 if (PTR_ERR(domain
) == -EINVAL
)
2607 return (dma_addr_t
)paddr
;
2608 else if (IS_ERR(domain
))
2609 return DMA_ERROR_CODE
;
2611 dma_mask
= *dev
->dma_mask
;
2613 spin_lock_irqsave(&domain
->lock
, flags
);
2615 addr
= __map_single(dev
, domain
->priv
, paddr
, size
, dir
, false,
2617 if (addr
== DMA_ERROR_CODE
)
2620 domain_flush_complete(domain
);
2623 spin_unlock_irqrestore(&domain
->lock
, flags
);
2629 * The exported unmap_single function for dma_ops.
2631 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
2632 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
2634 unsigned long flags
;
2635 struct protection_domain
*domain
;
2637 INC_STATS_COUNTER(cnt_unmap_single
);
2639 domain
= get_domain(dev
);
2643 spin_lock_irqsave(&domain
->lock
, flags
);
2645 __unmap_single(domain
->priv
, dma_addr
, size
, dir
);
2647 domain_flush_complete(domain
);
2649 spin_unlock_irqrestore(&domain
->lock
, flags
);
2653 * The exported map_sg function for dma_ops (handles scatter-gather
2656 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
2657 int nelems
, enum dma_data_direction dir
,
2658 struct dma_attrs
*attrs
)
2660 unsigned long flags
;
2661 struct protection_domain
*domain
;
2663 struct scatterlist
*s
;
2665 int mapped_elems
= 0;
2668 INC_STATS_COUNTER(cnt_map_sg
);
2670 domain
= get_domain(dev
);
2674 dma_mask
= *dev
->dma_mask
;
2676 spin_lock_irqsave(&domain
->lock
, flags
);
2678 for_each_sg(sglist
, s
, nelems
, i
) {
2681 s
->dma_address
= __map_single(dev
, domain
->priv
,
2682 paddr
, s
->length
, dir
, false,
2685 if (s
->dma_address
) {
2686 s
->dma_length
= s
->length
;
2692 domain_flush_complete(domain
);
2695 spin_unlock_irqrestore(&domain
->lock
, flags
);
2697 return mapped_elems
;
2699 for_each_sg(sglist
, s
, mapped_elems
, i
) {
2701 __unmap_single(domain
->priv
, s
->dma_address
,
2702 s
->dma_length
, dir
);
2703 s
->dma_address
= s
->dma_length
= 0;
2712 * The exported map_sg function for dma_ops (handles scatter-gather
2715 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
2716 int nelems
, enum dma_data_direction dir
,
2717 struct dma_attrs
*attrs
)
2719 unsigned long flags
;
2720 struct protection_domain
*domain
;
2721 struct scatterlist
*s
;
2724 INC_STATS_COUNTER(cnt_unmap_sg
);
2726 domain
= get_domain(dev
);
2730 spin_lock_irqsave(&domain
->lock
, flags
);
2732 for_each_sg(sglist
, s
, nelems
, i
) {
2733 __unmap_single(domain
->priv
, s
->dma_address
,
2734 s
->dma_length
, dir
);
2735 s
->dma_address
= s
->dma_length
= 0;
2738 domain_flush_complete(domain
);
2740 spin_unlock_irqrestore(&domain
->lock
, flags
);
2744 * The exported alloc_coherent function for dma_ops.
2746 static void *alloc_coherent(struct device
*dev
, size_t size
,
2747 dma_addr_t
*dma_addr
, gfp_t flag
,
2748 struct dma_attrs
*attrs
)
2750 u64 dma_mask
= dev
->coherent_dma_mask
;
2751 struct protection_domain
*domain
;
2752 unsigned long flags
;
2755 INC_STATS_COUNTER(cnt_alloc_coherent
);
2757 domain
= get_domain(dev
);
2758 if (PTR_ERR(domain
) == -EINVAL
) {
2759 page
= alloc_pages(flag
, get_order(size
));
2760 *dma_addr
= page_to_phys(page
);
2761 return page_address(page
);
2762 } else if (IS_ERR(domain
))
2765 size
= PAGE_ALIGN(size
);
2766 dma_mask
= dev
->coherent_dma_mask
;
2767 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
2770 page
= alloc_pages(flag
| __GFP_NOWARN
, get_order(size
));
2772 if (!(flag
& __GFP_WAIT
))
2775 page
= dma_alloc_from_contiguous(dev
, size
>> PAGE_SHIFT
,
2782 dma_mask
= *dev
->dma_mask
;
2784 spin_lock_irqsave(&domain
->lock
, flags
);
2786 *dma_addr
= __map_single(dev
, domain
->priv
, page_to_phys(page
),
2787 size
, DMA_BIDIRECTIONAL
, true, dma_mask
);
2789 if (*dma_addr
== DMA_ERROR_CODE
) {
2790 spin_unlock_irqrestore(&domain
->lock
, flags
);
2794 domain_flush_complete(domain
);
2796 spin_unlock_irqrestore(&domain
->lock
, flags
);
2798 return page_address(page
);
2802 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2803 __free_pages(page
, get_order(size
));
2809 * The exported free_coherent function for dma_ops.
2811 static void free_coherent(struct device
*dev
, size_t size
,
2812 void *virt_addr
, dma_addr_t dma_addr
,
2813 struct dma_attrs
*attrs
)
2815 struct protection_domain
*domain
;
2816 unsigned long flags
;
2819 INC_STATS_COUNTER(cnt_free_coherent
);
2821 page
= virt_to_page(virt_addr
);
2822 size
= PAGE_ALIGN(size
);
2824 domain
= get_domain(dev
);
2828 spin_lock_irqsave(&domain
->lock
, flags
);
2830 __unmap_single(domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
2832 domain_flush_complete(domain
);
2834 spin_unlock_irqrestore(&domain
->lock
, flags
);
2837 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2838 __free_pages(page
, get_order(size
));
2842 * This function is called by the DMA layer to find out if we can handle a
2843 * particular device. It is part of the dma_ops.
2845 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
2847 return check_device(dev
);
2850 static struct dma_map_ops amd_iommu_dma_ops
= {
2851 .alloc
= alloc_coherent
,
2852 .free
= free_coherent
,
2853 .map_page
= map_page
,
2854 .unmap_page
= unmap_page
,
2856 .unmap_sg
= unmap_sg
,
2857 .dma_supported
= amd_iommu_dma_supported
,
2860 int __init
amd_iommu_init_api(void)
2862 return bus_set_iommu(&pci_bus_type
, &amd_iommu_ops
);
2865 int __init
amd_iommu_init_dma_ops(void)
2870 amd_iommu_stats_init();
2872 if (amd_iommu_unmap_flush
)
2873 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2875 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2880 /*****************************************************************************
2882 * The following functions belong to the exported interface of AMD IOMMU
2884 * This interface allows access to lower level functions of the IOMMU
2885 * like protection domain handling and assignement of devices to domains
2886 * which is not possible with the dma_ops interface.
2888 *****************************************************************************/
2890 static void cleanup_domain(struct protection_domain
*domain
)
2892 struct iommu_dev_data
*entry
;
2893 unsigned long flags
;
2895 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2897 while (!list_empty(&domain
->dev_list
)) {
2898 entry
= list_first_entry(&domain
->dev_list
,
2899 struct iommu_dev_data
, list
);
2900 __detach_device(entry
);
2903 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2906 static void protection_domain_free(struct protection_domain
*domain
)
2911 del_domain_from_list(domain
);
2914 domain_id_free(domain
->id
);
2919 static struct protection_domain
*protection_domain_alloc(void)
2921 struct protection_domain
*domain
;
2923 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
2927 spin_lock_init(&domain
->lock
);
2928 mutex_init(&domain
->api_lock
);
2929 domain
->id
= domain_id_alloc();
2932 INIT_LIST_HEAD(&domain
->dev_list
);
2934 add_domain_to_list(domain
);
2944 static int alloc_passthrough_domain(void)
2946 if (pt_domain
!= NULL
)
2949 /* allocate passthrough domain */
2950 pt_domain
= protection_domain_alloc();
2954 pt_domain
->mode
= PAGE_MODE_NONE
;
2959 static struct iommu_domain
*amd_iommu_domain_alloc(unsigned type
)
2961 struct protection_domain
*pdomain
;
2962 struct dma_ops_domain
*dma_domain
;
2965 case IOMMU_DOMAIN_UNMANAGED
:
2966 pdomain
= protection_domain_alloc();
2970 pdomain
->mode
= PAGE_MODE_3_LEVEL
;
2971 pdomain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
2972 if (!pdomain
->pt_root
) {
2973 protection_domain_free(pdomain
);
2977 pdomain
->domain
.geometry
.aperture_start
= 0;
2978 pdomain
->domain
.geometry
.aperture_end
= ~0ULL;
2979 pdomain
->domain
.geometry
.force_aperture
= true;
2982 case IOMMU_DOMAIN_DMA
:
2983 dma_domain
= dma_ops_domain_alloc();
2985 pr_err("AMD-Vi: Failed to allocate\n");
2988 pdomain
= &dma_domain
->domain
;
2990 case IOMMU_DOMAIN_IDENTITY
:
2991 pdomain
= protection_domain_alloc();
2995 pdomain
->mode
= PAGE_MODE_NONE
;
3001 return &pdomain
->domain
;
3004 static void amd_iommu_domain_free(struct iommu_domain
*dom
)
3006 struct protection_domain
*domain
;
3011 domain
= to_pdomain(dom
);
3013 if (domain
->dev_cnt
> 0)
3014 cleanup_domain(domain
);
3016 BUG_ON(domain
->dev_cnt
!= 0);
3018 if (domain
->mode
!= PAGE_MODE_NONE
)
3019 free_pagetable(domain
);
3021 if (domain
->flags
& PD_IOMMUV2_MASK
)
3022 free_gcr3_table(domain
);
3024 protection_domain_free(domain
);
3027 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
3030 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
3031 struct amd_iommu
*iommu
;
3034 if (!check_device(dev
))
3037 devid
= get_device_id(dev
);
3039 if (dev_data
->domain
!= NULL
)
3042 iommu
= amd_iommu_rlookup_table
[devid
];
3046 iommu_completion_wait(iommu
);
3049 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
3052 struct protection_domain
*domain
= to_pdomain(dom
);
3053 struct iommu_dev_data
*dev_data
;
3054 struct amd_iommu
*iommu
;
3057 if (!check_device(dev
))
3060 dev_data
= dev
->archdata
.iommu
;
3062 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3066 if (dev_data
->domain
)
3069 ret
= attach_device(dev
, domain
);
3071 iommu_completion_wait(iommu
);
3076 static int amd_iommu_map(struct iommu_domain
*dom
, unsigned long iova
,
3077 phys_addr_t paddr
, size_t page_size
, int iommu_prot
)
3079 struct protection_domain
*domain
= to_pdomain(dom
);
3083 if (domain
->mode
== PAGE_MODE_NONE
)
3086 if (iommu_prot
& IOMMU_READ
)
3087 prot
|= IOMMU_PROT_IR
;
3088 if (iommu_prot
& IOMMU_WRITE
)
3089 prot
|= IOMMU_PROT_IW
;
3091 mutex_lock(&domain
->api_lock
);
3092 ret
= iommu_map_page(domain
, iova
, paddr
, prot
, page_size
);
3093 mutex_unlock(&domain
->api_lock
);
3098 static size_t amd_iommu_unmap(struct iommu_domain
*dom
, unsigned long iova
,
3101 struct protection_domain
*domain
= to_pdomain(dom
);
3104 if (domain
->mode
== PAGE_MODE_NONE
)
3107 mutex_lock(&domain
->api_lock
);
3108 unmap_size
= iommu_unmap_page(domain
, iova
, page_size
);
3109 mutex_unlock(&domain
->api_lock
);
3111 domain_flush_tlb_pde(domain
);
3116 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
3119 struct protection_domain
*domain
= to_pdomain(dom
);
3120 unsigned long offset_mask
, pte_pgsize
;
3123 if (domain
->mode
== PAGE_MODE_NONE
)
3126 pte
= fetch_pte(domain
, iova
, &pte_pgsize
);
3128 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
3131 offset_mask
= pte_pgsize
- 1;
3132 __pte
= *pte
& PM_ADDR_MASK
;
3134 return (__pte
& ~offset_mask
) | (iova
& offset_mask
);
3137 static bool amd_iommu_capable(enum iommu_cap cap
)
3140 case IOMMU_CAP_CACHE_COHERENCY
:
3142 case IOMMU_CAP_INTR_REMAP
:
3143 return (irq_remapping_enabled
== 1);
3144 case IOMMU_CAP_NOEXEC
:
3151 static void amd_iommu_get_dm_regions(struct device
*dev
,
3152 struct list_head
*head
)
3154 struct unity_map_entry
*entry
;
3157 devid
= get_device_id(dev
);
3159 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
3160 struct iommu_dm_region
*region
;
3162 if (devid
< entry
->devid_start
|| devid
> entry
->devid_end
)
3165 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
3167 pr_err("Out of memory allocating dm-regions for %s\n",
3172 region
->start
= entry
->address_start
;
3173 region
->length
= entry
->address_end
- entry
->address_start
;
3174 if (entry
->prot
& IOMMU_PROT_IR
)
3175 region
->prot
|= IOMMU_READ
;
3176 if (entry
->prot
& IOMMU_PROT_IW
)
3177 region
->prot
|= IOMMU_WRITE
;
3179 list_add_tail(®ion
->list
, head
);
3183 static void amd_iommu_put_dm_regions(struct device
*dev
,
3184 struct list_head
*head
)
3186 struct iommu_dm_region
*entry
, *next
;
3188 list_for_each_entry_safe(entry
, next
, head
, list
)
3192 static const struct iommu_ops amd_iommu_ops
= {
3193 .capable
= amd_iommu_capable
,
3194 .domain_alloc
= amd_iommu_domain_alloc
,
3195 .domain_free
= amd_iommu_domain_free
,
3196 .attach_dev
= amd_iommu_attach_device
,
3197 .detach_dev
= amd_iommu_detach_device
,
3198 .map
= amd_iommu_map
,
3199 .unmap
= amd_iommu_unmap
,
3200 .map_sg
= default_iommu_map_sg
,
3201 .iova_to_phys
= amd_iommu_iova_to_phys
,
3202 .add_device
= amd_iommu_add_device
,
3203 .remove_device
= amd_iommu_remove_device
,
3204 .get_dm_regions
= amd_iommu_get_dm_regions
,
3205 .put_dm_regions
= amd_iommu_put_dm_regions
,
3206 .pgsize_bitmap
= AMD_IOMMU_PGSIZES
,
3209 /*****************************************************************************
3211 * The next functions do a basic initialization of IOMMU for pass through
3214 * In passthrough mode the IOMMU is initialized and enabled but not used for
3215 * DMA-API translation.
3217 *****************************************************************************/
3219 int __init
amd_iommu_init_passthrough(void)
3221 struct iommu_dev_data
*dev_data
;
3222 struct pci_dev
*dev
= NULL
;
3225 ret
= alloc_passthrough_domain();
3229 for_each_pci_dev(dev
) {
3230 if (!check_device(&dev
->dev
))
3233 dev_data
= get_dev_data(&dev
->dev
);
3234 dev_data
->passthrough
= true;
3236 attach_device(&dev
->dev
, pt_domain
);
3239 amd_iommu_stats_init();
3241 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3246 /* IOMMUv2 specific functions */
3247 int amd_iommu_register_ppr_notifier(struct notifier_block
*nb
)
3249 return atomic_notifier_chain_register(&ppr_notifier
, nb
);
3251 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier
);
3253 int amd_iommu_unregister_ppr_notifier(struct notifier_block
*nb
)
3255 return atomic_notifier_chain_unregister(&ppr_notifier
, nb
);
3257 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier
);
3259 void amd_iommu_domain_direct_map(struct iommu_domain
*dom
)
3261 struct protection_domain
*domain
= to_pdomain(dom
);
3262 unsigned long flags
;
3264 spin_lock_irqsave(&domain
->lock
, flags
);
3266 /* Update data structure */
3267 domain
->mode
= PAGE_MODE_NONE
;
3268 domain
->updated
= true;
3270 /* Make changes visible to IOMMUs */
3271 update_domain(domain
);
3273 /* Page-table is not visible to IOMMU anymore, so free it */
3274 free_pagetable(domain
);
3276 spin_unlock_irqrestore(&domain
->lock
, flags
);
3278 EXPORT_SYMBOL(amd_iommu_domain_direct_map
);
3280 int amd_iommu_domain_enable_v2(struct iommu_domain
*dom
, int pasids
)
3282 struct protection_domain
*domain
= to_pdomain(dom
);
3283 unsigned long flags
;
3286 if (pasids
<= 0 || pasids
> (PASID_MASK
+ 1))
3289 /* Number of GCR3 table levels required */
3290 for (levels
= 0; (pasids
- 1) & ~0x1ff; pasids
>>= 9)
3293 if (levels
> amd_iommu_max_glx_val
)
3296 spin_lock_irqsave(&domain
->lock
, flags
);
3299 * Save us all sanity checks whether devices already in the
3300 * domain support IOMMUv2. Just force that the domain has no
3301 * devices attached when it is switched into IOMMUv2 mode.
3304 if (domain
->dev_cnt
> 0 || domain
->flags
& PD_IOMMUV2_MASK
)
3308 domain
->gcr3_tbl
= (void *)get_zeroed_page(GFP_ATOMIC
);
3309 if (domain
->gcr3_tbl
== NULL
)
3312 domain
->glx
= levels
;
3313 domain
->flags
|= PD_IOMMUV2_MASK
;
3314 domain
->updated
= true;
3316 update_domain(domain
);
3321 spin_unlock_irqrestore(&domain
->lock
, flags
);
3325 EXPORT_SYMBOL(amd_iommu_domain_enable_v2
);
3327 static int __flush_pasid(struct protection_domain
*domain
, int pasid
,
3328 u64 address
, bool size
)
3330 struct iommu_dev_data
*dev_data
;
3331 struct iommu_cmd cmd
;
3334 if (!(domain
->flags
& PD_IOMMUV2_MASK
))
3337 build_inv_iommu_pasid(&cmd
, domain
->id
, pasid
, address
, size
);
3340 * IOMMU TLB needs to be flushed before Device TLB to
3341 * prevent device TLB refill from IOMMU TLB
3343 for (i
= 0; i
< amd_iommus_present
; ++i
) {
3344 if (domain
->dev_iommu
[i
] == 0)
3347 ret
= iommu_queue_command(amd_iommus
[i
], &cmd
);
3352 /* Wait until IOMMU TLB flushes are complete */
3353 domain_flush_complete(domain
);
3355 /* Now flush device TLBs */
3356 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
3357 struct amd_iommu
*iommu
;
3360 BUG_ON(!dev_data
->ats
.enabled
);
3362 qdep
= dev_data
->ats
.qdep
;
3363 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3365 build_inv_iotlb_pasid(&cmd
, dev_data
->devid
, pasid
,
3366 qdep
, address
, size
);
3368 ret
= iommu_queue_command(iommu
, &cmd
);
3373 /* Wait until all device TLBs are flushed */
3374 domain_flush_complete(domain
);
3383 static int __amd_iommu_flush_page(struct protection_domain
*domain
, int pasid
,
3386 INC_STATS_COUNTER(invalidate_iotlb
);
3388 return __flush_pasid(domain
, pasid
, address
, false);
3391 int amd_iommu_flush_page(struct iommu_domain
*dom
, int pasid
,
3394 struct protection_domain
*domain
= to_pdomain(dom
);
3395 unsigned long flags
;
3398 spin_lock_irqsave(&domain
->lock
, flags
);
3399 ret
= __amd_iommu_flush_page(domain
, pasid
, address
);
3400 spin_unlock_irqrestore(&domain
->lock
, flags
);
3404 EXPORT_SYMBOL(amd_iommu_flush_page
);
3406 static int __amd_iommu_flush_tlb(struct protection_domain
*domain
, int pasid
)
3408 INC_STATS_COUNTER(invalidate_iotlb_all
);
3410 return __flush_pasid(domain
, pasid
, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
3414 int amd_iommu_flush_tlb(struct iommu_domain
*dom
, int pasid
)
3416 struct protection_domain
*domain
= to_pdomain(dom
);
3417 unsigned long flags
;
3420 spin_lock_irqsave(&domain
->lock
, flags
);
3421 ret
= __amd_iommu_flush_tlb(domain
, pasid
);
3422 spin_unlock_irqrestore(&domain
->lock
, flags
);
3426 EXPORT_SYMBOL(amd_iommu_flush_tlb
);
3428 static u64
*__get_gcr3_pte(u64
*root
, int level
, int pasid
, bool alloc
)
3435 index
= (pasid
>> (9 * level
)) & 0x1ff;
3441 if (!(*pte
& GCR3_VALID
)) {
3445 root
= (void *)get_zeroed_page(GFP_ATOMIC
);
3449 *pte
= __pa(root
) | GCR3_VALID
;
3452 root
= __va(*pte
& PAGE_MASK
);
3460 static int __set_gcr3(struct protection_domain
*domain
, int pasid
,
3465 if (domain
->mode
!= PAGE_MODE_NONE
)
3468 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, true);
3472 *pte
= (cr3
& PAGE_MASK
) | GCR3_VALID
;
3474 return __amd_iommu_flush_tlb(domain
, pasid
);
3477 static int __clear_gcr3(struct protection_domain
*domain
, int pasid
)
3481 if (domain
->mode
!= PAGE_MODE_NONE
)
3484 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, false);
3490 return __amd_iommu_flush_tlb(domain
, pasid
);
3493 int amd_iommu_domain_set_gcr3(struct iommu_domain
*dom
, int pasid
,
3496 struct protection_domain
*domain
= to_pdomain(dom
);
3497 unsigned long flags
;
3500 spin_lock_irqsave(&domain
->lock
, flags
);
3501 ret
= __set_gcr3(domain
, pasid
, cr3
);
3502 spin_unlock_irqrestore(&domain
->lock
, flags
);
3506 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3
);
3508 int amd_iommu_domain_clear_gcr3(struct iommu_domain
*dom
, int pasid
)
3510 struct protection_domain
*domain
= to_pdomain(dom
);
3511 unsigned long flags
;
3514 spin_lock_irqsave(&domain
->lock
, flags
);
3515 ret
= __clear_gcr3(domain
, pasid
);
3516 spin_unlock_irqrestore(&domain
->lock
, flags
);
3520 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3
);
3522 int amd_iommu_complete_ppr(struct pci_dev
*pdev
, int pasid
,
3523 int status
, int tag
)
3525 struct iommu_dev_data
*dev_data
;
3526 struct amd_iommu
*iommu
;
3527 struct iommu_cmd cmd
;
3529 INC_STATS_COUNTER(complete_ppr
);
3531 dev_data
= get_dev_data(&pdev
->dev
);
3532 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3534 build_complete_ppr(&cmd
, dev_data
->devid
, pasid
, status
,
3535 tag
, dev_data
->pri_tlp
);
3537 return iommu_queue_command(iommu
, &cmd
);
3539 EXPORT_SYMBOL(amd_iommu_complete_ppr
);
3541 struct iommu_domain
*amd_iommu_get_v2_domain(struct pci_dev
*pdev
)
3543 struct protection_domain
*pdomain
;
3545 pdomain
= get_domain(&pdev
->dev
);
3546 if (IS_ERR(pdomain
))
3549 /* Only return IOMMUv2 domains */
3550 if (!(pdomain
->flags
& PD_IOMMUV2_MASK
))
3553 return &pdomain
->domain
;
3555 EXPORT_SYMBOL(amd_iommu_get_v2_domain
);
3557 void amd_iommu_enable_device_erratum(struct pci_dev
*pdev
, u32 erratum
)
3559 struct iommu_dev_data
*dev_data
;
3561 if (!amd_iommu_v2_supported())
3564 dev_data
= get_dev_data(&pdev
->dev
);
3565 dev_data
->errata
|= (1 << erratum
);
3567 EXPORT_SYMBOL(amd_iommu_enable_device_erratum
);
3569 int amd_iommu_device_info(struct pci_dev
*pdev
,
3570 struct amd_iommu_device_info
*info
)
3575 if (pdev
== NULL
|| info
== NULL
)
3578 if (!amd_iommu_v2_supported())
3581 memset(info
, 0, sizeof(*info
));
3583 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ATS
);
3585 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_ATS_SUP
;
3587 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
3589 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRI_SUP
;
3591 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PASID
);
3595 max_pasids
= 1 << (9 * (amd_iommu_max_glx_val
+ 1));
3596 max_pasids
= min(max_pasids
, (1 << 20));
3598 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PASID_SUP
;
3599 info
->max_pasids
= min(pci_max_pasids(pdev
), max_pasids
);
3601 features
= pci_pasid_features(pdev
);
3602 if (features
& PCI_PASID_CAP_EXEC
)
3603 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP
;
3604 if (features
& PCI_PASID_CAP_PRIV
)
3605 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP
;
3610 EXPORT_SYMBOL(amd_iommu_device_info
);
3612 #ifdef CONFIG_IRQ_REMAP
3614 /*****************************************************************************
3616 * Interrupt Remapping Implementation
3618 *****************************************************************************/
3636 u16 devid
; /* Device ID for IRTE table */
3637 u16 index
; /* Index into IRTE table*/
3640 struct amd_ir_data
{
3641 struct irq_2_irte irq_2_irte
;
3642 union irte irte_entry
;
3644 struct msi_msg msi_entry
;
3648 static struct irq_chip amd_ir_chip
;
3650 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3651 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3652 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3653 #define DTE_IRQ_REMAP_ENABLE 1ULL
3655 static void set_dte_irq_entry(u16 devid
, struct irq_remap_table
*table
)
3659 dte
= amd_iommu_dev_table
[devid
].data
[2];
3660 dte
&= ~DTE_IRQ_PHYS_ADDR_MASK
;
3661 dte
|= virt_to_phys(table
->table
);
3662 dte
|= DTE_IRQ_REMAP_INTCTL
;
3663 dte
|= DTE_IRQ_TABLE_LEN
;
3664 dte
|= DTE_IRQ_REMAP_ENABLE
;
3666 amd_iommu_dev_table
[devid
].data
[2] = dte
;
3669 #define IRTE_ALLOCATED (~1U)
3671 static struct irq_remap_table
*get_irq_table(u16 devid
, bool ioapic
)
3673 struct irq_remap_table
*table
= NULL
;
3674 struct amd_iommu
*iommu
;
3675 unsigned long flags
;
3678 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
3680 iommu
= amd_iommu_rlookup_table
[devid
];
3684 table
= irq_lookup_table
[devid
];
3688 alias
= amd_iommu_alias_table
[devid
];
3689 table
= irq_lookup_table
[alias
];
3691 irq_lookup_table
[devid
] = table
;
3692 set_dte_irq_entry(devid
, table
);
3693 iommu_flush_dte(iommu
, devid
);
3697 /* Nothing there yet, allocate new irq remapping table */
3698 table
= kzalloc(sizeof(*table
), GFP_ATOMIC
);
3702 /* Initialize table spin-lock */
3703 spin_lock_init(&table
->lock
);
3706 /* Keep the first 32 indexes free for IOAPIC interrupts */
3707 table
->min_index
= 32;
3709 table
->table
= kmem_cache_alloc(amd_iommu_irq_cache
, GFP_ATOMIC
);
3710 if (!table
->table
) {
3716 memset(table
->table
, 0, MAX_IRQS_PER_TABLE
* sizeof(u32
));
3721 for (i
= 0; i
< 32; ++i
)
3722 table
->table
[i
] = IRTE_ALLOCATED
;
3725 irq_lookup_table
[devid
] = table
;
3726 set_dte_irq_entry(devid
, table
);
3727 iommu_flush_dte(iommu
, devid
);
3728 if (devid
!= alias
) {
3729 irq_lookup_table
[alias
] = table
;
3730 set_dte_irq_entry(alias
, table
);
3731 iommu_flush_dte(iommu
, alias
);
3735 iommu_completion_wait(iommu
);
3738 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
3743 static int alloc_irq_index(u16 devid
, int count
)
3745 struct irq_remap_table
*table
;
3746 unsigned long flags
;
3749 table
= get_irq_table(devid
, false);
3753 spin_lock_irqsave(&table
->lock
, flags
);
3755 /* Scan table for free entries */
3756 for (c
= 0, index
= table
->min_index
;
3757 index
< MAX_IRQS_PER_TABLE
;
3759 if (table
->table
[index
] == 0)
3766 table
->table
[index
- c
+ 1] = IRTE_ALLOCATED
;
3776 spin_unlock_irqrestore(&table
->lock
, flags
);
3781 static int modify_irte(u16 devid
, int index
, union irte irte
)
3783 struct irq_remap_table
*table
;
3784 struct amd_iommu
*iommu
;
3785 unsigned long flags
;
3787 iommu
= amd_iommu_rlookup_table
[devid
];
3791 table
= get_irq_table(devid
, false);
3795 spin_lock_irqsave(&table
->lock
, flags
);
3796 table
->table
[index
] = irte
.val
;
3797 spin_unlock_irqrestore(&table
->lock
, flags
);
3799 iommu_flush_irt(iommu
, devid
);
3800 iommu_completion_wait(iommu
);
3805 static void free_irte(u16 devid
, int index
)
3807 struct irq_remap_table
*table
;
3808 struct amd_iommu
*iommu
;
3809 unsigned long flags
;
3811 iommu
= amd_iommu_rlookup_table
[devid
];
3815 table
= get_irq_table(devid
, false);
3819 spin_lock_irqsave(&table
->lock
, flags
);
3820 table
->table
[index
] = 0;
3821 spin_unlock_irqrestore(&table
->lock
, flags
);
3823 iommu_flush_irt(iommu
, devid
);
3824 iommu_completion_wait(iommu
);
3827 static int get_devid(struct irq_alloc_info
*info
)
3831 switch (info
->type
) {
3832 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
3833 devid
= get_ioapic_devid(info
->ioapic_id
);
3835 case X86_IRQ_ALLOC_TYPE_HPET
:
3836 devid
= get_hpet_devid(info
->hpet_id
);
3838 case X86_IRQ_ALLOC_TYPE_MSI
:
3839 case X86_IRQ_ALLOC_TYPE_MSIX
:
3840 devid
= get_device_id(&info
->msi_dev
->dev
);
3850 static struct irq_domain
*get_ir_irq_domain(struct irq_alloc_info
*info
)
3852 struct amd_iommu
*iommu
;
3858 devid
= get_devid(info
);
3860 iommu
= amd_iommu_rlookup_table
[devid
];
3862 return iommu
->ir_domain
;
3868 static struct irq_domain
*get_irq_domain(struct irq_alloc_info
*info
)
3870 struct amd_iommu
*iommu
;
3876 switch (info
->type
) {
3877 case X86_IRQ_ALLOC_TYPE_MSI
:
3878 case X86_IRQ_ALLOC_TYPE_MSIX
:
3879 devid
= get_device_id(&info
->msi_dev
->dev
);
3881 iommu
= amd_iommu_rlookup_table
[devid
];
3883 return iommu
->msi_domain
;
3893 struct irq_remap_ops amd_iommu_irq_ops
= {
3894 .prepare
= amd_iommu_prepare
,
3895 .enable
= amd_iommu_enable
,
3896 .disable
= amd_iommu_disable
,
3897 .reenable
= amd_iommu_reenable
,
3898 .enable_faulting
= amd_iommu_enable_faulting
,
3899 .get_ir_irq_domain
= get_ir_irq_domain
,
3900 .get_irq_domain
= get_irq_domain
,
3903 static void irq_remapping_prepare_irte(struct amd_ir_data
*data
,
3904 struct irq_cfg
*irq_cfg
,
3905 struct irq_alloc_info
*info
,
3906 int devid
, int index
, int sub_handle
)
3908 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
3909 struct msi_msg
*msg
= &data
->msi_entry
;
3910 union irte
*irte
= &data
->irte_entry
;
3911 struct IO_APIC_route_entry
*entry
;
3913 data
->irq_2_irte
.devid
= devid
;
3914 data
->irq_2_irte
.index
= index
+ sub_handle
;
3916 /* Setup IRTE for IOMMU */
3918 irte
->fields
.vector
= irq_cfg
->vector
;
3919 irte
->fields
.int_type
= apic
->irq_delivery_mode
;
3920 irte
->fields
.destination
= irq_cfg
->dest_apicid
;
3921 irte
->fields
.dm
= apic
->irq_dest_mode
;
3922 irte
->fields
.valid
= 1;
3924 switch (info
->type
) {
3925 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
3926 /* Setup IOAPIC entry */
3927 entry
= info
->ioapic_entry
;
3928 info
->ioapic_entry
= NULL
;
3929 memset(entry
, 0, sizeof(*entry
));
3930 entry
->vector
= index
;
3932 entry
->trigger
= info
->ioapic_trigger
;
3933 entry
->polarity
= info
->ioapic_polarity
;
3934 /* Mask level triggered irqs. */
3935 if (info
->ioapic_trigger
)
3939 case X86_IRQ_ALLOC_TYPE_HPET
:
3940 case X86_IRQ_ALLOC_TYPE_MSI
:
3941 case X86_IRQ_ALLOC_TYPE_MSIX
:
3942 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3943 msg
->address_lo
= MSI_ADDR_BASE_LO
;
3944 msg
->data
= irte_info
->index
;
3953 static int irq_remapping_alloc(struct irq_domain
*domain
, unsigned int virq
,
3954 unsigned int nr_irqs
, void *arg
)
3956 struct irq_alloc_info
*info
= arg
;
3957 struct irq_data
*irq_data
;
3958 struct amd_ir_data
*data
;
3959 struct irq_cfg
*cfg
;
3965 if (nr_irqs
> 1 && info
->type
!= X86_IRQ_ALLOC_TYPE_MSI
&&
3966 info
->type
!= X86_IRQ_ALLOC_TYPE_MSIX
)
3970 * With IRQ remapping enabled, don't need contiguous CPU vectors
3971 * to support multiple MSI interrupts.
3973 if (info
->type
== X86_IRQ_ALLOC_TYPE_MSI
)
3974 info
->flags
&= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS
;
3976 devid
= get_devid(info
);
3980 ret
= irq_domain_alloc_irqs_parent(domain
, virq
, nr_irqs
, arg
);
3985 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
3987 goto out_free_parent
;
3989 if (info
->type
== X86_IRQ_ALLOC_TYPE_IOAPIC
) {
3990 if (get_irq_table(devid
, true))
3991 index
= info
->ioapic_pin
;
3995 index
= alloc_irq_index(devid
, nr_irqs
);
3998 pr_warn("Failed to allocate IRTE\n");
4000 goto out_free_parent
;
4003 for (i
= 0; i
< nr_irqs
; i
++) {
4004 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4005 cfg
= irqd_cfg(irq_data
);
4006 if (!irq_data
|| !cfg
) {
4012 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
4016 irq_data
->hwirq
= (devid
<< 16) + i
;
4017 irq_data
->chip_data
= data
;
4018 irq_data
->chip
= &amd_ir_chip
;
4019 irq_remapping_prepare_irte(data
, cfg
, info
, devid
, index
, i
);
4020 irq_set_status_flags(virq
+ i
, IRQ_MOVE_PCNTXT
);
4025 for (i
--; i
>= 0; i
--) {
4026 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4028 kfree(irq_data
->chip_data
);
4030 for (i
= 0; i
< nr_irqs
; i
++)
4031 free_irte(devid
, index
+ i
);
4033 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4037 static void irq_remapping_free(struct irq_domain
*domain
, unsigned int virq
,
4038 unsigned int nr_irqs
)
4040 struct irq_2_irte
*irte_info
;
4041 struct irq_data
*irq_data
;
4042 struct amd_ir_data
*data
;
4045 for (i
= 0; i
< nr_irqs
; i
++) {
4046 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4047 if (irq_data
&& irq_data
->chip_data
) {
4048 data
= irq_data
->chip_data
;
4049 irte_info
= &data
->irq_2_irte
;
4050 free_irte(irte_info
->devid
, irte_info
->index
);
4054 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4057 static void irq_remapping_activate(struct irq_domain
*domain
,
4058 struct irq_data
*irq_data
)
4060 struct amd_ir_data
*data
= irq_data
->chip_data
;
4061 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4063 modify_irte(irte_info
->devid
, irte_info
->index
, data
->irte_entry
);
4066 static void irq_remapping_deactivate(struct irq_domain
*domain
,
4067 struct irq_data
*irq_data
)
4069 struct amd_ir_data
*data
= irq_data
->chip_data
;
4070 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4074 modify_irte(irte_info
->devid
, irte_info
->index
, data
->irte_entry
);
4077 static struct irq_domain_ops amd_ir_domain_ops
= {
4078 .alloc
= irq_remapping_alloc
,
4079 .free
= irq_remapping_free
,
4080 .activate
= irq_remapping_activate
,
4081 .deactivate
= irq_remapping_deactivate
,
4084 static int amd_ir_set_affinity(struct irq_data
*data
,
4085 const struct cpumask
*mask
, bool force
)
4087 struct amd_ir_data
*ir_data
= data
->chip_data
;
4088 struct irq_2_irte
*irte_info
= &ir_data
->irq_2_irte
;
4089 struct irq_cfg
*cfg
= irqd_cfg(data
);
4090 struct irq_data
*parent
= data
->parent_data
;
4093 ret
= parent
->chip
->irq_set_affinity(parent
, mask
, force
);
4094 if (ret
< 0 || ret
== IRQ_SET_MASK_OK_DONE
)
4098 * Atomically updates the IRTE with the new destination, vector
4099 * and flushes the interrupt entry cache.
4101 ir_data
->irte_entry
.fields
.vector
= cfg
->vector
;
4102 ir_data
->irte_entry
.fields
.destination
= cfg
->dest_apicid
;
4103 modify_irte(irte_info
->devid
, irte_info
->index
, ir_data
->irte_entry
);
4106 * After this point, all the interrupts will start arriving
4107 * at the new destination. So, time to cleanup the previous
4108 * vector allocation.
4110 send_cleanup_vector(cfg
);
4112 return IRQ_SET_MASK_OK_DONE
;
4115 static void ir_compose_msi_msg(struct irq_data
*irq_data
, struct msi_msg
*msg
)
4117 struct amd_ir_data
*ir_data
= irq_data
->chip_data
;
4119 *msg
= ir_data
->msi_entry
;
4122 static struct irq_chip amd_ir_chip
= {
4123 .irq_ack
= ir_ack_apic_edge
,
4124 .irq_set_affinity
= amd_ir_set_affinity
,
4125 .irq_compose_msi_msg
= ir_compose_msi_msg
,
4128 int amd_iommu_create_irq_domain(struct amd_iommu
*iommu
)
4130 iommu
->ir_domain
= irq_domain_add_tree(NULL
, &amd_ir_domain_ops
, iommu
);
4131 if (!iommu
->ir_domain
)
4134 iommu
->ir_domain
->parent
= arch_get_ir_parent_domain();
4135 iommu
->msi_domain
= arch_create_msi_irq_domain(iommu
->ir_domain
);