2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <linux/dma-contiguous.h>
37 #include <linux/irqdomain.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/io_apic.h>
41 #include <asm/hw_irq.h>
42 #include <asm/msidef.h>
43 #include <asm/proto.h>
44 #include <asm/iommu.h>
48 #include "amd_iommu_proto.h"
49 #include "amd_iommu_types.h"
50 #include "irq_remapping.h"
52 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
54 #define LOOP_TIMEOUT 100000
57 * This bitmap is used to advertise the page sizes our hardware support
58 * to the IOMMU core, which will then use this information to split
59 * physically contiguous memory regions it is mapping into page sizes
62 * 512GB Pages are not supported due to a hardware bug
64 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
66 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
68 /* List of all available dev_data structures */
69 static LIST_HEAD(dev_data_list
);
70 static DEFINE_SPINLOCK(dev_data_list_lock
);
72 LIST_HEAD(ioapic_map
);
76 * Domain for untranslated devices - only allocated
77 * if iommu=pt passed on kernel cmd line.
79 static struct protection_domain
*pt_domain
;
81 static const struct iommu_ops amd_iommu_ops
;
83 static ATOMIC_NOTIFIER_HEAD(ppr_notifier
);
84 int amd_iommu_max_glx_val
= -1;
86 static struct dma_map_ops amd_iommu_dma_ops
;
89 * This struct contains device specific data for the IOMMU
91 struct iommu_dev_data
{
92 struct list_head list
; /* For domain->dev_list */
93 struct list_head dev_data_list
; /* For global dev_data_list */
94 struct list_head alias_list
; /* Link alias-groups together */
95 struct iommu_dev_data
*alias_data
;/* The alias dev_data */
96 struct protection_domain
*domain
; /* Domain the device is bound to */
97 u16 devid
; /* PCI Device ID */
98 bool iommu_v2
; /* Device can make use of IOMMUv2 */
99 bool passthrough
; /* Default for device is pt_domain */
103 } ats
; /* ATS state */
104 bool pri_tlp
; /* PASID TLB required for
106 u32 errata
; /* Bitmap for errata to apply */
110 * general struct to manage commands send to an IOMMU
116 struct kmem_cache
*amd_iommu_irq_cache
;
118 static void update_domain(struct protection_domain
*domain
);
119 static int alloc_passthrough_domain(void);
120 static int protection_domain_init(struct protection_domain
*domain
);
122 /****************************************************************************
126 ****************************************************************************/
128 static struct protection_domain
*to_pdomain(struct iommu_domain
*dom
)
130 return container_of(dom
, struct protection_domain
, domain
);
133 static struct iommu_dev_data
*alloc_dev_data(u16 devid
)
135 struct iommu_dev_data
*dev_data
;
138 dev_data
= kzalloc(sizeof(*dev_data
), GFP_KERNEL
);
142 INIT_LIST_HEAD(&dev_data
->alias_list
);
144 dev_data
->devid
= devid
;
146 spin_lock_irqsave(&dev_data_list_lock
, flags
);
147 list_add_tail(&dev_data
->dev_data_list
, &dev_data_list
);
148 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
153 static void free_dev_data(struct iommu_dev_data
*dev_data
)
157 spin_lock_irqsave(&dev_data_list_lock
, flags
);
158 list_del(&dev_data
->dev_data_list
);
159 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
164 static struct iommu_dev_data
*search_dev_data(u16 devid
)
166 struct iommu_dev_data
*dev_data
;
169 spin_lock_irqsave(&dev_data_list_lock
, flags
);
170 list_for_each_entry(dev_data
, &dev_data_list
, dev_data_list
) {
171 if (dev_data
->devid
== devid
)
178 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
183 static struct iommu_dev_data
*find_dev_data(u16 devid
)
185 struct iommu_dev_data
*dev_data
;
187 dev_data
= search_dev_data(devid
);
189 if (dev_data
== NULL
)
190 dev_data
= alloc_dev_data(devid
);
195 static inline u16
get_device_id(struct device
*dev
)
197 struct pci_dev
*pdev
= to_pci_dev(dev
);
199 return PCI_DEVID(pdev
->bus
->number
, pdev
->devfn
);
202 static struct iommu_dev_data
*get_dev_data(struct device
*dev
)
204 return dev
->archdata
.iommu
;
207 static bool pci_iommuv2_capable(struct pci_dev
*pdev
)
209 static const int caps
[] = {
212 PCI_EXT_CAP_ID_PASID
,
216 for (i
= 0; i
< 3; ++i
) {
217 pos
= pci_find_ext_capability(pdev
, caps
[i
]);
225 static bool pdev_pri_erratum(struct pci_dev
*pdev
, u32 erratum
)
227 struct iommu_dev_data
*dev_data
;
229 dev_data
= get_dev_data(&pdev
->dev
);
231 return dev_data
->errata
& (1 << erratum
) ? true : false;
235 * This function actually applies the mapping to the page table of the
238 static void alloc_unity_mapping(struct dma_ops_domain
*dma_dom
,
239 struct unity_map_entry
*e
)
243 for (addr
= e
->address_start
; addr
< e
->address_end
;
245 if (addr
< dma_dom
->aperture_size
)
246 __set_bit(addr
>> PAGE_SHIFT
,
247 dma_dom
->aperture
[0]->bitmap
);
252 * Inits the unity mappings required for a specific device
254 static void init_unity_mappings_for_device(struct device
*dev
,
255 struct dma_ops_domain
*dma_dom
)
257 struct unity_map_entry
*e
;
260 devid
= get_device_id(dev
);
262 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
263 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
265 alloc_unity_mapping(dma_dom
, e
);
270 * This function checks if the driver got a valid device from the caller to
271 * avoid dereferencing invalid pointers.
273 static bool check_device(struct device
*dev
)
277 if (!dev
|| !dev
->dma_mask
)
281 if (!dev_is_pci(dev
))
284 devid
= get_device_id(dev
);
286 /* Out of our scope? */
287 if (devid
> amd_iommu_last_bdf
)
290 if (amd_iommu_rlookup_table
[devid
] == NULL
)
296 static void init_iommu_group(struct device
*dev
)
298 struct dma_ops_domain
*dma_domain
;
299 struct iommu_domain
*domain
;
300 struct iommu_group
*group
;
302 group
= iommu_group_get_for_dev(dev
);
306 domain
= iommu_group_default_domain(group
);
310 dma_domain
= to_pdomain(domain
)->priv
;
312 init_unity_mappings_for_device(dev
, dma_domain
);
314 iommu_group_put(group
);
317 static int __last_alias(struct pci_dev
*pdev
, u16 alias
, void *data
)
319 *(u16
*)data
= alias
;
323 static u16
get_alias(struct device
*dev
)
325 struct pci_dev
*pdev
= to_pci_dev(dev
);
326 u16 devid
, ivrs_alias
, pci_alias
;
328 devid
= get_device_id(dev
);
329 ivrs_alias
= amd_iommu_alias_table
[devid
];
330 pci_for_each_dma_alias(pdev
, __last_alias
, &pci_alias
);
332 if (ivrs_alias
== pci_alias
)
338 * The IVRS is fairly reliable in telling us about aliases, but it
339 * can't know about every screwy device. If we don't have an IVRS
340 * reported alias, use the PCI reported alias. In that case we may
341 * still need to initialize the rlookup and dev_table entries if the
342 * alias is to a non-existent device.
344 if (ivrs_alias
== devid
) {
345 if (!amd_iommu_rlookup_table
[pci_alias
]) {
346 amd_iommu_rlookup_table
[pci_alias
] =
347 amd_iommu_rlookup_table
[devid
];
348 memcpy(amd_iommu_dev_table
[pci_alias
].data
,
349 amd_iommu_dev_table
[devid
].data
,
350 sizeof(amd_iommu_dev_table
[pci_alias
].data
));
356 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
357 "for device %s[%04x:%04x], kernel reported alias "
358 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias
), PCI_SLOT(ivrs_alias
),
359 PCI_FUNC(ivrs_alias
), dev_name(dev
), pdev
->vendor
, pdev
->device
,
360 PCI_BUS_NUM(pci_alias
), PCI_SLOT(pci_alias
),
361 PCI_FUNC(pci_alias
));
364 * If we don't have a PCI DMA alias and the IVRS alias is on the same
365 * bus, then the IVRS table may know about a quirk that we don't.
367 if (pci_alias
== devid
&&
368 PCI_BUS_NUM(ivrs_alias
) == pdev
->bus
->number
) {
369 pdev
->dev_flags
|= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN
;
370 pdev
->dma_alias_devfn
= ivrs_alias
& 0xff;
371 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
372 PCI_SLOT(ivrs_alias
), PCI_FUNC(ivrs_alias
),
379 static int iommu_init_device(struct device
*dev
)
381 struct pci_dev
*pdev
= to_pci_dev(dev
);
382 struct iommu_dev_data
*dev_data
;
385 if (dev
->archdata
.iommu
)
388 dev_data
= find_dev_data(get_device_id(dev
));
392 alias
= get_alias(dev
);
394 if (alias
!= dev_data
->devid
) {
395 struct iommu_dev_data
*alias_data
;
397 alias_data
= find_dev_data(alias
);
398 if (alias_data
== NULL
) {
399 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
401 free_dev_data(dev_data
);
404 dev_data
->alias_data
= alias_data
;
406 /* Add device to the alias_list */
407 list_add(&dev_data
->alias_list
, &alias_data
->alias_list
);
410 if (pci_iommuv2_capable(pdev
)) {
411 struct amd_iommu
*iommu
;
413 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
414 dev_data
->iommu_v2
= iommu
->is_iommu_v2
;
417 dev
->archdata
.iommu
= dev_data
;
419 iommu_device_link(amd_iommu_rlookup_table
[dev_data
->devid
]->iommu_dev
,
425 static void iommu_ignore_device(struct device
*dev
)
429 devid
= get_device_id(dev
);
430 alias
= amd_iommu_alias_table
[devid
];
432 memset(&amd_iommu_dev_table
[devid
], 0, sizeof(struct dev_table_entry
));
433 memset(&amd_iommu_dev_table
[alias
], 0, sizeof(struct dev_table_entry
));
435 amd_iommu_rlookup_table
[devid
] = NULL
;
436 amd_iommu_rlookup_table
[alias
] = NULL
;
439 static void iommu_uninit_device(struct device
*dev
)
441 struct iommu_dev_data
*dev_data
= search_dev_data(get_device_id(dev
));
446 iommu_device_unlink(amd_iommu_rlookup_table
[dev_data
->devid
]->iommu_dev
,
449 iommu_group_remove_device(dev
);
451 /* Unlink from alias, it may change if another device is re-plugged */
452 dev_data
->alias_data
= NULL
;
455 dev
->archdata
.dma_ops
= NULL
;
458 * We keep dev_data around for unplugged devices and reuse it when the
459 * device is re-plugged - not doing so would introduce a ton of races.
463 #ifdef CONFIG_AMD_IOMMU_STATS
466 * Initialization code for statistics collection
469 DECLARE_STATS_COUNTER(compl_wait
);
470 DECLARE_STATS_COUNTER(cnt_map_single
);
471 DECLARE_STATS_COUNTER(cnt_unmap_single
);
472 DECLARE_STATS_COUNTER(cnt_map_sg
);
473 DECLARE_STATS_COUNTER(cnt_unmap_sg
);
474 DECLARE_STATS_COUNTER(cnt_alloc_coherent
);
475 DECLARE_STATS_COUNTER(cnt_free_coherent
);
476 DECLARE_STATS_COUNTER(cross_page
);
477 DECLARE_STATS_COUNTER(domain_flush_single
);
478 DECLARE_STATS_COUNTER(domain_flush_all
);
479 DECLARE_STATS_COUNTER(alloced_io_mem
);
480 DECLARE_STATS_COUNTER(total_map_requests
);
481 DECLARE_STATS_COUNTER(complete_ppr
);
482 DECLARE_STATS_COUNTER(invalidate_iotlb
);
483 DECLARE_STATS_COUNTER(invalidate_iotlb_all
);
484 DECLARE_STATS_COUNTER(pri_requests
);
486 static struct dentry
*stats_dir
;
487 static struct dentry
*de_fflush
;
489 static void amd_iommu_stats_add(struct __iommu_counter
*cnt
)
491 if (stats_dir
== NULL
)
494 cnt
->dent
= debugfs_create_u64(cnt
->name
, 0444, stats_dir
,
498 static void amd_iommu_stats_init(void)
500 stats_dir
= debugfs_create_dir("amd-iommu", NULL
);
501 if (stats_dir
== NULL
)
504 de_fflush
= debugfs_create_bool("fullflush", 0444, stats_dir
,
505 &amd_iommu_unmap_flush
);
507 amd_iommu_stats_add(&compl_wait
);
508 amd_iommu_stats_add(&cnt_map_single
);
509 amd_iommu_stats_add(&cnt_unmap_single
);
510 amd_iommu_stats_add(&cnt_map_sg
);
511 amd_iommu_stats_add(&cnt_unmap_sg
);
512 amd_iommu_stats_add(&cnt_alloc_coherent
);
513 amd_iommu_stats_add(&cnt_free_coherent
);
514 amd_iommu_stats_add(&cross_page
);
515 amd_iommu_stats_add(&domain_flush_single
);
516 amd_iommu_stats_add(&domain_flush_all
);
517 amd_iommu_stats_add(&alloced_io_mem
);
518 amd_iommu_stats_add(&total_map_requests
);
519 amd_iommu_stats_add(&complete_ppr
);
520 amd_iommu_stats_add(&invalidate_iotlb
);
521 amd_iommu_stats_add(&invalidate_iotlb_all
);
522 amd_iommu_stats_add(&pri_requests
);
527 /****************************************************************************
529 * Interrupt handling functions
531 ****************************************************************************/
533 static void dump_dte_entry(u16 devid
)
537 for (i
= 0; i
< 4; ++i
)
538 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i
,
539 amd_iommu_dev_table
[devid
].data
[i
]);
542 static void dump_command(unsigned long phys_addr
)
544 struct iommu_cmd
*cmd
= phys_to_virt(phys_addr
);
547 for (i
= 0; i
< 4; ++i
)
548 pr_err("AMD-Vi: CMD[%d]: %08x\n", i
, cmd
->data
[i
]);
551 static void iommu_print_event(struct amd_iommu
*iommu
, void *__evt
)
553 int type
, devid
, domid
, flags
;
554 volatile u32
*event
= __evt
;
559 type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
560 devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
561 domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
562 flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
563 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
566 /* Did we hit the erratum? */
567 if (++count
== LOOP_TIMEOUT
) {
568 pr_err("AMD-Vi: No event written to event log\n");
575 printk(KERN_ERR
"AMD-Vi: Event logged [");
578 case EVENT_TYPE_ILL_DEV
:
579 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
580 "address=0x%016llx flags=0x%04x]\n",
581 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
583 dump_dte_entry(devid
);
585 case EVENT_TYPE_IO_FAULT
:
586 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
587 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
588 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
589 domid
, address
, flags
);
591 case EVENT_TYPE_DEV_TAB_ERR
:
592 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
593 "address=0x%016llx flags=0x%04x]\n",
594 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
597 case EVENT_TYPE_PAGE_TAB_ERR
:
598 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
599 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
600 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
601 domid
, address
, flags
);
603 case EVENT_TYPE_ILL_CMD
:
604 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
605 dump_command(address
);
607 case EVENT_TYPE_CMD_HARD_ERR
:
608 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
609 "flags=0x%04x]\n", address
, flags
);
611 case EVENT_TYPE_IOTLB_INV_TO
:
612 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
613 "address=0x%016llx]\n",
614 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
617 case EVENT_TYPE_INV_DEV_REQ
:
618 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
619 "address=0x%016llx flags=0x%04x]\n",
620 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
624 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
627 memset(__evt
, 0, 4 * sizeof(u32
));
630 static void iommu_poll_events(struct amd_iommu
*iommu
)
634 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
635 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
637 while (head
!= tail
) {
638 iommu_print_event(iommu
, iommu
->evt_buf
+ head
);
639 head
= (head
+ EVENT_ENTRY_SIZE
) % iommu
->evt_buf_size
;
642 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
645 static void iommu_handle_ppr_entry(struct amd_iommu
*iommu
, u64
*raw
)
647 struct amd_iommu_fault fault
;
649 INC_STATS_COUNTER(pri_requests
);
651 if (PPR_REQ_TYPE(raw
[0]) != PPR_REQ_FAULT
) {
652 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
656 fault
.address
= raw
[1];
657 fault
.pasid
= PPR_PASID(raw
[0]);
658 fault
.device_id
= PPR_DEVID(raw
[0]);
659 fault
.tag
= PPR_TAG(raw
[0]);
660 fault
.flags
= PPR_FLAGS(raw
[0]);
662 atomic_notifier_call_chain(&ppr_notifier
, 0, &fault
);
665 static void iommu_poll_ppr_log(struct amd_iommu
*iommu
)
669 if (iommu
->ppr_log
== NULL
)
672 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
673 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
675 while (head
!= tail
) {
680 raw
= (u64
*)(iommu
->ppr_log
+ head
);
683 * Hardware bug: Interrupt may arrive before the entry is
684 * written to memory. If this happens we need to wait for the
687 for (i
= 0; i
< LOOP_TIMEOUT
; ++i
) {
688 if (PPR_REQ_TYPE(raw
[0]) != 0)
693 /* Avoid memcpy function-call overhead */
698 * To detect the hardware bug we need to clear the entry
701 raw
[0] = raw
[1] = 0UL;
703 /* Update head pointer of hardware ring-buffer */
704 head
= (head
+ PPR_ENTRY_SIZE
) % PPR_LOG_SIZE
;
705 writel(head
, iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
707 /* Handle PPR entry */
708 iommu_handle_ppr_entry(iommu
, entry
);
710 /* Refresh ring-buffer information */
711 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
712 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
716 irqreturn_t
amd_iommu_int_thread(int irq
, void *data
)
718 struct amd_iommu
*iommu
= (struct amd_iommu
*) data
;
719 u32 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
721 while (status
& (MMIO_STATUS_EVT_INT_MASK
| MMIO_STATUS_PPR_INT_MASK
)) {
722 /* Enable EVT and PPR interrupts again */
723 writel((MMIO_STATUS_EVT_INT_MASK
| MMIO_STATUS_PPR_INT_MASK
),
724 iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
726 if (status
& MMIO_STATUS_EVT_INT_MASK
) {
727 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
728 iommu_poll_events(iommu
);
731 if (status
& MMIO_STATUS_PPR_INT_MASK
) {
732 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
733 iommu_poll_ppr_log(iommu
);
737 * Hardware bug: ERBT1312
738 * When re-enabling interrupt (by writing 1
739 * to clear the bit), the hardware might also try to set
740 * the interrupt bit in the event status register.
741 * In this scenario, the bit will be set, and disable
742 * subsequent interrupts.
744 * Workaround: The IOMMU driver should read back the
745 * status register and check if the interrupt bits are cleared.
746 * If not, driver will need to go through the interrupt handler
747 * again and re-clear the bits
749 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
754 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
756 return IRQ_WAKE_THREAD
;
759 /****************************************************************************
761 * IOMMU command queuing functions
763 ****************************************************************************/
765 static int wait_on_sem(volatile u64
*sem
)
769 while (*sem
== 0 && i
< LOOP_TIMEOUT
) {
774 if (i
== LOOP_TIMEOUT
) {
775 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
782 static void copy_cmd_to_buffer(struct amd_iommu
*iommu
,
783 struct iommu_cmd
*cmd
,
788 target
= iommu
->cmd_buf
+ tail
;
789 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
791 /* Copy command to buffer */
792 memcpy(target
, cmd
, sizeof(*cmd
));
794 /* Tell the IOMMU about it */
795 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
798 static void build_completion_wait(struct iommu_cmd
*cmd
, u64 address
)
800 WARN_ON(address
& 0x7ULL
);
802 memset(cmd
, 0, sizeof(*cmd
));
803 cmd
->data
[0] = lower_32_bits(__pa(address
)) | CMD_COMPL_WAIT_STORE_MASK
;
804 cmd
->data
[1] = upper_32_bits(__pa(address
));
806 CMD_SET_TYPE(cmd
, CMD_COMPL_WAIT
);
809 static void build_inv_dte(struct iommu_cmd
*cmd
, u16 devid
)
811 memset(cmd
, 0, sizeof(*cmd
));
812 cmd
->data
[0] = devid
;
813 CMD_SET_TYPE(cmd
, CMD_INV_DEV_ENTRY
);
816 static void build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
817 size_t size
, u16 domid
, int pde
)
822 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
827 * If we have to flush more than one page, flush all
828 * TLB entries for this domain
830 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
834 address
&= PAGE_MASK
;
836 memset(cmd
, 0, sizeof(*cmd
));
837 cmd
->data
[1] |= domid
;
838 cmd
->data
[2] = lower_32_bits(address
);
839 cmd
->data
[3] = upper_32_bits(address
);
840 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
841 if (s
) /* size bit - we flush more than one 4kb page */
842 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
843 if (pde
) /* PDE bit - we want to flush everything, not only the PTEs */
844 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
847 static void build_inv_iotlb_pages(struct iommu_cmd
*cmd
, u16 devid
, int qdep
,
848 u64 address
, size_t size
)
853 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
858 * If we have to flush more than one page, flush all
859 * TLB entries for this domain
861 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
865 address
&= PAGE_MASK
;
867 memset(cmd
, 0, sizeof(*cmd
));
868 cmd
->data
[0] = devid
;
869 cmd
->data
[0] |= (qdep
& 0xff) << 24;
870 cmd
->data
[1] = devid
;
871 cmd
->data
[2] = lower_32_bits(address
);
872 cmd
->data
[3] = upper_32_bits(address
);
873 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
875 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
878 static void build_inv_iommu_pasid(struct iommu_cmd
*cmd
, u16 domid
, int pasid
,
879 u64 address
, bool size
)
881 memset(cmd
, 0, sizeof(*cmd
));
883 address
&= ~(0xfffULL
);
885 cmd
->data
[0] = pasid
;
886 cmd
->data
[1] = domid
;
887 cmd
->data
[2] = lower_32_bits(address
);
888 cmd
->data
[3] = upper_32_bits(address
);
889 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
890 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
892 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
893 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
896 static void build_inv_iotlb_pasid(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
897 int qdep
, u64 address
, bool size
)
899 memset(cmd
, 0, sizeof(*cmd
));
901 address
&= ~(0xfffULL
);
903 cmd
->data
[0] = devid
;
904 cmd
->data
[0] |= ((pasid
>> 8) & 0xff) << 16;
905 cmd
->data
[0] |= (qdep
& 0xff) << 24;
906 cmd
->data
[1] = devid
;
907 cmd
->data
[1] |= (pasid
& 0xff) << 16;
908 cmd
->data
[2] = lower_32_bits(address
);
909 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
910 cmd
->data
[3] = upper_32_bits(address
);
912 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
913 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
916 static void build_complete_ppr(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
917 int status
, int tag
, bool gn
)
919 memset(cmd
, 0, sizeof(*cmd
));
921 cmd
->data
[0] = devid
;
923 cmd
->data
[1] = pasid
;
924 cmd
->data
[2] = CMD_INV_IOMMU_PAGES_GN_MASK
;
926 cmd
->data
[3] = tag
& 0x1ff;
927 cmd
->data
[3] |= (status
& PPR_STATUS_MASK
) << PPR_STATUS_SHIFT
;
929 CMD_SET_TYPE(cmd
, CMD_COMPLETE_PPR
);
932 static void build_inv_all(struct iommu_cmd
*cmd
)
934 memset(cmd
, 0, sizeof(*cmd
));
935 CMD_SET_TYPE(cmd
, CMD_INV_ALL
);
938 static void build_inv_irt(struct iommu_cmd
*cmd
, u16 devid
)
940 memset(cmd
, 0, sizeof(*cmd
));
941 cmd
->data
[0] = devid
;
942 CMD_SET_TYPE(cmd
, CMD_INV_IRT
);
946 * Writes the command to the IOMMUs command buffer and informs the
947 * hardware about the new command.
949 static int iommu_queue_command_sync(struct amd_iommu
*iommu
,
950 struct iommu_cmd
*cmd
,
953 u32 left
, tail
, head
, next_tail
;
956 WARN_ON(iommu
->cmd_buf_size
& CMD_BUFFER_UNINITIALIZED
);
959 spin_lock_irqsave(&iommu
->lock
, flags
);
961 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
962 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
963 next_tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
964 left
= (head
- next_tail
) % iommu
->cmd_buf_size
;
967 struct iommu_cmd sync_cmd
;
968 volatile u64 sem
= 0;
971 build_completion_wait(&sync_cmd
, (u64
)&sem
);
972 copy_cmd_to_buffer(iommu
, &sync_cmd
, tail
);
974 spin_unlock_irqrestore(&iommu
->lock
, flags
);
976 if ((ret
= wait_on_sem(&sem
)) != 0)
982 copy_cmd_to_buffer(iommu
, cmd
, tail
);
984 /* We need to sync now to make sure all commands are processed */
985 iommu
->need_sync
= sync
;
987 spin_unlock_irqrestore(&iommu
->lock
, flags
);
992 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
994 return iommu_queue_command_sync(iommu
, cmd
, true);
998 * This function queues a completion wait command into the command
1001 static int iommu_completion_wait(struct amd_iommu
*iommu
)
1003 struct iommu_cmd cmd
;
1004 volatile u64 sem
= 0;
1007 if (!iommu
->need_sync
)
1010 build_completion_wait(&cmd
, (u64
)&sem
);
1012 ret
= iommu_queue_command_sync(iommu
, &cmd
, false);
1016 return wait_on_sem(&sem
);
1019 static int iommu_flush_dte(struct amd_iommu
*iommu
, u16 devid
)
1021 struct iommu_cmd cmd
;
1023 build_inv_dte(&cmd
, devid
);
1025 return iommu_queue_command(iommu
, &cmd
);
1028 static void iommu_flush_dte_all(struct amd_iommu
*iommu
)
1032 for (devid
= 0; devid
<= 0xffff; ++devid
)
1033 iommu_flush_dte(iommu
, devid
);
1035 iommu_completion_wait(iommu
);
1039 * This function uses heavy locking and may disable irqs for some time. But
1040 * this is no issue because it is only called during resume.
1042 static void iommu_flush_tlb_all(struct amd_iommu
*iommu
)
1046 for (dom_id
= 0; dom_id
<= 0xffff; ++dom_id
) {
1047 struct iommu_cmd cmd
;
1048 build_inv_iommu_pages(&cmd
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
1050 iommu_queue_command(iommu
, &cmd
);
1053 iommu_completion_wait(iommu
);
1056 static void iommu_flush_all(struct amd_iommu
*iommu
)
1058 struct iommu_cmd cmd
;
1060 build_inv_all(&cmd
);
1062 iommu_queue_command(iommu
, &cmd
);
1063 iommu_completion_wait(iommu
);
1066 static void iommu_flush_irt(struct amd_iommu
*iommu
, u16 devid
)
1068 struct iommu_cmd cmd
;
1070 build_inv_irt(&cmd
, devid
);
1072 iommu_queue_command(iommu
, &cmd
);
1075 static void iommu_flush_irt_all(struct amd_iommu
*iommu
)
1079 for (devid
= 0; devid
<= MAX_DEV_TABLE_ENTRIES
; devid
++)
1080 iommu_flush_irt(iommu
, devid
);
1082 iommu_completion_wait(iommu
);
1085 void iommu_flush_all_caches(struct amd_iommu
*iommu
)
1087 if (iommu_feature(iommu
, FEATURE_IA
)) {
1088 iommu_flush_all(iommu
);
1090 iommu_flush_dte_all(iommu
);
1091 iommu_flush_irt_all(iommu
);
1092 iommu_flush_tlb_all(iommu
);
1097 * Command send function for flushing on-device TLB
1099 static int device_flush_iotlb(struct iommu_dev_data
*dev_data
,
1100 u64 address
, size_t size
)
1102 struct amd_iommu
*iommu
;
1103 struct iommu_cmd cmd
;
1106 qdep
= dev_data
->ats
.qdep
;
1107 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1109 build_inv_iotlb_pages(&cmd
, dev_data
->devid
, qdep
, address
, size
);
1111 return iommu_queue_command(iommu
, &cmd
);
1115 * Command send function for invalidating a device table entry
1117 static int device_flush_dte(struct iommu_dev_data
*dev_data
)
1119 struct amd_iommu
*iommu
;
1122 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1124 ret
= iommu_flush_dte(iommu
, dev_data
->devid
);
1128 if (dev_data
->ats
.enabled
)
1129 ret
= device_flush_iotlb(dev_data
, 0, ~0UL);
1135 * TLB invalidation function which is called from the mapping functions.
1136 * It invalidates a single PTE if the range to flush is within a single
1137 * page. Otherwise it flushes the whole TLB of the IOMMU.
1139 static void __domain_flush_pages(struct protection_domain
*domain
,
1140 u64 address
, size_t size
, int pde
)
1142 struct iommu_dev_data
*dev_data
;
1143 struct iommu_cmd cmd
;
1146 build_inv_iommu_pages(&cmd
, address
, size
, domain
->id
, pde
);
1148 for (i
= 0; i
< amd_iommus_present
; ++i
) {
1149 if (!domain
->dev_iommu
[i
])
1153 * Devices of this domain are behind this IOMMU
1154 * We need a TLB flush
1156 ret
|= iommu_queue_command(amd_iommus
[i
], &cmd
);
1159 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
1161 if (!dev_data
->ats
.enabled
)
1164 ret
|= device_flush_iotlb(dev_data
, address
, size
);
1170 static void domain_flush_pages(struct protection_domain
*domain
,
1171 u64 address
, size_t size
)
1173 __domain_flush_pages(domain
, address
, size
, 0);
1176 /* Flush the whole IO/TLB for a given protection domain */
1177 static void domain_flush_tlb(struct protection_domain
*domain
)
1179 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 0);
1182 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1183 static void domain_flush_tlb_pde(struct protection_domain
*domain
)
1185 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 1);
1188 static void domain_flush_complete(struct protection_domain
*domain
)
1192 for (i
= 0; i
< amd_iommus_present
; ++i
) {
1193 if (!domain
->dev_iommu
[i
])
1197 * Devices of this domain are behind this IOMMU
1198 * We need to wait for completion of all commands.
1200 iommu_completion_wait(amd_iommus
[i
]);
1206 * This function flushes the DTEs for all devices in domain
1208 static void domain_flush_devices(struct protection_domain
*domain
)
1210 struct iommu_dev_data
*dev_data
;
1212 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
1213 device_flush_dte(dev_data
);
1216 /****************************************************************************
1218 * The functions below are used the create the page table mappings for
1219 * unity mapped regions.
1221 ****************************************************************************/
1224 * This function is used to add another level to an IO page table. Adding
1225 * another level increases the size of the address space by 9 bits to a size up
1228 static bool increase_address_space(struct protection_domain
*domain
,
1233 if (domain
->mode
== PAGE_MODE_6_LEVEL
)
1234 /* address space already 64 bit large */
1237 pte
= (void *)get_zeroed_page(gfp
);
1241 *pte
= PM_LEVEL_PDE(domain
->mode
,
1242 virt_to_phys(domain
->pt_root
));
1243 domain
->pt_root
= pte
;
1245 domain
->updated
= true;
1250 static u64
*alloc_pte(struct protection_domain
*domain
,
1251 unsigned long address
,
1252 unsigned long page_size
,
1259 BUG_ON(!is_power_of_2(page_size
));
1261 while (address
> PM_LEVEL_SIZE(domain
->mode
))
1262 increase_address_space(domain
, gfp
);
1264 level
= domain
->mode
- 1;
1265 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1266 address
= PAGE_SIZE_ALIGN(address
, page_size
);
1267 end_lvl
= PAGE_SIZE_LEVEL(page_size
);
1269 while (level
> end_lvl
) {
1270 if (!IOMMU_PTE_PRESENT(*pte
)) {
1271 page
= (u64
*)get_zeroed_page(gfp
);
1274 *pte
= PM_LEVEL_PDE(level
, virt_to_phys(page
));
1277 /* No level skipping support yet */
1278 if (PM_PTE_LEVEL(*pte
) != level
)
1283 pte
= IOMMU_PTE_PAGE(*pte
);
1285 if (pte_page
&& level
== end_lvl
)
1288 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1295 * This function checks if there is a PTE for a given dma address. If
1296 * there is one, it returns the pointer to it.
1298 static u64
*fetch_pte(struct protection_domain
*domain
,
1299 unsigned long address
,
1300 unsigned long *page_size
)
1305 if (address
> PM_LEVEL_SIZE(domain
->mode
))
1308 level
= domain
->mode
- 1;
1309 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1310 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1315 if (!IOMMU_PTE_PRESENT(*pte
))
1319 if (PM_PTE_LEVEL(*pte
) == 7 ||
1320 PM_PTE_LEVEL(*pte
) == 0)
1323 /* No level skipping support yet */
1324 if (PM_PTE_LEVEL(*pte
) != level
)
1329 /* Walk to the next level */
1330 pte
= IOMMU_PTE_PAGE(*pte
);
1331 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1332 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1335 if (PM_PTE_LEVEL(*pte
) == 0x07) {
1336 unsigned long pte_mask
;
1339 * If we have a series of large PTEs, make
1340 * sure to return a pointer to the first one.
1342 *page_size
= pte_mask
= PTE_PAGE_SIZE(*pte
);
1343 pte_mask
= ~((PAGE_SIZE_PTE_COUNT(pte_mask
) << 3) - 1);
1344 pte
= (u64
*)(((unsigned long)pte
) & pte_mask
);
1351 * Generic mapping functions. It maps a physical address into a DMA
1352 * address space. It allocates the page table pages if necessary.
1353 * In the future it can be extended to a generic mapping function
1354 * supporting all features of AMD IOMMU page tables like level skipping
1355 * and full 64 bit address spaces.
1357 static int iommu_map_page(struct protection_domain
*dom
,
1358 unsigned long bus_addr
,
1359 unsigned long phys_addr
,
1361 unsigned long page_size
)
1366 BUG_ON(!IS_ALIGNED(bus_addr
, page_size
));
1367 BUG_ON(!IS_ALIGNED(phys_addr
, page_size
));
1369 if (!(prot
& IOMMU_PROT_MASK
))
1372 count
= PAGE_SIZE_PTE_COUNT(page_size
);
1373 pte
= alloc_pte(dom
, bus_addr
, page_size
, NULL
, GFP_KERNEL
);
1378 for (i
= 0; i
< count
; ++i
)
1379 if (IOMMU_PTE_PRESENT(pte
[i
]))
1383 __pte
= PAGE_SIZE_PTE(phys_addr
, page_size
);
1384 __pte
|= PM_LEVEL_ENC(7) | IOMMU_PTE_P
| IOMMU_PTE_FC
;
1386 __pte
= phys_addr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1388 if (prot
& IOMMU_PROT_IR
)
1389 __pte
|= IOMMU_PTE_IR
;
1390 if (prot
& IOMMU_PROT_IW
)
1391 __pte
|= IOMMU_PTE_IW
;
1393 for (i
= 0; i
< count
; ++i
)
1401 static unsigned long iommu_unmap_page(struct protection_domain
*dom
,
1402 unsigned long bus_addr
,
1403 unsigned long page_size
)
1405 unsigned long long unmapped
;
1406 unsigned long unmap_size
;
1409 BUG_ON(!is_power_of_2(page_size
));
1413 while (unmapped
< page_size
) {
1415 pte
= fetch_pte(dom
, bus_addr
, &unmap_size
);
1420 count
= PAGE_SIZE_PTE_COUNT(unmap_size
);
1421 for (i
= 0; i
< count
; i
++)
1425 bus_addr
= (bus_addr
& ~(unmap_size
- 1)) + unmap_size
;
1426 unmapped
+= unmap_size
;
1429 BUG_ON(unmapped
&& !is_power_of_2(unmapped
));
1434 /****************************************************************************
1436 * The next functions belong to the address allocator for the dma_ops
1437 * interface functions. They work like the allocators in the other IOMMU
1438 * drivers. Its basically a bitmap which marks the allocated pages in
1439 * the aperture. Maybe it could be enhanced in the future to a more
1440 * efficient allocator.
1442 ****************************************************************************/
1445 * The address allocator core functions.
1447 * called with domain->lock held
1451 * Used to reserve address ranges in the aperture (e.g. for exclusion
1454 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
1455 unsigned long start_page
,
1458 unsigned int i
, last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
1460 if (start_page
+ pages
> last_page
)
1461 pages
= last_page
- start_page
;
1463 for (i
= start_page
; i
< start_page
+ pages
; ++i
) {
1464 int index
= i
/ APERTURE_RANGE_PAGES
;
1465 int page
= i
% APERTURE_RANGE_PAGES
;
1466 __set_bit(page
, dom
->aperture
[index
]->bitmap
);
1471 * This function is used to add a new aperture range to an existing
1472 * aperture in case of dma_ops domain allocation or address allocation
1475 static int alloc_new_range(struct dma_ops_domain
*dma_dom
,
1476 bool populate
, gfp_t gfp
)
1478 int index
= dma_dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1479 struct amd_iommu
*iommu
;
1480 unsigned long i
, old_size
, pte_pgsize
;
1482 #ifdef CONFIG_IOMMU_STRESS
1486 if (index
>= APERTURE_MAX_RANGES
)
1489 dma_dom
->aperture
[index
] = kzalloc(sizeof(struct aperture_range
), gfp
);
1490 if (!dma_dom
->aperture
[index
])
1493 dma_dom
->aperture
[index
]->bitmap
= (void *)get_zeroed_page(gfp
);
1494 if (!dma_dom
->aperture
[index
]->bitmap
)
1497 dma_dom
->aperture
[index
]->offset
= dma_dom
->aperture_size
;
1500 unsigned long address
= dma_dom
->aperture_size
;
1501 int i
, num_ptes
= APERTURE_RANGE_PAGES
/ 512;
1502 u64
*pte
, *pte_page
;
1504 for (i
= 0; i
< num_ptes
; ++i
) {
1505 pte
= alloc_pte(&dma_dom
->domain
, address
, PAGE_SIZE
,
1510 dma_dom
->aperture
[index
]->pte_pages
[i
] = pte_page
;
1512 address
+= APERTURE_RANGE_SIZE
/ 64;
1516 old_size
= dma_dom
->aperture_size
;
1517 dma_dom
->aperture_size
+= APERTURE_RANGE_SIZE
;
1519 /* Reserve address range used for MSI messages */
1520 if (old_size
< MSI_ADDR_BASE_LO
&&
1521 dma_dom
->aperture_size
> MSI_ADDR_BASE_LO
) {
1522 unsigned long spage
;
1525 pages
= iommu_num_pages(MSI_ADDR_BASE_LO
, 0x10000, PAGE_SIZE
);
1526 spage
= MSI_ADDR_BASE_LO
>> PAGE_SHIFT
;
1528 dma_ops_reserve_addresses(dma_dom
, spage
, pages
);
1531 /* Initialize the exclusion range if necessary */
1532 for_each_iommu(iommu
) {
1533 if (iommu
->exclusion_start
&&
1534 iommu
->exclusion_start
>= dma_dom
->aperture
[index
]->offset
1535 && iommu
->exclusion_start
< dma_dom
->aperture_size
) {
1536 unsigned long startpage
;
1537 int pages
= iommu_num_pages(iommu
->exclusion_start
,
1538 iommu
->exclusion_length
,
1540 startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
1541 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
1546 * Check for areas already mapped as present in the new aperture
1547 * range and mark those pages as reserved in the allocator. Such
1548 * mappings may already exist as a result of requested unity
1549 * mappings for devices.
1551 for (i
= dma_dom
->aperture
[index
]->offset
;
1552 i
< dma_dom
->aperture_size
;
1554 u64
*pte
= fetch_pte(&dma_dom
->domain
, i
, &pte_pgsize
);
1555 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
1558 dma_ops_reserve_addresses(dma_dom
, i
>> PAGE_SHIFT
,
1562 update_domain(&dma_dom
->domain
);
1567 update_domain(&dma_dom
->domain
);
1569 free_page((unsigned long)dma_dom
->aperture
[index
]->bitmap
);
1571 kfree(dma_dom
->aperture
[index
]);
1572 dma_dom
->aperture
[index
] = NULL
;
1577 static unsigned long dma_ops_area_alloc(struct device
*dev
,
1578 struct dma_ops_domain
*dom
,
1580 unsigned long align_mask
,
1582 unsigned long start
)
1584 unsigned long next_bit
= dom
->next_address
% APERTURE_RANGE_SIZE
;
1585 int max_index
= dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1586 int i
= start
>> APERTURE_RANGE_SHIFT
;
1587 unsigned long boundary_size
, mask
;
1588 unsigned long address
= -1;
1589 unsigned long limit
;
1591 next_bit
>>= PAGE_SHIFT
;
1593 mask
= dma_get_seg_boundary(dev
);
1595 boundary_size
= mask
+ 1 ? ALIGN(mask
+ 1, PAGE_SIZE
) >> PAGE_SHIFT
:
1596 1UL << (BITS_PER_LONG
- PAGE_SHIFT
);
1598 for (;i
< max_index
; ++i
) {
1599 unsigned long offset
= dom
->aperture
[i
]->offset
>> PAGE_SHIFT
;
1601 if (dom
->aperture
[i
]->offset
>= dma_mask
)
1604 limit
= iommu_device_max_index(APERTURE_RANGE_PAGES
, offset
,
1605 dma_mask
>> PAGE_SHIFT
);
1607 address
= iommu_area_alloc(dom
->aperture
[i
]->bitmap
,
1608 limit
, next_bit
, pages
, 0,
1609 boundary_size
, align_mask
);
1610 if (address
!= -1) {
1611 address
= dom
->aperture
[i
]->offset
+
1612 (address
<< PAGE_SHIFT
);
1613 dom
->next_address
= address
+ (pages
<< PAGE_SHIFT
);
1623 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
1624 struct dma_ops_domain
*dom
,
1626 unsigned long align_mask
,
1629 unsigned long address
;
1631 #ifdef CONFIG_IOMMU_STRESS
1632 dom
->next_address
= 0;
1633 dom
->need_flush
= true;
1636 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1637 dma_mask
, dom
->next_address
);
1639 if (address
== -1) {
1640 dom
->next_address
= 0;
1641 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1643 dom
->need_flush
= true;
1646 if (unlikely(address
== -1))
1647 address
= DMA_ERROR_CODE
;
1649 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
1655 * The address free function.
1657 * called with domain->lock held
1659 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
1660 unsigned long address
,
1663 unsigned i
= address
>> APERTURE_RANGE_SHIFT
;
1664 struct aperture_range
*range
= dom
->aperture
[i
];
1666 BUG_ON(i
>= APERTURE_MAX_RANGES
|| range
== NULL
);
1668 #ifdef CONFIG_IOMMU_STRESS
1673 if (address
>= dom
->next_address
)
1674 dom
->need_flush
= true;
1676 address
= (address
% APERTURE_RANGE_SIZE
) >> PAGE_SHIFT
;
1678 bitmap_clear(range
->bitmap
, address
, pages
);
1682 /****************************************************************************
1684 * The next functions belong to the domain allocation. A domain is
1685 * allocated for every IOMMU as the default domain. If device isolation
1686 * is enabled, every device get its own domain. The most important thing
1687 * about domains is the page table mapping the DMA address space they
1690 ****************************************************************************/
1693 * This function adds a protection domain to the global protection domain list
1695 static void add_domain_to_list(struct protection_domain
*domain
)
1697 unsigned long flags
;
1699 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1700 list_add(&domain
->list
, &amd_iommu_pd_list
);
1701 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1705 * This function removes a protection domain to the global
1706 * protection domain list
1708 static void del_domain_from_list(struct protection_domain
*domain
)
1710 unsigned long flags
;
1712 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1713 list_del(&domain
->list
);
1714 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1717 static u16
domain_id_alloc(void)
1719 unsigned long flags
;
1722 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1723 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
1725 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1726 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
1729 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1734 static void domain_id_free(int id
)
1736 unsigned long flags
;
1738 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1739 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1740 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
1741 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1744 #define DEFINE_FREE_PT_FN(LVL, FN) \
1745 static void free_pt_##LVL (unsigned long __pt) \
1753 for (i = 0; i < 512; ++i) { \
1754 /* PTE present? */ \
1755 if (!IOMMU_PTE_PRESENT(pt[i])) \
1759 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1760 PM_PTE_LEVEL(pt[i]) == 7) \
1763 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1766 free_page((unsigned long)pt); \
1769 DEFINE_FREE_PT_FN(l2
, free_page
)
1770 DEFINE_FREE_PT_FN(l3
, free_pt_l2
)
1771 DEFINE_FREE_PT_FN(l4
, free_pt_l3
)
1772 DEFINE_FREE_PT_FN(l5
, free_pt_l4
)
1773 DEFINE_FREE_PT_FN(l6
, free_pt_l5
)
1775 static void free_pagetable(struct protection_domain
*domain
)
1777 unsigned long root
= (unsigned long)domain
->pt_root
;
1779 switch (domain
->mode
) {
1780 case PAGE_MODE_NONE
:
1782 case PAGE_MODE_1_LEVEL
:
1785 case PAGE_MODE_2_LEVEL
:
1788 case PAGE_MODE_3_LEVEL
:
1791 case PAGE_MODE_4_LEVEL
:
1794 case PAGE_MODE_5_LEVEL
:
1797 case PAGE_MODE_6_LEVEL
:
1805 static void free_gcr3_tbl_level1(u64
*tbl
)
1810 for (i
= 0; i
< 512; ++i
) {
1811 if (!(tbl
[i
] & GCR3_VALID
))
1814 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1816 free_page((unsigned long)ptr
);
1820 static void free_gcr3_tbl_level2(u64
*tbl
)
1825 for (i
= 0; i
< 512; ++i
) {
1826 if (!(tbl
[i
] & GCR3_VALID
))
1829 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1831 free_gcr3_tbl_level1(ptr
);
1835 static void free_gcr3_table(struct protection_domain
*domain
)
1837 if (domain
->glx
== 2)
1838 free_gcr3_tbl_level2(domain
->gcr3_tbl
);
1839 else if (domain
->glx
== 1)
1840 free_gcr3_tbl_level1(domain
->gcr3_tbl
);
1841 else if (domain
->glx
!= 0)
1844 free_page((unsigned long)domain
->gcr3_tbl
);
1848 * Free a domain, only used if something went wrong in the
1849 * allocation path and we need to free an already allocated page table
1851 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
1858 del_domain_from_list(&dom
->domain
);
1860 free_pagetable(&dom
->domain
);
1862 for (i
= 0; i
< APERTURE_MAX_RANGES
; ++i
) {
1863 if (!dom
->aperture
[i
])
1865 free_page((unsigned long)dom
->aperture
[i
]->bitmap
);
1866 kfree(dom
->aperture
[i
]);
1873 * Allocates a new protection domain usable for the dma_ops functions.
1874 * It also initializes the page table and the address allocator data
1875 * structures required for the dma_ops interface
1877 static struct dma_ops_domain
*dma_ops_domain_alloc(void)
1879 struct dma_ops_domain
*dma_dom
;
1881 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
1885 if (protection_domain_init(&dma_dom
->domain
))
1888 dma_dom
->domain
.mode
= PAGE_MODE_2_LEVEL
;
1889 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
1890 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
1891 dma_dom
->domain
.priv
= dma_dom
;
1892 if (!dma_dom
->domain
.pt_root
)
1895 dma_dom
->need_flush
= false;
1897 add_domain_to_list(&dma_dom
->domain
);
1899 if (alloc_new_range(dma_dom
, true, GFP_KERNEL
))
1903 * mark the first page as allocated so we never return 0 as
1904 * a valid dma-address. So we can use 0 as error value
1906 dma_dom
->aperture
[0]->bitmap
[0] = 1;
1907 dma_dom
->next_address
= 0;
1913 dma_ops_domain_free(dma_dom
);
1919 * little helper function to check whether a given protection domain is a
1922 static bool dma_ops_domain(struct protection_domain
*domain
)
1924 return domain
->flags
& PD_DMA_OPS_MASK
;
1927 static void set_dte_entry(u16 devid
, struct protection_domain
*domain
, bool ats
)
1932 if (domain
->mode
!= PAGE_MODE_NONE
)
1933 pte_root
= virt_to_phys(domain
->pt_root
);
1935 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
1936 << DEV_ENTRY_MODE_SHIFT
;
1937 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
1939 flags
= amd_iommu_dev_table
[devid
].data
[1];
1942 flags
|= DTE_FLAG_IOTLB
;
1944 if (domain
->flags
& PD_IOMMUV2_MASK
) {
1945 u64 gcr3
= __pa(domain
->gcr3_tbl
);
1946 u64 glx
= domain
->glx
;
1949 pte_root
|= DTE_FLAG_GV
;
1950 pte_root
|= (glx
& DTE_GLX_MASK
) << DTE_GLX_SHIFT
;
1952 /* First mask out possible old values for GCR3 table */
1953 tmp
= DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B
;
1956 tmp
= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C
;
1959 /* Encode GCR3 table into DTE */
1960 tmp
= DTE_GCR3_VAL_A(gcr3
) << DTE_GCR3_SHIFT_A
;
1963 tmp
= DTE_GCR3_VAL_B(gcr3
) << DTE_GCR3_SHIFT_B
;
1966 tmp
= DTE_GCR3_VAL_C(gcr3
) << DTE_GCR3_SHIFT_C
;
1970 flags
&= ~(0xffffUL
);
1971 flags
|= domain
->id
;
1973 amd_iommu_dev_table
[devid
].data
[1] = flags
;
1974 amd_iommu_dev_table
[devid
].data
[0] = pte_root
;
1977 static void clear_dte_entry(u16 devid
)
1979 /* remove entry from the device table seen by the hardware */
1980 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
1981 amd_iommu_dev_table
[devid
].data
[1] = 0;
1983 amd_iommu_apply_erratum_63(devid
);
1986 static void do_attach(struct iommu_dev_data
*dev_data
,
1987 struct protection_domain
*domain
)
1989 struct amd_iommu
*iommu
;
1992 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1993 ats
= dev_data
->ats
.enabled
;
1995 /* Update data structures */
1996 dev_data
->domain
= domain
;
1997 list_add(&dev_data
->list
, &domain
->dev_list
);
1998 set_dte_entry(dev_data
->devid
, domain
, ats
);
2000 /* Do reference counting */
2001 domain
->dev_iommu
[iommu
->index
] += 1;
2002 domain
->dev_cnt
+= 1;
2004 /* Flush the DTE entry */
2005 device_flush_dte(dev_data
);
2008 static void do_detach(struct iommu_dev_data
*dev_data
)
2010 struct amd_iommu
*iommu
;
2012 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
2014 /* decrease reference counters */
2015 dev_data
->domain
->dev_iommu
[iommu
->index
] -= 1;
2016 dev_data
->domain
->dev_cnt
-= 1;
2018 /* Update data structures */
2019 dev_data
->domain
= NULL
;
2020 list_del(&dev_data
->list
);
2021 clear_dte_entry(dev_data
->devid
);
2023 /* Flush the DTE entry */
2024 device_flush_dte(dev_data
);
2028 * If a device is not yet associated with a domain, this function does
2029 * assigns it visible for the hardware
2031 static int __attach_device(struct iommu_dev_data
*dev_data
,
2032 struct protection_domain
*domain
)
2034 struct iommu_dev_data
*head
, *entry
;
2038 spin_lock(&domain
->lock
);
2042 if (head
->alias_data
!= NULL
)
2043 head
= head
->alias_data
;
2045 /* Now we have the root of the alias group, if any */
2048 if (head
->domain
!= NULL
)
2051 /* Attach alias group root */
2052 do_attach(head
, domain
);
2054 /* Attach other devices in the alias group */
2055 list_for_each_entry(entry
, &head
->alias_list
, alias_list
)
2056 do_attach(entry
, domain
);
2063 spin_unlock(&domain
->lock
);
2069 static void pdev_iommuv2_disable(struct pci_dev
*pdev
)
2071 pci_disable_ats(pdev
);
2072 pci_disable_pri(pdev
);
2073 pci_disable_pasid(pdev
);
2076 /* FIXME: Change generic reset-function to do the same */
2077 static int pri_reset_while_enabled(struct pci_dev
*pdev
)
2082 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2086 pci_read_config_word(pdev
, pos
+ PCI_PRI_CTRL
, &control
);
2087 control
|= PCI_PRI_CTRL_RESET
;
2088 pci_write_config_word(pdev
, pos
+ PCI_PRI_CTRL
, control
);
2093 static int pdev_iommuv2_enable(struct pci_dev
*pdev
)
2098 /* FIXME: Hardcode number of outstanding requests for now */
2100 if (pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE
))
2102 reset_enable
= pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_ENABLE_RESET
);
2104 /* Only allow access to user-accessible pages */
2105 ret
= pci_enable_pasid(pdev
, 0);
2109 /* First reset the PRI state of the device */
2110 ret
= pci_reset_pri(pdev
);
2115 ret
= pci_enable_pri(pdev
, reqs
);
2120 ret
= pri_reset_while_enabled(pdev
);
2125 ret
= pci_enable_ats(pdev
, PAGE_SHIFT
);
2132 pci_disable_pri(pdev
);
2133 pci_disable_pasid(pdev
);
2138 /* FIXME: Move this to PCI code */
2139 #define PCI_PRI_TLP_OFF (1 << 15)
2141 static bool pci_pri_tlp_required(struct pci_dev
*pdev
)
2146 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2150 pci_read_config_word(pdev
, pos
+ PCI_PRI_STATUS
, &status
);
2152 return (status
& PCI_PRI_TLP_OFF
) ? true : false;
2156 * If a device is not yet associated with a domain, this function
2157 * assigns it visible for the hardware
2159 static int attach_device(struct device
*dev
,
2160 struct protection_domain
*domain
)
2162 struct pci_dev
*pdev
= to_pci_dev(dev
);
2163 struct iommu_dev_data
*dev_data
;
2164 unsigned long flags
;
2167 dev_data
= get_dev_data(dev
);
2169 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2170 if (!dev_data
->iommu_v2
|| !dev_data
->passthrough
)
2173 if (pdev_iommuv2_enable(pdev
) != 0)
2176 dev_data
->ats
.enabled
= true;
2177 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2178 dev_data
->pri_tlp
= pci_pri_tlp_required(pdev
);
2179 } else if (amd_iommu_iotlb_sup
&&
2180 pci_enable_ats(pdev
, PAGE_SHIFT
) == 0) {
2181 dev_data
->ats
.enabled
= true;
2182 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2185 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2186 ret
= __attach_device(dev_data
, domain
);
2187 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2190 * We might boot into a crash-kernel here. The crashed kernel
2191 * left the caches in the IOMMU dirty. So we have to flush
2192 * here to evict all dirty stuff.
2194 domain_flush_tlb_pde(domain
);
2200 * Removes a device from a protection domain (unlocked)
2202 static void __detach_device(struct iommu_dev_data
*dev_data
)
2204 struct iommu_dev_data
*head
, *entry
;
2205 struct protection_domain
*domain
;
2206 unsigned long flags
;
2208 BUG_ON(!dev_data
->domain
);
2210 domain
= dev_data
->domain
;
2212 spin_lock_irqsave(&domain
->lock
, flags
);
2215 if (head
->alias_data
!= NULL
)
2216 head
= head
->alias_data
;
2218 list_for_each_entry(entry
, &head
->alias_list
, alias_list
)
2223 spin_unlock_irqrestore(&domain
->lock
, flags
);
2226 * If we run in passthrough mode the device must be assigned to the
2227 * passthrough domain if it is detached from any other domain.
2228 * Make sure we can deassign from the pt_domain itself.
2230 if (dev_data
->passthrough
&&
2231 (dev_data
->domain
== NULL
&& domain
!= pt_domain
))
2232 __attach_device(dev_data
, pt_domain
);
2236 * Removes a device from a protection domain (with devtable_lock held)
2238 static void detach_device(struct device
*dev
)
2240 struct protection_domain
*domain
;
2241 struct iommu_dev_data
*dev_data
;
2242 unsigned long flags
;
2244 dev_data
= get_dev_data(dev
);
2245 domain
= dev_data
->domain
;
2247 /* lock device table */
2248 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2249 __detach_device(dev_data
);
2250 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2252 if (domain
->flags
& PD_IOMMUV2_MASK
)
2253 pdev_iommuv2_disable(to_pci_dev(dev
));
2254 else if (dev_data
->ats
.enabled
)
2255 pci_disable_ats(to_pci_dev(dev
));
2257 dev_data
->ats
.enabled
= false;
2260 static int amd_iommu_add_device(struct device
*dev
)
2262 struct iommu_dev_data
*dev_data
;
2263 struct iommu_domain
*domain
;
2264 struct amd_iommu
*iommu
;
2268 if (!check_device(dev
) || get_dev_data(dev
))
2271 devid
= get_device_id(dev
);
2272 iommu
= amd_iommu_rlookup_table
[devid
];
2274 ret
= iommu_init_device(dev
);
2276 if (ret
!= -ENOTSUPP
)
2277 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2280 iommu_ignore_device(dev
);
2281 dev
->archdata
.dma_ops
= &nommu_dma_ops
;
2284 init_iommu_group(dev
);
2286 dev_data
= get_dev_data(dev
);
2290 if (dev_data
->iommu_v2
)
2291 iommu_request_dm_for_dev(dev
);
2293 /* Domains are initialized for this device - have a look what we ended up with */
2294 domain
= iommu_get_domain_for_dev(dev
);
2295 if (domain
->type
== IOMMU_DOMAIN_IDENTITY
) {
2296 dev_data
->passthrough
= true;
2297 dev
->archdata
.dma_ops
= &nommu_dma_ops
;
2299 dev
->archdata
.dma_ops
= &amd_iommu_dma_ops
;
2303 iommu_completion_wait(iommu
);
2308 static void amd_iommu_remove_device(struct device
*dev
)
2310 struct amd_iommu
*iommu
;
2313 if (!check_device(dev
))
2316 devid
= get_device_id(dev
);
2317 iommu
= amd_iommu_rlookup_table
[devid
];
2319 iommu_uninit_device(dev
);
2320 iommu_completion_wait(iommu
);
2323 /*****************************************************************************
2325 * The next functions belong to the dma_ops mapping/unmapping code.
2327 *****************************************************************************/
2330 * In the dma_ops path we only have the struct device. This function
2331 * finds the corresponding IOMMU, the protection domain and the
2332 * requestor id for a given device.
2333 * If the device is not yet associated with a domain this is also done
2336 static struct protection_domain
*get_domain(struct device
*dev
)
2338 struct protection_domain
*domain
;
2339 struct iommu_domain
*io_domain
;
2341 if (!check_device(dev
))
2342 return ERR_PTR(-EINVAL
);
2344 io_domain
= iommu_get_domain_for_dev(dev
);
2348 domain
= to_pdomain(io_domain
);
2349 if (!dma_ops_domain(domain
))
2350 return ERR_PTR(-EBUSY
);
2355 static void update_device_table(struct protection_domain
*domain
)
2357 struct iommu_dev_data
*dev_data
;
2359 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
2360 set_dte_entry(dev_data
->devid
, domain
, dev_data
->ats
.enabled
);
2363 static void update_domain(struct protection_domain
*domain
)
2365 if (!domain
->updated
)
2368 update_device_table(domain
);
2370 domain_flush_devices(domain
);
2371 domain_flush_tlb_pde(domain
);
2373 domain
->updated
= false;
2377 * This function fetches the PTE for a given address in the aperture
2379 static u64
* dma_ops_get_pte(struct dma_ops_domain
*dom
,
2380 unsigned long address
)
2382 struct aperture_range
*aperture
;
2383 u64
*pte
, *pte_page
;
2385 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
2389 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
2391 pte
= alloc_pte(&dom
->domain
, address
, PAGE_SIZE
, &pte_page
,
2393 aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)] = pte_page
;
2395 pte
+= PM_LEVEL_INDEX(0, address
);
2397 update_domain(&dom
->domain
);
2403 * This is the generic map function. It maps one 4kb page at paddr to
2404 * the given address in the DMA address space for the domain.
2406 static dma_addr_t
dma_ops_domain_map(struct dma_ops_domain
*dom
,
2407 unsigned long address
,
2413 WARN_ON(address
> dom
->aperture_size
);
2417 pte
= dma_ops_get_pte(dom
, address
);
2419 return DMA_ERROR_CODE
;
2421 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
2423 if (direction
== DMA_TO_DEVICE
)
2424 __pte
|= IOMMU_PTE_IR
;
2425 else if (direction
== DMA_FROM_DEVICE
)
2426 __pte
|= IOMMU_PTE_IW
;
2427 else if (direction
== DMA_BIDIRECTIONAL
)
2428 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
2434 return (dma_addr_t
)address
;
2438 * The generic unmapping function for on page in the DMA address space.
2440 static void dma_ops_domain_unmap(struct dma_ops_domain
*dom
,
2441 unsigned long address
)
2443 struct aperture_range
*aperture
;
2446 if (address
>= dom
->aperture_size
)
2449 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
2453 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
2457 pte
+= PM_LEVEL_INDEX(0, address
);
2465 * This function contains common code for mapping of a physically
2466 * contiguous memory region into DMA address space. It is used by all
2467 * mapping functions provided with this IOMMU driver.
2468 * Must be called with the domain lock held.
2470 static dma_addr_t
__map_single(struct device
*dev
,
2471 struct dma_ops_domain
*dma_dom
,
2478 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
2479 dma_addr_t address
, start
, ret
;
2481 unsigned long align_mask
= 0;
2484 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
2487 INC_STATS_COUNTER(total_map_requests
);
2490 INC_STATS_COUNTER(cross_page
);
2493 align_mask
= (1UL << get_order(size
)) - 1;
2496 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
, align_mask
,
2498 if (unlikely(address
== DMA_ERROR_CODE
)) {
2500 * setting next_address here will let the address
2501 * allocator only scan the new allocated range in the
2502 * first run. This is a small optimization.
2504 dma_dom
->next_address
= dma_dom
->aperture_size
;
2506 if (alloc_new_range(dma_dom
, false, GFP_ATOMIC
))
2510 * aperture was successfully enlarged by 128 MB, try
2517 for (i
= 0; i
< pages
; ++i
) {
2518 ret
= dma_ops_domain_map(dma_dom
, start
, paddr
, dir
);
2519 if (ret
== DMA_ERROR_CODE
)
2527 ADD_STATS_COUNTER(alloced_io_mem
, size
);
2529 if (unlikely(dma_dom
->need_flush
&& !amd_iommu_unmap_flush
)) {
2530 domain_flush_tlb(&dma_dom
->domain
);
2531 dma_dom
->need_flush
= false;
2532 } else if (unlikely(amd_iommu_np_cache
))
2533 domain_flush_pages(&dma_dom
->domain
, address
, size
);
2540 for (--i
; i
>= 0; --i
) {
2542 dma_ops_domain_unmap(dma_dom
, start
);
2545 dma_ops_free_addresses(dma_dom
, address
, pages
);
2547 return DMA_ERROR_CODE
;
2551 * Does the reverse of the __map_single function. Must be called with
2552 * the domain lock held too
2554 static void __unmap_single(struct dma_ops_domain
*dma_dom
,
2555 dma_addr_t dma_addr
,
2559 dma_addr_t flush_addr
;
2560 dma_addr_t i
, start
;
2563 if ((dma_addr
== DMA_ERROR_CODE
) ||
2564 (dma_addr
+ size
> dma_dom
->aperture_size
))
2567 flush_addr
= dma_addr
;
2568 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
2569 dma_addr
&= PAGE_MASK
;
2572 for (i
= 0; i
< pages
; ++i
) {
2573 dma_ops_domain_unmap(dma_dom
, start
);
2577 SUB_STATS_COUNTER(alloced_io_mem
, size
);
2579 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
2581 if (amd_iommu_unmap_flush
|| dma_dom
->need_flush
) {
2582 domain_flush_pages(&dma_dom
->domain
, flush_addr
, size
);
2583 dma_dom
->need_flush
= false;
2588 * The exported map_single function for dma_ops.
2590 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
2591 unsigned long offset
, size_t size
,
2592 enum dma_data_direction dir
,
2593 struct dma_attrs
*attrs
)
2595 unsigned long flags
;
2596 struct protection_domain
*domain
;
2599 phys_addr_t paddr
= page_to_phys(page
) + offset
;
2601 INC_STATS_COUNTER(cnt_map_single
);
2603 domain
= get_domain(dev
);
2604 if (PTR_ERR(domain
) == -EINVAL
)
2605 return (dma_addr_t
)paddr
;
2606 else if (IS_ERR(domain
))
2607 return DMA_ERROR_CODE
;
2609 dma_mask
= *dev
->dma_mask
;
2611 spin_lock_irqsave(&domain
->lock
, flags
);
2613 addr
= __map_single(dev
, domain
->priv
, paddr
, size
, dir
, false,
2615 if (addr
== DMA_ERROR_CODE
)
2618 domain_flush_complete(domain
);
2621 spin_unlock_irqrestore(&domain
->lock
, flags
);
2627 * The exported unmap_single function for dma_ops.
2629 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
2630 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
2632 unsigned long flags
;
2633 struct protection_domain
*domain
;
2635 INC_STATS_COUNTER(cnt_unmap_single
);
2637 domain
= get_domain(dev
);
2641 spin_lock_irqsave(&domain
->lock
, flags
);
2643 __unmap_single(domain
->priv
, dma_addr
, size
, dir
);
2645 domain_flush_complete(domain
);
2647 spin_unlock_irqrestore(&domain
->lock
, flags
);
2651 * The exported map_sg function for dma_ops (handles scatter-gather
2654 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
2655 int nelems
, enum dma_data_direction dir
,
2656 struct dma_attrs
*attrs
)
2658 unsigned long flags
;
2659 struct protection_domain
*domain
;
2661 struct scatterlist
*s
;
2663 int mapped_elems
= 0;
2666 INC_STATS_COUNTER(cnt_map_sg
);
2668 domain
= get_domain(dev
);
2672 dma_mask
= *dev
->dma_mask
;
2674 spin_lock_irqsave(&domain
->lock
, flags
);
2676 for_each_sg(sglist
, s
, nelems
, i
) {
2679 s
->dma_address
= __map_single(dev
, domain
->priv
,
2680 paddr
, s
->length
, dir
, false,
2683 if (s
->dma_address
) {
2684 s
->dma_length
= s
->length
;
2690 domain_flush_complete(domain
);
2693 spin_unlock_irqrestore(&domain
->lock
, flags
);
2695 return mapped_elems
;
2697 for_each_sg(sglist
, s
, mapped_elems
, i
) {
2699 __unmap_single(domain
->priv
, s
->dma_address
,
2700 s
->dma_length
, dir
);
2701 s
->dma_address
= s
->dma_length
= 0;
2710 * The exported map_sg function for dma_ops (handles scatter-gather
2713 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
2714 int nelems
, enum dma_data_direction dir
,
2715 struct dma_attrs
*attrs
)
2717 unsigned long flags
;
2718 struct protection_domain
*domain
;
2719 struct scatterlist
*s
;
2722 INC_STATS_COUNTER(cnt_unmap_sg
);
2724 domain
= get_domain(dev
);
2728 spin_lock_irqsave(&domain
->lock
, flags
);
2730 for_each_sg(sglist
, s
, nelems
, i
) {
2731 __unmap_single(domain
->priv
, s
->dma_address
,
2732 s
->dma_length
, dir
);
2733 s
->dma_address
= s
->dma_length
= 0;
2736 domain_flush_complete(domain
);
2738 spin_unlock_irqrestore(&domain
->lock
, flags
);
2742 * The exported alloc_coherent function for dma_ops.
2744 static void *alloc_coherent(struct device
*dev
, size_t size
,
2745 dma_addr_t
*dma_addr
, gfp_t flag
,
2746 struct dma_attrs
*attrs
)
2748 u64 dma_mask
= dev
->coherent_dma_mask
;
2749 struct protection_domain
*domain
;
2750 unsigned long flags
;
2753 INC_STATS_COUNTER(cnt_alloc_coherent
);
2755 domain
= get_domain(dev
);
2756 if (PTR_ERR(domain
) == -EINVAL
) {
2757 page
= alloc_pages(flag
, get_order(size
));
2758 *dma_addr
= page_to_phys(page
);
2759 return page_address(page
);
2760 } else if (IS_ERR(domain
))
2763 size
= PAGE_ALIGN(size
);
2764 dma_mask
= dev
->coherent_dma_mask
;
2765 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
2768 page
= alloc_pages(flag
| __GFP_NOWARN
, get_order(size
));
2770 if (!(flag
& __GFP_WAIT
))
2773 page
= dma_alloc_from_contiguous(dev
, size
>> PAGE_SHIFT
,
2780 dma_mask
= *dev
->dma_mask
;
2782 spin_lock_irqsave(&domain
->lock
, flags
);
2784 *dma_addr
= __map_single(dev
, domain
->priv
, page_to_phys(page
),
2785 size
, DMA_BIDIRECTIONAL
, true, dma_mask
);
2787 if (*dma_addr
== DMA_ERROR_CODE
) {
2788 spin_unlock_irqrestore(&domain
->lock
, flags
);
2792 domain_flush_complete(domain
);
2794 spin_unlock_irqrestore(&domain
->lock
, flags
);
2796 return page_address(page
);
2800 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2801 __free_pages(page
, get_order(size
));
2807 * The exported free_coherent function for dma_ops.
2809 static void free_coherent(struct device
*dev
, size_t size
,
2810 void *virt_addr
, dma_addr_t dma_addr
,
2811 struct dma_attrs
*attrs
)
2813 struct protection_domain
*domain
;
2814 unsigned long flags
;
2817 INC_STATS_COUNTER(cnt_free_coherent
);
2819 page
= virt_to_page(virt_addr
);
2820 size
= PAGE_ALIGN(size
);
2822 domain
= get_domain(dev
);
2826 spin_lock_irqsave(&domain
->lock
, flags
);
2828 __unmap_single(domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
2830 domain_flush_complete(domain
);
2832 spin_unlock_irqrestore(&domain
->lock
, flags
);
2835 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2836 __free_pages(page
, get_order(size
));
2840 * This function is called by the DMA layer to find out if we can handle a
2841 * particular device. It is part of the dma_ops.
2843 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
2845 return check_device(dev
);
2848 static struct dma_map_ops amd_iommu_dma_ops
= {
2849 .alloc
= alloc_coherent
,
2850 .free
= free_coherent
,
2851 .map_page
= map_page
,
2852 .unmap_page
= unmap_page
,
2854 .unmap_sg
= unmap_sg
,
2855 .dma_supported
= amd_iommu_dma_supported
,
2858 int __init
amd_iommu_init_api(void)
2860 return bus_set_iommu(&pci_bus_type
, &amd_iommu_ops
);
2863 int __init
amd_iommu_init_dma_ops(void)
2868 amd_iommu_stats_init();
2870 if (amd_iommu_unmap_flush
)
2871 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2873 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2878 /*****************************************************************************
2880 * The following functions belong to the exported interface of AMD IOMMU
2882 * This interface allows access to lower level functions of the IOMMU
2883 * like protection domain handling and assignement of devices to domains
2884 * which is not possible with the dma_ops interface.
2886 *****************************************************************************/
2888 static void cleanup_domain(struct protection_domain
*domain
)
2890 struct iommu_dev_data
*entry
;
2891 unsigned long flags
;
2893 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2895 while (!list_empty(&domain
->dev_list
)) {
2896 entry
= list_first_entry(&domain
->dev_list
,
2897 struct iommu_dev_data
, list
);
2898 __detach_device(entry
);
2901 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2904 static void protection_domain_free(struct protection_domain
*domain
)
2909 del_domain_from_list(domain
);
2912 domain_id_free(domain
->id
);
2917 static int protection_domain_init(struct protection_domain
*domain
)
2919 spin_lock_init(&domain
->lock
);
2920 mutex_init(&domain
->api_lock
);
2921 domain
->id
= domain_id_alloc();
2924 INIT_LIST_HEAD(&domain
->dev_list
);
2929 static struct protection_domain
*protection_domain_alloc(void)
2931 struct protection_domain
*domain
;
2933 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
2937 if (protection_domain_init(domain
))
2940 add_domain_to_list(domain
);
2950 static int alloc_passthrough_domain(void)
2952 if (pt_domain
!= NULL
)
2955 /* allocate passthrough domain */
2956 pt_domain
= protection_domain_alloc();
2960 pt_domain
->mode
= PAGE_MODE_NONE
;
2965 static struct iommu_domain
*amd_iommu_domain_alloc(unsigned type
)
2967 struct protection_domain
*pdomain
;
2968 struct dma_ops_domain
*dma_domain
;
2971 case IOMMU_DOMAIN_UNMANAGED
:
2972 pdomain
= protection_domain_alloc();
2976 pdomain
->mode
= PAGE_MODE_3_LEVEL
;
2977 pdomain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
2978 if (!pdomain
->pt_root
) {
2979 protection_domain_free(pdomain
);
2983 pdomain
->domain
.geometry
.aperture_start
= 0;
2984 pdomain
->domain
.geometry
.aperture_end
= ~0ULL;
2985 pdomain
->domain
.geometry
.force_aperture
= true;
2988 case IOMMU_DOMAIN_DMA
:
2989 dma_domain
= dma_ops_domain_alloc();
2991 pr_err("AMD-Vi: Failed to allocate\n");
2994 pdomain
= &dma_domain
->domain
;
2996 case IOMMU_DOMAIN_IDENTITY
:
2997 pdomain
= protection_domain_alloc();
3001 pdomain
->mode
= PAGE_MODE_NONE
;
3007 return &pdomain
->domain
;
3010 static void amd_iommu_domain_free(struct iommu_domain
*dom
)
3012 struct protection_domain
*domain
;
3017 domain
= to_pdomain(dom
);
3019 if (domain
->dev_cnt
> 0)
3020 cleanup_domain(domain
);
3022 BUG_ON(domain
->dev_cnt
!= 0);
3024 if (domain
->mode
!= PAGE_MODE_NONE
)
3025 free_pagetable(domain
);
3027 if (domain
->flags
& PD_IOMMUV2_MASK
)
3028 free_gcr3_table(domain
);
3030 protection_domain_free(domain
);
3033 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
3036 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
3037 struct amd_iommu
*iommu
;
3040 if (!check_device(dev
))
3043 devid
= get_device_id(dev
);
3045 if (dev_data
->domain
!= NULL
)
3048 iommu
= amd_iommu_rlookup_table
[devid
];
3052 iommu_completion_wait(iommu
);
3055 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
3058 struct protection_domain
*domain
= to_pdomain(dom
);
3059 struct iommu_dev_data
*dev_data
;
3060 struct amd_iommu
*iommu
;
3063 if (!check_device(dev
))
3066 dev_data
= dev
->archdata
.iommu
;
3068 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3072 if (dev_data
->domain
)
3075 ret
= attach_device(dev
, domain
);
3077 iommu_completion_wait(iommu
);
3082 static int amd_iommu_map(struct iommu_domain
*dom
, unsigned long iova
,
3083 phys_addr_t paddr
, size_t page_size
, int iommu_prot
)
3085 struct protection_domain
*domain
= to_pdomain(dom
);
3089 if (domain
->mode
== PAGE_MODE_NONE
)
3092 if (iommu_prot
& IOMMU_READ
)
3093 prot
|= IOMMU_PROT_IR
;
3094 if (iommu_prot
& IOMMU_WRITE
)
3095 prot
|= IOMMU_PROT_IW
;
3097 mutex_lock(&domain
->api_lock
);
3098 ret
= iommu_map_page(domain
, iova
, paddr
, prot
, page_size
);
3099 mutex_unlock(&domain
->api_lock
);
3104 static size_t amd_iommu_unmap(struct iommu_domain
*dom
, unsigned long iova
,
3107 struct protection_domain
*domain
= to_pdomain(dom
);
3110 if (domain
->mode
== PAGE_MODE_NONE
)
3113 mutex_lock(&domain
->api_lock
);
3114 unmap_size
= iommu_unmap_page(domain
, iova
, page_size
);
3115 mutex_unlock(&domain
->api_lock
);
3117 domain_flush_tlb_pde(domain
);
3122 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
3125 struct protection_domain
*domain
= to_pdomain(dom
);
3126 unsigned long offset_mask
, pte_pgsize
;
3129 if (domain
->mode
== PAGE_MODE_NONE
)
3132 pte
= fetch_pte(domain
, iova
, &pte_pgsize
);
3134 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
3137 offset_mask
= pte_pgsize
- 1;
3138 __pte
= *pte
& PM_ADDR_MASK
;
3140 return (__pte
& ~offset_mask
) | (iova
& offset_mask
);
3143 static bool amd_iommu_capable(enum iommu_cap cap
)
3146 case IOMMU_CAP_CACHE_COHERENCY
:
3148 case IOMMU_CAP_INTR_REMAP
:
3149 return (irq_remapping_enabled
== 1);
3150 case IOMMU_CAP_NOEXEC
:
3157 static void amd_iommu_get_dm_regions(struct device
*dev
,
3158 struct list_head
*head
)
3160 struct unity_map_entry
*entry
;
3163 devid
= get_device_id(dev
);
3165 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
3166 struct iommu_dm_region
*region
;
3168 if (devid
< entry
->devid_start
|| devid
> entry
->devid_end
)
3171 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
3173 pr_err("Out of memory allocating dm-regions for %s\n",
3178 region
->start
= entry
->address_start
;
3179 region
->length
= entry
->address_end
- entry
->address_start
;
3180 if (entry
->prot
& IOMMU_PROT_IR
)
3181 region
->prot
|= IOMMU_READ
;
3182 if (entry
->prot
& IOMMU_PROT_IW
)
3183 region
->prot
|= IOMMU_WRITE
;
3185 list_add_tail(®ion
->list
, head
);
3189 static void amd_iommu_put_dm_regions(struct device
*dev
,
3190 struct list_head
*head
)
3192 struct iommu_dm_region
*entry
, *next
;
3194 list_for_each_entry_safe(entry
, next
, head
, list
)
3198 static const struct iommu_ops amd_iommu_ops
= {
3199 .capable
= amd_iommu_capable
,
3200 .domain_alloc
= amd_iommu_domain_alloc
,
3201 .domain_free
= amd_iommu_domain_free
,
3202 .attach_dev
= amd_iommu_attach_device
,
3203 .detach_dev
= amd_iommu_detach_device
,
3204 .map
= amd_iommu_map
,
3205 .unmap
= amd_iommu_unmap
,
3206 .map_sg
= default_iommu_map_sg
,
3207 .iova_to_phys
= amd_iommu_iova_to_phys
,
3208 .add_device
= amd_iommu_add_device
,
3209 .remove_device
= amd_iommu_remove_device
,
3210 .get_dm_regions
= amd_iommu_get_dm_regions
,
3211 .put_dm_regions
= amd_iommu_put_dm_regions
,
3212 .pgsize_bitmap
= AMD_IOMMU_PGSIZES
,
3215 /*****************************************************************************
3217 * The next functions do a basic initialization of IOMMU for pass through
3220 * In passthrough mode the IOMMU is initialized and enabled but not used for
3221 * DMA-API translation.
3223 *****************************************************************************/
3225 int __init
amd_iommu_init_passthrough(void)
3227 struct iommu_dev_data
*dev_data
;
3228 struct pci_dev
*dev
= NULL
;
3231 ret
= alloc_passthrough_domain();
3235 for_each_pci_dev(dev
) {
3236 if (!check_device(&dev
->dev
))
3239 dev_data
= get_dev_data(&dev
->dev
);
3240 dev_data
->passthrough
= true;
3242 attach_device(&dev
->dev
, pt_domain
);
3245 amd_iommu_stats_init();
3247 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3252 /* IOMMUv2 specific functions */
3253 int amd_iommu_register_ppr_notifier(struct notifier_block
*nb
)
3255 return atomic_notifier_chain_register(&ppr_notifier
, nb
);
3257 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier
);
3259 int amd_iommu_unregister_ppr_notifier(struct notifier_block
*nb
)
3261 return atomic_notifier_chain_unregister(&ppr_notifier
, nb
);
3263 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier
);
3265 void amd_iommu_domain_direct_map(struct iommu_domain
*dom
)
3267 struct protection_domain
*domain
= to_pdomain(dom
);
3268 unsigned long flags
;
3270 spin_lock_irqsave(&domain
->lock
, flags
);
3272 /* Update data structure */
3273 domain
->mode
= PAGE_MODE_NONE
;
3274 domain
->updated
= true;
3276 /* Make changes visible to IOMMUs */
3277 update_domain(domain
);
3279 /* Page-table is not visible to IOMMU anymore, so free it */
3280 free_pagetable(domain
);
3282 spin_unlock_irqrestore(&domain
->lock
, flags
);
3284 EXPORT_SYMBOL(amd_iommu_domain_direct_map
);
3286 int amd_iommu_domain_enable_v2(struct iommu_domain
*dom
, int pasids
)
3288 struct protection_domain
*domain
= to_pdomain(dom
);
3289 unsigned long flags
;
3292 if (pasids
<= 0 || pasids
> (PASID_MASK
+ 1))
3295 /* Number of GCR3 table levels required */
3296 for (levels
= 0; (pasids
- 1) & ~0x1ff; pasids
>>= 9)
3299 if (levels
> amd_iommu_max_glx_val
)
3302 spin_lock_irqsave(&domain
->lock
, flags
);
3305 * Save us all sanity checks whether devices already in the
3306 * domain support IOMMUv2. Just force that the domain has no
3307 * devices attached when it is switched into IOMMUv2 mode.
3310 if (domain
->dev_cnt
> 0 || domain
->flags
& PD_IOMMUV2_MASK
)
3314 domain
->gcr3_tbl
= (void *)get_zeroed_page(GFP_ATOMIC
);
3315 if (domain
->gcr3_tbl
== NULL
)
3318 domain
->glx
= levels
;
3319 domain
->flags
|= PD_IOMMUV2_MASK
;
3320 domain
->updated
= true;
3322 update_domain(domain
);
3327 spin_unlock_irqrestore(&domain
->lock
, flags
);
3331 EXPORT_SYMBOL(amd_iommu_domain_enable_v2
);
3333 static int __flush_pasid(struct protection_domain
*domain
, int pasid
,
3334 u64 address
, bool size
)
3336 struct iommu_dev_data
*dev_data
;
3337 struct iommu_cmd cmd
;
3340 if (!(domain
->flags
& PD_IOMMUV2_MASK
))
3343 build_inv_iommu_pasid(&cmd
, domain
->id
, pasid
, address
, size
);
3346 * IOMMU TLB needs to be flushed before Device TLB to
3347 * prevent device TLB refill from IOMMU TLB
3349 for (i
= 0; i
< amd_iommus_present
; ++i
) {
3350 if (domain
->dev_iommu
[i
] == 0)
3353 ret
= iommu_queue_command(amd_iommus
[i
], &cmd
);
3358 /* Wait until IOMMU TLB flushes are complete */
3359 domain_flush_complete(domain
);
3361 /* Now flush device TLBs */
3362 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
3363 struct amd_iommu
*iommu
;
3366 BUG_ON(!dev_data
->ats
.enabled
);
3368 qdep
= dev_data
->ats
.qdep
;
3369 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3371 build_inv_iotlb_pasid(&cmd
, dev_data
->devid
, pasid
,
3372 qdep
, address
, size
);
3374 ret
= iommu_queue_command(iommu
, &cmd
);
3379 /* Wait until all device TLBs are flushed */
3380 domain_flush_complete(domain
);
3389 static int __amd_iommu_flush_page(struct protection_domain
*domain
, int pasid
,
3392 INC_STATS_COUNTER(invalidate_iotlb
);
3394 return __flush_pasid(domain
, pasid
, address
, false);
3397 int amd_iommu_flush_page(struct iommu_domain
*dom
, int pasid
,
3400 struct protection_domain
*domain
= to_pdomain(dom
);
3401 unsigned long flags
;
3404 spin_lock_irqsave(&domain
->lock
, flags
);
3405 ret
= __amd_iommu_flush_page(domain
, pasid
, address
);
3406 spin_unlock_irqrestore(&domain
->lock
, flags
);
3410 EXPORT_SYMBOL(amd_iommu_flush_page
);
3412 static int __amd_iommu_flush_tlb(struct protection_domain
*domain
, int pasid
)
3414 INC_STATS_COUNTER(invalidate_iotlb_all
);
3416 return __flush_pasid(domain
, pasid
, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
3420 int amd_iommu_flush_tlb(struct iommu_domain
*dom
, int pasid
)
3422 struct protection_domain
*domain
= to_pdomain(dom
);
3423 unsigned long flags
;
3426 spin_lock_irqsave(&domain
->lock
, flags
);
3427 ret
= __amd_iommu_flush_tlb(domain
, pasid
);
3428 spin_unlock_irqrestore(&domain
->lock
, flags
);
3432 EXPORT_SYMBOL(amd_iommu_flush_tlb
);
3434 static u64
*__get_gcr3_pte(u64
*root
, int level
, int pasid
, bool alloc
)
3441 index
= (pasid
>> (9 * level
)) & 0x1ff;
3447 if (!(*pte
& GCR3_VALID
)) {
3451 root
= (void *)get_zeroed_page(GFP_ATOMIC
);
3455 *pte
= __pa(root
) | GCR3_VALID
;
3458 root
= __va(*pte
& PAGE_MASK
);
3466 static int __set_gcr3(struct protection_domain
*domain
, int pasid
,
3471 if (domain
->mode
!= PAGE_MODE_NONE
)
3474 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, true);
3478 *pte
= (cr3
& PAGE_MASK
) | GCR3_VALID
;
3480 return __amd_iommu_flush_tlb(domain
, pasid
);
3483 static int __clear_gcr3(struct protection_domain
*domain
, int pasid
)
3487 if (domain
->mode
!= PAGE_MODE_NONE
)
3490 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, false);
3496 return __amd_iommu_flush_tlb(domain
, pasid
);
3499 int amd_iommu_domain_set_gcr3(struct iommu_domain
*dom
, int pasid
,
3502 struct protection_domain
*domain
= to_pdomain(dom
);
3503 unsigned long flags
;
3506 spin_lock_irqsave(&domain
->lock
, flags
);
3507 ret
= __set_gcr3(domain
, pasid
, cr3
);
3508 spin_unlock_irqrestore(&domain
->lock
, flags
);
3512 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3
);
3514 int amd_iommu_domain_clear_gcr3(struct iommu_domain
*dom
, int pasid
)
3516 struct protection_domain
*domain
= to_pdomain(dom
);
3517 unsigned long flags
;
3520 spin_lock_irqsave(&domain
->lock
, flags
);
3521 ret
= __clear_gcr3(domain
, pasid
);
3522 spin_unlock_irqrestore(&domain
->lock
, flags
);
3526 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3
);
3528 int amd_iommu_complete_ppr(struct pci_dev
*pdev
, int pasid
,
3529 int status
, int tag
)
3531 struct iommu_dev_data
*dev_data
;
3532 struct amd_iommu
*iommu
;
3533 struct iommu_cmd cmd
;
3535 INC_STATS_COUNTER(complete_ppr
);
3537 dev_data
= get_dev_data(&pdev
->dev
);
3538 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3540 build_complete_ppr(&cmd
, dev_data
->devid
, pasid
, status
,
3541 tag
, dev_data
->pri_tlp
);
3543 return iommu_queue_command(iommu
, &cmd
);
3545 EXPORT_SYMBOL(amd_iommu_complete_ppr
);
3547 struct iommu_domain
*amd_iommu_get_v2_domain(struct pci_dev
*pdev
)
3549 struct protection_domain
*pdomain
;
3551 pdomain
= get_domain(&pdev
->dev
);
3552 if (IS_ERR(pdomain
))
3555 /* Only return IOMMUv2 domains */
3556 if (!(pdomain
->flags
& PD_IOMMUV2_MASK
))
3559 return &pdomain
->domain
;
3561 EXPORT_SYMBOL(amd_iommu_get_v2_domain
);
3563 void amd_iommu_enable_device_erratum(struct pci_dev
*pdev
, u32 erratum
)
3565 struct iommu_dev_data
*dev_data
;
3567 if (!amd_iommu_v2_supported())
3570 dev_data
= get_dev_data(&pdev
->dev
);
3571 dev_data
->errata
|= (1 << erratum
);
3573 EXPORT_SYMBOL(amd_iommu_enable_device_erratum
);
3575 int amd_iommu_device_info(struct pci_dev
*pdev
,
3576 struct amd_iommu_device_info
*info
)
3581 if (pdev
== NULL
|| info
== NULL
)
3584 if (!amd_iommu_v2_supported())
3587 memset(info
, 0, sizeof(*info
));
3589 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ATS
);
3591 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_ATS_SUP
;
3593 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
3595 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRI_SUP
;
3597 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PASID
);
3601 max_pasids
= 1 << (9 * (amd_iommu_max_glx_val
+ 1));
3602 max_pasids
= min(max_pasids
, (1 << 20));
3604 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PASID_SUP
;
3605 info
->max_pasids
= min(pci_max_pasids(pdev
), max_pasids
);
3607 features
= pci_pasid_features(pdev
);
3608 if (features
& PCI_PASID_CAP_EXEC
)
3609 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP
;
3610 if (features
& PCI_PASID_CAP_PRIV
)
3611 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP
;
3616 EXPORT_SYMBOL(amd_iommu_device_info
);
3618 #ifdef CONFIG_IRQ_REMAP
3620 /*****************************************************************************
3622 * Interrupt Remapping Implementation
3624 *****************************************************************************/
3642 u16 devid
; /* Device ID for IRTE table */
3643 u16 index
; /* Index into IRTE table*/
3646 struct amd_ir_data
{
3647 struct irq_2_irte irq_2_irte
;
3648 union irte irte_entry
;
3650 struct msi_msg msi_entry
;
3654 static struct irq_chip amd_ir_chip
;
3656 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3657 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3658 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3659 #define DTE_IRQ_REMAP_ENABLE 1ULL
3661 static void set_dte_irq_entry(u16 devid
, struct irq_remap_table
*table
)
3665 dte
= amd_iommu_dev_table
[devid
].data
[2];
3666 dte
&= ~DTE_IRQ_PHYS_ADDR_MASK
;
3667 dte
|= virt_to_phys(table
->table
);
3668 dte
|= DTE_IRQ_REMAP_INTCTL
;
3669 dte
|= DTE_IRQ_TABLE_LEN
;
3670 dte
|= DTE_IRQ_REMAP_ENABLE
;
3672 amd_iommu_dev_table
[devid
].data
[2] = dte
;
3675 #define IRTE_ALLOCATED (~1U)
3677 static struct irq_remap_table
*get_irq_table(u16 devid
, bool ioapic
)
3679 struct irq_remap_table
*table
= NULL
;
3680 struct amd_iommu
*iommu
;
3681 unsigned long flags
;
3684 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
3686 iommu
= amd_iommu_rlookup_table
[devid
];
3690 table
= irq_lookup_table
[devid
];
3694 alias
= amd_iommu_alias_table
[devid
];
3695 table
= irq_lookup_table
[alias
];
3697 irq_lookup_table
[devid
] = table
;
3698 set_dte_irq_entry(devid
, table
);
3699 iommu_flush_dte(iommu
, devid
);
3703 /* Nothing there yet, allocate new irq remapping table */
3704 table
= kzalloc(sizeof(*table
), GFP_ATOMIC
);
3708 /* Initialize table spin-lock */
3709 spin_lock_init(&table
->lock
);
3712 /* Keep the first 32 indexes free for IOAPIC interrupts */
3713 table
->min_index
= 32;
3715 table
->table
= kmem_cache_alloc(amd_iommu_irq_cache
, GFP_ATOMIC
);
3716 if (!table
->table
) {
3722 memset(table
->table
, 0, MAX_IRQS_PER_TABLE
* sizeof(u32
));
3727 for (i
= 0; i
< 32; ++i
)
3728 table
->table
[i
] = IRTE_ALLOCATED
;
3731 irq_lookup_table
[devid
] = table
;
3732 set_dte_irq_entry(devid
, table
);
3733 iommu_flush_dte(iommu
, devid
);
3734 if (devid
!= alias
) {
3735 irq_lookup_table
[alias
] = table
;
3736 set_dte_irq_entry(alias
, table
);
3737 iommu_flush_dte(iommu
, alias
);
3741 iommu_completion_wait(iommu
);
3744 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
3749 static int alloc_irq_index(u16 devid
, int count
)
3751 struct irq_remap_table
*table
;
3752 unsigned long flags
;
3755 table
= get_irq_table(devid
, false);
3759 spin_lock_irqsave(&table
->lock
, flags
);
3761 /* Scan table for free entries */
3762 for (c
= 0, index
= table
->min_index
;
3763 index
< MAX_IRQS_PER_TABLE
;
3765 if (table
->table
[index
] == 0)
3772 table
->table
[index
- c
+ 1] = IRTE_ALLOCATED
;
3782 spin_unlock_irqrestore(&table
->lock
, flags
);
3787 static int modify_irte(u16 devid
, int index
, union irte irte
)
3789 struct irq_remap_table
*table
;
3790 struct amd_iommu
*iommu
;
3791 unsigned long flags
;
3793 iommu
= amd_iommu_rlookup_table
[devid
];
3797 table
= get_irq_table(devid
, false);
3801 spin_lock_irqsave(&table
->lock
, flags
);
3802 table
->table
[index
] = irte
.val
;
3803 spin_unlock_irqrestore(&table
->lock
, flags
);
3805 iommu_flush_irt(iommu
, devid
);
3806 iommu_completion_wait(iommu
);
3811 static void free_irte(u16 devid
, int index
)
3813 struct irq_remap_table
*table
;
3814 struct amd_iommu
*iommu
;
3815 unsigned long flags
;
3817 iommu
= amd_iommu_rlookup_table
[devid
];
3821 table
= get_irq_table(devid
, false);
3825 spin_lock_irqsave(&table
->lock
, flags
);
3826 table
->table
[index
] = 0;
3827 spin_unlock_irqrestore(&table
->lock
, flags
);
3829 iommu_flush_irt(iommu
, devid
);
3830 iommu_completion_wait(iommu
);
3833 static int get_devid(struct irq_alloc_info
*info
)
3837 switch (info
->type
) {
3838 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
3839 devid
= get_ioapic_devid(info
->ioapic_id
);
3841 case X86_IRQ_ALLOC_TYPE_HPET
:
3842 devid
= get_hpet_devid(info
->hpet_id
);
3844 case X86_IRQ_ALLOC_TYPE_MSI
:
3845 case X86_IRQ_ALLOC_TYPE_MSIX
:
3846 devid
= get_device_id(&info
->msi_dev
->dev
);
3856 static struct irq_domain
*get_ir_irq_domain(struct irq_alloc_info
*info
)
3858 struct amd_iommu
*iommu
;
3864 devid
= get_devid(info
);
3866 iommu
= amd_iommu_rlookup_table
[devid
];
3868 return iommu
->ir_domain
;
3874 static struct irq_domain
*get_irq_domain(struct irq_alloc_info
*info
)
3876 struct amd_iommu
*iommu
;
3882 switch (info
->type
) {
3883 case X86_IRQ_ALLOC_TYPE_MSI
:
3884 case X86_IRQ_ALLOC_TYPE_MSIX
:
3885 devid
= get_device_id(&info
->msi_dev
->dev
);
3887 iommu
= amd_iommu_rlookup_table
[devid
];
3889 return iommu
->msi_domain
;
3899 struct irq_remap_ops amd_iommu_irq_ops
= {
3900 .prepare
= amd_iommu_prepare
,
3901 .enable
= amd_iommu_enable
,
3902 .disable
= amd_iommu_disable
,
3903 .reenable
= amd_iommu_reenable
,
3904 .enable_faulting
= amd_iommu_enable_faulting
,
3905 .get_ir_irq_domain
= get_ir_irq_domain
,
3906 .get_irq_domain
= get_irq_domain
,
3909 static void irq_remapping_prepare_irte(struct amd_ir_data
*data
,
3910 struct irq_cfg
*irq_cfg
,
3911 struct irq_alloc_info
*info
,
3912 int devid
, int index
, int sub_handle
)
3914 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
3915 struct msi_msg
*msg
= &data
->msi_entry
;
3916 union irte
*irte
= &data
->irte_entry
;
3917 struct IO_APIC_route_entry
*entry
;
3919 data
->irq_2_irte
.devid
= devid
;
3920 data
->irq_2_irte
.index
= index
+ sub_handle
;
3922 /* Setup IRTE for IOMMU */
3924 irte
->fields
.vector
= irq_cfg
->vector
;
3925 irte
->fields
.int_type
= apic
->irq_delivery_mode
;
3926 irte
->fields
.destination
= irq_cfg
->dest_apicid
;
3927 irte
->fields
.dm
= apic
->irq_dest_mode
;
3928 irte
->fields
.valid
= 1;
3930 switch (info
->type
) {
3931 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
3932 /* Setup IOAPIC entry */
3933 entry
= info
->ioapic_entry
;
3934 info
->ioapic_entry
= NULL
;
3935 memset(entry
, 0, sizeof(*entry
));
3936 entry
->vector
= index
;
3938 entry
->trigger
= info
->ioapic_trigger
;
3939 entry
->polarity
= info
->ioapic_polarity
;
3940 /* Mask level triggered irqs. */
3941 if (info
->ioapic_trigger
)
3945 case X86_IRQ_ALLOC_TYPE_HPET
:
3946 case X86_IRQ_ALLOC_TYPE_MSI
:
3947 case X86_IRQ_ALLOC_TYPE_MSIX
:
3948 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3949 msg
->address_lo
= MSI_ADDR_BASE_LO
;
3950 msg
->data
= irte_info
->index
;
3959 static int irq_remapping_alloc(struct irq_domain
*domain
, unsigned int virq
,
3960 unsigned int nr_irqs
, void *arg
)
3962 struct irq_alloc_info
*info
= arg
;
3963 struct irq_data
*irq_data
;
3964 struct amd_ir_data
*data
;
3965 struct irq_cfg
*cfg
;
3971 if (nr_irqs
> 1 && info
->type
!= X86_IRQ_ALLOC_TYPE_MSI
&&
3972 info
->type
!= X86_IRQ_ALLOC_TYPE_MSIX
)
3976 * With IRQ remapping enabled, don't need contiguous CPU vectors
3977 * to support multiple MSI interrupts.
3979 if (info
->type
== X86_IRQ_ALLOC_TYPE_MSI
)
3980 info
->flags
&= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS
;
3982 devid
= get_devid(info
);
3986 ret
= irq_domain_alloc_irqs_parent(domain
, virq
, nr_irqs
, arg
);
3991 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
3993 goto out_free_parent
;
3995 if (info
->type
== X86_IRQ_ALLOC_TYPE_IOAPIC
) {
3996 if (get_irq_table(devid
, true))
3997 index
= info
->ioapic_pin
;
4001 index
= alloc_irq_index(devid
, nr_irqs
);
4004 pr_warn("Failed to allocate IRTE\n");
4006 goto out_free_parent
;
4009 for (i
= 0; i
< nr_irqs
; i
++) {
4010 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4011 cfg
= irqd_cfg(irq_data
);
4012 if (!irq_data
|| !cfg
) {
4018 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
4022 irq_data
->hwirq
= (devid
<< 16) + i
;
4023 irq_data
->chip_data
= data
;
4024 irq_data
->chip
= &amd_ir_chip
;
4025 irq_remapping_prepare_irte(data
, cfg
, info
, devid
, index
, i
);
4026 irq_set_status_flags(virq
+ i
, IRQ_MOVE_PCNTXT
);
4031 for (i
--; i
>= 0; i
--) {
4032 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4034 kfree(irq_data
->chip_data
);
4036 for (i
= 0; i
< nr_irqs
; i
++)
4037 free_irte(devid
, index
+ i
);
4039 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4043 static void irq_remapping_free(struct irq_domain
*domain
, unsigned int virq
,
4044 unsigned int nr_irqs
)
4046 struct irq_2_irte
*irte_info
;
4047 struct irq_data
*irq_data
;
4048 struct amd_ir_data
*data
;
4051 for (i
= 0; i
< nr_irqs
; i
++) {
4052 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4053 if (irq_data
&& irq_data
->chip_data
) {
4054 data
= irq_data
->chip_data
;
4055 irte_info
= &data
->irq_2_irte
;
4056 free_irte(irte_info
->devid
, irte_info
->index
);
4060 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4063 static void irq_remapping_activate(struct irq_domain
*domain
,
4064 struct irq_data
*irq_data
)
4066 struct amd_ir_data
*data
= irq_data
->chip_data
;
4067 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4069 modify_irte(irte_info
->devid
, irte_info
->index
, data
->irte_entry
);
4072 static void irq_remapping_deactivate(struct irq_domain
*domain
,
4073 struct irq_data
*irq_data
)
4075 struct amd_ir_data
*data
= irq_data
->chip_data
;
4076 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4080 modify_irte(irte_info
->devid
, irte_info
->index
, data
->irte_entry
);
4083 static struct irq_domain_ops amd_ir_domain_ops
= {
4084 .alloc
= irq_remapping_alloc
,
4085 .free
= irq_remapping_free
,
4086 .activate
= irq_remapping_activate
,
4087 .deactivate
= irq_remapping_deactivate
,
4090 static int amd_ir_set_affinity(struct irq_data
*data
,
4091 const struct cpumask
*mask
, bool force
)
4093 struct amd_ir_data
*ir_data
= data
->chip_data
;
4094 struct irq_2_irte
*irte_info
= &ir_data
->irq_2_irte
;
4095 struct irq_cfg
*cfg
= irqd_cfg(data
);
4096 struct irq_data
*parent
= data
->parent_data
;
4099 ret
= parent
->chip
->irq_set_affinity(parent
, mask
, force
);
4100 if (ret
< 0 || ret
== IRQ_SET_MASK_OK_DONE
)
4104 * Atomically updates the IRTE with the new destination, vector
4105 * and flushes the interrupt entry cache.
4107 ir_data
->irte_entry
.fields
.vector
= cfg
->vector
;
4108 ir_data
->irte_entry
.fields
.destination
= cfg
->dest_apicid
;
4109 modify_irte(irte_info
->devid
, irte_info
->index
, ir_data
->irte_entry
);
4112 * After this point, all the interrupts will start arriving
4113 * at the new destination. So, time to cleanup the previous
4114 * vector allocation.
4116 send_cleanup_vector(cfg
);
4118 return IRQ_SET_MASK_OK_DONE
;
4121 static void ir_compose_msi_msg(struct irq_data
*irq_data
, struct msi_msg
*msg
)
4123 struct amd_ir_data
*ir_data
= irq_data
->chip_data
;
4125 *msg
= ir_data
->msi_entry
;
4128 static struct irq_chip amd_ir_chip
= {
4129 .irq_ack
= ir_ack_apic_edge
,
4130 .irq_set_affinity
= amd_ir_set_affinity
,
4131 .irq_compose_msi_msg
= ir_compose_msi_msg
,
4134 int amd_iommu_create_irq_domain(struct amd_iommu
*iommu
)
4136 iommu
->ir_domain
= irq_domain_add_tree(NULL
, &amd_ir_domain_ops
, iommu
);
4137 if (!iommu
->ir_domain
)
4140 iommu
->ir_domain
->parent
= arch_get_ir_parent_domain();
4141 iommu
->msi_domain
= arch_create_msi_irq_domain(iommu
->ir_domain
);