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NVMe: per-cpu io queues
[deliverable/linux.git] / drivers / iommu / amd_iommu_init.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <linux/amd-iommu.h>
28 #include <linux/export.h>
29 #include <asm/pci-direct.h>
30 #include <asm/iommu.h>
31 #include <asm/gart.h>
32 #include <asm/x86_init.h>
33 #include <asm/iommu_table.h>
34 #include <asm/io_apic.h>
35 #include <asm/irq_remapping.h>
36
37 #include "amd_iommu_proto.h"
38 #include "amd_iommu_types.h"
39 #include "irq_remapping.h"
40
41 /*
42 * definitions for the ACPI scanning code
43 */
44 #define IVRS_HEADER_LENGTH 48
45
46 #define ACPI_IVHD_TYPE 0x10
47 #define ACPI_IVMD_TYPE_ALL 0x20
48 #define ACPI_IVMD_TYPE 0x21
49 #define ACPI_IVMD_TYPE_RANGE 0x22
50
51 #define IVHD_DEV_ALL 0x01
52 #define IVHD_DEV_SELECT 0x02
53 #define IVHD_DEV_SELECT_RANGE_START 0x03
54 #define IVHD_DEV_RANGE_END 0x04
55 #define IVHD_DEV_ALIAS 0x42
56 #define IVHD_DEV_ALIAS_RANGE 0x43
57 #define IVHD_DEV_EXT_SELECT 0x46
58 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
59 #define IVHD_DEV_SPECIAL 0x48
60
61 #define IVHD_SPECIAL_IOAPIC 1
62 #define IVHD_SPECIAL_HPET 2
63
64 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
65 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
66 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
67 #define IVHD_FLAG_ISOC_EN_MASK 0x08
68
69 #define IVMD_FLAG_EXCL_RANGE 0x08
70 #define IVMD_FLAG_UNITY_MAP 0x01
71
72 #define ACPI_DEVFLAG_INITPASS 0x01
73 #define ACPI_DEVFLAG_EXTINT 0x02
74 #define ACPI_DEVFLAG_NMI 0x04
75 #define ACPI_DEVFLAG_SYSMGT1 0x10
76 #define ACPI_DEVFLAG_SYSMGT2 0x20
77 #define ACPI_DEVFLAG_LINT0 0x40
78 #define ACPI_DEVFLAG_LINT1 0x80
79 #define ACPI_DEVFLAG_ATSDIS 0x10000000
80
81 /*
82 * ACPI table definitions
83 *
84 * These data structures are laid over the table to parse the important values
85 * out of it.
86 */
87
88 /*
89 * structure describing one IOMMU in the ACPI table. Typically followed by one
90 * or more ivhd_entrys.
91 */
92 struct ivhd_header {
93 u8 type;
94 u8 flags;
95 u16 length;
96 u16 devid;
97 u16 cap_ptr;
98 u64 mmio_phys;
99 u16 pci_seg;
100 u16 info;
101 u32 efr;
102 } __attribute__((packed));
103
104 /*
105 * A device entry describing which devices a specific IOMMU translates and
106 * which requestor ids they use.
107 */
108 struct ivhd_entry {
109 u8 type;
110 u16 devid;
111 u8 flags;
112 u32 ext;
113 } __attribute__((packed));
114
115 /*
116 * An AMD IOMMU memory definition structure. It defines things like exclusion
117 * ranges for devices and regions that should be unity mapped.
118 */
119 struct ivmd_header {
120 u8 type;
121 u8 flags;
122 u16 length;
123 u16 devid;
124 u16 aux;
125 u64 resv;
126 u64 range_start;
127 u64 range_length;
128 } __attribute__((packed));
129
130 bool amd_iommu_dump;
131 bool amd_iommu_irq_remap __read_mostly;
132
133 static bool amd_iommu_detected;
134 static bool __initdata amd_iommu_disabled;
135
136 u16 amd_iommu_last_bdf; /* largest PCI device id we have
137 to handle */
138 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
139 we find in ACPI */
140 u32 amd_iommu_unmap_flush; /* if true, flush on every unmap */
141
142 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
143 system */
144
145 /* Array to assign indices to IOMMUs*/
146 struct amd_iommu *amd_iommus[MAX_IOMMUS];
147 int amd_iommus_present;
148
149 /* IOMMUs have a non-present cache? */
150 bool amd_iommu_np_cache __read_mostly;
151 bool amd_iommu_iotlb_sup __read_mostly = true;
152
153 u32 amd_iommu_max_pasids __read_mostly = ~0;
154
155 bool amd_iommu_v2_present __read_mostly;
156 bool amd_iommu_pc_present __read_mostly;
157
158 bool amd_iommu_force_isolation __read_mostly;
159
160 /*
161 * List of protection domains - used during resume
162 */
163 LIST_HEAD(amd_iommu_pd_list);
164 spinlock_t amd_iommu_pd_lock;
165
166 /*
167 * Pointer to the device table which is shared by all AMD IOMMUs
168 * it is indexed by the PCI device id or the HT unit id and contains
169 * information about the domain the device belongs to as well as the
170 * page table root pointer.
171 */
172 struct dev_table_entry *amd_iommu_dev_table;
173
174 /*
175 * The alias table is a driver specific data structure which contains the
176 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
177 * More than one device can share the same requestor id.
178 */
179 u16 *amd_iommu_alias_table;
180
181 /*
182 * The rlookup table is used to find the IOMMU which is responsible
183 * for a specific device. It is also indexed by the PCI device id.
184 */
185 struct amd_iommu **amd_iommu_rlookup_table;
186
187 /*
188 * This table is used to find the irq remapping table for a given device id
189 * quickly.
190 */
191 struct irq_remap_table **irq_lookup_table;
192
193 /*
194 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
195 * to know which ones are already in use.
196 */
197 unsigned long *amd_iommu_pd_alloc_bitmap;
198
199 static u32 dev_table_size; /* size of the device table */
200 static u32 alias_table_size; /* size of the alias table */
201 static u32 rlookup_table_size; /* size if the rlookup table */
202
203 enum iommu_init_state {
204 IOMMU_START_STATE,
205 IOMMU_IVRS_DETECTED,
206 IOMMU_ACPI_FINISHED,
207 IOMMU_ENABLED,
208 IOMMU_PCI_INIT,
209 IOMMU_INTERRUPTS_EN,
210 IOMMU_DMA_OPS,
211 IOMMU_INITIALIZED,
212 IOMMU_NOT_FOUND,
213 IOMMU_INIT_ERROR,
214 };
215
216 /* Early ioapic and hpet maps from kernel command line */
217 #define EARLY_MAP_SIZE 4
218 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
219 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
220 static int __initdata early_ioapic_map_size;
221 static int __initdata early_hpet_map_size;
222 static bool __initdata cmdline_maps;
223
224 static enum iommu_init_state init_state = IOMMU_START_STATE;
225
226 static int amd_iommu_enable_interrupts(void);
227 static int __init iommu_go_to_state(enum iommu_init_state state);
228
229 static inline void update_last_devid(u16 devid)
230 {
231 if (devid > amd_iommu_last_bdf)
232 amd_iommu_last_bdf = devid;
233 }
234
235 static inline unsigned long tbl_size(int entry_size)
236 {
237 unsigned shift = PAGE_SHIFT +
238 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
239
240 return 1UL << shift;
241 }
242
243 /* Access to l1 and l2 indexed register spaces */
244
245 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
246 {
247 u32 val;
248
249 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
250 pci_read_config_dword(iommu->dev, 0xfc, &val);
251 return val;
252 }
253
254 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
255 {
256 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
257 pci_write_config_dword(iommu->dev, 0xfc, val);
258 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
259 }
260
261 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
262 {
263 u32 val;
264
265 pci_write_config_dword(iommu->dev, 0xf0, address);
266 pci_read_config_dword(iommu->dev, 0xf4, &val);
267 return val;
268 }
269
270 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
271 {
272 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
273 pci_write_config_dword(iommu->dev, 0xf4, val);
274 }
275
276 /****************************************************************************
277 *
278 * AMD IOMMU MMIO register space handling functions
279 *
280 * These functions are used to program the IOMMU device registers in
281 * MMIO space required for that driver.
282 *
283 ****************************************************************************/
284
285 /*
286 * This function set the exclusion range in the IOMMU. DMA accesses to the
287 * exclusion range are passed through untranslated
288 */
289 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
290 {
291 u64 start = iommu->exclusion_start & PAGE_MASK;
292 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
293 u64 entry;
294
295 if (!iommu->exclusion_start)
296 return;
297
298 entry = start | MMIO_EXCL_ENABLE_MASK;
299 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
300 &entry, sizeof(entry));
301
302 entry = limit;
303 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
304 &entry, sizeof(entry));
305 }
306
307 /* Programs the physical address of the device table into the IOMMU hardware */
308 static void iommu_set_device_table(struct amd_iommu *iommu)
309 {
310 u64 entry;
311
312 BUG_ON(iommu->mmio_base == NULL);
313
314 entry = virt_to_phys(amd_iommu_dev_table);
315 entry |= (dev_table_size >> 12) - 1;
316 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
317 &entry, sizeof(entry));
318 }
319
320 /* Generic functions to enable/disable certain features of the IOMMU. */
321 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
322 {
323 u32 ctrl;
324
325 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
326 ctrl |= (1 << bit);
327 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
328 }
329
330 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
331 {
332 u32 ctrl;
333
334 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
335 ctrl &= ~(1 << bit);
336 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
337 }
338
339 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
340 {
341 u32 ctrl;
342
343 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
344 ctrl &= ~CTRL_INV_TO_MASK;
345 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
346 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
347 }
348
349 /* Function to enable the hardware */
350 static void iommu_enable(struct amd_iommu *iommu)
351 {
352 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
353 }
354
355 static void iommu_disable(struct amd_iommu *iommu)
356 {
357 /* Disable command buffer */
358 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
359
360 /* Disable event logging and event interrupts */
361 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
362 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
363
364 /* Disable IOMMU hardware itself */
365 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
366 }
367
368 /*
369 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
370 * the system has one.
371 */
372 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
373 {
374 if (!request_mem_region(address, end, "amd_iommu")) {
375 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
376 address, end);
377 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
378 return NULL;
379 }
380
381 return (u8 __iomem *)ioremap_nocache(address, end);
382 }
383
384 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
385 {
386 if (iommu->mmio_base)
387 iounmap(iommu->mmio_base);
388 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
389 }
390
391 /****************************************************************************
392 *
393 * The functions below belong to the first pass of AMD IOMMU ACPI table
394 * parsing. In this pass we try to find out the highest device id this
395 * code has to handle. Upon this information the size of the shared data
396 * structures is determined later.
397 *
398 ****************************************************************************/
399
400 /*
401 * This function calculates the length of a given IVHD entry
402 */
403 static inline int ivhd_entry_length(u8 *ivhd)
404 {
405 return 0x04 << (*ivhd >> 6);
406 }
407
408 /*
409 * This function reads the last device id the IOMMU has to handle from the PCI
410 * capability header for this IOMMU
411 */
412 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
413 {
414 u32 cap;
415
416 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
417 update_last_devid(PCI_DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
418
419 return 0;
420 }
421
422 /*
423 * After reading the highest device id from the IOMMU PCI capability header
424 * this function looks if there is a higher device id defined in the ACPI table
425 */
426 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
427 {
428 u8 *p = (void *)h, *end = (void *)h;
429 struct ivhd_entry *dev;
430
431 p += sizeof(*h);
432 end += h->length;
433
434 find_last_devid_on_pci(PCI_BUS_NUM(h->devid),
435 PCI_SLOT(h->devid),
436 PCI_FUNC(h->devid),
437 h->cap_ptr);
438
439 while (p < end) {
440 dev = (struct ivhd_entry *)p;
441 switch (dev->type) {
442 case IVHD_DEV_SELECT:
443 case IVHD_DEV_RANGE_END:
444 case IVHD_DEV_ALIAS:
445 case IVHD_DEV_EXT_SELECT:
446 /* all the above subfield types refer to device ids */
447 update_last_devid(dev->devid);
448 break;
449 default:
450 break;
451 }
452 p += ivhd_entry_length(p);
453 }
454
455 WARN_ON(p != end);
456
457 return 0;
458 }
459
460 /*
461 * Iterate over all IVHD entries in the ACPI table and find the highest device
462 * id which we need to handle. This is the first of three functions which parse
463 * the ACPI table. So we check the checksum here.
464 */
465 static int __init find_last_devid_acpi(struct acpi_table_header *table)
466 {
467 int i;
468 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
469 struct ivhd_header *h;
470
471 /*
472 * Validate checksum here so we don't need to do it when
473 * we actually parse the table
474 */
475 for (i = 0; i < table->length; ++i)
476 checksum += p[i];
477 if (checksum != 0)
478 /* ACPI table corrupt */
479 return -ENODEV;
480
481 p += IVRS_HEADER_LENGTH;
482
483 end += table->length;
484 while (p < end) {
485 h = (struct ivhd_header *)p;
486 switch (h->type) {
487 case ACPI_IVHD_TYPE:
488 find_last_devid_from_ivhd(h);
489 break;
490 default:
491 break;
492 }
493 p += h->length;
494 }
495 WARN_ON(p != end);
496
497 return 0;
498 }
499
500 /****************************************************************************
501 *
502 * The following functions belong to the code path which parses the ACPI table
503 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
504 * data structures, initialize the device/alias/rlookup table and also
505 * basically initialize the hardware.
506 *
507 ****************************************************************************/
508
509 /*
510 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
511 * write commands to that buffer later and the IOMMU will execute them
512 * asynchronously
513 */
514 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
515 {
516 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
517 get_order(CMD_BUFFER_SIZE));
518
519 if (cmd_buf == NULL)
520 return NULL;
521
522 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
523
524 return cmd_buf;
525 }
526
527 /*
528 * This function resets the command buffer if the IOMMU stopped fetching
529 * commands from it.
530 */
531 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
532 {
533 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
534
535 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
536 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
537
538 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
539 }
540
541 /*
542 * This function writes the command buffer address to the hardware and
543 * enables it.
544 */
545 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
546 {
547 u64 entry;
548
549 BUG_ON(iommu->cmd_buf == NULL);
550
551 entry = (u64)virt_to_phys(iommu->cmd_buf);
552 entry |= MMIO_CMD_SIZE_512;
553
554 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
555 &entry, sizeof(entry));
556
557 amd_iommu_reset_cmd_buffer(iommu);
558 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
559 }
560
561 static void __init free_command_buffer(struct amd_iommu *iommu)
562 {
563 free_pages((unsigned long)iommu->cmd_buf,
564 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
565 }
566
567 /* allocates the memory where the IOMMU will log its events to */
568 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
569 {
570 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
571 get_order(EVT_BUFFER_SIZE));
572
573 if (iommu->evt_buf == NULL)
574 return NULL;
575
576 iommu->evt_buf_size = EVT_BUFFER_SIZE;
577
578 return iommu->evt_buf;
579 }
580
581 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
582 {
583 u64 entry;
584
585 BUG_ON(iommu->evt_buf == NULL);
586
587 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
588
589 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
590 &entry, sizeof(entry));
591
592 /* set head and tail to zero manually */
593 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
594 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
595
596 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
597 }
598
599 static void __init free_event_buffer(struct amd_iommu *iommu)
600 {
601 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
602 }
603
604 /* allocates the memory where the IOMMU will log its events to */
605 static u8 * __init alloc_ppr_log(struct amd_iommu *iommu)
606 {
607 iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
608 get_order(PPR_LOG_SIZE));
609
610 if (iommu->ppr_log == NULL)
611 return NULL;
612
613 return iommu->ppr_log;
614 }
615
616 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
617 {
618 u64 entry;
619
620 if (iommu->ppr_log == NULL)
621 return;
622
623 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
624
625 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
626 &entry, sizeof(entry));
627
628 /* set head and tail to zero manually */
629 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
630 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
631
632 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
633 iommu_feature_enable(iommu, CONTROL_PPR_EN);
634 }
635
636 static void __init free_ppr_log(struct amd_iommu *iommu)
637 {
638 if (iommu->ppr_log == NULL)
639 return;
640
641 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
642 }
643
644 static void iommu_enable_gt(struct amd_iommu *iommu)
645 {
646 if (!iommu_feature(iommu, FEATURE_GT))
647 return;
648
649 iommu_feature_enable(iommu, CONTROL_GT_EN);
650 }
651
652 /* sets a specific bit in the device table entry. */
653 static void set_dev_entry_bit(u16 devid, u8 bit)
654 {
655 int i = (bit >> 6) & 0x03;
656 int _bit = bit & 0x3f;
657
658 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
659 }
660
661 static int get_dev_entry_bit(u16 devid, u8 bit)
662 {
663 int i = (bit >> 6) & 0x03;
664 int _bit = bit & 0x3f;
665
666 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
667 }
668
669
670 void amd_iommu_apply_erratum_63(u16 devid)
671 {
672 int sysmgt;
673
674 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
675 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
676
677 if (sysmgt == 0x01)
678 set_dev_entry_bit(devid, DEV_ENTRY_IW);
679 }
680
681 /* Writes the specific IOMMU for a device into the rlookup table */
682 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
683 {
684 amd_iommu_rlookup_table[devid] = iommu;
685 }
686
687 /*
688 * This function takes the device specific flags read from the ACPI
689 * table and sets up the device table entry with that information
690 */
691 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
692 u16 devid, u32 flags, u32 ext_flags)
693 {
694 if (flags & ACPI_DEVFLAG_INITPASS)
695 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
696 if (flags & ACPI_DEVFLAG_EXTINT)
697 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
698 if (flags & ACPI_DEVFLAG_NMI)
699 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
700 if (flags & ACPI_DEVFLAG_SYSMGT1)
701 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
702 if (flags & ACPI_DEVFLAG_SYSMGT2)
703 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
704 if (flags & ACPI_DEVFLAG_LINT0)
705 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
706 if (flags & ACPI_DEVFLAG_LINT1)
707 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
708
709 amd_iommu_apply_erratum_63(devid);
710
711 set_iommu_for_device(iommu, devid);
712 }
713
714 static int __init add_special_device(u8 type, u8 id, u16 devid, bool cmd_line)
715 {
716 struct devid_map *entry;
717 struct list_head *list;
718
719 if (type == IVHD_SPECIAL_IOAPIC)
720 list = &ioapic_map;
721 else if (type == IVHD_SPECIAL_HPET)
722 list = &hpet_map;
723 else
724 return -EINVAL;
725
726 list_for_each_entry(entry, list, list) {
727 if (!(entry->id == id && entry->cmd_line))
728 continue;
729
730 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
731 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
732
733 return 0;
734 }
735
736 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
737 if (!entry)
738 return -ENOMEM;
739
740 entry->id = id;
741 entry->devid = devid;
742 entry->cmd_line = cmd_line;
743
744 list_add_tail(&entry->list, list);
745
746 return 0;
747 }
748
749 static int __init add_early_maps(void)
750 {
751 int i, ret;
752
753 for (i = 0; i < early_ioapic_map_size; ++i) {
754 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
755 early_ioapic_map[i].id,
756 early_ioapic_map[i].devid,
757 early_ioapic_map[i].cmd_line);
758 if (ret)
759 return ret;
760 }
761
762 for (i = 0; i < early_hpet_map_size; ++i) {
763 ret = add_special_device(IVHD_SPECIAL_HPET,
764 early_hpet_map[i].id,
765 early_hpet_map[i].devid,
766 early_hpet_map[i].cmd_line);
767 if (ret)
768 return ret;
769 }
770
771 return 0;
772 }
773
774 /*
775 * Reads the device exclusion range from ACPI and initializes the IOMMU with
776 * it
777 */
778 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
779 {
780 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
781
782 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
783 return;
784
785 if (iommu) {
786 /*
787 * We only can configure exclusion ranges per IOMMU, not
788 * per device. But we can enable the exclusion range per
789 * device. This is done here
790 */
791 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
792 iommu->exclusion_start = m->range_start;
793 iommu->exclusion_length = m->range_length;
794 }
795 }
796
797 /*
798 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
799 * initializes the hardware and our data structures with it.
800 */
801 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
802 struct ivhd_header *h)
803 {
804 u8 *p = (u8 *)h;
805 u8 *end = p, flags = 0;
806 u16 devid = 0, devid_start = 0, devid_to = 0;
807 u32 dev_i, ext_flags = 0;
808 bool alias = false;
809 struct ivhd_entry *e;
810 int ret;
811
812
813 ret = add_early_maps();
814 if (ret)
815 return ret;
816
817 /*
818 * First save the recommended feature enable bits from ACPI
819 */
820 iommu->acpi_flags = h->flags;
821
822 /*
823 * Done. Now parse the device entries
824 */
825 p += sizeof(struct ivhd_header);
826 end += h->length;
827
828
829 while (p < end) {
830 e = (struct ivhd_entry *)p;
831 switch (e->type) {
832 case IVHD_DEV_ALL:
833
834 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
835 " last device %02x:%02x.%x flags: %02x\n",
836 PCI_BUS_NUM(iommu->first_device),
837 PCI_SLOT(iommu->first_device),
838 PCI_FUNC(iommu->first_device),
839 PCI_BUS_NUM(iommu->last_device),
840 PCI_SLOT(iommu->last_device),
841 PCI_FUNC(iommu->last_device),
842 e->flags);
843
844 for (dev_i = iommu->first_device;
845 dev_i <= iommu->last_device; ++dev_i)
846 set_dev_entry_from_acpi(iommu, dev_i,
847 e->flags, 0);
848 break;
849 case IVHD_DEV_SELECT:
850
851 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
852 "flags: %02x\n",
853 PCI_BUS_NUM(e->devid),
854 PCI_SLOT(e->devid),
855 PCI_FUNC(e->devid),
856 e->flags);
857
858 devid = e->devid;
859 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
860 break;
861 case IVHD_DEV_SELECT_RANGE_START:
862
863 DUMP_printk(" DEV_SELECT_RANGE_START\t "
864 "devid: %02x:%02x.%x flags: %02x\n",
865 PCI_BUS_NUM(e->devid),
866 PCI_SLOT(e->devid),
867 PCI_FUNC(e->devid),
868 e->flags);
869
870 devid_start = e->devid;
871 flags = e->flags;
872 ext_flags = 0;
873 alias = false;
874 break;
875 case IVHD_DEV_ALIAS:
876
877 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
878 "flags: %02x devid_to: %02x:%02x.%x\n",
879 PCI_BUS_NUM(e->devid),
880 PCI_SLOT(e->devid),
881 PCI_FUNC(e->devid),
882 e->flags,
883 PCI_BUS_NUM(e->ext >> 8),
884 PCI_SLOT(e->ext >> 8),
885 PCI_FUNC(e->ext >> 8));
886
887 devid = e->devid;
888 devid_to = e->ext >> 8;
889 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
890 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
891 amd_iommu_alias_table[devid] = devid_to;
892 break;
893 case IVHD_DEV_ALIAS_RANGE:
894
895 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
896 "devid: %02x:%02x.%x flags: %02x "
897 "devid_to: %02x:%02x.%x\n",
898 PCI_BUS_NUM(e->devid),
899 PCI_SLOT(e->devid),
900 PCI_FUNC(e->devid),
901 e->flags,
902 PCI_BUS_NUM(e->ext >> 8),
903 PCI_SLOT(e->ext >> 8),
904 PCI_FUNC(e->ext >> 8));
905
906 devid_start = e->devid;
907 flags = e->flags;
908 devid_to = e->ext >> 8;
909 ext_flags = 0;
910 alias = true;
911 break;
912 case IVHD_DEV_EXT_SELECT:
913
914 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
915 "flags: %02x ext: %08x\n",
916 PCI_BUS_NUM(e->devid),
917 PCI_SLOT(e->devid),
918 PCI_FUNC(e->devid),
919 e->flags, e->ext);
920
921 devid = e->devid;
922 set_dev_entry_from_acpi(iommu, devid, e->flags,
923 e->ext);
924 break;
925 case IVHD_DEV_EXT_SELECT_RANGE:
926
927 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
928 "%02x:%02x.%x flags: %02x ext: %08x\n",
929 PCI_BUS_NUM(e->devid),
930 PCI_SLOT(e->devid),
931 PCI_FUNC(e->devid),
932 e->flags, e->ext);
933
934 devid_start = e->devid;
935 flags = e->flags;
936 ext_flags = e->ext;
937 alias = false;
938 break;
939 case IVHD_DEV_RANGE_END:
940
941 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
942 PCI_BUS_NUM(e->devid),
943 PCI_SLOT(e->devid),
944 PCI_FUNC(e->devid));
945
946 devid = e->devid;
947 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
948 if (alias) {
949 amd_iommu_alias_table[dev_i] = devid_to;
950 set_dev_entry_from_acpi(iommu,
951 devid_to, flags, ext_flags);
952 }
953 set_dev_entry_from_acpi(iommu, dev_i,
954 flags, ext_flags);
955 }
956 break;
957 case IVHD_DEV_SPECIAL: {
958 u8 handle, type;
959 const char *var;
960 u16 devid;
961 int ret;
962
963 handle = e->ext & 0xff;
964 devid = (e->ext >> 8) & 0xffff;
965 type = (e->ext >> 24) & 0xff;
966
967 if (type == IVHD_SPECIAL_IOAPIC)
968 var = "IOAPIC";
969 else if (type == IVHD_SPECIAL_HPET)
970 var = "HPET";
971 else
972 var = "UNKNOWN";
973
974 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
975 var, (int)handle,
976 PCI_BUS_NUM(devid),
977 PCI_SLOT(devid),
978 PCI_FUNC(devid));
979
980 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
981 ret = add_special_device(type, handle, devid, false);
982 if (ret)
983 return ret;
984 break;
985 }
986 default:
987 break;
988 }
989
990 p += ivhd_entry_length(p);
991 }
992
993 return 0;
994 }
995
996 /* Initializes the device->iommu mapping for the driver */
997 static int __init init_iommu_devices(struct amd_iommu *iommu)
998 {
999 u32 i;
1000
1001 for (i = iommu->first_device; i <= iommu->last_device; ++i)
1002 set_iommu_for_device(iommu, i);
1003
1004 return 0;
1005 }
1006
1007 static void __init free_iommu_one(struct amd_iommu *iommu)
1008 {
1009 free_command_buffer(iommu);
1010 free_event_buffer(iommu);
1011 free_ppr_log(iommu);
1012 iommu_unmap_mmio_space(iommu);
1013 }
1014
1015 static void __init free_iommu_all(void)
1016 {
1017 struct amd_iommu *iommu, *next;
1018
1019 for_each_iommu_safe(iommu, next) {
1020 list_del(&iommu->list);
1021 free_iommu_one(iommu);
1022 kfree(iommu);
1023 }
1024 }
1025
1026 /*
1027 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1028 * Workaround:
1029 * BIOS should disable L2B micellaneous clock gating by setting
1030 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1031 */
1032 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1033 {
1034 u32 value;
1035
1036 if ((boot_cpu_data.x86 != 0x15) ||
1037 (boot_cpu_data.x86_model < 0x10) ||
1038 (boot_cpu_data.x86_model > 0x1f))
1039 return;
1040
1041 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1042 pci_read_config_dword(iommu->dev, 0xf4, &value);
1043
1044 if (value & BIT(2))
1045 return;
1046
1047 /* Select NB indirect register 0x90 and enable writing */
1048 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1049
1050 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1051 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1052 dev_name(&iommu->dev->dev));
1053
1054 /* Clear the enable writing bit */
1055 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1056 }
1057
1058 /*
1059 * This function clues the initialization function for one IOMMU
1060 * together and also allocates the command buffer and programs the
1061 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1062 */
1063 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1064 {
1065 int ret;
1066
1067 spin_lock_init(&iommu->lock);
1068
1069 /* Add IOMMU to internal data structures */
1070 list_add_tail(&iommu->list, &amd_iommu_list);
1071 iommu->index = amd_iommus_present++;
1072
1073 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1074 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1075 return -ENOSYS;
1076 }
1077
1078 /* Index is fine - add IOMMU to the array */
1079 amd_iommus[iommu->index] = iommu;
1080
1081 /*
1082 * Copy data from ACPI table entry to the iommu struct
1083 */
1084 iommu->devid = h->devid;
1085 iommu->cap_ptr = h->cap_ptr;
1086 iommu->pci_seg = h->pci_seg;
1087 iommu->mmio_phys = h->mmio_phys;
1088
1089 /* Check if IVHD EFR contains proper max banks/counters */
1090 if ((h->efr != 0) &&
1091 ((h->efr & (0xF << 13)) != 0) &&
1092 ((h->efr & (0x3F << 17)) != 0)) {
1093 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1094 } else {
1095 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1096 }
1097
1098 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1099 iommu->mmio_phys_end);
1100 if (!iommu->mmio_base)
1101 return -ENOMEM;
1102
1103 iommu->cmd_buf = alloc_command_buffer(iommu);
1104 if (!iommu->cmd_buf)
1105 return -ENOMEM;
1106
1107 iommu->evt_buf = alloc_event_buffer(iommu);
1108 if (!iommu->evt_buf)
1109 return -ENOMEM;
1110
1111 iommu->int_enabled = false;
1112
1113 ret = init_iommu_from_acpi(iommu, h);
1114 if (ret)
1115 return ret;
1116
1117 /*
1118 * Make sure IOMMU is not considered to translate itself. The IVRS
1119 * table tells us so, but this is a lie!
1120 */
1121 amd_iommu_rlookup_table[iommu->devid] = NULL;
1122
1123 init_iommu_devices(iommu);
1124
1125 return 0;
1126 }
1127
1128 /*
1129 * Iterates over all IOMMU entries in the ACPI table, allocates the
1130 * IOMMU structure and initializes it with init_iommu_one()
1131 */
1132 static int __init init_iommu_all(struct acpi_table_header *table)
1133 {
1134 u8 *p = (u8 *)table, *end = (u8 *)table;
1135 struct ivhd_header *h;
1136 struct amd_iommu *iommu;
1137 int ret;
1138
1139 end += table->length;
1140 p += IVRS_HEADER_LENGTH;
1141
1142 while (p < end) {
1143 h = (struct ivhd_header *)p;
1144 switch (*p) {
1145 case ACPI_IVHD_TYPE:
1146
1147 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1148 "seg: %d flags: %01x info %04x\n",
1149 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1150 PCI_FUNC(h->devid), h->cap_ptr,
1151 h->pci_seg, h->flags, h->info);
1152 DUMP_printk(" mmio-addr: %016llx\n",
1153 h->mmio_phys);
1154
1155 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1156 if (iommu == NULL)
1157 return -ENOMEM;
1158
1159 ret = init_iommu_one(iommu, h);
1160 if (ret)
1161 return ret;
1162 break;
1163 default:
1164 break;
1165 }
1166 p += h->length;
1167
1168 }
1169 WARN_ON(p != end);
1170
1171 return 0;
1172 }
1173
1174
1175 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1176 {
1177 u64 val = 0xabcd, val2 = 0;
1178
1179 if (!iommu_feature(iommu, FEATURE_PC))
1180 return;
1181
1182 amd_iommu_pc_present = true;
1183
1184 /* Check if the performance counters can be written to */
1185 if ((0 != amd_iommu_pc_get_set_reg_val(0, 0, 0, 0, &val, true)) ||
1186 (0 != amd_iommu_pc_get_set_reg_val(0, 0, 0, 0, &val2, false)) ||
1187 (val != val2)) {
1188 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1189 amd_iommu_pc_present = false;
1190 return;
1191 }
1192
1193 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1194
1195 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1196 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1197 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1198 }
1199
1200
1201 static int iommu_init_pci(struct amd_iommu *iommu)
1202 {
1203 int cap_ptr = iommu->cap_ptr;
1204 u32 range, misc, low, high;
1205
1206 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
1207 iommu->devid & 0xff);
1208 if (!iommu->dev)
1209 return -ENODEV;
1210
1211 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1212 &iommu->cap);
1213 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1214 &range);
1215 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1216 &misc);
1217
1218 iommu->first_device = PCI_DEVID(MMIO_GET_BUS(range),
1219 MMIO_GET_FD(range));
1220 iommu->last_device = PCI_DEVID(MMIO_GET_BUS(range),
1221 MMIO_GET_LD(range));
1222
1223 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1224 amd_iommu_iotlb_sup = false;
1225
1226 /* read extended feature bits */
1227 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1228 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1229
1230 iommu->features = ((u64)high << 32) | low;
1231
1232 if (iommu_feature(iommu, FEATURE_GT)) {
1233 int glxval;
1234 u32 pasids;
1235 u64 shift;
1236
1237 shift = iommu->features & FEATURE_PASID_MASK;
1238 shift >>= FEATURE_PASID_SHIFT;
1239 pasids = (1 << shift);
1240
1241 amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids);
1242
1243 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1244 glxval >>= FEATURE_GLXVAL_SHIFT;
1245
1246 if (amd_iommu_max_glx_val == -1)
1247 amd_iommu_max_glx_val = glxval;
1248 else
1249 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1250 }
1251
1252 if (iommu_feature(iommu, FEATURE_GT) &&
1253 iommu_feature(iommu, FEATURE_PPR)) {
1254 iommu->is_iommu_v2 = true;
1255 amd_iommu_v2_present = true;
1256 }
1257
1258 if (iommu_feature(iommu, FEATURE_PPR)) {
1259 iommu->ppr_log = alloc_ppr_log(iommu);
1260 if (!iommu->ppr_log)
1261 return -ENOMEM;
1262 }
1263
1264 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1265 amd_iommu_np_cache = true;
1266
1267 init_iommu_perf_ctr(iommu);
1268
1269 if (is_rd890_iommu(iommu->dev)) {
1270 int i, j;
1271
1272 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1273 PCI_DEVFN(0, 0));
1274
1275 /*
1276 * Some rd890 systems may not be fully reconfigured by the
1277 * BIOS, so it's necessary for us to store this information so
1278 * it can be reprogrammed on resume
1279 */
1280 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1281 &iommu->stored_addr_lo);
1282 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1283 &iommu->stored_addr_hi);
1284
1285 /* Low bit locks writes to configuration space */
1286 iommu->stored_addr_lo &= ~1;
1287
1288 for (i = 0; i < 6; i++)
1289 for (j = 0; j < 0x12; j++)
1290 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1291
1292 for (i = 0; i < 0x83; i++)
1293 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1294 }
1295
1296 amd_iommu_erratum_746_workaround(iommu);
1297
1298 return pci_enable_device(iommu->dev);
1299 }
1300
1301 static void print_iommu_info(void)
1302 {
1303 static const char * const feat_str[] = {
1304 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1305 "IA", "GA", "HE", "PC"
1306 };
1307 struct amd_iommu *iommu;
1308
1309 for_each_iommu(iommu) {
1310 int i;
1311
1312 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1313 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1314
1315 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1316 pr_info("AMD-Vi: Extended features: ");
1317 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1318 if (iommu_feature(iommu, (1ULL << i)))
1319 pr_cont(" %s", feat_str[i]);
1320 }
1321 pr_cont("\n");
1322 }
1323 }
1324 if (irq_remapping_enabled)
1325 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1326 }
1327
1328 static int __init amd_iommu_init_pci(void)
1329 {
1330 struct amd_iommu *iommu;
1331 int ret = 0;
1332
1333 for_each_iommu(iommu) {
1334 ret = iommu_init_pci(iommu);
1335 if (ret)
1336 break;
1337 }
1338
1339 ret = amd_iommu_init_devices();
1340
1341 print_iommu_info();
1342
1343 return ret;
1344 }
1345
1346 /****************************************************************************
1347 *
1348 * The following functions initialize the MSI interrupts for all IOMMUs
1349 * in the system. It's a bit challenging because there could be multiple
1350 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1351 * pci_dev.
1352 *
1353 ****************************************************************************/
1354
1355 static int iommu_setup_msi(struct amd_iommu *iommu)
1356 {
1357 int r;
1358
1359 r = pci_enable_msi(iommu->dev);
1360 if (r)
1361 return r;
1362
1363 r = request_threaded_irq(iommu->dev->irq,
1364 amd_iommu_int_handler,
1365 amd_iommu_int_thread,
1366 0, "AMD-Vi",
1367 iommu);
1368
1369 if (r) {
1370 pci_disable_msi(iommu->dev);
1371 return r;
1372 }
1373
1374 iommu->int_enabled = true;
1375
1376 return 0;
1377 }
1378
1379 static int iommu_init_msi(struct amd_iommu *iommu)
1380 {
1381 int ret;
1382
1383 if (iommu->int_enabled)
1384 goto enable_faults;
1385
1386 if (iommu->dev->msi_cap)
1387 ret = iommu_setup_msi(iommu);
1388 else
1389 ret = -ENODEV;
1390
1391 if (ret)
1392 return ret;
1393
1394 enable_faults:
1395 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1396
1397 if (iommu->ppr_log != NULL)
1398 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1399
1400 return 0;
1401 }
1402
1403 /****************************************************************************
1404 *
1405 * The next functions belong to the third pass of parsing the ACPI
1406 * table. In this last pass the memory mapping requirements are
1407 * gathered (like exclusion and unity mapping ranges).
1408 *
1409 ****************************************************************************/
1410
1411 static void __init free_unity_maps(void)
1412 {
1413 struct unity_map_entry *entry, *next;
1414
1415 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1416 list_del(&entry->list);
1417 kfree(entry);
1418 }
1419 }
1420
1421 /* called when we find an exclusion range definition in ACPI */
1422 static int __init init_exclusion_range(struct ivmd_header *m)
1423 {
1424 int i;
1425
1426 switch (m->type) {
1427 case ACPI_IVMD_TYPE:
1428 set_device_exclusion_range(m->devid, m);
1429 break;
1430 case ACPI_IVMD_TYPE_ALL:
1431 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1432 set_device_exclusion_range(i, m);
1433 break;
1434 case ACPI_IVMD_TYPE_RANGE:
1435 for (i = m->devid; i <= m->aux; ++i)
1436 set_device_exclusion_range(i, m);
1437 break;
1438 default:
1439 break;
1440 }
1441
1442 return 0;
1443 }
1444
1445 /* called for unity map ACPI definition */
1446 static int __init init_unity_map_range(struct ivmd_header *m)
1447 {
1448 struct unity_map_entry *e = NULL;
1449 char *s;
1450
1451 e = kzalloc(sizeof(*e), GFP_KERNEL);
1452 if (e == NULL)
1453 return -ENOMEM;
1454
1455 switch (m->type) {
1456 default:
1457 kfree(e);
1458 return 0;
1459 case ACPI_IVMD_TYPE:
1460 s = "IVMD_TYPEi\t\t\t";
1461 e->devid_start = e->devid_end = m->devid;
1462 break;
1463 case ACPI_IVMD_TYPE_ALL:
1464 s = "IVMD_TYPE_ALL\t\t";
1465 e->devid_start = 0;
1466 e->devid_end = amd_iommu_last_bdf;
1467 break;
1468 case ACPI_IVMD_TYPE_RANGE:
1469 s = "IVMD_TYPE_RANGE\t\t";
1470 e->devid_start = m->devid;
1471 e->devid_end = m->aux;
1472 break;
1473 }
1474 e->address_start = PAGE_ALIGN(m->range_start);
1475 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1476 e->prot = m->flags >> 1;
1477
1478 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1479 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1480 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1481 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
1482 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1483 e->address_start, e->address_end, m->flags);
1484
1485 list_add_tail(&e->list, &amd_iommu_unity_map);
1486
1487 return 0;
1488 }
1489
1490 /* iterates over all memory definitions we find in the ACPI table */
1491 static int __init init_memory_definitions(struct acpi_table_header *table)
1492 {
1493 u8 *p = (u8 *)table, *end = (u8 *)table;
1494 struct ivmd_header *m;
1495
1496 end += table->length;
1497 p += IVRS_HEADER_LENGTH;
1498
1499 while (p < end) {
1500 m = (struct ivmd_header *)p;
1501 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1502 init_exclusion_range(m);
1503 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1504 init_unity_map_range(m);
1505
1506 p += m->length;
1507 }
1508
1509 return 0;
1510 }
1511
1512 /*
1513 * Init the device table to not allow DMA access for devices and
1514 * suppress all page faults
1515 */
1516 static void init_device_table_dma(void)
1517 {
1518 u32 devid;
1519
1520 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1521 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1522 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1523 }
1524 }
1525
1526 static void __init uninit_device_table_dma(void)
1527 {
1528 u32 devid;
1529
1530 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1531 amd_iommu_dev_table[devid].data[0] = 0ULL;
1532 amd_iommu_dev_table[devid].data[1] = 0ULL;
1533 }
1534 }
1535
1536 static void init_device_table(void)
1537 {
1538 u32 devid;
1539
1540 if (!amd_iommu_irq_remap)
1541 return;
1542
1543 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1544 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1545 }
1546
1547 static void iommu_init_flags(struct amd_iommu *iommu)
1548 {
1549 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1550 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1551 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1552
1553 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1554 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1555 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1556
1557 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1558 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1559 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1560
1561 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1562 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1563 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1564
1565 /*
1566 * make IOMMU memory accesses cache coherent
1567 */
1568 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1569
1570 /* Set IOTLB invalidation timeout to 1s */
1571 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1572 }
1573
1574 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1575 {
1576 int i, j;
1577 u32 ioc_feature_control;
1578 struct pci_dev *pdev = iommu->root_pdev;
1579
1580 /* RD890 BIOSes may not have completely reconfigured the iommu */
1581 if (!is_rd890_iommu(iommu->dev) || !pdev)
1582 return;
1583
1584 /*
1585 * First, we need to ensure that the iommu is enabled. This is
1586 * controlled by a register in the northbridge
1587 */
1588
1589 /* Select Northbridge indirect register 0x75 and enable writing */
1590 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1591 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1592
1593 /* Enable the iommu */
1594 if (!(ioc_feature_control & 0x1))
1595 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1596
1597 /* Restore the iommu BAR */
1598 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1599 iommu->stored_addr_lo);
1600 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1601 iommu->stored_addr_hi);
1602
1603 /* Restore the l1 indirect regs for each of the 6 l1s */
1604 for (i = 0; i < 6; i++)
1605 for (j = 0; j < 0x12; j++)
1606 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1607
1608 /* Restore the l2 indirect regs */
1609 for (i = 0; i < 0x83; i++)
1610 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1611
1612 /* Lock PCI setup registers */
1613 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1614 iommu->stored_addr_lo | 1);
1615 }
1616
1617 /*
1618 * This function finally enables all IOMMUs found in the system after
1619 * they have been initialized
1620 */
1621 static void early_enable_iommus(void)
1622 {
1623 struct amd_iommu *iommu;
1624
1625 for_each_iommu(iommu) {
1626 iommu_disable(iommu);
1627 iommu_init_flags(iommu);
1628 iommu_set_device_table(iommu);
1629 iommu_enable_command_buffer(iommu);
1630 iommu_enable_event_buffer(iommu);
1631 iommu_set_exclusion_range(iommu);
1632 iommu_enable(iommu);
1633 iommu_flush_all_caches(iommu);
1634 }
1635 }
1636
1637 static void enable_iommus_v2(void)
1638 {
1639 struct amd_iommu *iommu;
1640
1641 for_each_iommu(iommu) {
1642 iommu_enable_ppr_log(iommu);
1643 iommu_enable_gt(iommu);
1644 }
1645 }
1646
1647 static void enable_iommus(void)
1648 {
1649 early_enable_iommus();
1650
1651 enable_iommus_v2();
1652 }
1653
1654 static void disable_iommus(void)
1655 {
1656 struct amd_iommu *iommu;
1657
1658 for_each_iommu(iommu)
1659 iommu_disable(iommu);
1660 }
1661
1662 /*
1663 * Suspend/Resume support
1664 * disable suspend until real resume implemented
1665 */
1666
1667 static void amd_iommu_resume(void)
1668 {
1669 struct amd_iommu *iommu;
1670
1671 for_each_iommu(iommu)
1672 iommu_apply_resume_quirks(iommu);
1673
1674 /* re-load the hardware */
1675 enable_iommus();
1676
1677 amd_iommu_enable_interrupts();
1678 }
1679
1680 static int amd_iommu_suspend(void)
1681 {
1682 /* disable IOMMUs to go out of the way for BIOS */
1683 disable_iommus();
1684
1685 return 0;
1686 }
1687
1688 static struct syscore_ops amd_iommu_syscore_ops = {
1689 .suspend = amd_iommu_suspend,
1690 .resume = amd_iommu_resume,
1691 };
1692
1693 static void __init free_on_init_error(void)
1694 {
1695 free_pages((unsigned long)irq_lookup_table,
1696 get_order(rlookup_table_size));
1697
1698 if (amd_iommu_irq_cache) {
1699 kmem_cache_destroy(amd_iommu_irq_cache);
1700 amd_iommu_irq_cache = NULL;
1701
1702 }
1703
1704 free_pages((unsigned long)amd_iommu_rlookup_table,
1705 get_order(rlookup_table_size));
1706
1707 free_pages((unsigned long)amd_iommu_alias_table,
1708 get_order(alias_table_size));
1709
1710 free_pages((unsigned long)amd_iommu_dev_table,
1711 get_order(dev_table_size));
1712
1713 free_iommu_all();
1714
1715 #ifdef CONFIG_GART_IOMMU
1716 /*
1717 * We failed to initialize the AMD IOMMU - try fallback to GART
1718 * if possible.
1719 */
1720 gart_iommu_init();
1721
1722 #endif
1723 }
1724
1725 /* SB IOAPIC is always on this device in AMD systems */
1726 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
1727
1728 static bool __init check_ioapic_information(void)
1729 {
1730 const char *fw_bug = FW_BUG;
1731 bool ret, has_sb_ioapic;
1732 int idx;
1733
1734 has_sb_ioapic = false;
1735 ret = false;
1736
1737 /*
1738 * If we have map overrides on the kernel command line the
1739 * messages in this function might not describe firmware bugs
1740 * anymore - so be careful
1741 */
1742 if (cmdline_maps)
1743 fw_bug = "";
1744
1745 for (idx = 0; idx < nr_ioapics; idx++) {
1746 int devid, id = mpc_ioapic_id(idx);
1747
1748 devid = get_ioapic_devid(id);
1749 if (devid < 0) {
1750 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
1751 fw_bug, id);
1752 ret = false;
1753 } else if (devid == IOAPIC_SB_DEVID) {
1754 has_sb_ioapic = true;
1755 ret = true;
1756 }
1757 }
1758
1759 if (!has_sb_ioapic) {
1760 /*
1761 * We expect the SB IOAPIC to be listed in the IVRS
1762 * table. The system timer is connected to the SB IOAPIC
1763 * and if we don't have it in the list the system will
1764 * panic at boot time. This situation usually happens
1765 * when the BIOS is buggy and provides us the wrong
1766 * device id for the IOAPIC in the system.
1767 */
1768 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
1769 }
1770
1771 if (!ret)
1772 pr_err("AMD-Vi: Disabling interrupt remapping\n");
1773
1774 return ret;
1775 }
1776
1777 static void __init free_dma_resources(void)
1778 {
1779 amd_iommu_uninit_devices();
1780
1781 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1782 get_order(MAX_DOMAIN_ID/8));
1783
1784 free_unity_maps();
1785 }
1786
1787 /*
1788 * This is the hardware init function for AMD IOMMU in the system.
1789 * This function is called either from amd_iommu_init or from the interrupt
1790 * remapping setup code.
1791 *
1792 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1793 * three times:
1794 *
1795 * 1 pass) Find the highest PCI device id the driver has to handle.
1796 * Upon this information the size of the data structures is
1797 * determined that needs to be allocated.
1798 *
1799 * 2 pass) Initialize the data structures just allocated with the
1800 * information in the ACPI table about available AMD IOMMUs
1801 * in the system. It also maps the PCI devices in the
1802 * system to specific IOMMUs
1803 *
1804 * 3 pass) After the basic data structures are allocated and
1805 * initialized we update them with information about memory
1806 * remapping requirements parsed out of the ACPI table in
1807 * this last pass.
1808 *
1809 * After everything is set up the IOMMUs are enabled and the necessary
1810 * hotplug and suspend notifiers are registered.
1811 */
1812 static int __init early_amd_iommu_init(void)
1813 {
1814 struct acpi_table_header *ivrs_base;
1815 acpi_size ivrs_size;
1816 acpi_status status;
1817 int i, ret = 0;
1818
1819 if (!amd_iommu_detected)
1820 return -ENODEV;
1821
1822 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1823 if (status == AE_NOT_FOUND)
1824 return -ENODEV;
1825 else if (ACPI_FAILURE(status)) {
1826 const char *err = acpi_format_exception(status);
1827 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1828 return -EINVAL;
1829 }
1830
1831 /*
1832 * First parse ACPI tables to find the largest Bus/Dev/Func
1833 * we need to handle. Upon this information the shared data
1834 * structures for the IOMMUs in the system will be allocated
1835 */
1836 ret = find_last_devid_acpi(ivrs_base);
1837 if (ret)
1838 goto out;
1839
1840 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1841 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1842 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1843
1844 /* Device table - directly used by all IOMMUs */
1845 ret = -ENOMEM;
1846 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1847 get_order(dev_table_size));
1848 if (amd_iommu_dev_table == NULL)
1849 goto out;
1850
1851 /*
1852 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1853 * IOMMU see for that device
1854 */
1855 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1856 get_order(alias_table_size));
1857 if (amd_iommu_alias_table == NULL)
1858 goto out;
1859
1860 /* IOMMU rlookup table - find the IOMMU for a specific device */
1861 amd_iommu_rlookup_table = (void *)__get_free_pages(
1862 GFP_KERNEL | __GFP_ZERO,
1863 get_order(rlookup_table_size));
1864 if (amd_iommu_rlookup_table == NULL)
1865 goto out;
1866
1867 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1868 GFP_KERNEL | __GFP_ZERO,
1869 get_order(MAX_DOMAIN_ID/8));
1870 if (amd_iommu_pd_alloc_bitmap == NULL)
1871 goto out;
1872
1873 /*
1874 * let all alias entries point to itself
1875 */
1876 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1877 amd_iommu_alias_table[i] = i;
1878
1879 /*
1880 * never allocate domain 0 because its used as the non-allocated and
1881 * error value placeholder
1882 */
1883 amd_iommu_pd_alloc_bitmap[0] = 1;
1884
1885 spin_lock_init(&amd_iommu_pd_lock);
1886
1887 /*
1888 * now the data structures are allocated and basically initialized
1889 * start the real acpi table scan
1890 */
1891 ret = init_iommu_all(ivrs_base);
1892 if (ret)
1893 goto out;
1894
1895 if (amd_iommu_irq_remap)
1896 amd_iommu_irq_remap = check_ioapic_information();
1897
1898 if (amd_iommu_irq_remap) {
1899 /*
1900 * Interrupt remapping enabled, create kmem_cache for the
1901 * remapping tables.
1902 */
1903 ret = -ENOMEM;
1904 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
1905 MAX_IRQS_PER_TABLE * sizeof(u32),
1906 IRQ_TABLE_ALIGNMENT,
1907 0, NULL);
1908 if (!amd_iommu_irq_cache)
1909 goto out;
1910
1911 irq_lookup_table = (void *)__get_free_pages(
1912 GFP_KERNEL | __GFP_ZERO,
1913 get_order(rlookup_table_size));
1914 if (!irq_lookup_table)
1915 goto out;
1916 }
1917
1918 ret = init_memory_definitions(ivrs_base);
1919 if (ret)
1920 goto out;
1921
1922 /* init the device table */
1923 init_device_table();
1924
1925 out:
1926 /* Don't leak any ACPI memory */
1927 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1928 ivrs_base = NULL;
1929
1930 return ret;
1931 }
1932
1933 static int amd_iommu_enable_interrupts(void)
1934 {
1935 struct amd_iommu *iommu;
1936 int ret = 0;
1937
1938 for_each_iommu(iommu) {
1939 ret = iommu_init_msi(iommu);
1940 if (ret)
1941 goto out;
1942 }
1943
1944 out:
1945 return ret;
1946 }
1947
1948 static bool detect_ivrs(void)
1949 {
1950 struct acpi_table_header *ivrs_base;
1951 acpi_size ivrs_size;
1952 acpi_status status;
1953
1954 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1955 if (status == AE_NOT_FOUND)
1956 return false;
1957 else if (ACPI_FAILURE(status)) {
1958 const char *err = acpi_format_exception(status);
1959 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1960 return false;
1961 }
1962
1963 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1964
1965 /* Make sure ACS will be enabled during PCI probe */
1966 pci_request_acs();
1967
1968 if (!disable_irq_remap)
1969 amd_iommu_irq_remap = true;
1970
1971 return true;
1972 }
1973
1974 static int amd_iommu_init_dma(void)
1975 {
1976 struct amd_iommu *iommu;
1977 int ret;
1978
1979 if (iommu_pass_through)
1980 ret = amd_iommu_init_passthrough();
1981 else
1982 ret = amd_iommu_init_dma_ops();
1983
1984 if (ret)
1985 return ret;
1986
1987 init_device_table_dma();
1988
1989 for_each_iommu(iommu)
1990 iommu_flush_all_caches(iommu);
1991
1992 amd_iommu_init_api();
1993
1994 amd_iommu_init_notifier();
1995
1996 return 0;
1997 }
1998
1999 /****************************************************************************
2000 *
2001 * AMD IOMMU Initialization State Machine
2002 *
2003 ****************************************************************************/
2004
2005 static int __init state_next(void)
2006 {
2007 int ret = 0;
2008
2009 switch (init_state) {
2010 case IOMMU_START_STATE:
2011 if (!detect_ivrs()) {
2012 init_state = IOMMU_NOT_FOUND;
2013 ret = -ENODEV;
2014 } else {
2015 init_state = IOMMU_IVRS_DETECTED;
2016 }
2017 break;
2018 case IOMMU_IVRS_DETECTED:
2019 ret = early_amd_iommu_init();
2020 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2021 break;
2022 case IOMMU_ACPI_FINISHED:
2023 early_enable_iommus();
2024 register_syscore_ops(&amd_iommu_syscore_ops);
2025 x86_platform.iommu_shutdown = disable_iommus;
2026 init_state = IOMMU_ENABLED;
2027 break;
2028 case IOMMU_ENABLED:
2029 ret = amd_iommu_init_pci();
2030 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2031 enable_iommus_v2();
2032 break;
2033 case IOMMU_PCI_INIT:
2034 ret = amd_iommu_enable_interrupts();
2035 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2036 break;
2037 case IOMMU_INTERRUPTS_EN:
2038 ret = amd_iommu_init_dma();
2039 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2040 break;
2041 case IOMMU_DMA_OPS:
2042 init_state = IOMMU_INITIALIZED;
2043 break;
2044 case IOMMU_INITIALIZED:
2045 /* Nothing to do */
2046 break;
2047 case IOMMU_NOT_FOUND:
2048 case IOMMU_INIT_ERROR:
2049 /* Error states => do nothing */
2050 ret = -EINVAL;
2051 break;
2052 default:
2053 /* Unknown state */
2054 BUG();
2055 }
2056
2057 return ret;
2058 }
2059
2060 static int __init iommu_go_to_state(enum iommu_init_state state)
2061 {
2062 int ret = 0;
2063
2064 while (init_state != state) {
2065 ret = state_next();
2066 if (init_state == IOMMU_NOT_FOUND ||
2067 init_state == IOMMU_INIT_ERROR)
2068 break;
2069 }
2070
2071 return ret;
2072 }
2073
2074 #ifdef CONFIG_IRQ_REMAP
2075 int __init amd_iommu_prepare(void)
2076 {
2077 return iommu_go_to_state(IOMMU_ACPI_FINISHED);
2078 }
2079
2080 int __init amd_iommu_supported(void)
2081 {
2082 return amd_iommu_irq_remap ? 1 : 0;
2083 }
2084
2085 int __init amd_iommu_enable(void)
2086 {
2087 int ret;
2088
2089 ret = iommu_go_to_state(IOMMU_ENABLED);
2090 if (ret)
2091 return ret;
2092
2093 irq_remapping_enabled = 1;
2094
2095 return 0;
2096 }
2097
2098 void amd_iommu_disable(void)
2099 {
2100 amd_iommu_suspend();
2101 }
2102
2103 int amd_iommu_reenable(int mode)
2104 {
2105 amd_iommu_resume();
2106
2107 return 0;
2108 }
2109
2110 int __init amd_iommu_enable_faulting(void)
2111 {
2112 /* We enable MSI later when PCI is initialized */
2113 return 0;
2114 }
2115 #endif
2116
2117 /*
2118 * This is the core init function for AMD IOMMU hardware in the system.
2119 * This function is called from the generic x86 DMA layer initialization
2120 * code.
2121 */
2122 static int __init amd_iommu_init(void)
2123 {
2124 int ret;
2125
2126 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2127 if (ret) {
2128 free_dma_resources();
2129 if (!irq_remapping_enabled) {
2130 disable_iommus();
2131 free_on_init_error();
2132 } else {
2133 struct amd_iommu *iommu;
2134
2135 uninit_device_table_dma();
2136 for_each_iommu(iommu)
2137 iommu_flush_all_caches(iommu);
2138 }
2139 }
2140
2141 return ret;
2142 }
2143
2144 /****************************************************************************
2145 *
2146 * Early detect code. This code runs at IOMMU detection time in the DMA
2147 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2148 * IOMMUs
2149 *
2150 ****************************************************************************/
2151 int __init amd_iommu_detect(void)
2152 {
2153 int ret;
2154
2155 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2156 return -ENODEV;
2157
2158 if (amd_iommu_disabled)
2159 return -ENODEV;
2160
2161 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2162 if (ret)
2163 return ret;
2164
2165 amd_iommu_detected = true;
2166 iommu_detected = 1;
2167 x86_init.iommu.iommu_init = amd_iommu_init;
2168
2169 return 0;
2170 }
2171
2172 /****************************************************************************
2173 *
2174 * Parsing functions for the AMD IOMMU specific kernel command line
2175 * options.
2176 *
2177 ****************************************************************************/
2178
2179 static int __init parse_amd_iommu_dump(char *str)
2180 {
2181 amd_iommu_dump = true;
2182
2183 return 1;
2184 }
2185
2186 static int __init parse_amd_iommu_options(char *str)
2187 {
2188 for (; *str; ++str) {
2189 if (strncmp(str, "fullflush", 9) == 0)
2190 amd_iommu_unmap_flush = true;
2191 if (strncmp(str, "off", 3) == 0)
2192 amd_iommu_disabled = true;
2193 if (strncmp(str, "force_isolation", 15) == 0)
2194 amd_iommu_force_isolation = true;
2195 }
2196
2197 return 1;
2198 }
2199
2200 static int __init parse_ivrs_ioapic(char *str)
2201 {
2202 unsigned int bus, dev, fn;
2203 int ret, id, i;
2204 u16 devid;
2205
2206 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2207
2208 if (ret != 4) {
2209 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2210 return 1;
2211 }
2212
2213 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2214 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2215 str);
2216 return 1;
2217 }
2218
2219 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2220
2221 cmdline_maps = true;
2222 i = early_ioapic_map_size++;
2223 early_ioapic_map[i].id = id;
2224 early_ioapic_map[i].devid = devid;
2225 early_ioapic_map[i].cmd_line = true;
2226
2227 return 1;
2228 }
2229
2230 static int __init parse_ivrs_hpet(char *str)
2231 {
2232 unsigned int bus, dev, fn;
2233 int ret, id, i;
2234 u16 devid;
2235
2236 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2237
2238 if (ret != 4) {
2239 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2240 return 1;
2241 }
2242
2243 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2244 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2245 str);
2246 return 1;
2247 }
2248
2249 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2250
2251 cmdline_maps = true;
2252 i = early_hpet_map_size++;
2253 early_hpet_map[i].id = id;
2254 early_hpet_map[i].devid = devid;
2255 early_hpet_map[i].cmd_line = true;
2256
2257 return 1;
2258 }
2259
2260 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2261 __setup("amd_iommu=", parse_amd_iommu_options);
2262 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2263 __setup("ivrs_hpet", parse_ivrs_hpet);
2264
2265 IOMMU_INIT_FINISH(amd_iommu_detect,
2266 gart_iommu_hole_init,
2267 NULL,
2268 NULL);
2269
2270 bool amd_iommu_v2_supported(void)
2271 {
2272 return amd_iommu_v2_present;
2273 }
2274 EXPORT_SYMBOL(amd_iommu_v2_supported);
2275
2276 /****************************************************************************
2277 *
2278 * IOMMU EFR Performance Counter support functionality. This code allows
2279 * access to the IOMMU PC functionality.
2280 *
2281 ****************************************************************************/
2282
2283 u8 amd_iommu_pc_get_max_banks(u16 devid)
2284 {
2285 struct amd_iommu *iommu;
2286 u8 ret = 0;
2287
2288 /* locate the iommu governing the devid */
2289 iommu = amd_iommu_rlookup_table[devid];
2290 if (iommu)
2291 ret = iommu->max_banks;
2292
2293 return ret;
2294 }
2295 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2296
2297 bool amd_iommu_pc_supported(void)
2298 {
2299 return amd_iommu_pc_present;
2300 }
2301 EXPORT_SYMBOL(amd_iommu_pc_supported);
2302
2303 u8 amd_iommu_pc_get_max_counters(u16 devid)
2304 {
2305 struct amd_iommu *iommu;
2306 u8 ret = 0;
2307
2308 /* locate the iommu governing the devid */
2309 iommu = amd_iommu_rlookup_table[devid];
2310 if (iommu)
2311 ret = iommu->max_counters;
2312
2313 return ret;
2314 }
2315 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2316
2317 int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
2318 u64 *value, bool is_write)
2319 {
2320 struct amd_iommu *iommu;
2321 u32 offset;
2322 u32 max_offset_lim;
2323
2324 /* Make sure the IOMMU PC resource is available */
2325 if (!amd_iommu_pc_present)
2326 return -ENODEV;
2327
2328 /* Locate the iommu associated with the device ID */
2329 iommu = amd_iommu_rlookup_table[devid];
2330
2331 /* Check for valid iommu and pc register indexing */
2332 if (WARN_ON((iommu == NULL) || (fxn > 0x28) || (fxn & 7)))
2333 return -ENODEV;
2334
2335 offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
2336
2337 /* Limit the offset to the hw defined mmio region aperture */
2338 max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) |
2339 (iommu->max_counters << 8) | 0x28);
2340 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2341 (offset > max_offset_lim))
2342 return -EINVAL;
2343
2344 if (is_write) {
2345 writel((u32)*value, iommu->mmio_base + offset);
2346 writel((*value >> 32), iommu->mmio_base + offset + 4);
2347 } else {
2348 *value = readl(iommu->mmio_base + offset + 4);
2349 *value <<= 32;
2350 *value = readl(iommu->mmio_base + offset);
2351 }
2352
2353 return 0;
2354 }
2355 EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);
Linux kernel - Deliverables
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