drivers/iommu/amd_iommu_types.h

   1 /*
   2  * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
   3  * Author: Joerg Roedel <joerg.roedel@amd.com>
   4  *         Leo Duran <leo.duran@amd.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
  21 #define _ASM_X86_AMD_IOMMU_TYPES_H
  22
  23 #include <linux/types.h>
  24 #include <linux/mutex.h>
  25 #include <linux/list.h>
  26 #include <linux/spinlock.h>
  27
  28 /*
  29  * Maximum number of IOMMUs supported
  30  */
  31 #define MAX_IOMMUS      32
  32
  33 /*
  34  * some size calculation constants
  35  */
  36 #define DEV_TABLE_ENTRY_SIZE            32
  37 #define ALIAS_TABLE_ENTRY_SIZE          2
  38 #define RLOOKUP_TABLE_ENTRY_SIZE        (sizeof(void *))
  39
  40 /* Length of the MMIO region for the AMD IOMMU */
  41 #define MMIO_REGION_LENGTH       0x4000
  42
  43 /* Capability offsets used by the driver */
  44 #define MMIO_CAP_HDR_OFFSET     0x00
  45 #define MMIO_RANGE_OFFSET       0x0c
  46 #define MMIO_MISC_OFFSET        0x10
  47
  48 /* Masks, shifts and macros to parse the device range capability */
  49 #define MMIO_RANGE_LD_MASK      0xff000000
  50 #define MMIO_RANGE_FD_MASK      0x00ff0000
  51 #define MMIO_RANGE_BUS_MASK     0x0000ff00
  52 #define MMIO_RANGE_LD_SHIFT     24
  53 #define MMIO_RANGE_FD_SHIFT     16
  54 #define MMIO_RANGE_BUS_SHIFT    8
  55 #define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
  56 #define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
  57 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
  58 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
  59
  60 /* Flag masks for the AMD IOMMU exclusion range */
  61 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
  62 #define MMIO_EXCL_ALLOW_MASK  0x02ULL
  63
  64 /* Used offsets into the MMIO space */
  65 #define MMIO_DEV_TABLE_OFFSET   0x0000
  66 #define MMIO_CMD_BUF_OFFSET     0x0008
  67 #define MMIO_EVT_BUF_OFFSET     0x0010
  68 #define MMIO_CONTROL_OFFSET     0x0018
  69 #define MMIO_EXCL_BASE_OFFSET   0x0020
  70 #define MMIO_EXCL_LIMIT_OFFSET  0x0028
  71 #define MMIO_EXT_FEATURES       0x0030
  72 #define MMIO_PPR_LOG_OFFSET     0x0038
  73 #define MMIO_CMD_HEAD_OFFSET    0x2000
  74 #define MMIO_CMD_TAIL_OFFSET    0x2008
  75 #define MMIO_EVT_HEAD_OFFSET    0x2010
  76 #define MMIO_EVT_TAIL_OFFSET    0x2018
  77 #define MMIO_STATUS_OFFSET      0x2020
  78 #define MMIO_PPR_HEAD_OFFSET    0x2030
  79 #define MMIO_PPR_TAIL_OFFSET    0x2038
  80
  81
  82 /* Extended Feature Bits */
  83 #define FEATURE_PREFETCH        (1ULL<<0)
  84 #define FEATURE_PPR             (1ULL<<1)
  85 #define FEATURE_X2APIC          (1ULL<<2)
  86 #define FEATURE_NX              (1ULL<<3)
  87 #define FEATURE_GT              (1ULL<<4)
  88 #define FEATURE_IA              (1ULL<<6)
  89 #define FEATURE_GA              (1ULL<<7)
  90 #define FEATURE_HE              (1ULL<<8)
  91 #define FEATURE_PC              (1ULL<<9)
  92
  93 #define FEATURE_PASID_SHIFT     32
  94 #define FEATURE_PASID_MASK      (0x1fULL << FEATURE_PASID_SHIFT)
  95
  96 /* MMIO status bits */
  97 #define MMIO_STATUS_COM_WAIT_INT_MASK   0x04
  98
  99 /* event logging constants */
 100 #define EVENT_ENTRY_SIZE        0x10
 101 #define EVENT_TYPE_SHIFT        28
 102 #define EVENT_TYPE_MASK         0xf
 103 #define EVENT_TYPE_ILL_DEV      0x1
 104 #define EVENT_TYPE_IO_FAULT     0x2
 105 #define EVENT_TYPE_DEV_TAB_ERR  0x3
 106 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
 107 #define EVENT_TYPE_ILL_CMD      0x5
 108 #define EVENT_TYPE_CMD_HARD_ERR 0x6
 109 #define EVENT_TYPE_IOTLB_INV_TO 0x7
 110 #define EVENT_TYPE_INV_DEV_REQ  0x8
 111 #define EVENT_DEVID_MASK        0xffff
 112 #define EVENT_DEVID_SHIFT       0
 113 #define EVENT_DOMID_MASK        0xffff
 114 #define EVENT_DOMID_SHIFT       0
 115 #define EVENT_FLAGS_MASK        0xfff
 116 #define EVENT_FLAGS_SHIFT       0x10
 117
 118 /* feature control bits */
 119 #define CONTROL_IOMMU_EN        0x00ULL
 120 #define CONTROL_HT_TUN_EN       0x01ULL
 121 #define CONTROL_EVT_LOG_EN      0x02ULL
 122 #define CONTROL_EVT_INT_EN      0x03ULL
 123 #define CONTROL_COMWAIT_EN      0x04ULL
 124 #define CONTROL_PASSPW_EN       0x08ULL
 125 #define CONTROL_RESPASSPW_EN    0x09ULL
 126 #define CONTROL_COHERENT_EN     0x0aULL
 127 #define CONTROL_ISOC_EN         0x0bULL
 128 #define CONTROL_CMDBUF_EN       0x0cULL
 129 #define CONTROL_PPFLOG_EN       0x0dULL
 130 #define CONTROL_PPFINT_EN       0x0eULL
 131 #define CONTROL_PPR_EN          0x0fULL
 132 #define CONTROL_GT_EN           0x10ULL
 133
 134 /* command specific defines */
 135 #define CMD_COMPL_WAIT          0x01
 136 #define CMD_INV_DEV_ENTRY       0x02
 137 #define CMD_INV_IOMMU_PAGES     0x03
 138 #define CMD_INV_IOTLB_PAGES     0x04
 139 #define CMD_INV_ALL             0x08
 140
 141 #define CMD_COMPL_WAIT_STORE_MASK       0x01
 142 #define CMD_COMPL_WAIT_INT_MASK         0x02
 143 #define CMD_INV_IOMMU_PAGES_SIZE_MASK   0x01
 144 #define CMD_INV_IOMMU_PAGES_PDE_MASK    0x02
 145
 146 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
 147
 148 /* macros and definitions for device table entries */
 149 #define DEV_ENTRY_VALID         0x00
 150 #define DEV_ENTRY_TRANSLATION   0x01
 151 #define DEV_ENTRY_IR            0x3d
 152 #define DEV_ENTRY_IW            0x3e
 153 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
 154 #define DEV_ENTRY_EX            0x67
 155 #define DEV_ENTRY_SYSMGT1       0x68
 156 #define DEV_ENTRY_SYSMGT2       0x69
 157 #define DEV_ENTRY_INIT_PASS     0xb8
 158 #define DEV_ENTRY_EINT_PASS     0xb9
 159 #define DEV_ENTRY_NMI_PASS      0xba
 160 #define DEV_ENTRY_LINT0_PASS    0xbe
 161 #define DEV_ENTRY_LINT1_PASS    0xbf
 162 #define DEV_ENTRY_MODE_MASK     0x07
 163 #define DEV_ENTRY_MODE_SHIFT    0x09
 164
 165 /* constants to configure the command buffer */
 166 #define CMD_BUFFER_SIZE    8192
 167 #define CMD_BUFFER_UNINITIALIZED 1
 168 #define CMD_BUFFER_ENTRIES 512
 169 #define MMIO_CMD_SIZE_SHIFT 56
 170 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
 171
 172 /* constants for event buffer handling */
 173 #define EVT_BUFFER_SIZE         8192 /* 512 entries */
 174 #define EVT_LEN_MASK            (0x9ULL << 56)
 175
 176 /* Constants for PPR Log handling */
 177 #define PPR_LOG_ENTRIES         512
 178 #define PPR_LOG_SIZE_SHIFT      56
 179 #define PPR_LOG_SIZE_512        (0x9ULL << PPR_LOG_SIZE_SHIFT)
 180 #define PPR_ENTRY_SIZE          16
 181 #define PPR_LOG_SIZE            (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
 182
 183 #define PAGE_MODE_NONE    0x00
 184 #define PAGE_MODE_1_LEVEL 0x01
 185 #define PAGE_MODE_2_LEVEL 0x02
 186 #define PAGE_MODE_3_LEVEL 0x03
 187 #define PAGE_MODE_4_LEVEL 0x04
 188 #define PAGE_MODE_5_LEVEL 0x05
 189 #define PAGE_MODE_6_LEVEL 0x06
 190
 191 #define PM_LEVEL_SHIFT(x)       (12 + ((x) * 9))
 192 #define PM_LEVEL_SIZE(x)        (((x) < 6) ? \
 193                                   ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
 194                                    (0xffffffffffffffffULL))
 195 #define PM_LEVEL_INDEX(x, a)    (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
 196 #define PM_LEVEL_ENC(x)         (((x) << 9) & 0xe00ULL)
 197 #define PM_LEVEL_PDE(x, a)      ((a) | PM_LEVEL_ENC((x)) | \
 198                                  IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
 199 #define PM_PTE_LEVEL(pte)       (((pte) >> 9) & 0x7ULL)
 200
 201 #define PM_MAP_4k               0
 202 #define PM_ADDR_MASK            0x000ffffffffff000ULL
 203 #define PM_MAP_MASK(lvl)        (PM_ADDR_MASK & \
 204                                 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
 205 #define PM_ALIGNED(lvl, addr)   ((PM_MAP_MASK(lvl) & (addr)) == (addr))
 206
 207 /*
 208  * Returns the page table level to use for a given page size
 209  * Pagesize is expected to be a power-of-two
 210  */
 211 #define PAGE_SIZE_LEVEL(pagesize) \
 212                 ((__ffs(pagesize) - 12) / 9)
 213 /*
 214  * Returns the number of ptes to use for a given page size
 215  * Pagesize is expected to be a power-of-two
 216  */
 217 #define PAGE_SIZE_PTE_COUNT(pagesize) \
 218                 (1ULL << ((__ffs(pagesize) - 12) % 9))
 219
 220 /*
 221  * Aligns a given io-virtual address to a given page size
 222  * Pagesize is expected to be a power-of-two
 223  */
 224 #define PAGE_SIZE_ALIGN(address, pagesize) \
 225                 ((address) & ~((pagesize) - 1))
 226 /*
 227  * Creates an IOMMU PTE for an address an a given pagesize
 228  * The PTE has no permission bits set
 229  * Pagesize is expected to be a power-of-two larger than 4096
 230  */
 231 #define PAGE_SIZE_PTE(address, pagesize)                \
 232                 (((address) | ((pagesize) - 1)) &       \
 233                  (~(pagesize >> 1)) & PM_ADDR_MASK)
 234
 235 /*
 236  * Takes a PTE value with mode=0x07 and returns the page size it maps
 237  */
 238 #define PTE_PAGE_SIZE(pte) \
 239         (1ULL << (1 + ffz(((pte) | 0xfffULL))))
 240
 241 #define IOMMU_PTE_P  (1ULL << 0)
 242 #define IOMMU_PTE_TV (1ULL << 1)
 243 #define IOMMU_PTE_U  (1ULL << 59)
 244 #define IOMMU_PTE_FC (1ULL << 60)
 245 #define IOMMU_PTE_IR (1ULL << 61)
 246 #define IOMMU_PTE_IW (1ULL << 62)
 247
 248 #define DTE_FLAG_IOTLB  (0x01UL << 32)
 249
 250 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
 251 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
 252 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
 253 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
 254
 255 #define IOMMU_PROT_MASK 0x03
 256 #define IOMMU_PROT_IR 0x01
 257 #define IOMMU_PROT_IW 0x02
 258
 259 /* IOMMU capabilities */
 260 #define IOMMU_CAP_IOTLB   24
 261 #define IOMMU_CAP_NPCACHE 26
 262 #define IOMMU_CAP_EFR     27
 263
 264 #define MAX_DOMAIN_ID 65536
 265
 266 /* FIXME: move this macro to <linux/pci.h> */
 267 #define PCI_BUS(x) (((x) >> 8) & 0xff)
 268
 269 /* Protection domain flags */
 270 #define PD_DMA_OPS_MASK         (1UL << 0) /* domain used for dma_ops */
 271 #define PD_DEFAULT_MASK         (1UL << 1) /* domain is a default dma_ops
 272                                               domain for an IOMMU */
 273 #define PD_PASSTHROUGH_MASK     (1UL << 2) /* domain has no page
 274                                               translation */
 275
 276 extern bool amd_iommu_dump;
 277 #define DUMP_printk(format, arg...)                                     \
 278         do {                                                            \
 279                 if (amd_iommu_dump)                                             \
 280                         printk(KERN_INFO "AMD-Vi: " format, ## arg);    \
 281         } while(0);
 282
 283 /* global flag if IOMMUs cache non-present entries */
 284 extern bool amd_iommu_np_cache;
 285 /* Only true if all IOMMUs support device IOTLBs */
 286 extern bool amd_iommu_iotlb_sup;
 287
 288 /*
 289  * Make iterating over all IOMMUs easier
 290  */
 291 #define for_each_iommu(iommu) \
 292         list_for_each_entry((iommu), &amd_iommu_list, list)
 293 #define for_each_iommu_safe(iommu, next) \
 294         list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
 295
 296 #define APERTURE_RANGE_SHIFT    27      /* 128 MB */
 297 #define APERTURE_RANGE_SIZE     (1ULL << APERTURE_RANGE_SHIFT)
 298 #define APERTURE_RANGE_PAGES    (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
 299 #define APERTURE_MAX_RANGES     32      /* allows 4GB of DMA address space */
 300 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
 301 #define APERTURE_PAGE_INDEX(a)  (((a) >> 21) & 0x3fULL)
 302
 303 /*
 304  * This structure contains generic data for  IOMMU protection domains
 305  * independent of their use.
 306  */
 307 struct protection_domain {
 308         struct list_head list;  /* for list of all protection domains */
 309         struct list_head dev_list; /* List of all devices in this domain */
 310         spinlock_t lock;        /* mostly used to lock the page table*/
 311         struct mutex api_lock;  /* protect page tables in the iommu-api path */
 312         u16 id;                 /* the domain id written to the device table */
 313         int mode;               /* paging mode (0-6 levels) */
 314         u64 *pt_root;           /* page table root pointer */
 315         unsigned long flags;    /* flags to find out type of domain */
 316         bool updated;           /* complete domain flush required */
 317         unsigned dev_cnt;       /* devices assigned to this domain */
 318         unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
 319         void *priv;             /* private data */
 320
 321 };
 322
 323 /*
 324  * This struct contains device specific data for the IOMMU
 325  */
 326 struct iommu_dev_data {
 327         struct list_head list;            /* For domain->dev_list */
 328         struct list_head dev_data_list;   /* For global dev_data_list */
 329         struct iommu_dev_data *alias_data;/* The alias dev_data */
 330         struct protection_domain *domain; /* Domain the device is bound to */
 331         atomic_t bind;                    /* Domain attach reverent count */
 332         u16 devid;                        /* PCI Device ID */
 333         struct {
 334                 bool enabled;
 335                 int qdep;
 336         } ats;                            /* ATS state */
 337 };
 338
 339 /*
 340  * For dynamic growth the aperture size is split into ranges of 128MB of
 341  * DMA address space each. This struct represents one such range.
 342  */
 343 struct aperture_range {
 344
 345         /* address allocation bitmap */
 346         unsigned long *bitmap;
 347
 348         /*
 349          * Array of PTE pages for the aperture. In this array we save all the
 350          * leaf pages of the domain page table used for the aperture. This way
 351          * we don't need to walk the page table to find a specific PTE. We can
 352          * just calculate its address in constant time.
 353          */
 354         u64 *pte_pages[64];
 355
 356         unsigned long offset;
 357 };
 358
 359 /*
 360  * Data container for a dma_ops specific protection domain
 361  */
 362 struct dma_ops_domain {
 363         struct list_head list;
 364
 365         /* generic protection domain information */
 366         struct protection_domain domain;
 367
 368         /* size of the aperture for the mappings */
 369         unsigned long aperture_size;
 370
 371         /* address we start to search for free addresses */
 372         unsigned long next_address;
 373
 374         /* address space relevant data */
 375         struct aperture_range *aperture[APERTURE_MAX_RANGES];
 376
 377         /* This will be set to true when TLB needs to be flushed */
 378         bool need_flush;
 379
 380         /*
 381          * if this is a preallocated domain, keep the device for which it was
 382          * preallocated in this variable
 383          */
 384         u16 target_dev;
 385 };
 386
 387 /*
 388  * Structure where we save information about one hardware AMD IOMMU in the
 389  * system.
 390  */
 391 struct amd_iommu {
 392         struct list_head list;
 393
 394         /* Index within the IOMMU array */
 395         int index;
 396
 397         /* locks the accesses to the hardware */
 398         spinlock_t lock;
 399
 400         /* Pointer to PCI device of this IOMMU */
 401         struct pci_dev *dev;
 402
 403         /* physical address of MMIO space */
 404         u64 mmio_phys;
 405         /* virtual address of MMIO space */
 406         u8 *mmio_base;
 407
 408         /* capabilities of that IOMMU read from ACPI */
 409         u32 cap;
 410
 411         /* flags read from acpi table */
 412         u8 acpi_flags;
 413
 414         /* Extended features */
 415         u64 features;
 416
 417         /* IOMMUv2 */
 418         bool is_iommu_v2;
 419
 420         /*
 421          * Capability pointer. There could be more than one IOMMU per PCI
 422          * device function if there are more than one AMD IOMMU capability
 423          * pointers.
 424          */
 425         u16 cap_ptr;
 426
 427         /* pci domain of this IOMMU */
 428         u16 pci_seg;
 429
 430         /* first device this IOMMU handles. read from PCI */
 431         u16 first_device;
 432         /* last device this IOMMU handles. read from PCI */
 433         u16 last_device;
 434
 435         /* start of exclusion range of that IOMMU */
 436         u64 exclusion_start;
 437         /* length of exclusion range of that IOMMU */
 438         u64 exclusion_length;
 439
 440         /* command buffer virtual address */
 441         u8 *cmd_buf;
 442         /* size of command buffer */
 443         u32 cmd_buf_size;
 444
 445         /* size of event buffer */
 446         u32 evt_buf_size;
 447         /* event buffer virtual address */
 448         u8 *evt_buf;
 449         /* MSI number for event interrupt */
 450         u16 evt_msi_num;
 451
 452         /* Base of the PPR log, if present */
 453         u8 *ppr_log;
 454
 455         /* true if interrupts for this IOMMU are already enabled */
 456         bool int_enabled;
 457
 458         /* if one, we need to send a completion wait command */
 459         bool need_sync;
 460
 461         /* default dma_ops domain for that IOMMU */
 462         struct dma_ops_domain *default_dom;
 463
 464         /*
 465          * We can't rely on the BIOS to restore all values on reinit, so we
 466          * need to stash them
 467          */
 468
 469         /* The iommu BAR */
 470         u32 stored_addr_lo;
 471         u32 stored_addr_hi;
 472
 473         /*
 474          * Each iommu has 6 l1s, each of which is documented as having 0x12
 475          * registers
 476          */
 477         u32 stored_l1[6][0x12];
 478
 479         /* The l2 indirect registers */
 480         u32 stored_l2[0x83];
 481 };
 482
 483 /*
 484  * List with all IOMMUs in the system. This list is not locked because it is
 485  * only written and read at driver initialization or suspend time
 486  */
 487 extern struct list_head amd_iommu_list;
 488
 489 /*
 490  * Array with pointers to each IOMMU struct
 491  * The indices are referenced in the protection domains
 492  */
 493 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
 494
 495 /* Number of IOMMUs present in the system */
 496 extern int amd_iommus_present;
 497
 498 /*
 499  * Declarations for the global list of all protection domains
 500  */
 501 extern spinlock_t amd_iommu_pd_lock;
 502 extern struct list_head amd_iommu_pd_list;
 503
 504 /*
 505  * Structure defining one entry in the device table
 506  */
 507 struct dev_table_entry {
 508         u64 data[4];
 509 };
 510
 511 /*
 512  * One entry for unity mappings parsed out of the ACPI table.
 513  */
 514 struct unity_map_entry {
 515         struct list_head list;
 516
 517         /* starting device id this entry is used for (including) */
 518         u16 devid_start;
 519         /* end device id this entry is used for (including) */
 520         u16 devid_end;
 521
 522         /* start address to unity map (including) */
 523         u64 address_start;
 524         /* end address to unity map (including) */
 525         u64 address_end;
 526
 527         /* required protection */
 528         int prot;
 529 };
 530
 531 /*
 532  * List of all unity mappings. It is not locked because as runtime it is only
 533  * read. It is created at ACPI table parsing time.
 534  */
 535 extern struct list_head amd_iommu_unity_map;
 536
 537 /*
 538  * Data structures for device handling
 539  */
 540
 541 /*
 542  * Device table used by hardware. Read and write accesses by software are
 543  * locked with the amd_iommu_pd_table lock.
 544  */
 545 extern struct dev_table_entry *amd_iommu_dev_table;
 546
 547 /*
 548  * Alias table to find requestor ids to device ids. Not locked because only
 549  * read on runtime.
 550  */
 551 extern u16 *amd_iommu_alias_table;
 552
 553 /*
 554  * Reverse lookup table to find the IOMMU which translates a specific device.
 555  */
 556 extern struct amd_iommu **amd_iommu_rlookup_table;
 557
 558 /* size of the dma_ops aperture as power of 2 */
 559 extern unsigned amd_iommu_aperture_order;
 560
 561 /* largest PCI device id we expect translation requests for */
 562 extern u16 amd_iommu_last_bdf;
 563
 564 /* allocation bitmap for domain ids */
 565 extern unsigned long *amd_iommu_pd_alloc_bitmap;
 566
 567 /*
 568  * If true, the addresses will be flushed on unmap time, not when
 569  * they are reused
 570  */
 571 extern bool amd_iommu_unmap_flush;
 572
 573 /* Smallest number of PASIDs supported by any IOMMU in the system */
 574 extern u32 amd_iommu_max_pasids;
 575
 576 extern bool amd_iommu_v2_present;
 577
 578 /* takes bus and device/function and returns the device id
 579  * FIXME: should that be in generic PCI code? */
 580 static inline u16 calc_devid(u8 bus, u8 devfn)
 581 {
 582         return (((u16)bus) << 8) | devfn;
 583 }
 584
 585 #ifdef CONFIG_AMD_IOMMU_STATS
 586
 587 struct __iommu_counter {
 588         char *name;
 589         struct dentry *dent;
 590         u64 value;
 591 };
 592
 593 #define DECLARE_STATS_COUNTER(nm) \
 594         static struct __iommu_counter nm = {    \
 595                 .name = #nm,                    \
 596         }
 597
 598 #define INC_STATS_COUNTER(name)         name.value += 1
 599 #define ADD_STATS_COUNTER(name, x)      name.value += (x)
 600 #define SUB_STATS_COUNTER(name, x)      name.value -= (x)
 601
 602 #else /* CONFIG_AMD_IOMMU_STATS */
 603
 604 #define DECLARE_STATS_COUNTER(name)
 605 #define INC_STATS_COUNTER(name)
 606 #define ADD_STATS_COUNTER(name, x)
 607 #define SUB_STATS_COUNTER(name, x)
 608
 609 #endif /* CONFIG_AMD_IOMMU_STATS */
 610
 611 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */