drivers/iommu/amd_iommu_v2.c

   1 /*
   2  * Copyright (C) 2010-2012 Advanced Micro Devices, Inc.
   3  * Author: Joerg Roedel <joerg.roedel@amd.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  17  */
  18
  19 #include <linux/amd-iommu.h>
  20 #include <linux/mm_types.h>
  21 #include <linux/module.h>
  22 #include <linux/iommu.h>
  23 #include <linux/pci.h>
  24 #include <linux/gfp.h>
  25
  26 #include "amd_iommu_proto.h"
  27
  28 MODULE_LICENSE("GPL v2");
  29 MODULE_AUTHOR("Joerg Roedel <joerg.roedel@amd.com>");
  30
  31 #define MAX_DEVICES             0x10000
  32 #define PRI_QUEUE_SIZE          512
  33
  34 struct pri_queue {
  35         atomic_t inflight;
  36         bool finish;
  37 };
  38
  39 struct pasid_state {
  40         struct list_head list;                  /* For global state-list */
  41         atomic_t count;                         /* Reference count */
  42         struct task_struct *task;               /* Task bound to this PASID */
  43         struct mm_struct *mm;                   /* mm_struct for the faults */
  44         struct pri_queue pri[PRI_QUEUE_SIZE];   /* PRI tag states */
  45         struct device_state *device_state;      /* Link to our device_state */
  46         int pasid;                              /* PASID index */
  47 };
  48
  49 struct device_state {
  50         atomic_t count;
  51         struct pci_dev *pdev;
  52         struct pasid_state **states;
  53         struct iommu_domain *domain;
  54         int pasid_levels;
  55         int max_pasids;
  56         spinlock_t lock;
  57 };
  58
  59 struct device_state **state_table;
  60 static spinlock_t state_lock;
  61
  62 /* List and lock for all pasid_states */
  63 static LIST_HEAD(pasid_state_list);
  64
  65 static u16 device_id(struct pci_dev *pdev)
  66 {
  67         u16 devid;
  68
  69         devid = pdev->bus->number;
  70         devid = (devid << 8) | pdev->devfn;
  71
  72         return devid;
  73 }
  74
  75 static struct device_state *get_device_state(u16 devid)
  76 {
  77         struct device_state *dev_state;
  78         unsigned long flags;
  79
  80         spin_lock_irqsave(&state_lock, flags);
  81         dev_state = state_table[devid];
  82         if (dev_state != NULL)
  83                 atomic_inc(&dev_state->count);
  84         spin_unlock_irqrestore(&state_lock, flags);
  85
  86         return dev_state;
  87 }
  88
  89 static void free_device_state(struct device_state *dev_state)
  90 {
  91         iommu_detach_device(dev_state->domain, &dev_state->pdev->dev);
  92         iommu_domain_free(dev_state->domain);
  93         kfree(dev_state);
  94 }
  95
  96 static void put_device_state(struct device_state *dev_state)
  97 {
  98         if (atomic_dec_and_test(&dev_state->count))
  99                 free_device_state(dev_state);
 100 }
 101
 102 int amd_iommu_init_device(struct pci_dev *pdev, int pasids)
 103 {
 104         struct device_state *dev_state;
 105         unsigned long flags;
 106         int ret, tmp;
 107         u16 devid;
 108
 109         might_sleep();
 110
 111         if (!amd_iommu_v2_supported())
 112                 return -ENODEV;
 113
 114         if (pasids <= 0 || pasids > (PASID_MASK + 1))
 115                 return -EINVAL;
 116
 117         devid = device_id(pdev);
 118
 119         dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL);
 120         if (dev_state == NULL)
 121                 return -ENOMEM;
 122
 123         spin_lock_init(&dev_state->lock);
 124         dev_state->pdev = pdev;
 125
 126         tmp = pasids;
 127         for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9)
 128                 dev_state->pasid_levels += 1;
 129
 130         atomic_set(&dev_state->count, 1);
 131         dev_state->max_pasids = pasids;
 132
 133         ret = -ENOMEM;
 134         dev_state->states = (void *)get_zeroed_page(GFP_KERNEL);
 135         if (dev_state->states == NULL)
 136                 goto out_free_dev_state;
 137
 138         dev_state->domain = iommu_domain_alloc(&pci_bus_type);
 139         if (dev_state->domain == NULL)
 140                 goto out_free_states;
 141
 142         amd_iommu_domain_direct_map(dev_state->domain);
 143
 144         ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids);
 145         if (ret)
 146                 goto out_free_domain;
 147
 148         ret = iommu_attach_device(dev_state->domain, &pdev->dev);
 149         if (ret != 0)
 150                 goto out_free_domain;
 151
 152         spin_lock_irqsave(&state_lock, flags);
 153
 154         if (state_table[devid] != NULL) {
 155                 spin_unlock_irqrestore(&state_lock, flags);
 156                 ret = -EBUSY;
 157                 goto out_free_domain;
 158         }
 159
 160         state_table[devid] = dev_state;
 161
 162         spin_unlock_irqrestore(&state_lock, flags);
 163
 164         return 0;
 165
 166 out_free_domain:
 167         iommu_domain_free(dev_state->domain);
 168
 169 out_free_states:
 170         free_page((unsigned long)dev_state->states);
 171
 172 out_free_dev_state:
 173         kfree(dev_state);
 174
 175         return ret;
 176 }
 177 EXPORT_SYMBOL(amd_iommu_init_device);
 178
 179 void amd_iommu_free_device(struct pci_dev *pdev)
 180 {
 181         struct device_state *dev_state;
 182         unsigned long flags;
 183         u16 devid;
 184
 185         if (!amd_iommu_v2_supported())
 186                 return;
 187
 188         devid = device_id(pdev);
 189
 190         spin_lock_irqsave(&state_lock, flags);
 191
 192         dev_state = state_table[devid];
 193         if (dev_state == NULL) {
 194                 spin_unlock_irqrestore(&state_lock, flags);
 195                 return;
 196         }
 197
 198         state_table[devid] = NULL;
 199
 200         spin_unlock_irqrestore(&state_lock, flags);
 201
 202         put_device_state(dev_state);
 203 }
 204 EXPORT_SYMBOL(amd_iommu_free_device);
 205
 206 static int __init amd_iommu_v2_init(void)
 207 {
 208         size_t state_table_size;
 209
 210         pr_info("AMD IOMMUv2 driver by Joerg Roedel <joerg.roedel@amd.com>");
 211
 212         spin_lock_init(&state_lock);
 213
 214         state_table_size = MAX_DEVICES * sizeof(struct device_state *);
 215         state_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
 216                                                get_order(state_table_size));
 217         if (state_table == NULL)
 218                 return -ENOMEM;
 219
 220         return 0;
 221 }
 222
 223 static void __exit amd_iommu_v2_exit(void)
 224 {
 225         struct device_state *dev_state;
 226         size_t state_table_size;
 227         int i;
 228
 229         for (i = 0; i < MAX_DEVICES; ++i) {
 230                 dev_state = get_device_state(i);
 231
 232                 if (dev_state == NULL)
 233                         continue;
 234
 235                 WARN_ON_ONCE(1);
 236
 237                 amd_iommu_free_device(dev_state->pdev);
 238                 put_device_state(dev_state);
 239         }
 240
 241         state_table_size = MAX_DEVICES * sizeof(struct device_state *);
 242         free_pages((unsigned long)state_table, get_order(state_table_size));
 243 }
 244
 245 module_init(amd_iommu_v2_init);
 246 module_exit(amd_iommu_v2_exit);