2 * IOMMU API for ARM architected SMMU implementations.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 * Copyright (C) 2013 ARM Limited
19 * Author: Will Deacon <will.deacon@arm.com>
21 * This driver currently supports:
22 * - SMMUv1 and v2 implementations
23 * - Stream-matching and stream-indexing
24 * - v7/v8 long-descriptor format
25 * - Non-secure access to the SMMU
26 * - Context fault reporting
29 #define pr_fmt(fmt) "arm-smmu: " fmt
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/interrupt.h>
36 #include <linux/iommu.h>
37 #include <linux/iopoll.h>
38 #include <linux/module.h>
40 #include <linux/of_address.h>
41 #include <linux/pci.h>
42 #include <linux/platform_device.h>
43 #include <linux/slab.h>
44 #include <linux/spinlock.h>
46 #include <linux/amba/bus.h>
48 #include "io-pgtable.h"
50 /* Maximum number of stream IDs assigned to a single device */
51 #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS
53 /* Maximum number of context banks per SMMU */
54 #define ARM_SMMU_MAX_CBS 128
56 /* Maximum number of mapping groups per SMMU */
57 #define ARM_SMMU_MAX_SMRS 128
59 /* SMMU global address space */
60 #define ARM_SMMU_GR0(smmu) ((smmu)->base)
61 #define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift))
64 * SMMU global address space with conditional offset to access secure
65 * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
68 #define ARM_SMMU_GR0_NS(smmu) \
70 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
73 /* Configuration registers */
74 #define ARM_SMMU_GR0_sCR0 0x0
75 #define sCR0_CLIENTPD (1 << 0)
76 #define sCR0_GFRE (1 << 1)
77 #define sCR0_GFIE (1 << 2)
78 #define sCR0_GCFGFRE (1 << 4)
79 #define sCR0_GCFGFIE (1 << 5)
80 #define sCR0_USFCFG (1 << 10)
81 #define sCR0_VMIDPNE (1 << 11)
82 #define sCR0_PTM (1 << 12)
83 #define sCR0_FB (1 << 13)
84 #define sCR0_BSU_SHIFT 14
85 #define sCR0_BSU_MASK 0x3
87 /* Identification registers */
88 #define ARM_SMMU_GR0_ID0 0x20
89 #define ARM_SMMU_GR0_ID1 0x24
90 #define ARM_SMMU_GR0_ID2 0x28
91 #define ARM_SMMU_GR0_ID3 0x2c
92 #define ARM_SMMU_GR0_ID4 0x30
93 #define ARM_SMMU_GR0_ID5 0x34
94 #define ARM_SMMU_GR0_ID6 0x38
95 #define ARM_SMMU_GR0_ID7 0x3c
96 #define ARM_SMMU_GR0_sGFSR 0x48
97 #define ARM_SMMU_GR0_sGFSYNR0 0x50
98 #define ARM_SMMU_GR0_sGFSYNR1 0x54
99 #define ARM_SMMU_GR0_sGFSYNR2 0x58
101 #define ID0_S1TS (1 << 30)
102 #define ID0_S2TS (1 << 29)
103 #define ID0_NTS (1 << 28)
104 #define ID0_SMS (1 << 27)
105 #define ID0_ATOSNS (1 << 26)
106 #define ID0_CTTW (1 << 14)
107 #define ID0_NUMIRPT_SHIFT 16
108 #define ID0_NUMIRPT_MASK 0xff
109 #define ID0_NUMSIDB_SHIFT 9
110 #define ID0_NUMSIDB_MASK 0xf
111 #define ID0_NUMSMRG_SHIFT 0
112 #define ID0_NUMSMRG_MASK 0xff
114 #define ID1_PAGESIZE (1 << 31)
115 #define ID1_NUMPAGENDXB_SHIFT 28
116 #define ID1_NUMPAGENDXB_MASK 7
117 #define ID1_NUMS2CB_SHIFT 16
118 #define ID1_NUMS2CB_MASK 0xff
119 #define ID1_NUMCB_SHIFT 0
120 #define ID1_NUMCB_MASK 0xff
122 #define ID2_OAS_SHIFT 4
123 #define ID2_OAS_MASK 0xf
124 #define ID2_IAS_SHIFT 0
125 #define ID2_IAS_MASK 0xf
126 #define ID2_UBS_SHIFT 8
127 #define ID2_UBS_MASK 0xf
128 #define ID2_PTFS_4K (1 << 12)
129 #define ID2_PTFS_16K (1 << 13)
130 #define ID2_PTFS_64K (1 << 14)
132 /* Global TLB invalidation */
133 #define ARM_SMMU_GR0_TLBIVMID 0x64
134 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68
135 #define ARM_SMMU_GR0_TLBIALLH 0x6c
136 #define ARM_SMMU_GR0_sTLBGSYNC 0x70
137 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74
138 #define sTLBGSTATUS_GSACTIVE (1 << 0)
139 #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
141 /* Stream mapping registers */
142 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
143 #define SMR_VALID (1 << 31)
144 #define SMR_MASK_SHIFT 16
145 #define SMR_MASK_MASK 0x7fff
146 #define SMR_ID_SHIFT 0
147 #define SMR_ID_MASK 0x7fff
149 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
150 #define S2CR_CBNDX_SHIFT 0
151 #define S2CR_CBNDX_MASK 0xff
152 #define S2CR_TYPE_SHIFT 16
153 #define S2CR_TYPE_MASK 0x3
154 #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
155 #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
156 #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
158 /* Context bank attribute registers */
159 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
160 #define CBAR_VMID_SHIFT 0
161 #define CBAR_VMID_MASK 0xff
162 #define CBAR_S1_BPSHCFG_SHIFT 8
163 #define CBAR_S1_BPSHCFG_MASK 3
164 #define CBAR_S1_BPSHCFG_NSH 3
165 #define CBAR_S1_MEMATTR_SHIFT 12
166 #define CBAR_S1_MEMATTR_MASK 0xf
167 #define CBAR_S1_MEMATTR_WB 0xf
168 #define CBAR_TYPE_SHIFT 16
169 #define CBAR_TYPE_MASK 0x3
170 #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
171 #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
172 #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
173 #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
174 #define CBAR_IRPTNDX_SHIFT 24
175 #define CBAR_IRPTNDX_MASK 0xff
177 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
178 #define CBA2R_RW64_32BIT (0 << 0)
179 #define CBA2R_RW64_64BIT (1 << 0)
181 /* Translation context bank */
182 #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
183 #define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift))
185 #define ARM_SMMU_CB_SCTLR 0x0
186 #define ARM_SMMU_CB_RESUME 0x8
187 #define ARM_SMMU_CB_TTBCR2 0x10
188 #define ARM_SMMU_CB_TTBR0_LO 0x20
189 #define ARM_SMMU_CB_TTBR0_HI 0x24
190 #define ARM_SMMU_CB_TTBR1_LO 0x28
191 #define ARM_SMMU_CB_TTBR1_HI 0x2c
192 #define ARM_SMMU_CB_TTBCR 0x30
193 #define ARM_SMMU_CB_S1_MAIR0 0x38
194 #define ARM_SMMU_CB_S1_MAIR1 0x3c
195 #define ARM_SMMU_CB_PAR_LO 0x50
196 #define ARM_SMMU_CB_PAR_HI 0x54
197 #define ARM_SMMU_CB_FSR 0x58
198 #define ARM_SMMU_CB_FAR_LO 0x60
199 #define ARM_SMMU_CB_FAR_HI 0x64
200 #define ARM_SMMU_CB_FSYNR0 0x68
201 #define ARM_SMMU_CB_S1_TLBIVA 0x600
202 #define ARM_SMMU_CB_S1_TLBIASID 0x610
203 #define ARM_SMMU_CB_S1_TLBIVAL 0x620
204 #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
205 #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
206 #define ARM_SMMU_CB_ATS1PR 0x800
207 #define ARM_SMMU_CB_ATSR 0x8f0
209 #define SCTLR_S1_ASIDPNE (1 << 12)
210 #define SCTLR_CFCFG (1 << 7)
211 #define SCTLR_CFIE (1 << 6)
212 #define SCTLR_CFRE (1 << 5)
213 #define SCTLR_E (1 << 4)
214 #define SCTLR_AFE (1 << 2)
215 #define SCTLR_TRE (1 << 1)
216 #define SCTLR_M (1 << 0)
217 #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
219 #define CB_PAR_F (1 << 0)
221 #define ATSR_ACTIVE (1 << 0)
223 #define RESUME_RETRY (0 << 0)
224 #define RESUME_TERMINATE (1 << 0)
226 #define TTBCR2_SEP_SHIFT 15
227 #define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT)
229 #define TTBRn_HI_ASID_SHIFT 16
231 #define FSR_MULTI (1 << 31)
232 #define FSR_SS (1 << 30)
233 #define FSR_UUT (1 << 8)
234 #define FSR_ASF (1 << 7)
235 #define FSR_TLBLKF (1 << 6)
236 #define FSR_TLBMCF (1 << 5)
237 #define FSR_EF (1 << 4)
238 #define FSR_PF (1 << 3)
239 #define FSR_AFF (1 << 2)
240 #define FSR_TF (1 << 1)
242 #define FSR_IGN (FSR_AFF | FSR_ASF | \
243 FSR_TLBMCF | FSR_TLBLKF)
244 #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
245 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
247 #define FSYNR0_WNR (1 << 4)
249 static int force_stage
;
250 module_param_named(force_stage
, force_stage
, int, S_IRUGO
);
251 MODULE_PARM_DESC(force_stage
,
252 "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
254 enum arm_smmu_arch_version
{
259 struct arm_smmu_smr
{
265 struct arm_smmu_master_cfg
{
267 u16 streamids
[MAX_MASTER_STREAMIDS
];
268 struct arm_smmu_smr
*smrs
;
271 struct arm_smmu_master
{
272 struct device_node
*of_node
;
274 struct arm_smmu_master_cfg cfg
;
277 struct arm_smmu_device
{
282 unsigned long pgshift
;
284 #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
285 #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
286 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
287 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
288 #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
289 #define ARM_SMMU_FEAT_TRANS_OPS (1 << 5)
292 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
294 enum arm_smmu_arch_version version
;
296 u32 num_context_banks
;
297 u32 num_s2_context_banks
;
298 DECLARE_BITMAP(context_map
, ARM_SMMU_MAX_CBS
);
301 u32 num_mapping_groups
;
302 DECLARE_BITMAP(smr_map
, ARM_SMMU_MAX_SMRS
);
304 unsigned long va_size
;
305 unsigned long ipa_size
;
306 unsigned long pa_size
;
309 u32 num_context_irqs
;
312 struct list_head list
;
313 struct rb_root masters
;
316 struct arm_smmu_cfg
{
321 #define INVALID_IRPTNDX 0xff
323 #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx)
324 #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1)
326 enum arm_smmu_domain_stage
{
327 ARM_SMMU_DOMAIN_S1
= 0,
329 ARM_SMMU_DOMAIN_NESTED
,
332 struct arm_smmu_domain
{
333 struct arm_smmu_device
*smmu
;
334 struct io_pgtable_ops
*pgtbl_ops
;
335 spinlock_t pgtbl_lock
;
336 struct arm_smmu_cfg cfg
;
337 enum arm_smmu_domain_stage stage
;
338 struct mutex init_mutex
; /* Protects smmu pointer */
339 struct iommu_domain domain
;
342 static struct iommu_ops arm_smmu_ops
;
344 static DEFINE_SPINLOCK(arm_smmu_devices_lock
);
345 static LIST_HEAD(arm_smmu_devices
);
347 struct arm_smmu_option_prop
{
352 static struct arm_smmu_option_prop arm_smmu_options
[] = {
353 { ARM_SMMU_OPT_SECURE_CFG_ACCESS
, "calxeda,smmu-secure-config-access" },
357 static struct arm_smmu_domain
*to_smmu_domain(struct iommu_domain
*dom
)
359 return container_of(dom
, struct arm_smmu_domain
, domain
);
362 static void parse_driver_options(struct arm_smmu_device
*smmu
)
367 if (of_property_read_bool(smmu
->dev
->of_node
,
368 arm_smmu_options
[i
].prop
)) {
369 smmu
->options
|= arm_smmu_options
[i
].opt
;
370 dev_notice(smmu
->dev
, "option %s\n",
371 arm_smmu_options
[i
].prop
);
373 } while (arm_smmu_options
[++i
].opt
);
376 static struct device_node
*dev_get_dev_node(struct device
*dev
)
378 if (dev_is_pci(dev
)) {
379 struct pci_bus
*bus
= to_pci_dev(dev
)->bus
;
381 while (!pci_is_root_bus(bus
))
383 return bus
->bridge
->parent
->of_node
;
389 static struct arm_smmu_master
*find_smmu_master(struct arm_smmu_device
*smmu
,
390 struct device_node
*dev_node
)
392 struct rb_node
*node
= smmu
->masters
.rb_node
;
395 struct arm_smmu_master
*master
;
397 master
= container_of(node
, struct arm_smmu_master
, node
);
399 if (dev_node
< master
->of_node
)
400 node
= node
->rb_left
;
401 else if (dev_node
> master
->of_node
)
402 node
= node
->rb_right
;
410 static struct arm_smmu_master_cfg
*
411 find_smmu_master_cfg(struct device
*dev
)
413 struct arm_smmu_master_cfg
*cfg
= NULL
;
414 struct iommu_group
*group
= iommu_group_get(dev
);
417 cfg
= iommu_group_get_iommudata(group
);
418 iommu_group_put(group
);
424 static int insert_smmu_master(struct arm_smmu_device
*smmu
,
425 struct arm_smmu_master
*master
)
427 struct rb_node
**new, *parent
;
429 new = &smmu
->masters
.rb_node
;
432 struct arm_smmu_master
*this
433 = container_of(*new, struct arm_smmu_master
, node
);
436 if (master
->of_node
< this->of_node
)
437 new = &((*new)->rb_left
);
438 else if (master
->of_node
> this->of_node
)
439 new = &((*new)->rb_right
);
444 rb_link_node(&master
->node
, parent
, new);
445 rb_insert_color(&master
->node
, &smmu
->masters
);
449 static int register_smmu_master(struct arm_smmu_device
*smmu
,
451 struct of_phandle_args
*masterspec
)
454 struct arm_smmu_master
*master
;
456 master
= find_smmu_master(smmu
, masterspec
->np
);
459 "rejecting multiple registrations for master device %s\n",
460 masterspec
->np
->name
);
464 if (masterspec
->args_count
> MAX_MASTER_STREAMIDS
) {
466 "reached maximum number (%d) of stream IDs for master device %s\n",
467 MAX_MASTER_STREAMIDS
, masterspec
->np
->name
);
471 master
= devm_kzalloc(dev
, sizeof(*master
), GFP_KERNEL
);
475 master
->of_node
= masterspec
->np
;
476 master
->cfg
.num_streamids
= masterspec
->args_count
;
478 for (i
= 0; i
< master
->cfg
.num_streamids
; ++i
) {
479 u16 streamid
= masterspec
->args
[i
];
481 if (!(smmu
->features
& ARM_SMMU_FEAT_STREAM_MATCH
) &&
482 (streamid
>= smmu
->num_mapping_groups
)) {
484 "stream ID for master device %s greater than maximum allowed (%d)\n",
485 masterspec
->np
->name
, smmu
->num_mapping_groups
);
488 master
->cfg
.streamids
[i
] = streamid
;
490 return insert_smmu_master(smmu
, master
);
493 static struct arm_smmu_device
*find_smmu_for_device(struct device
*dev
)
495 struct arm_smmu_device
*smmu
;
496 struct arm_smmu_master
*master
= NULL
;
497 struct device_node
*dev_node
= dev_get_dev_node(dev
);
499 spin_lock(&arm_smmu_devices_lock
);
500 list_for_each_entry(smmu
, &arm_smmu_devices
, list
) {
501 master
= find_smmu_master(smmu
, dev_node
);
505 spin_unlock(&arm_smmu_devices_lock
);
507 return master
? smmu
: NULL
;
510 static int __arm_smmu_alloc_bitmap(unsigned long *map
, int start
, int end
)
515 idx
= find_next_zero_bit(map
, end
, start
);
518 } while (test_and_set_bit(idx
, map
));
523 static void __arm_smmu_free_bitmap(unsigned long *map
, int idx
)
528 /* Wait for any pending TLB invalidations to complete */
529 static void __arm_smmu_tlb_sync(struct arm_smmu_device
*smmu
)
532 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
534 writel_relaxed(0, gr0_base
+ ARM_SMMU_GR0_sTLBGSYNC
);
535 while (readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sTLBGSTATUS
)
536 & sTLBGSTATUS_GSACTIVE
) {
538 if (++count
== TLB_LOOP_TIMEOUT
) {
539 dev_err_ratelimited(smmu
->dev
,
540 "TLB sync timed out -- SMMU may be deadlocked\n");
547 static void arm_smmu_tlb_sync(void *cookie
)
549 struct arm_smmu_domain
*smmu_domain
= cookie
;
550 __arm_smmu_tlb_sync(smmu_domain
->smmu
);
553 static void arm_smmu_tlb_inv_context(void *cookie
)
555 struct arm_smmu_domain
*smmu_domain
= cookie
;
556 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
557 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
558 bool stage1
= cfg
->cbar
!= CBAR_TYPE_S2_TRANS
;
562 base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
563 writel_relaxed(ARM_SMMU_CB_ASID(cfg
),
564 base
+ ARM_SMMU_CB_S1_TLBIASID
);
566 base
= ARM_SMMU_GR0(smmu
);
567 writel_relaxed(ARM_SMMU_CB_VMID(cfg
),
568 base
+ ARM_SMMU_GR0_TLBIVMID
);
571 __arm_smmu_tlb_sync(smmu
);
574 static void arm_smmu_tlb_inv_range_nosync(unsigned long iova
, size_t size
,
575 bool leaf
, void *cookie
)
577 struct arm_smmu_domain
*smmu_domain
= cookie
;
578 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
579 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
580 bool stage1
= cfg
->cbar
!= CBAR_TYPE_S2_TRANS
;
584 reg
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
585 reg
+= leaf
? ARM_SMMU_CB_S1_TLBIVAL
: ARM_SMMU_CB_S1_TLBIVA
;
587 if (!IS_ENABLED(CONFIG_64BIT
) || smmu
->version
== ARM_SMMU_V1
) {
589 iova
|= ARM_SMMU_CB_ASID(cfg
);
590 writel_relaxed(iova
, reg
);
594 iova
|= (u64
)ARM_SMMU_CB_ASID(cfg
) << 48;
595 writeq_relaxed(iova
, reg
);
599 } else if (smmu
->version
== ARM_SMMU_V2
) {
600 reg
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
601 reg
+= leaf
? ARM_SMMU_CB_S2_TLBIIPAS2L
:
602 ARM_SMMU_CB_S2_TLBIIPAS2
;
603 writeq_relaxed(iova
>> 12, reg
);
606 reg
= ARM_SMMU_GR0(smmu
) + ARM_SMMU_GR0_TLBIVMID
;
607 writel_relaxed(ARM_SMMU_CB_VMID(cfg
), reg
);
611 static struct iommu_gather_ops arm_smmu_gather_ops
= {
612 .tlb_flush_all
= arm_smmu_tlb_inv_context
,
613 .tlb_add_flush
= arm_smmu_tlb_inv_range_nosync
,
614 .tlb_sync
= arm_smmu_tlb_sync
,
617 static irqreturn_t
arm_smmu_context_fault(int irq
, void *dev
)
620 u32 fsr
, far
, fsynr
, resume
;
622 struct iommu_domain
*domain
= dev
;
623 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
624 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
625 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
626 void __iomem
*cb_base
;
628 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
629 fsr
= readl_relaxed(cb_base
+ ARM_SMMU_CB_FSR
);
631 if (!(fsr
& FSR_FAULT
))
635 dev_err_ratelimited(smmu
->dev
,
636 "Unexpected context fault (fsr 0x%x)\n",
639 fsynr
= readl_relaxed(cb_base
+ ARM_SMMU_CB_FSYNR0
);
640 flags
= fsynr
& FSYNR0_WNR
? IOMMU_FAULT_WRITE
: IOMMU_FAULT_READ
;
642 far
= readl_relaxed(cb_base
+ ARM_SMMU_CB_FAR_LO
);
645 far
= readl_relaxed(cb_base
+ ARM_SMMU_CB_FAR_HI
);
646 iova
|= ((unsigned long)far
<< 32);
649 if (!report_iommu_fault(domain
, smmu
->dev
, iova
, flags
)) {
651 resume
= RESUME_RETRY
;
653 dev_err_ratelimited(smmu
->dev
,
654 "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
655 iova
, fsynr
, cfg
->cbndx
);
657 resume
= RESUME_TERMINATE
;
660 /* Clear the faulting FSR */
661 writel(fsr
, cb_base
+ ARM_SMMU_CB_FSR
);
663 /* Retry or terminate any stalled transactions */
665 writel_relaxed(resume
, cb_base
+ ARM_SMMU_CB_RESUME
);
670 static irqreturn_t
arm_smmu_global_fault(int irq
, void *dev
)
672 u32 gfsr
, gfsynr0
, gfsynr1
, gfsynr2
;
673 struct arm_smmu_device
*smmu
= dev
;
674 void __iomem
*gr0_base
= ARM_SMMU_GR0_NS(smmu
);
676 gfsr
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sGFSR
);
677 gfsynr0
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sGFSYNR0
);
678 gfsynr1
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sGFSYNR1
);
679 gfsynr2
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sGFSYNR2
);
684 dev_err_ratelimited(smmu
->dev
,
685 "Unexpected global fault, this could be serious\n");
686 dev_err_ratelimited(smmu
->dev
,
687 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
688 gfsr
, gfsynr0
, gfsynr1
, gfsynr2
);
690 writel(gfsr
, gr0_base
+ ARM_SMMU_GR0_sGFSR
);
694 static void arm_smmu_init_context_bank(struct arm_smmu_domain
*smmu_domain
,
695 struct io_pgtable_cfg
*pgtbl_cfg
)
699 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
700 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
701 void __iomem
*cb_base
, *gr0_base
, *gr1_base
;
703 gr0_base
= ARM_SMMU_GR0(smmu
);
704 gr1_base
= ARM_SMMU_GR1(smmu
);
705 stage1
= cfg
->cbar
!= CBAR_TYPE_S2_TRANS
;
706 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
708 if (smmu
->version
> ARM_SMMU_V1
) {
711 * *Must* be initialised before CBAR thanks to VMID16
712 * architectural oversight affected some implementations.
715 reg
= CBA2R_RW64_64BIT
;
717 reg
= CBA2R_RW64_32BIT
;
719 writel_relaxed(reg
, gr1_base
+ ARM_SMMU_GR1_CBA2R(cfg
->cbndx
));
724 if (smmu
->version
== ARM_SMMU_V1
)
725 reg
|= cfg
->irptndx
<< CBAR_IRPTNDX_SHIFT
;
728 * Use the weakest shareability/memory types, so they are
729 * overridden by the ttbcr/pte.
732 reg
|= (CBAR_S1_BPSHCFG_NSH
<< CBAR_S1_BPSHCFG_SHIFT
) |
733 (CBAR_S1_MEMATTR_WB
<< CBAR_S1_MEMATTR_SHIFT
);
735 reg
|= ARM_SMMU_CB_VMID(cfg
) << CBAR_VMID_SHIFT
;
737 writel_relaxed(reg
, gr1_base
+ ARM_SMMU_GR1_CBAR(cfg
->cbndx
));
741 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.ttbr
[0];
742 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBR0_LO
);
743 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.ttbr
[0] >> 32;
744 reg
|= ARM_SMMU_CB_ASID(cfg
) << TTBRn_HI_ASID_SHIFT
;
745 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBR0_HI
);
747 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.ttbr
[1];
748 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBR1_LO
);
749 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.ttbr
[1] >> 32;
750 reg
|= ARM_SMMU_CB_ASID(cfg
) << TTBRn_HI_ASID_SHIFT
;
751 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBR1_HI
);
753 reg
= pgtbl_cfg
->arm_lpae_s2_cfg
.vttbr
;
754 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBR0_LO
);
755 reg
= pgtbl_cfg
->arm_lpae_s2_cfg
.vttbr
>> 32;
756 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBR0_HI
);
761 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.tcr
;
762 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBCR
);
763 if (smmu
->version
> ARM_SMMU_V1
) {
764 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.tcr
>> 32;
765 reg
|= TTBCR2_SEP_UPSTREAM
;
766 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBCR2
);
769 reg
= pgtbl_cfg
->arm_lpae_s2_cfg
.vtcr
;
770 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBCR
);
773 /* MAIRs (stage-1 only) */
775 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.mair
[0];
776 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_S1_MAIR0
);
777 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.mair
[1];
778 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_S1_MAIR1
);
782 reg
= SCTLR_CFCFG
| SCTLR_CFIE
| SCTLR_CFRE
| SCTLR_M
| SCTLR_EAE_SBOP
;
784 reg
|= SCTLR_S1_ASIDPNE
;
788 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_SCTLR
);
791 static int arm_smmu_init_domain_context(struct iommu_domain
*domain
,
792 struct arm_smmu_device
*smmu
)
794 int irq
, start
, ret
= 0;
795 unsigned long ias
, oas
;
796 struct io_pgtable_ops
*pgtbl_ops
;
797 struct io_pgtable_cfg pgtbl_cfg
;
798 enum io_pgtable_fmt fmt
;
799 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
800 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
802 mutex_lock(&smmu_domain
->init_mutex
);
803 if (smmu_domain
->smmu
)
807 * Mapping the requested stage onto what we support is surprisingly
808 * complicated, mainly because the spec allows S1+S2 SMMUs without
809 * support for nested translation. That means we end up with the
812 * Requested Supported Actual
822 * Note that you can't actually request stage-2 mappings.
824 if (!(smmu
->features
& ARM_SMMU_FEAT_TRANS_S1
))
825 smmu_domain
->stage
= ARM_SMMU_DOMAIN_S2
;
826 if (!(smmu
->features
& ARM_SMMU_FEAT_TRANS_S2
))
827 smmu_domain
->stage
= ARM_SMMU_DOMAIN_S1
;
829 switch (smmu_domain
->stage
) {
830 case ARM_SMMU_DOMAIN_S1
:
831 cfg
->cbar
= CBAR_TYPE_S1_TRANS_S2_BYPASS
;
832 start
= smmu
->num_s2_context_banks
;
834 oas
= smmu
->ipa_size
;
835 if (IS_ENABLED(CONFIG_64BIT
))
836 fmt
= ARM_64_LPAE_S1
;
838 fmt
= ARM_32_LPAE_S1
;
840 case ARM_SMMU_DOMAIN_NESTED
:
842 * We will likely want to change this if/when KVM gets
845 case ARM_SMMU_DOMAIN_S2
:
846 cfg
->cbar
= CBAR_TYPE_S2_TRANS
;
848 ias
= smmu
->ipa_size
;
850 if (IS_ENABLED(CONFIG_64BIT
))
851 fmt
= ARM_64_LPAE_S2
;
853 fmt
= ARM_32_LPAE_S2
;
860 ret
= __arm_smmu_alloc_bitmap(smmu
->context_map
, start
,
861 smmu
->num_context_banks
);
862 if (IS_ERR_VALUE(ret
))
866 if (smmu
->version
== ARM_SMMU_V1
) {
867 cfg
->irptndx
= atomic_inc_return(&smmu
->irptndx
);
868 cfg
->irptndx
%= smmu
->num_context_irqs
;
870 cfg
->irptndx
= cfg
->cbndx
;
873 pgtbl_cfg
= (struct io_pgtable_cfg
) {
874 .pgsize_bitmap
= arm_smmu_ops
.pgsize_bitmap
,
877 .tlb
= &arm_smmu_gather_ops
,
878 .iommu_dev
= smmu
->dev
,
881 smmu_domain
->smmu
= smmu
;
882 pgtbl_ops
= alloc_io_pgtable_ops(fmt
, &pgtbl_cfg
, smmu_domain
);
888 /* Update our support page sizes to reflect the page table format */
889 arm_smmu_ops
.pgsize_bitmap
= pgtbl_cfg
.pgsize_bitmap
;
891 /* Initialise the context bank with our page table cfg */
892 arm_smmu_init_context_bank(smmu_domain
, &pgtbl_cfg
);
895 * Request context fault interrupt. Do this last to avoid the
896 * handler seeing a half-initialised domain state.
898 irq
= smmu
->irqs
[smmu
->num_global_irqs
+ cfg
->irptndx
];
899 ret
= request_irq(irq
, arm_smmu_context_fault
, IRQF_SHARED
,
900 "arm-smmu-context-fault", domain
);
901 if (IS_ERR_VALUE(ret
)) {
902 dev_err(smmu
->dev
, "failed to request context IRQ %d (%u)\n",
904 cfg
->irptndx
= INVALID_IRPTNDX
;
907 mutex_unlock(&smmu_domain
->init_mutex
);
909 /* Publish page table ops for map/unmap */
910 smmu_domain
->pgtbl_ops
= pgtbl_ops
;
914 smmu_domain
->smmu
= NULL
;
916 mutex_unlock(&smmu_domain
->init_mutex
);
920 static void arm_smmu_destroy_domain_context(struct iommu_domain
*domain
)
922 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
923 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
924 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
925 void __iomem
*cb_base
;
932 * Disable the context bank and free the page tables before freeing
935 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
936 writel_relaxed(0, cb_base
+ ARM_SMMU_CB_SCTLR
);
938 if (cfg
->irptndx
!= INVALID_IRPTNDX
) {
939 irq
= smmu
->irqs
[smmu
->num_global_irqs
+ cfg
->irptndx
];
940 free_irq(irq
, domain
);
943 if (smmu_domain
->pgtbl_ops
)
944 free_io_pgtable_ops(smmu_domain
->pgtbl_ops
);
946 __arm_smmu_free_bitmap(smmu
->context_map
, cfg
->cbndx
);
949 static struct iommu_domain
*arm_smmu_domain_alloc(unsigned type
)
951 struct arm_smmu_domain
*smmu_domain
;
953 if (type
!= IOMMU_DOMAIN_UNMANAGED
)
956 * Allocate the domain and initialise some of its data structures.
957 * We can't really do anything meaningful until we've added a
960 smmu_domain
= kzalloc(sizeof(*smmu_domain
), GFP_KERNEL
);
964 mutex_init(&smmu_domain
->init_mutex
);
965 spin_lock_init(&smmu_domain
->pgtbl_lock
);
967 return &smmu_domain
->domain
;
970 static void arm_smmu_domain_free(struct iommu_domain
*domain
)
972 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
975 * Free the domain resources. We assume that all devices have
976 * already been detached.
978 arm_smmu_destroy_domain_context(domain
);
982 static int arm_smmu_master_configure_smrs(struct arm_smmu_device
*smmu
,
983 struct arm_smmu_master_cfg
*cfg
)
986 struct arm_smmu_smr
*smrs
;
987 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
989 if (!(smmu
->features
& ARM_SMMU_FEAT_STREAM_MATCH
))
995 smrs
= kmalloc_array(cfg
->num_streamids
, sizeof(*smrs
), GFP_KERNEL
);
997 dev_err(smmu
->dev
, "failed to allocate %d SMRs\n",
1002 /* Allocate the SMRs on the SMMU */
1003 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1004 int idx
= __arm_smmu_alloc_bitmap(smmu
->smr_map
, 0,
1005 smmu
->num_mapping_groups
);
1006 if (IS_ERR_VALUE(idx
)) {
1007 dev_err(smmu
->dev
, "failed to allocate free SMR\n");
1011 smrs
[i
] = (struct arm_smmu_smr
) {
1013 .mask
= 0, /* We don't currently share SMRs */
1014 .id
= cfg
->streamids
[i
],
1018 /* It worked! Now, poke the actual hardware */
1019 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1020 u32 reg
= SMR_VALID
| smrs
[i
].id
<< SMR_ID_SHIFT
|
1021 smrs
[i
].mask
<< SMR_MASK_SHIFT
;
1022 writel_relaxed(reg
, gr0_base
+ ARM_SMMU_GR0_SMR(smrs
[i
].idx
));
1030 __arm_smmu_free_bitmap(smmu
->smr_map
, smrs
[i
].idx
);
1035 static void arm_smmu_master_free_smrs(struct arm_smmu_device
*smmu
,
1036 struct arm_smmu_master_cfg
*cfg
)
1039 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1040 struct arm_smmu_smr
*smrs
= cfg
->smrs
;
1045 /* Invalidate the SMRs before freeing back to the allocator */
1046 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1047 u8 idx
= smrs
[i
].idx
;
1049 writel_relaxed(~SMR_VALID
, gr0_base
+ ARM_SMMU_GR0_SMR(idx
));
1050 __arm_smmu_free_bitmap(smmu
->smr_map
, idx
);
1057 static int arm_smmu_domain_add_master(struct arm_smmu_domain
*smmu_domain
,
1058 struct arm_smmu_master_cfg
*cfg
)
1061 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
1062 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1064 /* Devices in an IOMMU group may already be configured */
1065 ret
= arm_smmu_master_configure_smrs(smmu
, cfg
);
1067 return ret
== -EEXIST
? 0 : ret
;
1069 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1072 idx
= cfg
->smrs
? cfg
->smrs
[i
].idx
: cfg
->streamids
[i
];
1073 s2cr
= S2CR_TYPE_TRANS
|
1074 (smmu_domain
->cfg
.cbndx
<< S2CR_CBNDX_SHIFT
);
1075 writel_relaxed(s2cr
, gr0_base
+ ARM_SMMU_GR0_S2CR(idx
));
1081 static void arm_smmu_domain_remove_master(struct arm_smmu_domain
*smmu_domain
,
1082 struct arm_smmu_master_cfg
*cfg
)
1085 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
1086 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1088 /* An IOMMU group is torn down by the first device to be removed */
1089 if ((smmu
->features
& ARM_SMMU_FEAT_STREAM_MATCH
) && !cfg
->smrs
)
1093 * We *must* clear the S2CR first, because freeing the SMR means
1094 * that it can be re-allocated immediately.
1096 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1097 u32 idx
= cfg
->smrs
? cfg
->smrs
[i
].idx
: cfg
->streamids
[i
];
1099 writel_relaxed(S2CR_TYPE_BYPASS
,
1100 gr0_base
+ ARM_SMMU_GR0_S2CR(idx
));
1103 arm_smmu_master_free_smrs(smmu
, cfg
);
1106 static int arm_smmu_attach_dev(struct iommu_domain
*domain
, struct device
*dev
)
1109 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1110 struct arm_smmu_device
*smmu
;
1111 struct arm_smmu_master_cfg
*cfg
;
1113 smmu
= find_smmu_for_device(dev
);
1115 dev_err(dev
, "cannot attach to SMMU, is it on the same bus?\n");
1119 if (dev
->archdata
.iommu
) {
1120 dev_err(dev
, "already attached to IOMMU domain\n");
1124 /* Ensure that the domain is finalised */
1125 ret
= arm_smmu_init_domain_context(domain
, smmu
);
1126 if (IS_ERR_VALUE(ret
))
1130 * Sanity check the domain. We don't support domains across
1133 if (smmu_domain
->smmu
!= smmu
) {
1135 "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1136 dev_name(smmu_domain
->smmu
->dev
), dev_name(smmu
->dev
));
1140 /* Looks ok, so add the device to the domain */
1141 cfg
= find_smmu_master_cfg(dev
);
1145 ret
= arm_smmu_domain_add_master(smmu_domain
, cfg
);
1147 dev
->archdata
.iommu
= domain
;
1151 static void arm_smmu_detach_dev(struct iommu_domain
*domain
, struct device
*dev
)
1153 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1154 struct arm_smmu_master_cfg
*cfg
;
1156 cfg
= find_smmu_master_cfg(dev
);
1160 dev
->archdata
.iommu
= NULL
;
1161 arm_smmu_domain_remove_master(smmu_domain
, cfg
);
1164 static int arm_smmu_map(struct iommu_domain
*domain
, unsigned long iova
,
1165 phys_addr_t paddr
, size_t size
, int prot
)
1168 unsigned long flags
;
1169 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1170 struct io_pgtable_ops
*ops
= smmu_domain
->pgtbl_ops
;
1175 spin_lock_irqsave(&smmu_domain
->pgtbl_lock
, flags
);
1176 ret
= ops
->map(ops
, iova
, paddr
, size
, prot
);
1177 spin_unlock_irqrestore(&smmu_domain
->pgtbl_lock
, flags
);
1181 static size_t arm_smmu_unmap(struct iommu_domain
*domain
, unsigned long iova
,
1185 unsigned long flags
;
1186 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1187 struct io_pgtable_ops
*ops
= smmu_domain
->pgtbl_ops
;
1192 spin_lock_irqsave(&smmu_domain
->pgtbl_lock
, flags
);
1193 ret
= ops
->unmap(ops
, iova
, size
);
1194 spin_unlock_irqrestore(&smmu_domain
->pgtbl_lock
, flags
);
1198 static phys_addr_t
arm_smmu_iova_to_phys_hard(struct iommu_domain
*domain
,
1201 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1202 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
1203 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
1204 struct io_pgtable_ops
*ops
= smmu_domain
->pgtbl_ops
;
1205 struct device
*dev
= smmu
->dev
;
1206 void __iomem
*cb_base
;
1211 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
1213 /* ATS1 registers can only be written atomically */
1214 va
= iova
& ~0xfffUL
;
1216 if (smmu
->version
== ARM_SMMU_V2
)
1217 writeq_relaxed(va
, cb_base
+ ARM_SMMU_CB_ATS1PR
);
1220 writel_relaxed(va
, cb_base
+ ARM_SMMU_CB_ATS1PR
);
1222 if (readl_poll_timeout_atomic(cb_base
+ ARM_SMMU_CB_ATSR
, tmp
,
1223 !(tmp
& ATSR_ACTIVE
), 5, 50)) {
1225 "iova to phys timed out on 0x%pad. Falling back to software table walk.\n",
1227 return ops
->iova_to_phys(ops
, iova
);
1230 phys
= readl_relaxed(cb_base
+ ARM_SMMU_CB_PAR_LO
);
1231 phys
|= ((u64
)readl_relaxed(cb_base
+ ARM_SMMU_CB_PAR_HI
)) << 32;
1233 if (phys
& CB_PAR_F
) {
1234 dev_err(dev
, "translation fault!\n");
1235 dev_err(dev
, "PAR = 0x%llx\n", phys
);
1239 return (phys
& GENMASK_ULL(39, 12)) | (iova
& 0xfff);
1242 static phys_addr_t
arm_smmu_iova_to_phys(struct iommu_domain
*domain
,
1246 unsigned long flags
;
1247 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1248 struct io_pgtable_ops
*ops
= smmu_domain
->pgtbl_ops
;
1253 spin_lock_irqsave(&smmu_domain
->pgtbl_lock
, flags
);
1254 if (smmu_domain
->smmu
->features
& ARM_SMMU_FEAT_TRANS_OPS
&&
1255 smmu_domain
->stage
== ARM_SMMU_DOMAIN_S1
) {
1256 ret
= arm_smmu_iova_to_phys_hard(domain
, iova
);
1258 ret
= ops
->iova_to_phys(ops
, iova
);
1261 spin_unlock_irqrestore(&smmu_domain
->pgtbl_lock
, flags
);
1266 static bool arm_smmu_capable(enum iommu_cap cap
)
1269 case IOMMU_CAP_CACHE_COHERENCY
:
1271 * Return true here as the SMMU can always send out coherent
1275 case IOMMU_CAP_INTR_REMAP
:
1276 return true; /* MSIs are just memory writes */
1277 case IOMMU_CAP_NOEXEC
:
1284 static int __arm_smmu_get_pci_sid(struct pci_dev
*pdev
, u16 alias
, void *data
)
1286 *((u16
*)data
) = alias
;
1287 return 0; /* Continue walking */
1290 static void __arm_smmu_release_pci_iommudata(void *data
)
1295 static int arm_smmu_init_pci_device(struct pci_dev
*pdev
,
1296 struct iommu_group
*group
)
1298 struct arm_smmu_master_cfg
*cfg
;
1302 cfg
= iommu_group_get_iommudata(group
);
1304 cfg
= kzalloc(sizeof(*cfg
), GFP_KERNEL
);
1308 iommu_group_set_iommudata(group
, cfg
,
1309 __arm_smmu_release_pci_iommudata
);
1312 if (cfg
->num_streamids
>= MAX_MASTER_STREAMIDS
)
1316 * Assume Stream ID == Requester ID for now.
1317 * We need a way to describe the ID mappings in FDT.
1319 pci_for_each_dma_alias(pdev
, __arm_smmu_get_pci_sid
, &sid
);
1320 for (i
= 0; i
< cfg
->num_streamids
; ++i
)
1321 if (cfg
->streamids
[i
] == sid
)
1324 /* Avoid duplicate SIDs, as this can lead to SMR conflicts */
1325 if (i
== cfg
->num_streamids
)
1326 cfg
->streamids
[cfg
->num_streamids
++] = sid
;
1331 static int arm_smmu_init_platform_device(struct device
*dev
,
1332 struct iommu_group
*group
)
1334 struct arm_smmu_device
*smmu
= find_smmu_for_device(dev
);
1335 struct arm_smmu_master
*master
;
1340 master
= find_smmu_master(smmu
, dev
->of_node
);
1344 iommu_group_set_iommudata(group
, &master
->cfg
, NULL
);
1349 static int arm_smmu_add_device(struct device
*dev
)
1351 struct iommu_group
*group
;
1353 group
= iommu_group_get_for_dev(dev
);
1355 return PTR_ERR(group
);
1360 static void arm_smmu_remove_device(struct device
*dev
)
1362 iommu_group_remove_device(dev
);
1365 static struct iommu_group
*arm_smmu_device_group(struct device
*dev
)
1367 struct iommu_group
*group
;
1370 if (dev_is_pci(dev
))
1371 group
= pci_device_group(dev
);
1373 group
= generic_device_group(dev
);
1378 if (dev_is_pci(dev
))
1379 ret
= arm_smmu_init_pci_device(to_pci_dev(dev
), group
);
1381 ret
= arm_smmu_init_platform_device(dev
, group
);
1384 iommu_group_put(group
);
1385 group
= ERR_PTR(ret
);
1391 static int arm_smmu_domain_get_attr(struct iommu_domain
*domain
,
1392 enum iommu_attr attr
, void *data
)
1394 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1397 case DOMAIN_ATTR_NESTING
:
1398 *(int *)data
= (smmu_domain
->stage
== ARM_SMMU_DOMAIN_NESTED
);
1405 static int arm_smmu_domain_set_attr(struct iommu_domain
*domain
,
1406 enum iommu_attr attr
, void *data
)
1409 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1411 mutex_lock(&smmu_domain
->init_mutex
);
1414 case DOMAIN_ATTR_NESTING
:
1415 if (smmu_domain
->smmu
) {
1421 smmu_domain
->stage
= ARM_SMMU_DOMAIN_NESTED
;
1423 smmu_domain
->stage
= ARM_SMMU_DOMAIN_S1
;
1431 mutex_unlock(&smmu_domain
->init_mutex
);
1435 static struct iommu_ops arm_smmu_ops
= {
1436 .capable
= arm_smmu_capable
,
1437 .domain_alloc
= arm_smmu_domain_alloc
,
1438 .domain_free
= arm_smmu_domain_free
,
1439 .attach_dev
= arm_smmu_attach_dev
,
1440 .detach_dev
= arm_smmu_detach_dev
,
1441 .map
= arm_smmu_map
,
1442 .unmap
= arm_smmu_unmap
,
1443 .map_sg
= default_iommu_map_sg
,
1444 .iova_to_phys
= arm_smmu_iova_to_phys
,
1445 .add_device
= arm_smmu_add_device
,
1446 .remove_device
= arm_smmu_remove_device
,
1447 .device_group
= arm_smmu_device_group
,
1448 .domain_get_attr
= arm_smmu_domain_get_attr
,
1449 .domain_set_attr
= arm_smmu_domain_set_attr
,
1450 .pgsize_bitmap
= -1UL, /* Restricted during device attach */
1453 static void arm_smmu_device_reset(struct arm_smmu_device
*smmu
)
1455 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1456 void __iomem
*cb_base
;
1460 /* clear global FSR */
1461 reg
= readl_relaxed(ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sGFSR
);
1462 writel(reg
, ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sGFSR
);
1464 /* Mark all SMRn as invalid and all S2CRn as bypass */
1465 for (i
= 0; i
< smmu
->num_mapping_groups
; ++i
) {
1466 writel_relaxed(0, gr0_base
+ ARM_SMMU_GR0_SMR(i
));
1467 writel_relaxed(S2CR_TYPE_BYPASS
,
1468 gr0_base
+ ARM_SMMU_GR0_S2CR(i
));
1471 /* Make sure all context banks are disabled and clear CB_FSR */
1472 for (i
= 0; i
< smmu
->num_context_banks
; ++i
) {
1473 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, i
);
1474 writel_relaxed(0, cb_base
+ ARM_SMMU_CB_SCTLR
);
1475 writel_relaxed(FSR_FAULT
, cb_base
+ ARM_SMMU_CB_FSR
);
1478 /* Invalidate the TLB, just in case */
1479 writel_relaxed(0, gr0_base
+ ARM_SMMU_GR0_TLBIALLH
);
1480 writel_relaxed(0, gr0_base
+ ARM_SMMU_GR0_TLBIALLNSNH
);
1482 reg
= readl_relaxed(ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sCR0
);
1484 /* Enable fault reporting */
1485 reg
|= (sCR0_GFRE
| sCR0_GFIE
| sCR0_GCFGFRE
| sCR0_GCFGFIE
);
1487 /* Disable TLB broadcasting. */
1488 reg
|= (sCR0_VMIDPNE
| sCR0_PTM
);
1490 /* Enable client access, but bypass when no mapping is found */
1491 reg
&= ~(sCR0_CLIENTPD
| sCR0_USFCFG
);
1493 /* Disable forced broadcasting */
1496 /* Don't upgrade barriers */
1497 reg
&= ~(sCR0_BSU_MASK
<< sCR0_BSU_SHIFT
);
1499 /* Push the button */
1500 __arm_smmu_tlb_sync(smmu
);
1501 writel(reg
, ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sCR0
);
1504 static int arm_smmu_id_size_to_bits(int size
)
1523 static int arm_smmu_device_cfg_probe(struct arm_smmu_device
*smmu
)
1526 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1528 bool cttw_dt
, cttw_reg
;
1530 dev_notice(smmu
->dev
, "probing hardware configuration...\n");
1531 dev_notice(smmu
->dev
, "SMMUv%d with:\n", smmu
->version
);
1534 id
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_ID0
);
1536 /* Restrict available stages based on module parameter */
1537 if (force_stage
== 1)
1538 id
&= ~(ID0_S2TS
| ID0_NTS
);
1539 else if (force_stage
== 2)
1540 id
&= ~(ID0_S1TS
| ID0_NTS
);
1542 if (id
& ID0_S1TS
) {
1543 smmu
->features
|= ARM_SMMU_FEAT_TRANS_S1
;
1544 dev_notice(smmu
->dev
, "\tstage 1 translation\n");
1547 if (id
& ID0_S2TS
) {
1548 smmu
->features
|= ARM_SMMU_FEAT_TRANS_S2
;
1549 dev_notice(smmu
->dev
, "\tstage 2 translation\n");
1553 smmu
->features
|= ARM_SMMU_FEAT_TRANS_NESTED
;
1554 dev_notice(smmu
->dev
, "\tnested translation\n");
1557 if (!(smmu
->features
&
1558 (ARM_SMMU_FEAT_TRANS_S1
| ARM_SMMU_FEAT_TRANS_S2
))) {
1559 dev_err(smmu
->dev
, "\tno translation support!\n");
1563 if ((id
& ID0_S1TS
) && ((smmu
->version
== 1) || !(id
& ID0_ATOSNS
))) {
1564 smmu
->features
|= ARM_SMMU_FEAT_TRANS_OPS
;
1565 dev_notice(smmu
->dev
, "\taddress translation ops\n");
1569 * In order for DMA API calls to work properly, we must defer to what
1570 * the DT says about coherency, regardless of what the hardware claims.
1571 * Fortunately, this also opens up a workaround for systems where the
1572 * ID register value has ended up configured incorrectly.
1574 cttw_dt
= of_dma_is_coherent(smmu
->dev
->of_node
);
1575 cttw_reg
= !!(id
& ID0_CTTW
);
1577 smmu
->features
|= ARM_SMMU_FEAT_COHERENT_WALK
;
1578 if (cttw_dt
|| cttw_reg
)
1579 dev_notice(smmu
->dev
, "\t%scoherent table walk\n",
1580 cttw_dt
? "" : "non-");
1581 if (cttw_dt
!= cttw_reg
)
1582 dev_notice(smmu
->dev
,
1583 "\t(IDR0.CTTW overridden by dma-coherent property)\n");
1588 smmu
->features
|= ARM_SMMU_FEAT_STREAM_MATCH
;
1589 smmu
->num_mapping_groups
= (id
>> ID0_NUMSMRG_SHIFT
) &
1591 if (smmu
->num_mapping_groups
== 0) {
1593 "stream-matching supported, but no SMRs present!\n");
1597 smr
= SMR_MASK_MASK
<< SMR_MASK_SHIFT
;
1598 smr
|= (SMR_ID_MASK
<< SMR_ID_SHIFT
);
1599 writel_relaxed(smr
, gr0_base
+ ARM_SMMU_GR0_SMR(0));
1600 smr
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_SMR(0));
1602 mask
= (smr
>> SMR_MASK_SHIFT
) & SMR_MASK_MASK
;
1603 sid
= (smr
>> SMR_ID_SHIFT
) & SMR_ID_MASK
;
1604 if ((mask
& sid
) != sid
) {
1606 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1611 dev_notice(smmu
->dev
,
1612 "\tstream matching with %u register groups, mask 0x%x",
1613 smmu
->num_mapping_groups
, mask
);
1615 smmu
->num_mapping_groups
= (id
>> ID0_NUMSIDB_SHIFT
) &
1620 id
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_ID1
);
1621 smmu
->pgshift
= (id
& ID1_PAGESIZE
) ? 16 : 12;
1623 /* Check for size mismatch of SMMU address space from mapped region */
1624 size
= 1 << (((id
>> ID1_NUMPAGENDXB_SHIFT
) & ID1_NUMPAGENDXB_MASK
) + 1);
1625 size
*= 2 << smmu
->pgshift
;
1626 if (smmu
->size
!= size
)
1628 "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1631 smmu
->num_s2_context_banks
= (id
>> ID1_NUMS2CB_SHIFT
) & ID1_NUMS2CB_MASK
;
1632 smmu
->num_context_banks
= (id
>> ID1_NUMCB_SHIFT
) & ID1_NUMCB_MASK
;
1633 if (smmu
->num_s2_context_banks
> smmu
->num_context_banks
) {
1634 dev_err(smmu
->dev
, "impossible number of S2 context banks!\n");
1637 dev_notice(smmu
->dev
, "\t%u context banks (%u stage-2 only)\n",
1638 smmu
->num_context_banks
, smmu
->num_s2_context_banks
);
1641 id
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_ID2
);
1642 size
= arm_smmu_id_size_to_bits((id
>> ID2_IAS_SHIFT
) & ID2_IAS_MASK
);
1643 smmu
->ipa_size
= size
;
1645 /* The output mask is also applied for bypass */
1646 size
= arm_smmu_id_size_to_bits((id
>> ID2_OAS_SHIFT
) & ID2_OAS_MASK
);
1647 smmu
->pa_size
= size
;
1650 * What the page table walker can address actually depends on which
1651 * descriptor format is in use, but since a) we don't know that yet,
1652 * and b) it can vary per context bank, this will have to do...
1654 if (dma_set_mask_and_coherent(smmu
->dev
, DMA_BIT_MASK(size
)))
1656 "failed to set DMA mask for table walker\n");
1658 if (smmu
->version
== ARM_SMMU_V1
) {
1659 smmu
->va_size
= smmu
->ipa_size
;
1660 size
= SZ_4K
| SZ_2M
| SZ_1G
;
1662 size
= (id
>> ID2_UBS_SHIFT
) & ID2_UBS_MASK
;
1663 smmu
->va_size
= arm_smmu_id_size_to_bits(size
);
1664 #ifndef CONFIG_64BIT
1665 smmu
->va_size
= min(32UL, smmu
->va_size
);
1668 if (id
& ID2_PTFS_4K
)
1669 size
|= SZ_4K
| SZ_2M
| SZ_1G
;
1670 if (id
& ID2_PTFS_16K
)
1671 size
|= SZ_16K
| SZ_32M
;
1672 if (id
& ID2_PTFS_64K
)
1673 size
|= SZ_64K
| SZ_512M
;
1676 arm_smmu_ops
.pgsize_bitmap
&= size
;
1677 dev_notice(smmu
->dev
, "\tSupported page sizes: 0x%08lx\n", size
);
1679 if (smmu
->features
& ARM_SMMU_FEAT_TRANS_S1
)
1680 dev_notice(smmu
->dev
, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n",
1681 smmu
->va_size
, smmu
->ipa_size
);
1683 if (smmu
->features
& ARM_SMMU_FEAT_TRANS_S2
)
1684 dev_notice(smmu
->dev
, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n",
1685 smmu
->ipa_size
, smmu
->pa_size
);
1690 static const struct of_device_id arm_smmu_of_match
[] = {
1691 { .compatible
= "arm,smmu-v1", .data
= (void *)ARM_SMMU_V1
},
1692 { .compatible
= "arm,smmu-v2", .data
= (void *)ARM_SMMU_V2
},
1693 { .compatible
= "arm,mmu-400", .data
= (void *)ARM_SMMU_V1
},
1694 { .compatible
= "arm,mmu-401", .data
= (void *)ARM_SMMU_V1
},
1695 { .compatible
= "arm,mmu-500", .data
= (void *)ARM_SMMU_V2
},
1698 MODULE_DEVICE_TABLE(of
, arm_smmu_of_match
);
1700 static int arm_smmu_device_dt_probe(struct platform_device
*pdev
)
1702 const struct of_device_id
*of_id
;
1703 struct resource
*res
;
1704 struct arm_smmu_device
*smmu
;
1705 struct device
*dev
= &pdev
->dev
;
1706 struct rb_node
*node
;
1707 struct of_phandle_args masterspec
;
1708 int num_irqs
, i
, err
;
1710 smmu
= devm_kzalloc(dev
, sizeof(*smmu
), GFP_KERNEL
);
1712 dev_err(dev
, "failed to allocate arm_smmu_device\n");
1717 of_id
= of_match_node(arm_smmu_of_match
, dev
->of_node
);
1718 smmu
->version
= (enum arm_smmu_arch_version
)of_id
->data
;
1720 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1721 smmu
->base
= devm_ioremap_resource(dev
, res
);
1722 if (IS_ERR(smmu
->base
))
1723 return PTR_ERR(smmu
->base
);
1724 smmu
->size
= resource_size(res
);
1726 if (of_property_read_u32(dev
->of_node
, "#global-interrupts",
1727 &smmu
->num_global_irqs
)) {
1728 dev_err(dev
, "missing #global-interrupts property\n");
1733 while ((res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, num_irqs
))) {
1735 if (num_irqs
> smmu
->num_global_irqs
)
1736 smmu
->num_context_irqs
++;
1739 if (!smmu
->num_context_irqs
) {
1740 dev_err(dev
, "found %d interrupts but expected at least %d\n",
1741 num_irqs
, smmu
->num_global_irqs
+ 1);
1745 smmu
->irqs
= devm_kzalloc(dev
, sizeof(*smmu
->irqs
) * num_irqs
,
1748 dev_err(dev
, "failed to allocate %d irqs\n", num_irqs
);
1752 for (i
= 0; i
< num_irqs
; ++i
) {
1753 int irq
= platform_get_irq(pdev
, i
);
1756 dev_err(dev
, "failed to get irq index %d\n", i
);
1759 smmu
->irqs
[i
] = irq
;
1762 err
= arm_smmu_device_cfg_probe(smmu
);
1767 smmu
->masters
= RB_ROOT
;
1768 while (!of_parse_phandle_with_args(dev
->of_node
, "mmu-masters",
1769 "#stream-id-cells", i
,
1771 err
= register_smmu_master(smmu
, dev
, &masterspec
);
1773 dev_err(dev
, "failed to add master %s\n",
1774 masterspec
.np
->name
);
1775 goto out_put_masters
;
1780 dev_notice(dev
, "registered %d master devices\n", i
);
1782 parse_driver_options(smmu
);
1784 if (smmu
->version
> ARM_SMMU_V1
&&
1785 smmu
->num_context_banks
!= smmu
->num_context_irqs
) {
1787 "found only %d context interrupt(s) but %d required\n",
1788 smmu
->num_context_irqs
, smmu
->num_context_banks
);
1790 goto out_put_masters
;
1793 for (i
= 0; i
< smmu
->num_global_irqs
; ++i
) {
1794 err
= request_irq(smmu
->irqs
[i
],
1795 arm_smmu_global_fault
,
1797 "arm-smmu global fault",
1800 dev_err(dev
, "failed to request global IRQ %d (%u)\n",
1806 INIT_LIST_HEAD(&smmu
->list
);
1807 spin_lock(&arm_smmu_devices_lock
);
1808 list_add(&smmu
->list
, &arm_smmu_devices
);
1809 spin_unlock(&arm_smmu_devices_lock
);
1811 arm_smmu_device_reset(smmu
);
1816 free_irq(smmu
->irqs
[i
], smmu
);
1819 for (node
= rb_first(&smmu
->masters
); node
; node
= rb_next(node
)) {
1820 struct arm_smmu_master
*master
1821 = container_of(node
, struct arm_smmu_master
, node
);
1822 of_node_put(master
->of_node
);
1828 static int arm_smmu_device_remove(struct platform_device
*pdev
)
1831 struct device
*dev
= &pdev
->dev
;
1832 struct arm_smmu_device
*curr
, *smmu
= NULL
;
1833 struct rb_node
*node
;
1835 spin_lock(&arm_smmu_devices_lock
);
1836 list_for_each_entry(curr
, &arm_smmu_devices
, list
) {
1837 if (curr
->dev
== dev
) {
1839 list_del(&smmu
->list
);
1843 spin_unlock(&arm_smmu_devices_lock
);
1848 for (node
= rb_first(&smmu
->masters
); node
; node
= rb_next(node
)) {
1849 struct arm_smmu_master
*master
1850 = container_of(node
, struct arm_smmu_master
, node
);
1851 of_node_put(master
->of_node
);
1854 if (!bitmap_empty(smmu
->context_map
, ARM_SMMU_MAX_CBS
))
1855 dev_err(dev
, "removing device with active domains!\n");
1857 for (i
= 0; i
< smmu
->num_global_irqs
; ++i
)
1858 free_irq(smmu
->irqs
[i
], smmu
);
1860 /* Turn the thing off */
1861 writel(sCR0_CLIENTPD
, ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sCR0
);
1865 static struct platform_driver arm_smmu_driver
= {
1868 .of_match_table
= of_match_ptr(arm_smmu_of_match
),
1870 .probe
= arm_smmu_device_dt_probe
,
1871 .remove
= arm_smmu_device_remove
,
1874 static int __init
arm_smmu_init(void)
1876 struct device_node
*np
;
1880 * Play nice with systems that don't have an ARM SMMU by checking that
1881 * an ARM SMMU exists in the system before proceeding with the driver
1882 * and IOMMU bus operation registration.
1884 np
= of_find_matching_node(NULL
, arm_smmu_of_match
);
1890 ret
= platform_driver_register(&arm_smmu_driver
);
1894 /* Oh, for a proper bus abstraction */
1895 if (!iommu_present(&platform_bus_type
))
1896 bus_set_iommu(&platform_bus_type
, &arm_smmu_ops
);
1898 #ifdef CONFIG_ARM_AMBA
1899 if (!iommu_present(&amba_bustype
))
1900 bus_set_iommu(&amba_bustype
, &arm_smmu_ops
);
1904 if (!iommu_present(&pci_bus_type
))
1905 bus_set_iommu(&pci_bus_type
, &arm_smmu_ops
);
1911 static void __exit
arm_smmu_exit(void)
1913 return platform_driver_unregister(&arm_smmu_driver
);
1916 subsys_initcall(arm_smmu_init
);
1917 module_exit(arm_smmu_exit
);
1919 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
1920 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1921 MODULE_LICENSE("GPL v2");