2 * Copyright (c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21 * Author: Fenghua Yu <fenghua.yu@intel.com>
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/export.h>
28 #include <linux/slab.h>
29 #include <linux/irq.h>
30 #include <linux/interrupt.h>
31 #include <linux/spinlock.h>
32 #include <linux/pci.h>
33 #include <linux/dmar.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/mempool.h>
36 #include <linux/timer.h>
37 #include <linux/iova.h>
38 #include <linux/iommu.h>
39 #include <linux/intel-iommu.h>
40 #include <linux/syscore_ops.h>
41 #include <linux/tboot.h>
42 #include <linux/dmi.h>
43 #include <linux/pci-ats.h>
44 #include <linux/memblock.h>
45 #include <asm/cacheflush.h>
46 #include <asm/iommu.h>
48 #define ROOT_SIZE VTD_PAGE_SIZE
49 #define CONTEXT_SIZE VTD_PAGE_SIZE
51 #define IS_BRIDGE_HOST_DEVICE(pdev) \
52 ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
53 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
54 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
55 #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
57 #define IOAPIC_RANGE_START (0xfee00000)
58 #define IOAPIC_RANGE_END (0xfeefffff)
59 #define IOVA_START_ADDR (0x1000)
61 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
63 #define MAX_AGAW_WIDTH 64
65 #define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
66 #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
68 /* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
69 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
70 #define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
71 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
72 #define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
74 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
75 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
76 #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
78 /* page table handling */
79 #define LEVEL_STRIDE (9)
80 #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
83 * This bitmap is used to advertise the page sizes our hardware support
84 * to the IOMMU core, which will then use this information to split
85 * physically contiguous memory regions it is mapping into page sizes
88 * Traditionally the IOMMU core just handed us the mappings directly,
89 * after making sure the size is an order of a 4KiB page and that the
90 * mapping has natural alignment.
92 * To retain this behavior, we currently advertise that we support
93 * all page sizes that are an order of 4KiB.
95 * If at some point we'd like to utilize the IOMMU core's new behavior,
96 * we could change this to advertise the real page sizes we support.
98 #define INTEL_IOMMU_PGSIZES (~0xFFFUL)
100 static inline int agaw_to_level(int agaw
)
105 static inline int agaw_to_width(int agaw
)
107 return 30 + agaw
* LEVEL_STRIDE
;
110 static inline int width_to_agaw(int width
)
112 return (width
- 30) / LEVEL_STRIDE
;
115 static inline unsigned int level_to_offset_bits(int level
)
117 return (level
- 1) * LEVEL_STRIDE
;
120 static inline int pfn_level_offset(unsigned long pfn
, int level
)
122 return (pfn
>> level_to_offset_bits(level
)) & LEVEL_MASK
;
125 static inline unsigned long level_mask(int level
)
127 return -1UL << level_to_offset_bits(level
);
130 static inline unsigned long level_size(int level
)
132 return 1UL << level_to_offset_bits(level
);
135 static inline unsigned long align_to_level(unsigned long pfn
, int level
)
137 return (pfn
+ level_size(level
) - 1) & level_mask(level
);
140 static inline unsigned long lvl_to_nr_pages(unsigned int lvl
)
142 return 1 << ((lvl
- 1) * LEVEL_STRIDE
);
145 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
146 are never going to work. */
147 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn
)
149 return dma_pfn
>> (PAGE_SHIFT
- VTD_PAGE_SHIFT
);
152 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn
)
154 return mm_pfn
<< (PAGE_SHIFT
- VTD_PAGE_SHIFT
);
156 static inline unsigned long page_to_dma_pfn(struct page
*pg
)
158 return mm_to_dma_pfn(page_to_pfn(pg
));
160 static inline unsigned long virt_to_dma_pfn(void *p
)
162 return page_to_dma_pfn(virt_to_page(p
));
165 /* global iommu list, set NULL for ignored DMAR units */
166 static struct intel_iommu
**g_iommus
;
168 static void __init
check_tylersburg_isoch(void);
169 static int rwbf_quirk
;
172 * set to 1 to panic kernel if can't successfully enable VT-d
173 * (used when kernel is launched w/ TXT)
175 static int force_on
= 0;
180 * 12-63: Context Ptr (12 - (haw-1))
187 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
188 static inline bool root_present(struct root_entry
*root
)
190 return (root
->val
& 1);
192 static inline void set_root_present(struct root_entry
*root
)
196 static inline void set_root_value(struct root_entry
*root
, unsigned long value
)
198 root
->val
|= value
& VTD_PAGE_MASK
;
201 static inline struct context_entry
*
202 get_context_addr_from_root(struct root_entry
*root
)
204 return (struct context_entry
*)
205 (root_present(root
)?phys_to_virt(
206 root
->val
& VTD_PAGE_MASK
) :
213 * 1: fault processing disable
214 * 2-3: translation type
215 * 12-63: address space root
221 struct context_entry
{
226 static inline bool context_present(struct context_entry
*context
)
228 return (context
->lo
& 1);
230 static inline void context_set_present(struct context_entry
*context
)
235 static inline void context_set_fault_enable(struct context_entry
*context
)
237 context
->lo
&= (((u64
)-1) << 2) | 1;
240 static inline void context_set_translation_type(struct context_entry
*context
,
243 context
->lo
&= (((u64
)-1) << 4) | 3;
244 context
->lo
|= (value
& 3) << 2;
247 static inline void context_set_address_root(struct context_entry
*context
,
250 context
->lo
|= value
& VTD_PAGE_MASK
;
253 static inline void context_set_address_width(struct context_entry
*context
,
256 context
->hi
|= value
& 7;
259 static inline void context_set_domain_id(struct context_entry
*context
,
262 context
->hi
|= (value
& ((1 << 16) - 1)) << 8;
265 static inline void context_clear_entry(struct context_entry
*context
)
278 * 12-63: Host physcial address
284 static inline void dma_clear_pte(struct dma_pte
*pte
)
289 static inline void dma_set_pte_readable(struct dma_pte
*pte
)
291 pte
->val
|= DMA_PTE_READ
;
294 static inline void dma_set_pte_writable(struct dma_pte
*pte
)
296 pte
->val
|= DMA_PTE_WRITE
;
299 static inline void dma_set_pte_snp(struct dma_pte
*pte
)
301 pte
->val
|= DMA_PTE_SNP
;
304 static inline void dma_set_pte_prot(struct dma_pte
*pte
, unsigned long prot
)
306 pte
->val
= (pte
->val
& ~3) | (prot
& 3);
309 static inline u64
dma_pte_addr(struct dma_pte
*pte
)
312 return pte
->val
& VTD_PAGE_MASK
;
314 /* Must have a full atomic 64-bit read */
315 return __cmpxchg64(&pte
->val
, 0ULL, 0ULL) & VTD_PAGE_MASK
;
319 static inline void dma_set_pte_pfn(struct dma_pte
*pte
, unsigned long pfn
)
321 pte
->val
|= (uint64_t)pfn
<< VTD_PAGE_SHIFT
;
324 static inline bool dma_pte_present(struct dma_pte
*pte
)
326 return (pte
->val
& 3) != 0;
329 static inline bool dma_pte_superpage(struct dma_pte
*pte
)
331 return (pte
->val
& (1 << 7));
334 static inline int first_pte_in_page(struct dma_pte
*pte
)
336 return !((unsigned long)pte
& ~VTD_PAGE_MASK
);
340 * This domain is a statically identity mapping domain.
341 * 1. This domain creats a static 1:1 mapping to all usable memory.
342 * 2. It maps to each iommu if successful.
343 * 3. Each iommu mapps to this domain if successful.
345 static struct dmar_domain
*si_domain
;
346 static int hw_pass_through
= 1;
348 /* devices under the same p2p bridge are owned in one domain */
349 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
351 /* domain represents a virtual machine, more than one devices
352 * across iommus may be owned in one domain, e.g. kvm guest.
354 #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
356 /* si_domain contains mulitple devices */
357 #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
360 int id
; /* domain id */
361 int nid
; /* node id */
362 unsigned long iommu_bmp
; /* bitmap of iommus this domain uses*/
364 struct list_head devices
; /* all devices' list */
365 struct iova_domain iovad
; /* iova's that belong to this domain */
367 struct dma_pte
*pgd
; /* virtual address */
368 int gaw
; /* max guest address width */
370 /* adjusted guest address width, 0 is level 2 30-bit */
373 int flags
; /* flags to find out type of domain */
375 int iommu_coherency
;/* indicate coherency of iommu access */
376 int iommu_snooping
; /* indicate snooping control feature*/
377 int iommu_count
; /* reference count of iommu */
378 int iommu_superpage
;/* Level of superpages supported:
379 0 == 4KiB (no superpages), 1 == 2MiB,
380 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
381 spinlock_t iommu_lock
; /* protect iommu set in domain */
382 u64 max_addr
; /* maximum mapped address */
385 /* PCI domain-device relationship */
386 struct device_domain_info
{
387 struct list_head link
; /* link to domain siblings */
388 struct list_head global
; /* link to global list */
389 int segment
; /* PCI domain */
390 u8 bus
; /* PCI bus number */
391 u8 devfn
; /* PCI devfn number */
392 struct pci_dev
*dev
; /* it's NULL for PCIe-to-PCI bridge */
393 struct intel_iommu
*iommu
; /* IOMMU used by this device */
394 struct dmar_domain
*domain
; /* pointer to domain */
397 static void flush_unmaps_timeout(unsigned long data
);
399 DEFINE_TIMER(unmap_timer
, flush_unmaps_timeout
, 0, 0);
401 #define HIGH_WATER_MARK 250
402 struct deferred_flush_tables
{
404 struct iova
*iova
[HIGH_WATER_MARK
];
405 struct dmar_domain
*domain
[HIGH_WATER_MARK
];
408 static struct deferred_flush_tables
*deferred_flush
;
410 /* bitmap for indexing intel_iommus */
411 static int g_num_of_iommus
;
413 static DEFINE_SPINLOCK(async_umap_flush_lock
);
414 static LIST_HEAD(unmaps_to_do
);
417 static long list_size
;
419 static void domain_remove_dev_info(struct dmar_domain
*domain
);
421 #ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
422 int dmar_disabled
= 0;
424 int dmar_disabled
= 1;
425 #endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
427 int intel_iommu_enabled
= 0;
428 EXPORT_SYMBOL_GPL(intel_iommu_enabled
);
430 static int dmar_map_gfx
= 1;
431 static int dmar_forcedac
;
432 static int intel_iommu_strict
;
433 static int intel_iommu_superpage
= 1;
435 int intel_iommu_gfx_mapped
;
436 EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped
);
438 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
439 static DEFINE_SPINLOCK(device_domain_lock
);
440 static LIST_HEAD(device_domain_list
);
442 static struct iommu_ops intel_iommu_ops
;
444 static int __init
intel_iommu_setup(char *str
)
449 if (!strncmp(str
, "on", 2)) {
451 printk(KERN_INFO
"Intel-IOMMU: enabled\n");
452 } else if (!strncmp(str
, "off", 3)) {
454 printk(KERN_INFO
"Intel-IOMMU: disabled\n");
455 } else if (!strncmp(str
, "igfx_off", 8)) {
458 "Intel-IOMMU: disable GFX device mapping\n");
459 } else if (!strncmp(str
, "forcedac", 8)) {
461 "Intel-IOMMU: Forcing DAC for PCI devices\n");
463 } else if (!strncmp(str
, "strict", 6)) {
465 "Intel-IOMMU: disable batched IOTLB flush\n");
466 intel_iommu_strict
= 1;
467 } else if (!strncmp(str
, "sp_off", 6)) {
469 "Intel-IOMMU: disable supported super page\n");
470 intel_iommu_superpage
= 0;
473 str
+= strcspn(str
, ",");
479 __setup("intel_iommu=", intel_iommu_setup
);
481 static struct kmem_cache
*iommu_domain_cache
;
482 static struct kmem_cache
*iommu_devinfo_cache
;
483 static struct kmem_cache
*iommu_iova_cache
;
485 static inline void *alloc_pgtable_page(int node
)
490 page
= alloc_pages_node(node
, GFP_ATOMIC
| __GFP_ZERO
, 0);
492 vaddr
= page_address(page
);
496 static inline void free_pgtable_page(void *vaddr
)
498 free_page((unsigned long)vaddr
);
501 static inline void *alloc_domain_mem(void)
503 return kmem_cache_alloc(iommu_domain_cache
, GFP_ATOMIC
);
506 static void free_domain_mem(void *vaddr
)
508 kmem_cache_free(iommu_domain_cache
, vaddr
);
511 static inline void * alloc_devinfo_mem(void)
513 return kmem_cache_alloc(iommu_devinfo_cache
, GFP_ATOMIC
);
516 static inline void free_devinfo_mem(void *vaddr
)
518 kmem_cache_free(iommu_devinfo_cache
, vaddr
);
521 struct iova
*alloc_iova_mem(void)
523 return kmem_cache_alloc(iommu_iova_cache
, GFP_ATOMIC
);
526 void free_iova_mem(struct iova
*iova
)
528 kmem_cache_free(iommu_iova_cache
, iova
);
532 static int __iommu_calculate_agaw(struct intel_iommu
*iommu
, int max_gaw
)
537 sagaw
= cap_sagaw(iommu
->cap
);
538 for (agaw
= width_to_agaw(max_gaw
);
540 if (test_bit(agaw
, &sagaw
))
548 * Calculate max SAGAW for each iommu.
550 int iommu_calculate_max_sagaw(struct intel_iommu
*iommu
)
552 return __iommu_calculate_agaw(iommu
, MAX_AGAW_WIDTH
);
556 * calculate agaw for each iommu.
557 * "SAGAW" may be different across iommus, use a default agaw, and
558 * get a supported less agaw for iommus that don't support the default agaw.
560 int iommu_calculate_agaw(struct intel_iommu
*iommu
)
562 return __iommu_calculate_agaw(iommu
, DEFAULT_DOMAIN_ADDRESS_WIDTH
);
565 /* This functionin only returns single iommu in a domain */
566 static struct intel_iommu
*domain_get_iommu(struct dmar_domain
*domain
)
570 /* si_domain and vm domain should not get here. */
571 BUG_ON(domain
->flags
& DOMAIN_FLAG_VIRTUAL_MACHINE
);
572 BUG_ON(domain
->flags
& DOMAIN_FLAG_STATIC_IDENTITY
);
574 iommu_id
= find_first_bit(&domain
->iommu_bmp
, g_num_of_iommus
);
575 if (iommu_id
< 0 || iommu_id
>= g_num_of_iommus
)
578 return g_iommus
[iommu_id
];
581 static void domain_update_iommu_coherency(struct dmar_domain
*domain
)
585 domain
->iommu_coherency
= 1;
587 for_each_set_bit(i
, &domain
->iommu_bmp
, g_num_of_iommus
) {
588 if (!ecap_coherent(g_iommus
[i
]->ecap
)) {
589 domain
->iommu_coherency
= 0;
595 static void domain_update_iommu_snooping(struct dmar_domain
*domain
)
599 domain
->iommu_snooping
= 1;
601 for_each_set_bit(i
, &domain
->iommu_bmp
, g_num_of_iommus
) {
602 if (!ecap_sc_support(g_iommus
[i
]->ecap
)) {
603 domain
->iommu_snooping
= 0;
609 static void domain_update_iommu_superpage(struct dmar_domain
*domain
)
611 struct dmar_drhd_unit
*drhd
;
612 struct intel_iommu
*iommu
= NULL
;
615 if (!intel_iommu_superpage
) {
616 domain
->iommu_superpage
= 0;
620 /* set iommu_superpage to the smallest common denominator */
621 for_each_active_iommu(iommu
, drhd
) {
622 mask
&= cap_super_page_val(iommu
->cap
);
627 domain
->iommu_superpage
= fls(mask
);
630 /* Some capabilities may be different across iommus */
631 static void domain_update_iommu_cap(struct dmar_domain
*domain
)
633 domain_update_iommu_coherency(domain
);
634 domain_update_iommu_snooping(domain
);
635 domain_update_iommu_superpage(domain
);
638 static struct intel_iommu
*device_to_iommu(int segment
, u8 bus
, u8 devfn
)
640 struct dmar_drhd_unit
*drhd
= NULL
;
643 for_each_drhd_unit(drhd
) {
646 if (segment
!= drhd
->segment
)
649 for (i
= 0; i
< drhd
->devices_cnt
; i
++) {
650 if (drhd
->devices
[i
] &&
651 drhd
->devices
[i
]->bus
->number
== bus
&&
652 drhd
->devices
[i
]->devfn
== devfn
)
654 if (drhd
->devices
[i
] &&
655 drhd
->devices
[i
]->subordinate
&&
656 drhd
->devices
[i
]->subordinate
->number
<= bus
&&
657 drhd
->devices
[i
]->subordinate
->subordinate
>= bus
)
661 if (drhd
->include_all
)
668 static void domain_flush_cache(struct dmar_domain
*domain
,
669 void *addr
, int size
)
671 if (!domain
->iommu_coherency
)
672 clflush_cache_range(addr
, size
);
675 /* Gets context entry for a given bus and devfn */
676 static struct context_entry
* device_to_context_entry(struct intel_iommu
*iommu
,
679 struct root_entry
*root
;
680 struct context_entry
*context
;
681 unsigned long phy_addr
;
684 spin_lock_irqsave(&iommu
->lock
, flags
);
685 root
= &iommu
->root_entry
[bus
];
686 context
= get_context_addr_from_root(root
);
688 context
= (struct context_entry
*)
689 alloc_pgtable_page(iommu
->node
);
691 spin_unlock_irqrestore(&iommu
->lock
, flags
);
694 __iommu_flush_cache(iommu
, (void *)context
, CONTEXT_SIZE
);
695 phy_addr
= virt_to_phys((void *)context
);
696 set_root_value(root
, phy_addr
);
697 set_root_present(root
);
698 __iommu_flush_cache(iommu
, root
, sizeof(*root
));
700 spin_unlock_irqrestore(&iommu
->lock
, flags
);
701 return &context
[devfn
];
704 static int device_context_mapped(struct intel_iommu
*iommu
, u8 bus
, u8 devfn
)
706 struct root_entry
*root
;
707 struct context_entry
*context
;
711 spin_lock_irqsave(&iommu
->lock
, flags
);
712 root
= &iommu
->root_entry
[bus
];
713 context
= get_context_addr_from_root(root
);
718 ret
= context_present(&context
[devfn
]);
720 spin_unlock_irqrestore(&iommu
->lock
, flags
);
724 static void clear_context_table(struct intel_iommu
*iommu
, u8 bus
, u8 devfn
)
726 struct root_entry
*root
;
727 struct context_entry
*context
;
730 spin_lock_irqsave(&iommu
->lock
, flags
);
731 root
= &iommu
->root_entry
[bus
];
732 context
= get_context_addr_from_root(root
);
734 context_clear_entry(&context
[devfn
]);
735 __iommu_flush_cache(iommu
, &context
[devfn
], \
738 spin_unlock_irqrestore(&iommu
->lock
, flags
);
741 static void free_context_table(struct intel_iommu
*iommu
)
743 struct root_entry
*root
;
746 struct context_entry
*context
;
748 spin_lock_irqsave(&iommu
->lock
, flags
);
749 if (!iommu
->root_entry
) {
752 for (i
= 0; i
< ROOT_ENTRY_NR
; i
++) {
753 root
= &iommu
->root_entry
[i
];
754 context
= get_context_addr_from_root(root
);
756 free_pgtable_page(context
);
758 free_pgtable_page(iommu
->root_entry
);
759 iommu
->root_entry
= NULL
;
761 spin_unlock_irqrestore(&iommu
->lock
, flags
);
764 static struct dma_pte
*pfn_to_dma_pte(struct dmar_domain
*domain
,
765 unsigned long pfn
, int target_level
)
767 int addr_width
= agaw_to_width(domain
->agaw
) - VTD_PAGE_SHIFT
;
768 struct dma_pte
*parent
, *pte
= NULL
;
769 int level
= agaw_to_level(domain
->agaw
);
772 BUG_ON(!domain
->pgd
);
773 BUG_ON(addr_width
< BITS_PER_LONG
&& pfn
>> addr_width
);
774 parent
= domain
->pgd
;
779 offset
= pfn_level_offset(pfn
, level
);
780 pte
= &parent
[offset
];
781 if (!target_level
&& (dma_pte_superpage(pte
) || !dma_pte_present(pte
)))
783 if (level
== target_level
)
786 if (!dma_pte_present(pte
)) {
789 tmp_page
= alloc_pgtable_page(domain
->nid
);
794 domain_flush_cache(domain
, tmp_page
, VTD_PAGE_SIZE
);
795 pteval
= ((uint64_t)virt_to_dma_pfn(tmp_page
) << VTD_PAGE_SHIFT
) | DMA_PTE_READ
| DMA_PTE_WRITE
;
796 if (cmpxchg64(&pte
->val
, 0ULL, pteval
)) {
797 /* Someone else set it while we were thinking; use theirs. */
798 free_pgtable_page(tmp_page
);
801 domain_flush_cache(domain
, pte
, sizeof(*pte
));
804 parent
= phys_to_virt(dma_pte_addr(pte
));
812 /* return address's pte at specific level */
813 static struct dma_pte
*dma_pfn_level_pte(struct dmar_domain
*domain
,
815 int level
, int *large_page
)
817 struct dma_pte
*parent
, *pte
= NULL
;
818 int total
= agaw_to_level(domain
->agaw
);
821 parent
= domain
->pgd
;
822 while (level
<= total
) {
823 offset
= pfn_level_offset(pfn
, total
);
824 pte
= &parent
[offset
];
828 if (!dma_pte_present(pte
)) {
833 if (pte
->val
& DMA_PTE_LARGE_PAGE
) {
838 parent
= phys_to_virt(dma_pte_addr(pte
));
844 /* clear last level pte, a tlb flush should be followed */
845 static int dma_pte_clear_range(struct dmar_domain
*domain
,
846 unsigned long start_pfn
,
847 unsigned long last_pfn
)
849 int addr_width
= agaw_to_width(domain
->agaw
) - VTD_PAGE_SHIFT
;
850 unsigned int large_page
= 1;
851 struct dma_pte
*first_pte
, *pte
;
854 BUG_ON(addr_width
< BITS_PER_LONG
&& start_pfn
>> addr_width
);
855 BUG_ON(addr_width
< BITS_PER_LONG
&& last_pfn
>> addr_width
);
856 BUG_ON(start_pfn
> last_pfn
);
858 /* we don't need lock here; nobody else touches the iova range */
861 first_pte
= pte
= dma_pfn_level_pte(domain
, start_pfn
, 1, &large_page
);
863 start_pfn
= align_to_level(start_pfn
+ 1, large_page
+ 1);
868 start_pfn
+= lvl_to_nr_pages(large_page
);
870 } while (start_pfn
<= last_pfn
&& !first_pte_in_page(pte
));
872 domain_flush_cache(domain
, first_pte
,
873 (void *)pte
- (void *)first_pte
);
875 } while (start_pfn
&& start_pfn
<= last_pfn
);
877 order
= (large_page
- 1) * 9;
881 /* free page table pages. last level pte should already be cleared */
882 static void dma_pte_free_pagetable(struct dmar_domain
*domain
,
883 unsigned long start_pfn
,
884 unsigned long last_pfn
)
886 int addr_width
= agaw_to_width(domain
->agaw
) - VTD_PAGE_SHIFT
;
887 struct dma_pte
*first_pte
, *pte
;
888 int total
= agaw_to_level(domain
->agaw
);
893 BUG_ON(addr_width
< BITS_PER_LONG
&& start_pfn
>> addr_width
);
894 BUG_ON(addr_width
< BITS_PER_LONG
&& last_pfn
>> addr_width
);
895 BUG_ON(start_pfn
> last_pfn
);
897 /* We don't need lock here; nobody else touches the iova range */
899 while (level
<= total
) {
900 tmp
= align_to_level(start_pfn
, level
);
902 /* If we can't even clear one PTE at this level, we're done */
903 if (tmp
+ level_size(level
) - 1 > last_pfn
)
908 first_pte
= pte
= dma_pfn_level_pte(domain
, tmp
, level
, &large_page
);
909 if (large_page
> level
)
910 level
= large_page
+ 1;
912 tmp
= align_to_level(tmp
+ 1, level
+ 1);
916 if (dma_pte_present(pte
)) {
917 free_pgtable_page(phys_to_virt(dma_pte_addr(pte
)));
921 tmp
+= level_size(level
);
922 } while (!first_pte_in_page(pte
) &&
923 tmp
+ level_size(level
) - 1 <= last_pfn
);
925 domain_flush_cache(domain
, first_pte
,
926 (void *)pte
- (void *)first_pte
);
928 } while (tmp
&& tmp
+ level_size(level
) - 1 <= last_pfn
);
932 if (start_pfn
== 0 && last_pfn
== DOMAIN_MAX_PFN(domain
->gaw
)) {
933 free_pgtable_page(domain
->pgd
);
939 static int iommu_alloc_root_entry(struct intel_iommu
*iommu
)
941 struct root_entry
*root
;
944 root
= (struct root_entry
*)alloc_pgtable_page(iommu
->node
);
948 __iommu_flush_cache(iommu
, root
, ROOT_SIZE
);
950 spin_lock_irqsave(&iommu
->lock
, flags
);
951 iommu
->root_entry
= root
;
952 spin_unlock_irqrestore(&iommu
->lock
, flags
);
957 static void iommu_set_root_entry(struct intel_iommu
*iommu
)
963 addr
= iommu
->root_entry
;
965 raw_spin_lock_irqsave(&iommu
->register_lock
, flag
);
966 dmar_writeq(iommu
->reg
+ DMAR_RTADDR_REG
, virt_to_phys(addr
));
968 writel(iommu
->gcmd
| DMA_GCMD_SRTP
, iommu
->reg
+ DMAR_GCMD_REG
);
970 /* Make sure hardware complete it */
971 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
972 readl
, (sts
& DMA_GSTS_RTPS
), sts
);
974 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
977 static void iommu_flush_write_buffer(struct intel_iommu
*iommu
)
982 if (!rwbf_quirk
&& !cap_rwbf(iommu
->cap
))
985 raw_spin_lock_irqsave(&iommu
->register_lock
, flag
);
986 writel(iommu
->gcmd
| DMA_GCMD_WBF
, iommu
->reg
+ DMAR_GCMD_REG
);
988 /* Make sure hardware complete it */
989 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
990 readl
, (!(val
& DMA_GSTS_WBFS
)), val
);
992 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
995 /* return value determine if we need a write buffer flush */
996 static void __iommu_flush_context(struct intel_iommu
*iommu
,
997 u16 did
, u16 source_id
, u8 function_mask
,
1004 case DMA_CCMD_GLOBAL_INVL
:
1005 val
= DMA_CCMD_GLOBAL_INVL
;
1007 case DMA_CCMD_DOMAIN_INVL
:
1008 val
= DMA_CCMD_DOMAIN_INVL
|DMA_CCMD_DID(did
);
1010 case DMA_CCMD_DEVICE_INVL
:
1011 val
= DMA_CCMD_DEVICE_INVL
|DMA_CCMD_DID(did
)
1012 | DMA_CCMD_SID(source_id
) | DMA_CCMD_FM(function_mask
);
1017 val
|= DMA_CCMD_ICC
;
1019 raw_spin_lock_irqsave(&iommu
->register_lock
, flag
);
1020 dmar_writeq(iommu
->reg
+ DMAR_CCMD_REG
, val
);
1022 /* Make sure hardware complete it */
1023 IOMMU_WAIT_OP(iommu
, DMAR_CCMD_REG
,
1024 dmar_readq
, (!(val
& DMA_CCMD_ICC
)), val
);
1026 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
1029 /* return value determine if we need a write buffer flush */
1030 static void __iommu_flush_iotlb(struct intel_iommu
*iommu
, u16 did
,
1031 u64 addr
, unsigned int size_order
, u64 type
)
1033 int tlb_offset
= ecap_iotlb_offset(iommu
->ecap
);
1034 u64 val
= 0, val_iva
= 0;
1038 case DMA_TLB_GLOBAL_FLUSH
:
1039 /* global flush doesn't need set IVA_REG */
1040 val
= DMA_TLB_GLOBAL_FLUSH
|DMA_TLB_IVT
;
1042 case DMA_TLB_DSI_FLUSH
:
1043 val
= DMA_TLB_DSI_FLUSH
|DMA_TLB_IVT
|DMA_TLB_DID(did
);
1045 case DMA_TLB_PSI_FLUSH
:
1046 val
= DMA_TLB_PSI_FLUSH
|DMA_TLB_IVT
|DMA_TLB_DID(did
);
1047 /* Note: always flush non-leaf currently */
1048 val_iva
= size_order
| addr
;
1053 /* Note: set drain read/write */
1056 * This is probably to be super secure.. Looks like we can
1057 * ignore it without any impact.
1059 if (cap_read_drain(iommu
->cap
))
1060 val
|= DMA_TLB_READ_DRAIN
;
1062 if (cap_write_drain(iommu
->cap
))
1063 val
|= DMA_TLB_WRITE_DRAIN
;
1065 raw_spin_lock_irqsave(&iommu
->register_lock
, flag
);
1066 /* Note: Only uses first TLB reg currently */
1068 dmar_writeq(iommu
->reg
+ tlb_offset
, val_iva
);
1069 dmar_writeq(iommu
->reg
+ tlb_offset
+ 8, val
);
1071 /* Make sure hardware complete it */
1072 IOMMU_WAIT_OP(iommu
, tlb_offset
+ 8,
1073 dmar_readq
, (!(val
& DMA_TLB_IVT
)), val
);
1075 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
1077 /* check IOTLB invalidation granularity */
1078 if (DMA_TLB_IAIG(val
) == 0)
1079 printk(KERN_ERR
"IOMMU: flush IOTLB failed\n");
1080 if (DMA_TLB_IAIG(val
) != DMA_TLB_IIRG(type
))
1081 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
1082 (unsigned long long)DMA_TLB_IIRG(type
),
1083 (unsigned long long)DMA_TLB_IAIG(val
));
1086 static struct device_domain_info
*iommu_support_dev_iotlb(
1087 struct dmar_domain
*domain
, int segment
, u8 bus
, u8 devfn
)
1090 unsigned long flags
;
1091 struct device_domain_info
*info
;
1092 struct intel_iommu
*iommu
= device_to_iommu(segment
, bus
, devfn
);
1094 if (!ecap_dev_iotlb_support(iommu
->ecap
))
1100 spin_lock_irqsave(&device_domain_lock
, flags
);
1101 list_for_each_entry(info
, &domain
->devices
, link
)
1102 if (info
->bus
== bus
&& info
->devfn
== devfn
) {
1106 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1108 if (!found
|| !info
->dev
)
1111 if (!pci_find_ext_capability(info
->dev
, PCI_EXT_CAP_ID_ATS
))
1114 if (!dmar_find_matched_atsr_unit(info
->dev
))
1117 info
->iommu
= iommu
;
1122 static void iommu_enable_dev_iotlb(struct device_domain_info
*info
)
1127 pci_enable_ats(info
->dev
, VTD_PAGE_SHIFT
);
1130 static void iommu_disable_dev_iotlb(struct device_domain_info
*info
)
1132 if (!info
->dev
|| !pci_ats_enabled(info
->dev
))
1135 pci_disable_ats(info
->dev
);
1138 static void iommu_flush_dev_iotlb(struct dmar_domain
*domain
,
1139 u64 addr
, unsigned mask
)
1142 unsigned long flags
;
1143 struct device_domain_info
*info
;
1145 spin_lock_irqsave(&device_domain_lock
, flags
);
1146 list_for_each_entry(info
, &domain
->devices
, link
) {
1147 if (!info
->dev
|| !pci_ats_enabled(info
->dev
))
1150 sid
= info
->bus
<< 8 | info
->devfn
;
1151 qdep
= pci_ats_queue_depth(info
->dev
);
1152 qi_flush_dev_iotlb(info
->iommu
, sid
, qdep
, addr
, mask
);
1154 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1157 static void iommu_flush_iotlb_psi(struct intel_iommu
*iommu
, u16 did
,
1158 unsigned long pfn
, unsigned int pages
, int map
)
1160 unsigned int mask
= ilog2(__roundup_pow_of_two(pages
));
1161 uint64_t addr
= (uint64_t)pfn
<< VTD_PAGE_SHIFT
;
1166 * Fallback to domain selective flush if no PSI support or the size is
1168 * PSI requires page size to be 2 ^ x, and the base address is naturally
1169 * aligned to the size
1171 if (!cap_pgsel_inv(iommu
->cap
) || mask
> cap_max_amask_val(iommu
->cap
))
1172 iommu
->flush
.flush_iotlb(iommu
, did
, 0, 0,
1175 iommu
->flush
.flush_iotlb(iommu
, did
, addr
, mask
,
1179 * In caching mode, changes of pages from non-present to present require
1180 * flush. However, device IOTLB doesn't need to be flushed in this case.
1182 if (!cap_caching_mode(iommu
->cap
) || !map
)
1183 iommu_flush_dev_iotlb(iommu
->domains
[did
], addr
, mask
);
1186 static void iommu_disable_protect_mem_regions(struct intel_iommu
*iommu
)
1189 unsigned long flags
;
1191 raw_spin_lock_irqsave(&iommu
->register_lock
, flags
);
1192 pmen
= readl(iommu
->reg
+ DMAR_PMEN_REG
);
1193 pmen
&= ~DMA_PMEN_EPM
;
1194 writel(pmen
, iommu
->reg
+ DMAR_PMEN_REG
);
1196 /* wait for the protected region status bit to clear */
1197 IOMMU_WAIT_OP(iommu
, DMAR_PMEN_REG
,
1198 readl
, !(pmen
& DMA_PMEN_PRS
), pmen
);
1200 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
1203 static int iommu_enable_translation(struct intel_iommu
*iommu
)
1206 unsigned long flags
;
1208 raw_spin_lock_irqsave(&iommu
->register_lock
, flags
);
1209 iommu
->gcmd
|= DMA_GCMD_TE
;
1210 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
1212 /* Make sure hardware complete it */
1213 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
1214 readl
, (sts
& DMA_GSTS_TES
), sts
);
1216 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
1220 static int iommu_disable_translation(struct intel_iommu
*iommu
)
1225 raw_spin_lock_irqsave(&iommu
->register_lock
, flag
);
1226 iommu
->gcmd
&= ~DMA_GCMD_TE
;
1227 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
1229 /* Make sure hardware complete it */
1230 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
1231 readl
, (!(sts
& DMA_GSTS_TES
)), sts
);
1233 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
1238 static int iommu_init_domains(struct intel_iommu
*iommu
)
1240 unsigned long ndomains
;
1241 unsigned long nlongs
;
1243 ndomains
= cap_ndoms(iommu
->cap
);
1244 pr_debug("IOMMU %d: Number of Domains supportd <%ld>\n", iommu
->seq_id
,
1246 nlongs
= BITS_TO_LONGS(ndomains
);
1248 spin_lock_init(&iommu
->lock
);
1250 /* TBD: there might be 64K domains,
1251 * consider other allocation for future chip
1253 iommu
->domain_ids
= kcalloc(nlongs
, sizeof(unsigned long), GFP_KERNEL
);
1254 if (!iommu
->domain_ids
) {
1255 printk(KERN_ERR
"Allocating domain id array failed\n");
1258 iommu
->domains
= kcalloc(ndomains
, sizeof(struct dmar_domain
*),
1260 if (!iommu
->domains
) {
1261 printk(KERN_ERR
"Allocating domain array failed\n");
1266 * if Caching mode is set, then invalid translations are tagged
1267 * with domainid 0. Hence we need to pre-allocate it.
1269 if (cap_caching_mode(iommu
->cap
))
1270 set_bit(0, iommu
->domain_ids
);
1275 static void domain_exit(struct dmar_domain
*domain
);
1276 static void vm_domain_exit(struct dmar_domain
*domain
);
1278 void free_dmar_iommu(struct intel_iommu
*iommu
)
1280 struct dmar_domain
*domain
;
1282 unsigned long flags
;
1284 if ((iommu
->domains
) && (iommu
->domain_ids
)) {
1285 for_each_set_bit(i
, iommu
->domain_ids
, cap_ndoms(iommu
->cap
)) {
1286 domain
= iommu
->domains
[i
];
1287 clear_bit(i
, iommu
->domain_ids
);
1289 spin_lock_irqsave(&domain
->iommu_lock
, flags
);
1290 if (--domain
->iommu_count
== 0) {
1291 if (domain
->flags
& DOMAIN_FLAG_VIRTUAL_MACHINE
)
1292 vm_domain_exit(domain
);
1294 domain_exit(domain
);
1296 spin_unlock_irqrestore(&domain
->iommu_lock
, flags
);
1300 if (iommu
->gcmd
& DMA_GCMD_TE
)
1301 iommu_disable_translation(iommu
);
1304 irq_set_handler_data(iommu
->irq
, NULL
);
1305 /* This will mask the irq */
1306 free_irq(iommu
->irq
, iommu
);
1307 destroy_irq(iommu
->irq
);
1310 kfree(iommu
->domains
);
1311 kfree(iommu
->domain_ids
);
1313 g_iommus
[iommu
->seq_id
] = NULL
;
1315 /* if all iommus are freed, free g_iommus */
1316 for (i
= 0; i
< g_num_of_iommus
; i
++) {
1321 if (i
== g_num_of_iommus
)
1324 /* free context mapping */
1325 free_context_table(iommu
);
1328 static struct dmar_domain
*alloc_domain(void)
1330 struct dmar_domain
*domain
;
1332 domain
= alloc_domain_mem();
1337 memset(&domain
->iommu_bmp
, 0, sizeof(unsigned long));
1343 static int iommu_attach_domain(struct dmar_domain
*domain
,
1344 struct intel_iommu
*iommu
)
1347 unsigned long ndomains
;
1348 unsigned long flags
;
1350 ndomains
= cap_ndoms(iommu
->cap
);
1352 spin_lock_irqsave(&iommu
->lock
, flags
);
1354 num
= find_first_zero_bit(iommu
->domain_ids
, ndomains
);
1355 if (num
>= ndomains
) {
1356 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1357 printk(KERN_ERR
"IOMMU: no free domain ids\n");
1362 set_bit(num
, iommu
->domain_ids
);
1363 set_bit(iommu
->seq_id
, &domain
->iommu_bmp
);
1364 iommu
->domains
[num
] = domain
;
1365 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1370 static void iommu_detach_domain(struct dmar_domain
*domain
,
1371 struct intel_iommu
*iommu
)
1373 unsigned long flags
;
1377 spin_lock_irqsave(&iommu
->lock
, flags
);
1378 ndomains
= cap_ndoms(iommu
->cap
);
1379 for_each_set_bit(num
, iommu
->domain_ids
, ndomains
) {
1380 if (iommu
->domains
[num
] == domain
) {
1387 clear_bit(num
, iommu
->domain_ids
);
1388 clear_bit(iommu
->seq_id
, &domain
->iommu_bmp
);
1389 iommu
->domains
[num
] = NULL
;
1391 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1394 static struct iova_domain reserved_iova_list
;
1395 static struct lock_class_key reserved_rbtree_key
;
1397 static int dmar_init_reserved_ranges(void)
1399 struct pci_dev
*pdev
= NULL
;
1403 init_iova_domain(&reserved_iova_list
, DMA_32BIT_PFN
);
1405 lockdep_set_class(&reserved_iova_list
.iova_rbtree_lock
,
1406 &reserved_rbtree_key
);
1408 /* IOAPIC ranges shouldn't be accessed by DMA */
1409 iova
= reserve_iova(&reserved_iova_list
, IOVA_PFN(IOAPIC_RANGE_START
),
1410 IOVA_PFN(IOAPIC_RANGE_END
));
1412 printk(KERN_ERR
"Reserve IOAPIC range failed\n");
1416 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1417 for_each_pci_dev(pdev
) {
1420 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1421 r
= &pdev
->resource
[i
];
1422 if (!r
->flags
|| !(r
->flags
& IORESOURCE_MEM
))
1424 iova
= reserve_iova(&reserved_iova_list
,
1428 printk(KERN_ERR
"Reserve iova failed\n");
1436 static void domain_reserve_special_ranges(struct dmar_domain
*domain
)
1438 copy_reserved_iova(&reserved_iova_list
, &domain
->iovad
);
1441 static inline int guestwidth_to_adjustwidth(int gaw
)
1444 int r
= (gaw
- 12) % 9;
1455 static int domain_init(struct dmar_domain
*domain
, int guest_width
)
1457 struct intel_iommu
*iommu
;
1458 int adjust_width
, agaw
;
1459 unsigned long sagaw
;
1461 init_iova_domain(&domain
->iovad
, DMA_32BIT_PFN
);
1462 spin_lock_init(&domain
->iommu_lock
);
1464 domain_reserve_special_ranges(domain
);
1466 /* calculate AGAW */
1467 iommu
= domain_get_iommu(domain
);
1468 if (guest_width
> cap_mgaw(iommu
->cap
))
1469 guest_width
= cap_mgaw(iommu
->cap
);
1470 domain
->gaw
= guest_width
;
1471 adjust_width
= guestwidth_to_adjustwidth(guest_width
);
1472 agaw
= width_to_agaw(adjust_width
);
1473 sagaw
= cap_sagaw(iommu
->cap
);
1474 if (!test_bit(agaw
, &sagaw
)) {
1475 /* hardware doesn't support it, choose a bigger one */
1476 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw
);
1477 agaw
= find_next_bit(&sagaw
, 5, agaw
);
1481 domain
->agaw
= agaw
;
1482 INIT_LIST_HEAD(&domain
->devices
);
1484 if (ecap_coherent(iommu
->ecap
))
1485 domain
->iommu_coherency
= 1;
1487 domain
->iommu_coherency
= 0;
1489 if (ecap_sc_support(iommu
->ecap
))
1490 domain
->iommu_snooping
= 1;
1492 domain
->iommu_snooping
= 0;
1494 domain
->iommu_superpage
= fls(cap_super_page_val(iommu
->cap
));
1495 domain
->iommu_count
= 1;
1496 domain
->nid
= iommu
->node
;
1498 /* always allocate the top pgd */
1499 domain
->pgd
= (struct dma_pte
*)alloc_pgtable_page(domain
->nid
);
1502 __iommu_flush_cache(iommu
, domain
->pgd
, PAGE_SIZE
);
1506 static void domain_exit(struct dmar_domain
*domain
)
1508 struct dmar_drhd_unit
*drhd
;
1509 struct intel_iommu
*iommu
;
1511 /* Domain 0 is reserved, so dont process it */
1515 /* Flush any lazy unmaps that may reference this domain */
1516 if (!intel_iommu_strict
)
1517 flush_unmaps_timeout(0);
1519 domain_remove_dev_info(domain
);
1521 put_iova_domain(&domain
->iovad
);
1524 dma_pte_clear_range(domain
, 0, DOMAIN_MAX_PFN(domain
->gaw
));
1526 /* free page tables */
1527 dma_pte_free_pagetable(domain
, 0, DOMAIN_MAX_PFN(domain
->gaw
));
1529 for_each_active_iommu(iommu
, drhd
)
1530 if (test_bit(iommu
->seq_id
, &domain
->iommu_bmp
))
1531 iommu_detach_domain(domain
, iommu
);
1533 free_domain_mem(domain
);
1536 static int domain_context_mapping_one(struct dmar_domain
*domain
, int segment
,
1537 u8 bus
, u8 devfn
, int translation
)
1539 struct context_entry
*context
;
1540 unsigned long flags
;
1541 struct intel_iommu
*iommu
;
1542 struct dma_pte
*pgd
;
1544 unsigned long ndomains
;
1547 struct device_domain_info
*info
= NULL
;
1549 pr_debug("Set context mapping for %02x:%02x.%d\n",
1550 bus
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
1552 BUG_ON(!domain
->pgd
);
1553 BUG_ON(translation
!= CONTEXT_TT_PASS_THROUGH
&&
1554 translation
!= CONTEXT_TT_MULTI_LEVEL
);
1556 iommu
= device_to_iommu(segment
, bus
, devfn
);
1560 context
= device_to_context_entry(iommu
, bus
, devfn
);
1563 spin_lock_irqsave(&iommu
->lock
, flags
);
1564 if (context_present(context
)) {
1565 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1572 if (domain
->flags
& DOMAIN_FLAG_VIRTUAL_MACHINE
||
1573 domain
->flags
& DOMAIN_FLAG_STATIC_IDENTITY
) {
1576 /* find an available domain id for this device in iommu */
1577 ndomains
= cap_ndoms(iommu
->cap
);
1578 for_each_set_bit(num
, iommu
->domain_ids
, ndomains
) {
1579 if (iommu
->domains
[num
] == domain
) {
1587 num
= find_first_zero_bit(iommu
->domain_ids
, ndomains
);
1588 if (num
>= ndomains
) {
1589 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1590 printk(KERN_ERR
"IOMMU: no free domain ids\n");
1594 set_bit(num
, iommu
->domain_ids
);
1595 iommu
->domains
[num
] = domain
;
1599 /* Skip top levels of page tables for
1600 * iommu which has less agaw than default.
1601 * Unnecessary for PT mode.
1603 if (translation
!= CONTEXT_TT_PASS_THROUGH
) {
1604 for (agaw
= domain
->agaw
; agaw
!= iommu
->agaw
; agaw
--) {
1605 pgd
= phys_to_virt(dma_pte_addr(pgd
));
1606 if (!dma_pte_present(pgd
)) {
1607 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1614 context_set_domain_id(context
, id
);
1616 if (translation
!= CONTEXT_TT_PASS_THROUGH
) {
1617 info
= iommu_support_dev_iotlb(domain
, segment
, bus
, devfn
);
1618 translation
= info
? CONTEXT_TT_DEV_IOTLB
:
1619 CONTEXT_TT_MULTI_LEVEL
;
1622 * In pass through mode, AW must be programmed to indicate the largest
1623 * AGAW value supported by hardware. And ASR is ignored by hardware.
1625 if (unlikely(translation
== CONTEXT_TT_PASS_THROUGH
))
1626 context_set_address_width(context
, iommu
->msagaw
);
1628 context_set_address_root(context
, virt_to_phys(pgd
));
1629 context_set_address_width(context
, iommu
->agaw
);
1632 context_set_translation_type(context
, translation
);
1633 context_set_fault_enable(context
);
1634 context_set_present(context
);
1635 domain_flush_cache(domain
, context
, sizeof(*context
));
1638 * It's a non-present to present mapping. If hardware doesn't cache
1639 * non-present entry we only need to flush the write-buffer. If the
1640 * _does_ cache non-present entries, then it does so in the special
1641 * domain #0, which we have to flush:
1643 if (cap_caching_mode(iommu
->cap
)) {
1644 iommu
->flush
.flush_context(iommu
, 0,
1645 (((u16
)bus
) << 8) | devfn
,
1646 DMA_CCMD_MASK_NOBIT
,
1647 DMA_CCMD_DEVICE_INVL
);
1648 iommu
->flush
.flush_iotlb(iommu
, domain
->id
, 0, 0, DMA_TLB_DSI_FLUSH
);
1650 iommu_flush_write_buffer(iommu
);
1652 iommu_enable_dev_iotlb(info
);
1653 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1655 spin_lock_irqsave(&domain
->iommu_lock
, flags
);
1656 if (!test_and_set_bit(iommu
->seq_id
, &domain
->iommu_bmp
)) {
1657 domain
->iommu_count
++;
1658 if (domain
->iommu_count
== 1)
1659 domain
->nid
= iommu
->node
;
1660 domain_update_iommu_cap(domain
);
1662 spin_unlock_irqrestore(&domain
->iommu_lock
, flags
);
1667 domain_context_mapping(struct dmar_domain
*domain
, struct pci_dev
*pdev
,
1671 struct pci_dev
*tmp
, *parent
;
1673 ret
= domain_context_mapping_one(domain
, pci_domain_nr(pdev
->bus
),
1674 pdev
->bus
->number
, pdev
->devfn
,
1679 /* dependent device mapping */
1680 tmp
= pci_find_upstream_pcie_bridge(pdev
);
1683 /* Secondary interface's bus number and devfn 0 */
1684 parent
= pdev
->bus
->self
;
1685 while (parent
!= tmp
) {
1686 ret
= domain_context_mapping_one(domain
,
1687 pci_domain_nr(parent
->bus
),
1688 parent
->bus
->number
,
1689 parent
->devfn
, translation
);
1692 parent
= parent
->bus
->self
;
1694 if (pci_is_pcie(tmp
)) /* this is a PCIe-to-PCI bridge */
1695 return domain_context_mapping_one(domain
,
1696 pci_domain_nr(tmp
->subordinate
),
1697 tmp
->subordinate
->number
, 0,
1699 else /* this is a legacy PCI bridge */
1700 return domain_context_mapping_one(domain
,
1701 pci_domain_nr(tmp
->bus
),
1707 static int domain_context_mapped(struct pci_dev
*pdev
)
1710 struct pci_dev
*tmp
, *parent
;
1711 struct intel_iommu
*iommu
;
1713 iommu
= device_to_iommu(pci_domain_nr(pdev
->bus
), pdev
->bus
->number
,
1718 ret
= device_context_mapped(iommu
, pdev
->bus
->number
, pdev
->devfn
);
1721 /* dependent device mapping */
1722 tmp
= pci_find_upstream_pcie_bridge(pdev
);
1725 /* Secondary interface's bus number and devfn 0 */
1726 parent
= pdev
->bus
->self
;
1727 while (parent
!= tmp
) {
1728 ret
= device_context_mapped(iommu
, parent
->bus
->number
,
1732 parent
= parent
->bus
->self
;
1734 if (pci_is_pcie(tmp
))
1735 return device_context_mapped(iommu
, tmp
->subordinate
->number
,
1738 return device_context_mapped(iommu
, tmp
->bus
->number
,
1742 /* Returns a number of VTD pages, but aligned to MM page size */
1743 static inline unsigned long aligned_nrpages(unsigned long host_addr
,
1746 host_addr
&= ~PAGE_MASK
;
1747 return PAGE_ALIGN(host_addr
+ size
) >> VTD_PAGE_SHIFT
;
1750 /* Return largest possible superpage level for a given mapping */
1751 static inline int hardware_largepage_caps(struct dmar_domain
*domain
,
1752 unsigned long iov_pfn
,
1753 unsigned long phy_pfn
,
1754 unsigned long pages
)
1756 int support
, level
= 1;
1757 unsigned long pfnmerge
;
1759 support
= domain
->iommu_superpage
;
1761 /* To use a large page, the virtual *and* physical addresses
1762 must be aligned to 2MiB/1GiB/etc. Lower bits set in either
1763 of them will mean we have to use smaller pages. So just
1764 merge them and check both at once. */
1765 pfnmerge
= iov_pfn
| phy_pfn
;
1767 while (support
&& !(pfnmerge
& ~VTD_STRIDE_MASK
)) {
1768 pages
>>= VTD_STRIDE_SHIFT
;
1771 pfnmerge
>>= VTD_STRIDE_SHIFT
;
1778 static int __domain_mapping(struct dmar_domain
*domain
, unsigned long iov_pfn
,
1779 struct scatterlist
*sg
, unsigned long phys_pfn
,
1780 unsigned long nr_pages
, int prot
)
1782 struct dma_pte
*first_pte
= NULL
, *pte
= NULL
;
1783 phys_addr_t
uninitialized_var(pteval
);
1784 int addr_width
= agaw_to_width(domain
->agaw
) - VTD_PAGE_SHIFT
;
1785 unsigned long sg_res
;
1786 unsigned int largepage_lvl
= 0;
1787 unsigned long lvl_pages
= 0;
1789 BUG_ON(addr_width
< BITS_PER_LONG
&& (iov_pfn
+ nr_pages
- 1) >> addr_width
);
1791 if ((prot
& (DMA_PTE_READ
|DMA_PTE_WRITE
)) == 0)
1794 prot
&= DMA_PTE_READ
| DMA_PTE_WRITE
| DMA_PTE_SNP
;
1799 sg_res
= nr_pages
+ 1;
1800 pteval
= ((phys_addr_t
)phys_pfn
<< VTD_PAGE_SHIFT
) | prot
;
1803 while (nr_pages
> 0) {
1807 sg_res
= aligned_nrpages(sg
->offset
, sg
->length
);
1808 sg
->dma_address
= ((dma_addr_t
)iov_pfn
<< VTD_PAGE_SHIFT
) + sg
->offset
;
1809 sg
->dma_length
= sg
->length
;
1810 pteval
= page_to_phys(sg_page(sg
)) | prot
;
1811 phys_pfn
= pteval
>> VTD_PAGE_SHIFT
;
1815 largepage_lvl
= hardware_largepage_caps(domain
, iov_pfn
, phys_pfn
, sg_res
);
1817 first_pte
= pte
= pfn_to_dma_pte(domain
, iov_pfn
, largepage_lvl
);
1820 /* It is large page*/
1821 if (largepage_lvl
> 1)
1822 pteval
|= DMA_PTE_LARGE_PAGE
;
1824 pteval
&= ~(uint64_t)DMA_PTE_LARGE_PAGE
;
1827 /* We don't need lock here, nobody else
1828 * touches the iova range
1830 tmp
= cmpxchg64_local(&pte
->val
, 0ULL, pteval
);
1832 static int dumps
= 5;
1833 printk(KERN_CRIT
"ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1834 iov_pfn
, tmp
, (unsigned long long)pteval
);
1837 debug_dma_dump_mappings(NULL
);
1842 lvl_pages
= lvl_to_nr_pages(largepage_lvl
);
1844 BUG_ON(nr_pages
< lvl_pages
);
1845 BUG_ON(sg_res
< lvl_pages
);
1847 nr_pages
-= lvl_pages
;
1848 iov_pfn
+= lvl_pages
;
1849 phys_pfn
+= lvl_pages
;
1850 pteval
+= lvl_pages
* VTD_PAGE_SIZE
;
1851 sg_res
-= lvl_pages
;
1853 /* If the next PTE would be the first in a new page, then we
1854 need to flush the cache on the entries we've just written.
1855 And then we'll need to recalculate 'pte', so clear it and
1856 let it get set again in the if (!pte) block above.
1858 If we're done (!nr_pages) we need to flush the cache too.
1860 Also if we've been setting superpages, we may need to
1861 recalculate 'pte' and switch back to smaller pages for the
1862 end of the mapping, if the trailing size is not enough to
1863 use another superpage (i.e. sg_res < lvl_pages). */
1865 if (!nr_pages
|| first_pte_in_page(pte
) ||
1866 (largepage_lvl
> 1 && sg_res
< lvl_pages
)) {
1867 domain_flush_cache(domain
, first_pte
,
1868 (void *)pte
- (void *)first_pte
);
1872 if (!sg_res
&& nr_pages
)
1878 static inline int domain_sg_mapping(struct dmar_domain
*domain
, unsigned long iov_pfn
,
1879 struct scatterlist
*sg
, unsigned long nr_pages
,
1882 return __domain_mapping(domain
, iov_pfn
, sg
, 0, nr_pages
, prot
);
1885 static inline int domain_pfn_mapping(struct dmar_domain
*domain
, unsigned long iov_pfn
,
1886 unsigned long phys_pfn
, unsigned long nr_pages
,
1889 return __domain_mapping(domain
, iov_pfn
, NULL
, phys_pfn
, nr_pages
, prot
);
1892 static void iommu_detach_dev(struct intel_iommu
*iommu
, u8 bus
, u8 devfn
)
1897 clear_context_table(iommu
, bus
, devfn
);
1898 iommu
->flush
.flush_context(iommu
, 0, 0, 0,
1899 DMA_CCMD_GLOBAL_INVL
);
1900 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH
);
1903 static void domain_remove_dev_info(struct dmar_domain
*domain
)
1905 struct device_domain_info
*info
;
1906 unsigned long flags
;
1907 struct intel_iommu
*iommu
;
1909 spin_lock_irqsave(&device_domain_lock
, flags
);
1910 while (!list_empty(&domain
->devices
)) {
1911 info
= list_entry(domain
->devices
.next
,
1912 struct device_domain_info
, link
);
1913 list_del(&info
->link
);
1914 list_del(&info
->global
);
1916 info
->dev
->dev
.archdata
.iommu
= NULL
;
1917 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1919 iommu_disable_dev_iotlb(info
);
1920 iommu
= device_to_iommu(info
->segment
, info
->bus
, info
->devfn
);
1921 iommu_detach_dev(iommu
, info
->bus
, info
->devfn
);
1922 free_devinfo_mem(info
);
1924 spin_lock_irqsave(&device_domain_lock
, flags
);
1926 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1931 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1933 static struct dmar_domain
*
1934 find_domain(struct pci_dev
*pdev
)
1936 struct device_domain_info
*info
;
1938 /* No lock here, assumes no domain exit in normal case */
1939 info
= pdev
->dev
.archdata
.iommu
;
1941 return info
->domain
;
1945 /* domain is initialized */
1946 static struct dmar_domain
*get_domain_for_dev(struct pci_dev
*pdev
, int gaw
)
1948 struct dmar_domain
*domain
, *found
= NULL
;
1949 struct intel_iommu
*iommu
;
1950 struct dmar_drhd_unit
*drhd
;
1951 struct device_domain_info
*info
, *tmp
;
1952 struct pci_dev
*dev_tmp
;
1953 unsigned long flags
;
1954 int bus
= 0, devfn
= 0;
1958 domain
= find_domain(pdev
);
1962 segment
= pci_domain_nr(pdev
->bus
);
1964 dev_tmp
= pci_find_upstream_pcie_bridge(pdev
);
1966 if (pci_is_pcie(dev_tmp
)) {
1967 bus
= dev_tmp
->subordinate
->number
;
1970 bus
= dev_tmp
->bus
->number
;
1971 devfn
= dev_tmp
->devfn
;
1973 spin_lock_irqsave(&device_domain_lock
, flags
);
1974 list_for_each_entry(info
, &device_domain_list
, global
) {
1975 if (info
->segment
== segment
&&
1976 info
->bus
== bus
&& info
->devfn
== devfn
) {
1977 found
= info
->domain
;
1981 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1982 /* pcie-pci bridge already has a domain, uses it */
1989 domain
= alloc_domain();
1993 /* Allocate new domain for the device */
1994 drhd
= dmar_find_matched_drhd_unit(pdev
);
1996 printk(KERN_ERR
"IOMMU: can't find DMAR for device %s\n",
2000 iommu
= drhd
->iommu
;
2002 ret
= iommu_attach_domain(domain
, iommu
);
2004 free_domain_mem(domain
);
2008 if (domain_init(domain
, gaw
)) {
2009 domain_exit(domain
);
2013 /* register pcie-to-pci device */
2015 info
= alloc_devinfo_mem();
2017 domain_exit(domain
);
2020 info
->segment
= segment
;
2022 info
->devfn
= devfn
;
2024 info
->domain
= domain
;
2025 /* This domain is shared by devices under p2p bridge */
2026 domain
->flags
|= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES
;
2028 /* pcie-to-pci bridge already has a domain, uses it */
2030 spin_lock_irqsave(&device_domain_lock
, flags
);
2031 list_for_each_entry(tmp
, &device_domain_list
, global
) {
2032 if (tmp
->segment
== segment
&&
2033 tmp
->bus
== bus
&& tmp
->devfn
== devfn
) {
2034 found
= tmp
->domain
;
2039 spin_unlock_irqrestore(&device_domain_lock
, flags
);
2040 free_devinfo_mem(info
);
2041 domain_exit(domain
);
2044 list_add(&info
->link
, &domain
->devices
);
2045 list_add(&info
->global
, &device_domain_list
);
2046 spin_unlock_irqrestore(&device_domain_lock
, flags
);
2051 info
= alloc_devinfo_mem();
2054 info
->segment
= segment
;
2055 info
->bus
= pdev
->bus
->number
;
2056 info
->devfn
= pdev
->devfn
;
2058 info
->domain
= domain
;
2059 spin_lock_irqsave(&device_domain_lock
, flags
);
2060 /* somebody is fast */
2061 found
= find_domain(pdev
);
2062 if (found
!= NULL
) {
2063 spin_unlock_irqrestore(&device_domain_lock
, flags
);
2064 if (found
!= domain
) {
2065 domain_exit(domain
);
2068 free_devinfo_mem(info
);
2071 list_add(&info
->link
, &domain
->devices
);
2072 list_add(&info
->global
, &device_domain_list
);
2073 pdev
->dev
.archdata
.iommu
= info
;
2074 spin_unlock_irqrestore(&device_domain_lock
, flags
);
2077 /* recheck it here, maybe others set it */
2078 return find_domain(pdev
);
2081 static int iommu_identity_mapping
;
2082 #define IDENTMAP_ALL 1
2083 #define IDENTMAP_GFX 2
2084 #define IDENTMAP_AZALIA 4
2086 static int iommu_domain_identity_map(struct dmar_domain
*domain
,
2087 unsigned long long start
,
2088 unsigned long long end
)
2090 unsigned long first_vpfn
= start
>> VTD_PAGE_SHIFT
;
2091 unsigned long last_vpfn
= end
>> VTD_PAGE_SHIFT
;
2093 if (!reserve_iova(&domain
->iovad
, dma_to_mm_pfn(first_vpfn
),
2094 dma_to_mm_pfn(last_vpfn
))) {
2095 printk(KERN_ERR
"IOMMU: reserve iova failed\n");
2099 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
2100 start
, end
, domain
->id
);
2102 * RMRR range might have overlap with physical memory range,
2105 dma_pte_clear_range(domain
, first_vpfn
, last_vpfn
);
2107 return domain_pfn_mapping(domain
, first_vpfn
, first_vpfn
,
2108 last_vpfn
- first_vpfn
+ 1,
2109 DMA_PTE_READ
|DMA_PTE_WRITE
);
2112 static int iommu_prepare_identity_map(struct pci_dev
*pdev
,
2113 unsigned long long start
,
2114 unsigned long long end
)
2116 struct dmar_domain
*domain
;
2119 domain
= get_domain_for_dev(pdev
, DEFAULT_DOMAIN_ADDRESS_WIDTH
);
2123 /* For _hardware_ passthrough, don't bother. But for software
2124 passthrough, we do it anyway -- it may indicate a memory
2125 range which is reserved in E820, so which didn't get set
2126 up to start with in si_domain */
2127 if (domain
== si_domain
&& hw_pass_through
) {
2128 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
2129 pci_name(pdev
), start
, end
);
2134 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
2135 pci_name(pdev
), start
, end
);
2138 WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
2139 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2140 dmi_get_system_info(DMI_BIOS_VENDOR
),
2141 dmi_get_system_info(DMI_BIOS_VERSION
),
2142 dmi_get_system_info(DMI_PRODUCT_VERSION
));
2147 if (end
>> agaw_to_width(domain
->agaw
)) {
2148 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
2149 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2150 agaw_to_width(domain
->agaw
),
2151 dmi_get_system_info(DMI_BIOS_VENDOR
),
2152 dmi_get_system_info(DMI_BIOS_VERSION
),
2153 dmi_get_system_info(DMI_PRODUCT_VERSION
));
2158 ret
= iommu_domain_identity_map(domain
, start
, end
);
2162 /* context entry init */
2163 ret
= domain_context_mapping(domain
, pdev
, CONTEXT_TT_MULTI_LEVEL
);
2170 domain_exit(domain
);
2174 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit
*rmrr
,
2175 struct pci_dev
*pdev
)
2177 if (pdev
->dev
.archdata
.iommu
== DUMMY_DEVICE_DOMAIN_INFO
)
2179 return iommu_prepare_identity_map(pdev
, rmrr
->base_address
,
2183 #ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
2184 static inline void iommu_prepare_isa(void)
2186 struct pci_dev
*pdev
;
2189 pdev
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
2193 printk(KERN_INFO
"IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
2194 ret
= iommu_prepare_identity_map(pdev
, 0, 16*1024*1024 - 1);
2197 printk(KERN_ERR
"IOMMU: Failed to create 0-16MiB identity map; "
2198 "floppy might not work\n");
2202 static inline void iommu_prepare_isa(void)
2206 #endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
2208 static int md_domain_init(struct dmar_domain
*domain
, int guest_width
);
2210 static int __init
si_domain_init(int hw
)
2212 struct dmar_drhd_unit
*drhd
;
2213 struct intel_iommu
*iommu
;
2216 si_domain
= alloc_domain();
2220 pr_debug("Identity mapping domain is domain %d\n", si_domain
->id
);
2222 for_each_active_iommu(iommu
, drhd
) {
2223 ret
= iommu_attach_domain(si_domain
, iommu
);
2225 domain_exit(si_domain
);
2230 if (md_domain_init(si_domain
, DEFAULT_DOMAIN_ADDRESS_WIDTH
)) {
2231 domain_exit(si_domain
);
2235 si_domain
->flags
= DOMAIN_FLAG_STATIC_IDENTITY
;
2240 for_each_online_node(nid
) {
2241 unsigned long start_pfn
, end_pfn
;
2244 for_each_mem_pfn_range(i
, nid
, &start_pfn
, &end_pfn
, NULL
) {
2245 ret
= iommu_domain_identity_map(si_domain
,
2246 PFN_PHYS(start_pfn
), PFN_PHYS(end_pfn
));
2255 static void domain_remove_one_dev_info(struct dmar_domain
*domain
,
2256 struct pci_dev
*pdev
);
2257 static int identity_mapping(struct pci_dev
*pdev
)
2259 struct device_domain_info
*info
;
2261 if (likely(!iommu_identity_mapping
))
2264 info
= pdev
->dev
.archdata
.iommu
;
2265 if (info
&& info
!= DUMMY_DEVICE_DOMAIN_INFO
)
2266 return (info
->domain
== si_domain
);
2271 static int domain_add_dev_info(struct dmar_domain
*domain
,
2272 struct pci_dev
*pdev
,
2275 struct device_domain_info
*info
;
2276 unsigned long flags
;
2279 info
= alloc_devinfo_mem();
2283 ret
= domain_context_mapping(domain
, pdev
, translation
);
2285 free_devinfo_mem(info
);
2289 info
->segment
= pci_domain_nr(pdev
->bus
);
2290 info
->bus
= pdev
->bus
->number
;
2291 info
->devfn
= pdev
->devfn
;
2293 info
->domain
= domain
;
2295 spin_lock_irqsave(&device_domain_lock
, flags
);
2296 list_add(&info
->link
, &domain
->devices
);
2297 list_add(&info
->global
, &device_domain_list
);
2298 pdev
->dev
.archdata
.iommu
= info
;
2299 spin_unlock_irqrestore(&device_domain_lock
, flags
);
2304 static int iommu_should_identity_map(struct pci_dev
*pdev
, int startup
)
2306 if ((iommu_identity_mapping
& IDENTMAP_AZALIA
) && IS_AZALIA(pdev
))
2309 if ((iommu_identity_mapping
& IDENTMAP_GFX
) && IS_GFX_DEVICE(pdev
))
2312 if (!(iommu_identity_mapping
& IDENTMAP_ALL
))
2316 * We want to start off with all devices in the 1:1 domain, and
2317 * take them out later if we find they can't access all of memory.
2319 * However, we can't do this for PCI devices behind bridges,
2320 * because all PCI devices behind the same bridge will end up
2321 * with the same source-id on their transactions.
2323 * Practically speaking, we can't change things around for these
2324 * devices at run-time, because we can't be sure there'll be no
2325 * DMA transactions in flight for any of their siblings.
2327 * So PCI devices (unless they're on the root bus) as well as
2328 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2329 * the 1:1 domain, just in _case_ one of their siblings turns out
2330 * not to be able to map all of memory.
2332 if (!pci_is_pcie(pdev
)) {
2333 if (!pci_is_root_bus(pdev
->bus
))
2335 if (pdev
->class >> 8 == PCI_CLASS_BRIDGE_PCI
)
2337 } else if (pdev
->pcie_type
== PCI_EXP_TYPE_PCI_BRIDGE
)
2341 * At boot time, we don't yet know if devices will be 64-bit capable.
2342 * Assume that they will -- if they turn out not to be, then we can
2343 * take them out of the 1:1 domain later.
2347 * If the device's dma_mask is less than the system's memory
2348 * size then this is not a candidate for identity mapping.
2350 u64 dma_mask
= pdev
->dma_mask
;
2352 if (pdev
->dev
.coherent_dma_mask
&&
2353 pdev
->dev
.coherent_dma_mask
< dma_mask
)
2354 dma_mask
= pdev
->dev
.coherent_dma_mask
;
2356 return dma_mask
>= dma_get_required_mask(&pdev
->dev
);
2362 static int __init
iommu_prepare_static_identity_mapping(int hw
)
2364 struct pci_dev
*pdev
= NULL
;
2367 ret
= si_domain_init(hw
);
2371 for_each_pci_dev(pdev
) {
2372 /* Skip Host/PCI Bridge devices */
2373 if (IS_BRIDGE_HOST_DEVICE(pdev
))
2375 if (iommu_should_identity_map(pdev
, 1)) {
2376 printk(KERN_INFO
"IOMMU: %s identity mapping for device %s\n",
2377 hw
? "hardware" : "software", pci_name(pdev
));
2379 ret
= domain_add_dev_info(si_domain
, pdev
,
2380 hw
? CONTEXT_TT_PASS_THROUGH
:
2381 CONTEXT_TT_MULTI_LEVEL
);
2390 static int __init
init_dmars(void)
2392 struct dmar_drhd_unit
*drhd
;
2393 struct dmar_rmrr_unit
*rmrr
;
2394 struct pci_dev
*pdev
;
2395 struct intel_iommu
*iommu
;
2401 * initialize and program root entry to not present
2404 for_each_drhd_unit(drhd
) {
2407 * lock not needed as this is only incremented in the single
2408 * threaded kernel __init code path all other access are read
2413 g_iommus
= kcalloc(g_num_of_iommus
, sizeof(struct intel_iommu
*),
2416 printk(KERN_ERR
"Allocating global iommu array failed\n");
2421 deferred_flush
= kzalloc(g_num_of_iommus
*
2422 sizeof(struct deferred_flush_tables
), GFP_KERNEL
);
2423 if (!deferred_flush
) {
2428 for_each_drhd_unit(drhd
) {
2432 iommu
= drhd
->iommu
;
2433 g_iommus
[iommu
->seq_id
] = iommu
;
2435 ret
= iommu_init_domains(iommu
);
2441 * we could share the same root & context tables
2442 * among all IOMMU's. Need to Split it later.
2444 ret
= iommu_alloc_root_entry(iommu
);
2446 printk(KERN_ERR
"IOMMU: allocate root entry failed\n");
2449 if (!ecap_pass_through(iommu
->ecap
))
2450 hw_pass_through
= 0;
2454 * Start from the sane iommu hardware state.
2456 for_each_drhd_unit(drhd
) {
2460 iommu
= drhd
->iommu
;
2463 * If the queued invalidation is already initialized by us
2464 * (for example, while enabling interrupt-remapping) then
2465 * we got the things already rolling from a sane state.
2471 * Clear any previous faults.
2473 dmar_fault(-1, iommu
);
2475 * Disable queued invalidation if supported and already enabled
2476 * before OS handover.
2478 dmar_disable_qi(iommu
);
2481 for_each_drhd_unit(drhd
) {
2485 iommu
= drhd
->iommu
;
2487 if (dmar_enable_qi(iommu
)) {
2489 * Queued Invalidate not enabled, use Register Based
2492 iommu
->flush
.flush_context
= __iommu_flush_context
;
2493 iommu
->flush
.flush_iotlb
= __iommu_flush_iotlb
;
2494 printk(KERN_INFO
"IOMMU %d 0x%Lx: using Register based "
2497 (unsigned long long)drhd
->reg_base_addr
);
2499 iommu
->flush
.flush_context
= qi_flush_context
;
2500 iommu
->flush
.flush_iotlb
= qi_flush_iotlb
;
2501 printk(KERN_INFO
"IOMMU %d 0x%Lx: using Queued "
2504 (unsigned long long)drhd
->reg_base_addr
);
2508 if (iommu_pass_through
)
2509 iommu_identity_mapping
|= IDENTMAP_ALL
;
2511 #ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
2512 iommu_identity_mapping
|= IDENTMAP_GFX
;
2515 check_tylersburg_isoch();
2518 * If pass through is not set or not enabled, setup context entries for
2519 * identity mappings for rmrr, gfx, and isa and may fall back to static
2520 * identity mapping if iommu_identity_mapping is set.
2522 if (iommu_identity_mapping
) {
2523 ret
= iommu_prepare_static_identity_mapping(hw_pass_through
);
2525 printk(KERN_CRIT
"Failed to setup IOMMU pass-through\n");
2531 * for each dev attached to rmrr
2533 * locate drhd for dev, alloc domain for dev
2534 * allocate free domain
2535 * allocate page table entries for rmrr
2536 * if context not allocated for bus
2537 * allocate and init context
2538 * set present in root table for this bus
2539 * init context with domain, translation etc
2543 printk(KERN_INFO
"IOMMU: Setting RMRR:\n");
2544 for_each_rmrr_units(rmrr
) {
2545 for (i
= 0; i
< rmrr
->devices_cnt
; i
++) {
2546 pdev
= rmrr
->devices
[i
];
2548 * some BIOS lists non-exist devices in DMAR
2553 ret
= iommu_prepare_rmrr_dev(rmrr
, pdev
);
2556 "IOMMU: mapping reserved region failed\n");
2560 iommu_prepare_isa();
2565 * global invalidate context cache
2566 * global invalidate iotlb
2567 * enable translation
2569 for_each_drhd_unit(drhd
) {
2570 if (drhd
->ignored
) {
2572 * we always have to disable PMRs or DMA may fail on
2576 iommu_disable_protect_mem_regions(drhd
->iommu
);
2579 iommu
= drhd
->iommu
;
2581 iommu_flush_write_buffer(iommu
);
2583 ret
= dmar_set_interrupt(iommu
);
2587 iommu_set_root_entry(iommu
);
2589 iommu
->flush
.flush_context(iommu
, 0, 0, 0, DMA_CCMD_GLOBAL_INVL
);
2590 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH
);
2592 ret
= iommu_enable_translation(iommu
);
2596 iommu_disable_protect_mem_regions(iommu
);
2601 for_each_drhd_unit(drhd
) {
2604 iommu
= drhd
->iommu
;
2611 /* This takes a number of _MM_ pages, not VTD pages */
2612 static struct iova
*intel_alloc_iova(struct device
*dev
,
2613 struct dmar_domain
*domain
,
2614 unsigned long nrpages
, uint64_t dma_mask
)
2616 struct pci_dev
*pdev
= to_pci_dev(dev
);
2617 struct iova
*iova
= NULL
;
2619 /* Restrict dma_mask to the width that the iommu can handle */
2620 dma_mask
= min_t(uint64_t, DOMAIN_MAX_ADDR(domain
->gaw
), dma_mask
);
2622 if (!dmar_forcedac
&& dma_mask
> DMA_BIT_MASK(32)) {
2624 * First try to allocate an io virtual address in
2625 * DMA_BIT_MASK(32) and if that fails then try allocating
2628 iova
= alloc_iova(&domain
->iovad
, nrpages
,
2629 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2633 iova
= alloc_iova(&domain
->iovad
, nrpages
, IOVA_PFN(dma_mask
), 1);
2634 if (unlikely(!iova
)) {
2635 printk(KERN_ERR
"Allocating %ld-page iova for %s failed",
2636 nrpages
, pci_name(pdev
));
2643 static struct dmar_domain
*__get_valid_domain_for_dev(struct pci_dev
*pdev
)
2645 struct dmar_domain
*domain
;
2648 domain
= get_domain_for_dev(pdev
,
2649 DEFAULT_DOMAIN_ADDRESS_WIDTH
);
2652 "Allocating domain for %s failed", pci_name(pdev
));
2656 /* make sure context mapping is ok */
2657 if (unlikely(!domain_context_mapped(pdev
))) {
2658 ret
= domain_context_mapping(domain
, pdev
,
2659 CONTEXT_TT_MULTI_LEVEL
);
2662 "Domain context map for %s failed",
2671 static inline struct dmar_domain
*get_valid_domain_for_dev(struct pci_dev
*dev
)
2673 struct device_domain_info
*info
;
2675 /* No lock here, assumes no domain exit in normal case */
2676 info
= dev
->dev
.archdata
.iommu
;
2678 return info
->domain
;
2680 return __get_valid_domain_for_dev(dev
);
2683 static int iommu_dummy(struct pci_dev
*pdev
)
2685 return pdev
->dev
.archdata
.iommu
== DUMMY_DEVICE_DOMAIN_INFO
;
2688 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2689 static int iommu_no_mapping(struct device
*dev
)
2691 struct pci_dev
*pdev
;
2694 if (unlikely(dev
->bus
!= &pci_bus_type
))
2697 pdev
= to_pci_dev(dev
);
2698 if (iommu_dummy(pdev
))
2701 if (!iommu_identity_mapping
)
2704 found
= identity_mapping(pdev
);
2706 if (iommu_should_identity_map(pdev
, 0))
2710 * 32 bit DMA is removed from si_domain and fall back
2711 * to non-identity mapping.
2713 domain_remove_one_dev_info(si_domain
, pdev
);
2714 printk(KERN_INFO
"32bit %s uses non-identity mapping\n",
2720 * In case of a detached 64 bit DMA device from vm, the device
2721 * is put into si_domain for identity mapping.
2723 if (iommu_should_identity_map(pdev
, 0)) {
2725 ret
= domain_add_dev_info(si_domain
, pdev
,
2727 CONTEXT_TT_PASS_THROUGH
:
2728 CONTEXT_TT_MULTI_LEVEL
);
2730 printk(KERN_INFO
"64bit %s uses identity mapping\n",
2740 static dma_addr_t
__intel_map_single(struct device
*hwdev
, phys_addr_t paddr
,
2741 size_t size
, int dir
, u64 dma_mask
)
2743 struct pci_dev
*pdev
= to_pci_dev(hwdev
);
2744 struct dmar_domain
*domain
;
2745 phys_addr_t start_paddr
;
2749 struct intel_iommu
*iommu
;
2750 unsigned long paddr_pfn
= paddr
>> PAGE_SHIFT
;
2752 BUG_ON(dir
== DMA_NONE
);
2754 if (iommu_no_mapping(hwdev
))
2757 domain
= get_valid_domain_for_dev(pdev
);
2761 iommu
= domain_get_iommu(domain
);
2762 size
= aligned_nrpages(paddr
, size
);
2764 iova
= intel_alloc_iova(hwdev
, domain
, dma_to_mm_pfn(size
), dma_mask
);
2769 * Check if DMAR supports zero-length reads on write only
2772 if (dir
== DMA_TO_DEVICE
|| dir
== DMA_BIDIRECTIONAL
|| \
2773 !cap_zlr(iommu
->cap
))
2774 prot
|= DMA_PTE_READ
;
2775 if (dir
== DMA_FROM_DEVICE
|| dir
== DMA_BIDIRECTIONAL
)
2776 prot
|= DMA_PTE_WRITE
;
2778 * paddr - (paddr + size) might be partial page, we should map the whole
2779 * page. Note: if two part of one page are separately mapped, we
2780 * might have two guest_addr mapping to the same host paddr, but this
2781 * is not a big problem
2783 ret
= domain_pfn_mapping(domain
, mm_to_dma_pfn(iova
->pfn_lo
),
2784 mm_to_dma_pfn(paddr_pfn
), size
, prot
);
2788 /* it's a non-present to present mapping. Only flush if caching mode */
2789 if (cap_caching_mode(iommu
->cap
))
2790 iommu_flush_iotlb_psi(iommu
, domain
->id
, mm_to_dma_pfn(iova
->pfn_lo
), size
, 1);
2792 iommu_flush_write_buffer(iommu
);
2794 start_paddr
= (phys_addr_t
)iova
->pfn_lo
<< PAGE_SHIFT
;
2795 start_paddr
+= paddr
& ~PAGE_MASK
;
2800 __free_iova(&domain
->iovad
, iova
);
2801 printk(KERN_ERR
"Device %s request: %zx@%llx dir %d --- failed\n",
2802 pci_name(pdev
), size
, (unsigned long long)paddr
, dir
);
2806 static dma_addr_t
intel_map_page(struct device
*dev
, struct page
*page
,
2807 unsigned long offset
, size_t size
,
2808 enum dma_data_direction dir
,
2809 struct dma_attrs
*attrs
)
2811 return __intel_map_single(dev
, page_to_phys(page
) + offset
, size
,
2812 dir
, to_pci_dev(dev
)->dma_mask
);
2815 static void flush_unmaps(void)
2821 /* just flush them all */
2822 for (i
= 0; i
< g_num_of_iommus
; i
++) {
2823 struct intel_iommu
*iommu
= g_iommus
[i
];
2827 if (!deferred_flush
[i
].next
)
2830 /* In caching mode, global flushes turn emulation expensive */
2831 if (!cap_caching_mode(iommu
->cap
))
2832 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0,
2833 DMA_TLB_GLOBAL_FLUSH
);
2834 for (j
= 0; j
< deferred_flush
[i
].next
; j
++) {
2836 struct iova
*iova
= deferred_flush
[i
].iova
[j
];
2837 struct dmar_domain
*domain
= deferred_flush
[i
].domain
[j
];
2839 /* On real hardware multiple invalidations are expensive */
2840 if (cap_caching_mode(iommu
->cap
))
2841 iommu_flush_iotlb_psi(iommu
, domain
->id
,
2842 iova
->pfn_lo
, iova
->pfn_hi
- iova
->pfn_lo
+ 1, 0);
2844 mask
= ilog2(mm_to_dma_pfn(iova
->pfn_hi
- iova
->pfn_lo
+ 1));
2845 iommu_flush_dev_iotlb(deferred_flush
[i
].domain
[j
],
2846 (uint64_t)iova
->pfn_lo
<< PAGE_SHIFT
, mask
);
2848 __free_iova(&deferred_flush
[i
].domain
[j
]->iovad
, iova
);
2850 deferred_flush
[i
].next
= 0;
2856 static void flush_unmaps_timeout(unsigned long data
)
2858 unsigned long flags
;
2860 spin_lock_irqsave(&async_umap_flush_lock
, flags
);
2862 spin_unlock_irqrestore(&async_umap_flush_lock
, flags
);
2865 static void add_unmap(struct dmar_domain
*dom
, struct iova
*iova
)
2867 unsigned long flags
;
2869 struct intel_iommu
*iommu
;
2871 spin_lock_irqsave(&async_umap_flush_lock
, flags
);
2872 if (list_size
== HIGH_WATER_MARK
)
2875 iommu
= domain_get_iommu(dom
);
2876 iommu_id
= iommu
->seq_id
;
2878 next
= deferred_flush
[iommu_id
].next
;
2879 deferred_flush
[iommu_id
].domain
[next
] = dom
;
2880 deferred_flush
[iommu_id
].iova
[next
] = iova
;
2881 deferred_flush
[iommu_id
].next
++;
2884 mod_timer(&unmap_timer
, jiffies
+ msecs_to_jiffies(10));
2888 spin_unlock_irqrestore(&async_umap_flush_lock
, flags
);
2891 static void intel_unmap_page(struct device
*dev
, dma_addr_t dev_addr
,
2892 size_t size
, enum dma_data_direction dir
,
2893 struct dma_attrs
*attrs
)
2895 struct pci_dev
*pdev
= to_pci_dev(dev
);
2896 struct dmar_domain
*domain
;
2897 unsigned long start_pfn
, last_pfn
;
2899 struct intel_iommu
*iommu
;
2901 if (iommu_no_mapping(dev
))
2904 domain
= find_domain(pdev
);
2907 iommu
= domain_get_iommu(domain
);
2909 iova
= find_iova(&domain
->iovad
, IOVA_PFN(dev_addr
));
2910 if (WARN_ONCE(!iova
, "Driver unmaps unmatched page at PFN %llx\n",
2911 (unsigned long long)dev_addr
))
2914 start_pfn
= mm_to_dma_pfn(iova
->pfn_lo
);
2915 last_pfn
= mm_to_dma_pfn(iova
->pfn_hi
+ 1) - 1;
2917 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2918 pci_name(pdev
), start_pfn
, last_pfn
);
2920 /* clear the whole page */
2921 dma_pte_clear_range(domain
, start_pfn
, last_pfn
);
2923 /* free page tables */
2924 dma_pte_free_pagetable(domain
, start_pfn
, last_pfn
);
2926 if (intel_iommu_strict
) {
2927 iommu_flush_iotlb_psi(iommu
, domain
->id
, start_pfn
,
2928 last_pfn
- start_pfn
+ 1, 0);
2930 __free_iova(&domain
->iovad
, iova
);
2932 add_unmap(domain
, iova
);
2934 * queue up the release of the unmap to save the 1/6th of the
2935 * cpu used up by the iotlb flush operation...
2940 static void *intel_alloc_coherent(struct device
*hwdev
, size_t size
,
2941 dma_addr_t
*dma_handle
, gfp_t flags
,
2942 struct dma_attrs
*attrs
)
2947 size
= PAGE_ALIGN(size
);
2948 order
= get_order(size
);
2950 if (!iommu_no_mapping(hwdev
))
2951 flags
&= ~(GFP_DMA
| GFP_DMA32
);
2952 else if (hwdev
->coherent_dma_mask
< dma_get_required_mask(hwdev
)) {
2953 if (hwdev
->coherent_dma_mask
< DMA_BIT_MASK(32))
2959 vaddr
= (void *)__get_free_pages(flags
, order
);
2962 memset(vaddr
, 0, size
);
2964 *dma_handle
= __intel_map_single(hwdev
, virt_to_bus(vaddr
), size
,
2966 hwdev
->coherent_dma_mask
);
2969 free_pages((unsigned long)vaddr
, order
);
2973 static void intel_free_coherent(struct device
*hwdev
, size_t size
, void *vaddr
,
2974 dma_addr_t dma_handle
, struct dma_attrs
*attrs
)
2978 size
= PAGE_ALIGN(size
);
2979 order
= get_order(size
);
2981 intel_unmap_page(hwdev
, dma_handle
, size
, DMA_BIDIRECTIONAL
, NULL
);
2982 free_pages((unsigned long)vaddr
, order
);
2985 static void intel_unmap_sg(struct device
*hwdev
, struct scatterlist
*sglist
,
2986 int nelems
, enum dma_data_direction dir
,
2987 struct dma_attrs
*attrs
)
2989 struct pci_dev
*pdev
= to_pci_dev(hwdev
);
2990 struct dmar_domain
*domain
;
2991 unsigned long start_pfn
, last_pfn
;
2993 struct intel_iommu
*iommu
;
2995 if (iommu_no_mapping(hwdev
))
2998 domain
= find_domain(pdev
);
3001 iommu
= domain_get_iommu(domain
);
3003 iova
= find_iova(&domain
->iovad
, IOVA_PFN(sglist
[0].dma_address
));
3004 if (WARN_ONCE(!iova
, "Driver unmaps unmatched sglist at PFN %llx\n",
3005 (unsigned long long)sglist
[0].dma_address
))
3008 start_pfn
= mm_to_dma_pfn(iova
->pfn_lo
);
3009 last_pfn
= mm_to_dma_pfn(iova
->pfn_hi
+ 1) - 1;
3011 /* clear the whole page */
3012 dma_pte_clear_range(domain
, start_pfn
, last_pfn
);
3014 /* free page tables */
3015 dma_pte_free_pagetable(domain
, start_pfn
, last_pfn
);
3017 if (intel_iommu_strict
) {
3018 iommu_flush_iotlb_psi(iommu
, domain
->id
, start_pfn
,
3019 last_pfn
- start_pfn
+ 1, 0);
3021 __free_iova(&domain
->iovad
, iova
);
3023 add_unmap(domain
, iova
);
3025 * queue up the release of the unmap to save the 1/6th of the
3026 * cpu used up by the iotlb flush operation...
3031 static int intel_nontranslate_map_sg(struct device
*hddev
,
3032 struct scatterlist
*sglist
, int nelems
, int dir
)
3035 struct scatterlist
*sg
;
3037 for_each_sg(sglist
, sg
, nelems
, i
) {
3038 BUG_ON(!sg_page(sg
));
3039 sg
->dma_address
= page_to_phys(sg_page(sg
)) + sg
->offset
;
3040 sg
->dma_length
= sg
->length
;
3045 static int intel_map_sg(struct device
*hwdev
, struct scatterlist
*sglist
, int nelems
,
3046 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
3049 struct pci_dev
*pdev
= to_pci_dev(hwdev
);
3050 struct dmar_domain
*domain
;
3053 struct iova
*iova
= NULL
;
3055 struct scatterlist
*sg
;
3056 unsigned long start_vpfn
;
3057 struct intel_iommu
*iommu
;
3059 BUG_ON(dir
== DMA_NONE
);
3060 if (iommu_no_mapping(hwdev
))
3061 return intel_nontranslate_map_sg(hwdev
, sglist
, nelems
, dir
);
3063 domain
= get_valid_domain_for_dev(pdev
);
3067 iommu
= domain_get_iommu(domain
);
3069 for_each_sg(sglist
, sg
, nelems
, i
)
3070 size
+= aligned_nrpages(sg
->offset
, sg
->length
);
3072 iova
= intel_alloc_iova(hwdev
, domain
, dma_to_mm_pfn(size
),
3075 sglist
->dma_length
= 0;
3080 * Check if DMAR supports zero-length reads on write only
3083 if (dir
== DMA_TO_DEVICE
|| dir
== DMA_BIDIRECTIONAL
|| \
3084 !cap_zlr(iommu
->cap
))
3085 prot
|= DMA_PTE_READ
;
3086 if (dir
== DMA_FROM_DEVICE
|| dir
== DMA_BIDIRECTIONAL
)
3087 prot
|= DMA_PTE_WRITE
;
3089 start_vpfn
= mm_to_dma_pfn(iova
->pfn_lo
);
3091 ret
= domain_sg_mapping(domain
, start_vpfn
, sglist
, size
, prot
);
3092 if (unlikely(ret
)) {
3093 /* clear the page */
3094 dma_pte_clear_range(domain
, start_vpfn
,
3095 start_vpfn
+ size
- 1);
3096 /* free page tables */
3097 dma_pte_free_pagetable(domain
, start_vpfn
,
3098 start_vpfn
+ size
- 1);
3100 __free_iova(&domain
->iovad
, iova
);
3104 /* it's a non-present to present mapping. Only flush if caching mode */
3105 if (cap_caching_mode(iommu
->cap
))
3106 iommu_flush_iotlb_psi(iommu
, domain
->id
, start_vpfn
, size
, 1);
3108 iommu_flush_write_buffer(iommu
);
3113 static int intel_mapping_error(struct device
*dev
, dma_addr_t dma_addr
)
3118 struct dma_map_ops intel_dma_ops
= {
3119 .alloc
= intel_alloc_coherent
,
3120 .free
= intel_free_coherent
,
3121 .map_sg
= intel_map_sg
,
3122 .unmap_sg
= intel_unmap_sg
,
3123 .map_page
= intel_map_page
,
3124 .unmap_page
= intel_unmap_page
,
3125 .mapping_error
= intel_mapping_error
,
3128 static inline int iommu_domain_cache_init(void)
3132 iommu_domain_cache
= kmem_cache_create("iommu_domain",
3133 sizeof(struct dmar_domain
),
3138 if (!iommu_domain_cache
) {
3139 printk(KERN_ERR
"Couldn't create iommu_domain cache\n");
3146 static inline int iommu_devinfo_cache_init(void)
3150 iommu_devinfo_cache
= kmem_cache_create("iommu_devinfo",
3151 sizeof(struct device_domain_info
),
3155 if (!iommu_devinfo_cache
) {
3156 printk(KERN_ERR
"Couldn't create devinfo cache\n");
3163 static inline int iommu_iova_cache_init(void)
3167 iommu_iova_cache
= kmem_cache_create("iommu_iova",
3168 sizeof(struct iova
),
3172 if (!iommu_iova_cache
) {
3173 printk(KERN_ERR
"Couldn't create iova cache\n");
3180 static int __init
iommu_init_mempool(void)
3183 ret
= iommu_iova_cache_init();
3187 ret
= iommu_domain_cache_init();
3191 ret
= iommu_devinfo_cache_init();
3195 kmem_cache_destroy(iommu_domain_cache
);
3197 kmem_cache_destroy(iommu_iova_cache
);
3202 static void __init
iommu_exit_mempool(void)
3204 kmem_cache_destroy(iommu_devinfo_cache
);
3205 kmem_cache_destroy(iommu_domain_cache
);
3206 kmem_cache_destroy(iommu_iova_cache
);
3210 static void quirk_ioat_snb_local_iommu(struct pci_dev
*pdev
)
3212 struct dmar_drhd_unit
*drhd
;
3216 /* We know that this device on this chipset has its own IOMMU.
3217 * If we find it under a different IOMMU, then the BIOS is lying
3218 * to us. Hope that the IOMMU for this device is actually
3219 * disabled, and it needs no translation...
3221 rc
= pci_bus_read_config_dword(pdev
->bus
, PCI_DEVFN(0, 0), 0xb0, &vtbar
);
3223 /* "can't" happen */
3224 dev_info(&pdev
->dev
, "failed to run vt-d quirk\n");
3227 vtbar
&= 0xffff0000;
3229 /* we know that the this iommu should be at offset 0xa000 from vtbar */
3230 drhd
= dmar_find_matched_drhd_unit(pdev
);
3231 if (WARN_TAINT_ONCE(!drhd
|| drhd
->reg_base_addr
- vtbar
!= 0xa000,
3232 TAINT_FIRMWARE_WORKAROUND
,
3233 "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
3234 pdev
->dev
.archdata
.iommu
= DUMMY_DEVICE_DOMAIN_INFO
;
3236 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_IOAT_SNB
, quirk_ioat_snb_local_iommu
);
3238 static void __init
init_no_remapping_devices(void)
3240 struct dmar_drhd_unit
*drhd
;
3242 for_each_drhd_unit(drhd
) {
3243 if (!drhd
->include_all
) {
3245 for (i
= 0; i
< drhd
->devices_cnt
; i
++)
3246 if (drhd
->devices
[i
] != NULL
)
3248 /* ignore DMAR unit if no pci devices exist */
3249 if (i
== drhd
->devices_cnt
)
3254 for_each_drhd_unit(drhd
) {
3256 if (drhd
->ignored
|| drhd
->include_all
)
3259 for (i
= 0; i
< drhd
->devices_cnt
; i
++)
3260 if (drhd
->devices
[i
] &&
3261 !IS_GFX_DEVICE(drhd
->devices
[i
]))
3264 if (i
< drhd
->devices_cnt
)
3267 /* This IOMMU has *only* gfx devices. Either bypass it or
3268 set the gfx_mapped flag, as appropriate */
3270 intel_iommu_gfx_mapped
= 1;
3273 for (i
= 0; i
< drhd
->devices_cnt
; i
++) {
3274 if (!drhd
->devices
[i
])
3276 drhd
->devices
[i
]->dev
.archdata
.iommu
= DUMMY_DEVICE_DOMAIN_INFO
;
3282 #ifdef CONFIG_SUSPEND
3283 static int init_iommu_hw(void)
3285 struct dmar_drhd_unit
*drhd
;
3286 struct intel_iommu
*iommu
= NULL
;
3288 for_each_active_iommu(iommu
, drhd
)
3290 dmar_reenable_qi(iommu
);
3292 for_each_iommu(iommu
, drhd
) {
3293 if (drhd
->ignored
) {
3295 * we always have to disable PMRs or DMA may fail on
3299 iommu_disable_protect_mem_regions(iommu
);
3303 iommu_flush_write_buffer(iommu
);
3305 iommu_set_root_entry(iommu
);
3307 iommu
->flush
.flush_context(iommu
, 0, 0, 0,
3308 DMA_CCMD_GLOBAL_INVL
);
3309 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0,
3310 DMA_TLB_GLOBAL_FLUSH
);
3311 if (iommu_enable_translation(iommu
))
3313 iommu_disable_protect_mem_regions(iommu
);
3319 static void iommu_flush_all(void)
3321 struct dmar_drhd_unit
*drhd
;
3322 struct intel_iommu
*iommu
;
3324 for_each_active_iommu(iommu
, drhd
) {
3325 iommu
->flush
.flush_context(iommu
, 0, 0, 0,
3326 DMA_CCMD_GLOBAL_INVL
);
3327 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0,
3328 DMA_TLB_GLOBAL_FLUSH
);
3332 static int iommu_suspend(void)
3334 struct dmar_drhd_unit
*drhd
;
3335 struct intel_iommu
*iommu
= NULL
;
3338 for_each_active_iommu(iommu
, drhd
) {
3339 iommu
->iommu_state
= kzalloc(sizeof(u32
) * MAX_SR_DMAR_REGS
,
3341 if (!iommu
->iommu_state
)
3347 for_each_active_iommu(iommu
, drhd
) {
3348 iommu_disable_translation(iommu
);
3350 raw_spin_lock_irqsave(&iommu
->register_lock
, flag
);
3352 iommu
->iommu_state
[SR_DMAR_FECTL_REG
] =
3353 readl(iommu
->reg
+ DMAR_FECTL_REG
);
3354 iommu
->iommu_state
[SR_DMAR_FEDATA_REG
] =
3355 readl(iommu
->reg
+ DMAR_FEDATA_REG
);
3356 iommu
->iommu_state
[SR_DMAR_FEADDR_REG
] =
3357 readl(iommu
->reg
+ DMAR_FEADDR_REG
);
3358 iommu
->iommu_state
[SR_DMAR_FEUADDR_REG
] =
3359 readl(iommu
->reg
+ DMAR_FEUADDR_REG
);
3361 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
3366 for_each_active_iommu(iommu
, drhd
)
3367 kfree(iommu
->iommu_state
);
3372 static void iommu_resume(void)
3374 struct dmar_drhd_unit
*drhd
;
3375 struct intel_iommu
*iommu
= NULL
;
3378 if (init_iommu_hw()) {
3380 panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3382 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3386 for_each_active_iommu(iommu
, drhd
) {
3388 raw_spin_lock_irqsave(&iommu
->register_lock
, flag
);
3390 writel(iommu
->iommu_state
[SR_DMAR_FECTL_REG
],
3391 iommu
->reg
+ DMAR_FECTL_REG
);
3392 writel(iommu
->iommu_state
[SR_DMAR_FEDATA_REG
],
3393 iommu
->reg
+ DMAR_FEDATA_REG
);
3394 writel(iommu
->iommu_state
[SR_DMAR_FEADDR_REG
],
3395 iommu
->reg
+ DMAR_FEADDR_REG
);
3396 writel(iommu
->iommu_state
[SR_DMAR_FEUADDR_REG
],
3397 iommu
->reg
+ DMAR_FEUADDR_REG
);
3399 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
3402 for_each_active_iommu(iommu
, drhd
)
3403 kfree(iommu
->iommu_state
);
3406 static struct syscore_ops iommu_syscore_ops
= {
3407 .resume
= iommu_resume
,
3408 .suspend
= iommu_suspend
,
3411 static void __init
init_iommu_pm_ops(void)
3413 register_syscore_ops(&iommu_syscore_ops
);
3417 static inline void init_iommu_pm_ops(void) {}
3418 #endif /* CONFIG_PM */
3420 LIST_HEAD(dmar_rmrr_units
);
3422 static void __init
dmar_register_rmrr_unit(struct dmar_rmrr_unit
*rmrr
)
3424 list_add(&rmrr
->list
, &dmar_rmrr_units
);
3428 int __init
dmar_parse_one_rmrr(struct acpi_dmar_header
*header
)
3430 struct acpi_dmar_reserved_memory
*rmrr
;
3431 struct dmar_rmrr_unit
*rmrru
;
3433 rmrru
= kzalloc(sizeof(*rmrru
), GFP_KERNEL
);
3437 rmrru
->hdr
= header
;
3438 rmrr
= (struct acpi_dmar_reserved_memory
*)header
;
3439 rmrru
->base_address
= rmrr
->base_address
;
3440 rmrru
->end_address
= rmrr
->end_address
;
3442 dmar_register_rmrr_unit(rmrru
);
3447 rmrr_parse_dev(struct dmar_rmrr_unit
*rmrru
)
3449 struct acpi_dmar_reserved_memory
*rmrr
;
3452 rmrr
= (struct acpi_dmar_reserved_memory
*) rmrru
->hdr
;
3453 ret
= dmar_parse_dev_scope((void *)(rmrr
+ 1),
3454 ((void *)rmrr
) + rmrr
->header
.length
,
3455 &rmrru
->devices_cnt
, &rmrru
->devices
, rmrr
->segment
);
3457 if (ret
|| (rmrru
->devices_cnt
== 0)) {
3458 list_del(&rmrru
->list
);
3464 static LIST_HEAD(dmar_atsr_units
);
3466 int __init
dmar_parse_one_atsr(struct acpi_dmar_header
*hdr
)
3468 struct acpi_dmar_atsr
*atsr
;
3469 struct dmar_atsr_unit
*atsru
;
3471 atsr
= container_of(hdr
, struct acpi_dmar_atsr
, header
);
3472 atsru
= kzalloc(sizeof(*atsru
), GFP_KERNEL
);
3477 atsru
->include_all
= atsr
->flags
& 0x1;
3479 list_add(&atsru
->list
, &dmar_atsr_units
);
3484 static int __init
atsr_parse_dev(struct dmar_atsr_unit
*atsru
)
3487 struct acpi_dmar_atsr
*atsr
;
3489 if (atsru
->include_all
)
3492 atsr
= container_of(atsru
->hdr
, struct acpi_dmar_atsr
, header
);
3493 rc
= dmar_parse_dev_scope((void *)(atsr
+ 1),
3494 (void *)atsr
+ atsr
->header
.length
,
3495 &atsru
->devices_cnt
, &atsru
->devices
,
3497 if (rc
|| !atsru
->devices_cnt
) {
3498 list_del(&atsru
->list
);
3505 int dmar_find_matched_atsr_unit(struct pci_dev
*dev
)
3508 struct pci_bus
*bus
;
3509 struct acpi_dmar_atsr
*atsr
;
3510 struct dmar_atsr_unit
*atsru
;
3512 dev
= pci_physfn(dev
);
3514 list_for_each_entry(atsru
, &dmar_atsr_units
, list
) {
3515 atsr
= container_of(atsru
->hdr
, struct acpi_dmar_atsr
, header
);
3516 if (atsr
->segment
== pci_domain_nr(dev
->bus
))
3523 for (bus
= dev
->bus
; bus
; bus
= bus
->parent
) {
3524 struct pci_dev
*bridge
= bus
->self
;
3526 if (!bridge
|| !pci_is_pcie(bridge
) ||
3527 bridge
->pcie_type
== PCI_EXP_TYPE_PCI_BRIDGE
)
3530 if (bridge
->pcie_type
== PCI_EXP_TYPE_ROOT_PORT
) {
3531 for (i
= 0; i
< atsru
->devices_cnt
; i
++)
3532 if (atsru
->devices
[i
] == bridge
)
3538 if (atsru
->include_all
)
3544 int __init
dmar_parse_rmrr_atsr_dev(void)
3546 struct dmar_rmrr_unit
*rmrr
, *rmrr_n
;
3547 struct dmar_atsr_unit
*atsr
, *atsr_n
;
3550 list_for_each_entry_safe(rmrr
, rmrr_n
, &dmar_rmrr_units
, list
) {
3551 ret
= rmrr_parse_dev(rmrr
);
3556 list_for_each_entry_safe(atsr
, atsr_n
, &dmar_atsr_units
, list
) {
3557 ret
= atsr_parse_dev(atsr
);
3566 * Here we only respond to action of unbound device from driver.
3568 * Added device is not attached to its DMAR domain here yet. That will happen
3569 * when mapping the device to iova.
3571 static int device_notifier(struct notifier_block
*nb
,
3572 unsigned long action
, void *data
)
3574 struct device
*dev
= data
;
3575 struct pci_dev
*pdev
= to_pci_dev(dev
);
3576 struct dmar_domain
*domain
;
3578 if (iommu_no_mapping(dev
))
3581 domain
= find_domain(pdev
);
3585 if (action
== BUS_NOTIFY_UNBOUND_DRIVER
&& !iommu_pass_through
) {
3586 domain_remove_one_dev_info(domain
, pdev
);
3588 if (!(domain
->flags
& DOMAIN_FLAG_VIRTUAL_MACHINE
) &&
3589 !(domain
->flags
& DOMAIN_FLAG_STATIC_IDENTITY
) &&
3590 list_empty(&domain
->devices
))
3591 domain_exit(domain
);
3597 static struct notifier_block device_nb
= {
3598 .notifier_call
= device_notifier
,
3601 int __init
intel_iommu_init(void)
3605 /* VT-d is required for a TXT/tboot launch, so enforce that */
3606 force_on
= tboot_force_iommu();
3608 if (dmar_table_init()) {
3610 panic("tboot: Failed to initialize DMAR table\n");
3614 if (dmar_dev_scope_init() < 0) {
3616 panic("tboot: Failed to initialize DMAR device scope\n");
3620 if (no_iommu
|| dmar_disabled
)
3623 if (iommu_init_mempool()) {
3625 panic("tboot: Failed to initialize iommu memory\n");
3629 if (list_empty(&dmar_rmrr_units
))
3630 printk(KERN_INFO
"DMAR: No RMRR found\n");
3632 if (list_empty(&dmar_atsr_units
))
3633 printk(KERN_INFO
"DMAR: No ATSR found\n");
3635 if (dmar_init_reserved_ranges()) {
3637 panic("tboot: Failed to reserve iommu ranges\n");
3641 init_no_remapping_devices();
3646 panic("tboot: Failed to initialize DMARs\n");
3647 printk(KERN_ERR
"IOMMU: dmar init failed\n");
3648 put_iova_domain(&reserved_iova_list
);
3649 iommu_exit_mempool();
3653 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3655 init_timer(&unmap_timer
);
3656 #ifdef CONFIG_SWIOTLB
3659 dma_ops
= &intel_dma_ops
;
3661 init_iommu_pm_ops();
3663 bus_set_iommu(&pci_bus_type
, &intel_iommu_ops
);
3665 bus_register_notifier(&pci_bus_type
, &device_nb
);
3667 intel_iommu_enabled
= 1;
3672 static void iommu_detach_dependent_devices(struct intel_iommu
*iommu
,
3673 struct pci_dev
*pdev
)
3675 struct pci_dev
*tmp
, *parent
;
3677 if (!iommu
|| !pdev
)
3680 /* dependent device detach */
3681 tmp
= pci_find_upstream_pcie_bridge(pdev
);
3682 /* Secondary interface's bus number and devfn 0 */
3684 parent
= pdev
->bus
->self
;
3685 while (parent
!= tmp
) {
3686 iommu_detach_dev(iommu
, parent
->bus
->number
,
3688 parent
= parent
->bus
->self
;
3690 if (pci_is_pcie(tmp
)) /* this is a PCIe-to-PCI bridge */
3691 iommu_detach_dev(iommu
,
3692 tmp
->subordinate
->number
, 0);
3693 else /* this is a legacy PCI bridge */
3694 iommu_detach_dev(iommu
, tmp
->bus
->number
,
3699 static void domain_remove_one_dev_info(struct dmar_domain
*domain
,
3700 struct pci_dev
*pdev
)
3702 struct device_domain_info
*info
;
3703 struct intel_iommu
*iommu
;
3704 unsigned long flags
;
3706 struct list_head
*entry
, *tmp
;
3708 iommu
= device_to_iommu(pci_domain_nr(pdev
->bus
), pdev
->bus
->number
,
3713 spin_lock_irqsave(&device_domain_lock
, flags
);
3714 list_for_each_safe(entry
, tmp
, &domain
->devices
) {
3715 info
= list_entry(entry
, struct device_domain_info
, link
);
3716 if (info
->segment
== pci_domain_nr(pdev
->bus
) &&
3717 info
->bus
== pdev
->bus
->number
&&
3718 info
->devfn
== pdev
->devfn
) {
3719 list_del(&info
->link
);
3720 list_del(&info
->global
);
3722 info
->dev
->dev
.archdata
.iommu
= NULL
;
3723 spin_unlock_irqrestore(&device_domain_lock
, flags
);
3725 iommu_disable_dev_iotlb(info
);
3726 iommu_detach_dev(iommu
, info
->bus
, info
->devfn
);
3727 iommu_detach_dependent_devices(iommu
, pdev
);
3728 free_devinfo_mem(info
);
3730 spin_lock_irqsave(&device_domain_lock
, flags
);
3738 /* if there is no other devices under the same iommu
3739 * owned by this domain, clear this iommu in iommu_bmp
3740 * update iommu count and coherency
3742 if (iommu
== device_to_iommu(info
->segment
, info
->bus
,
3747 spin_unlock_irqrestore(&device_domain_lock
, flags
);
3750 unsigned long tmp_flags
;
3751 spin_lock_irqsave(&domain
->iommu_lock
, tmp_flags
);
3752 clear_bit(iommu
->seq_id
, &domain
->iommu_bmp
);
3753 domain
->iommu_count
--;
3754 domain_update_iommu_cap(domain
);
3755 spin_unlock_irqrestore(&domain
->iommu_lock
, tmp_flags
);
3757 if (!(domain
->flags
& DOMAIN_FLAG_VIRTUAL_MACHINE
) &&
3758 !(domain
->flags
& DOMAIN_FLAG_STATIC_IDENTITY
)) {
3759 spin_lock_irqsave(&iommu
->lock
, tmp_flags
);
3760 clear_bit(domain
->id
, iommu
->domain_ids
);
3761 iommu
->domains
[domain
->id
] = NULL
;
3762 spin_unlock_irqrestore(&iommu
->lock
, tmp_flags
);
3767 static void vm_domain_remove_all_dev_info(struct dmar_domain
*domain
)
3769 struct device_domain_info
*info
;
3770 struct intel_iommu
*iommu
;
3771 unsigned long flags1
, flags2
;
3773 spin_lock_irqsave(&device_domain_lock
, flags1
);
3774 while (!list_empty(&domain
->devices
)) {
3775 info
= list_entry(domain
->devices
.next
,
3776 struct device_domain_info
, link
);
3777 list_del(&info
->link
);
3778 list_del(&info
->global
);
3780 info
->dev
->dev
.archdata
.iommu
= NULL
;
3782 spin_unlock_irqrestore(&device_domain_lock
, flags1
);
3784 iommu_disable_dev_iotlb(info
);
3785 iommu
= device_to_iommu(info
->segment
, info
->bus
, info
->devfn
);
3786 iommu_detach_dev(iommu
, info
->bus
, info
->devfn
);
3787 iommu_detach_dependent_devices(iommu
, info
->dev
);
3789 /* clear this iommu in iommu_bmp, update iommu count
3792 spin_lock_irqsave(&domain
->iommu_lock
, flags2
);
3793 if (test_and_clear_bit(iommu
->seq_id
,
3794 &domain
->iommu_bmp
)) {
3795 domain
->iommu_count
--;
3796 domain_update_iommu_cap(domain
);
3798 spin_unlock_irqrestore(&domain
->iommu_lock
, flags2
);
3800 free_devinfo_mem(info
);
3801 spin_lock_irqsave(&device_domain_lock
, flags1
);
3803 spin_unlock_irqrestore(&device_domain_lock
, flags1
);
3806 /* domain id for virtual machine, it won't be set in context */
3807 static unsigned long vm_domid
;
3809 static struct dmar_domain
*iommu_alloc_vm_domain(void)
3811 struct dmar_domain
*domain
;
3813 domain
= alloc_domain_mem();
3817 domain
->id
= vm_domid
++;
3819 memset(&domain
->iommu_bmp
, 0, sizeof(unsigned long));
3820 domain
->flags
= DOMAIN_FLAG_VIRTUAL_MACHINE
;
3825 static int md_domain_init(struct dmar_domain
*domain
, int guest_width
)
3829 init_iova_domain(&domain
->iovad
, DMA_32BIT_PFN
);
3830 spin_lock_init(&domain
->iommu_lock
);
3832 domain_reserve_special_ranges(domain
);
3834 /* calculate AGAW */
3835 domain
->gaw
= guest_width
;
3836 adjust_width
= guestwidth_to_adjustwidth(guest_width
);
3837 domain
->agaw
= width_to_agaw(adjust_width
);
3839 INIT_LIST_HEAD(&domain
->devices
);
3841 domain
->iommu_count
= 0;
3842 domain
->iommu_coherency
= 0;
3843 domain
->iommu_snooping
= 0;
3844 domain
->iommu_superpage
= 0;
3845 domain
->max_addr
= 0;
3848 /* always allocate the top pgd */
3849 domain
->pgd
= (struct dma_pte
*)alloc_pgtable_page(domain
->nid
);
3852 domain_flush_cache(domain
, domain
->pgd
, PAGE_SIZE
);
3856 static void iommu_free_vm_domain(struct dmar_domain
*domain
)
3858 unsigned long flags
;
3859 struct dmar_drhd_unit
*drhd
;
3860 struct intel_iommu
*iommu
;
3862 unsigned long ndomains
;
3864 for_each_drhd_unit(drhd
) {
3867 iommu
= drhd
->iommu
;
3869 ndomains
= cap_ndoms(iommu
->cap
);
3870 for_each_set_bit(i
, iommu
->domain_ids
, ndomains
) {
3871 if (iommu
->domains
[i
] == domain
) {
3872 spin_lock_irqsave(&iommu
->lock
, flags
);
3873 clear_bit(i
, iommu
->domain_ids
);
3874 iommu
->domains
[i
] = NULL
;
3875 spin_unlock_irqrestore(&iommu
->lock
, flags
);
3882 static void vm_domain_exit(struct dmar_domain
*domain
)
3884 /* Domain 0 is reserved, so dont process it */
3888 vm_domain_remove_all_dev_info(domain
);
3890 put_iova_domain(&domain
->iovad
);
3893 dma_pte_clear_range(domain
, 0, DOMAIN_MAX_PFN(domain
->gaw
));
3895 /* free page tables */
3896 dma_pte_free_pagetable(domain
, 0, DOMAIN_MAX_PFN(domain
->gaw
));
3898 iommu_free_vm_domain(domain
);
3899 free_domain_mem(domain
);
3902 static int intel_iommu_domain_init(struct iommu_domain
*domain
)
3904 struct dmar_domain
*dmar_domain
;
3906 dmar_domain
= iommu_alloc_vm_domain();
3909 "intel_iommu_domain_init: dmar_domain == NULL\n");
3912 if (md_domain_init(dmar_domain
, DEFAULT_DOMAIN_ADDRESS_WIDTH
)) {
3914 "intel_iommu_domain_init() failed\n");
3915 vm_domain_exit(dmar_domain
);
3918 domain_update_iommu_cap(dmar_domain
);
3919 domain
->priv
= dmar_domain
;
3924 static void intel_iommu_domain_destroy(struct iommu_domain
*domain
)
3926 struct dmar_domain
*dmar_domain
= domain
->priv
;
3928 domain
->priv
= NULL
;
3929 vm_domain_exit(dmar_domain
);
3932 static int intel_iommu_attach_device(struct iommu_domain
*domain
,
3935 struct dmar_domain
*dmar_domain
= domain
->priv
;
3936 struct pci_dev
*pdev
= to_pci_dev(dev
);
3937 struct intel_iommu
*iommu
;
3940 /* normally pdev is not mapped */
3941 if (unlikely(domain_context_mapped(pdev
))) {
3942 struct dmar_domain
*old_domain
;
3944 old_domain
= find_domain(pdev
);
3946 if (dmar_domain
->flags
& DOMAIN_FLAG_VIRTUAL_MACHINE
||
3947 dmar_domain
->flags
& DOMAIN_FLAG_STATIC_IDENTITY
)
3948 domain_remove_one_dev_info(old_domain
, pdev
);
3950 domain_remove_dev_info(old_domain
);
3954 iommu
= device_to_iommu(pci_domain_nr(pdev
->bus
), pdev
->bus
->number
,
3959 /* check if this iommu agaw is sufficient for max mapped address */
3960 addr_width
= agaw_to_width(iommu
->agaw
);
3961 if (addr_width
> cap_mgaw(iommu
->cap
))
3962 addr_width
= cap_mgaw(iommu
->cap
);
3964 if (dmar_domain
->max_addr
> (1LL << addr_width
)) {
3965 printk(KERN_ERR
"%s: iommu width (%d) is not "
3966 "sufficient for the mapped address (%llx)\n",
3967 __func__
, addr_width
, dmar_domain
->max_addr
);
3970 dmar_domain
->gaw
= addr_width
;
3973 * Knock out extra levels of page tables if necessary
3975 while (iommu
->agaw
< dmar_domain
->agaw
) {
3976 struct dma_pte
*pte
;
3978 pte
= dmar_domain
->pgd
;
3979 if (dma_pte_present(pte
)) {
3980 dmar_domain
->pgd
= (struct dma_pte
*)
3981 phys_to_virt(dma_pte_addr(pte
));
3982 free_pgtable_page(pte
);
3984 dmar_domain
->agaw
--;
3987 return domain_add_dev_info(dmar_domain
, pdev
, CONTEXT_TT_MULTI_LEVEL
);
3990 static void intel_iommu_detach_device(struct iommu_domain
*domain
,
3993 struct dmar_domain
*dmar_domain
= domain
->priv
;
3994 struct pci_dev
*pdev
= to_pci_dev(dev
);
3996 domain_remove_one_dev_info(dmar_domain
, pdev
);
3999 static int intel_iommu_map(struct iommu_domain
*domain
,
4000 unsigned long iova
, phys_addr_t hpa
,
4001 size_t size
, int iommu_prot
)
4003 struct dmar_domain
*dmar_domain
= domain
->priv
;
4008 if (iommu_prot
& IOMMU_READ
)
4009 prot
|= DMA_PTE_READ
;
4010 if (iommu_prot
& IOMMU_WRITE
)
4011 prot
|= DMA_PTE_WRITE
;
4012 if ((iommu_prot
& IOMMU_CACHE
) && dmar_domain
->iommu_snooping
)
4013 prot
|= DMA_PTE_SNP
;
4015 max_addr
= iova
+ size
;
4016 if (dmar_domain
->max_addr
< max_addr
) {
4019 /* check if minimum agaw is sufficient for mapped address */
4020 end
= __DOMAIN_MAX_ADDR(dmar_domain
->gaw
) + 1;
4021 if (end
< max_addr
) {
4022 printk(KERN_ERR
"%s: iommu width (%d) is not "
4023 "sufficient for the mapped address (%llx)\n",
4024 __func__
, dmar_domain
->gaw
, max_addr
);
4027 dmar_domain
->max_addr
= max_addr
;
4029 /* Round up size to next multiple of PAGE_SIZE, if it and
4030 the low bits of hpa would take us onto the next page */
4031 size
= aligned_nrpages(hpa
, size
);
4032 ret
= domain_pfn_mapping(dmar_domain
, iova
>> VTD_PAGE_SHIFT
,
4033 hpa
>> VTD_PAGE_SHIFT
, size
, prot
);
4037 static size_t intel_iommu_unmap(struct iommu_domain
*domain
,
4038 unsigned long iova
, size_t size
)
4040 struct dmar_domain
*dmar_domain
= domain
->priv
;
4043 order
= dma_pte_clear_range(dmar_domain
, iova
>> VTD_PAGE_SHIFT
,
4044 (iova
+ size
- 1) >> VTD_PAGE_SHIFT
);
4046 if (dmar_domain
->max_addr
== iova
+ size
)
4047 dmar_domain
->max_addr
= iova
;
4049 return PAGE_SIZE
<< order
;
4052 static phys_addr_t
intel_iommu_iova_to_phys(struct iommu_domain
*domain
,
4055 struct dmar_domain
*dmar_domain
= domain
->priv
;
4056 struct dma_pte
*pte
;
4059 pte
= pfn_to_dma_pte(dmar_domain
, iova
>> VTD_PAGE_SHIFT
, 0);
4061 phys
= dma_pte_addr(pte
);
4066 static int intel_iommu_domain_has_cap(struct iommu_domain
*domain
,
4069 struct dmar_domain
*dmar_domain
= domain
->priv
;
4071 if (cap
== IOMMU_CAP_CACHE_COHERENCY
)
4072 return dmar_domain
->iommu_snooping
;
4073 if (cap
== IOMMU_CAP_INTR_REMAP
)
4074 return intr_remapping_enabled
;
4080 * Group numbers are arbitrary. Device with the same group number
4081 * indicate the iommu cannot differentiate between them. To avoid
4082 * tracking used groups we just use the seg|bus|devfn of the lowest
4083 * level we're able to differentiate devices
4085 static int intel_iommu_device_group(struct device
*dev
, unsigned int *groupid
)
4087 struct pci_dev
*pdev
= to_pci_dev(dev
);
4088 struct pci_dev
*bridge
;
4098 if (iommu_no_mapping(dev
))
4101 id
.pci
.segment
= pci_domain_nr(pdev
->bus
);
4102 id
.pci
.bus
= pdev
->bus
->number
;
4103 id
.pci
.devfn
= pdev
->devfn
;
4105 if (!device_to_iommu(id
.pci
.segment
, id
.pci
.bus
, id
.pci
.devfn
))
4108 bridge
= pci_find_upstream_pcie_bridge(pdev
);
4110 if (pci_is_pcie(bridge
)) {
4111 id
.pci
.bus
= bridge
->subordinate
->number
;
4114 id
.pci
.bus
= bridge
->bus
->number
;
4115 id
.pci
.devfn
= bridge
->devfn
;
4119 if (!pdev
->is_virtfn
&& iommu_group_mf
)
4120 id
.pci
.devfn
= PCI_DEVFN(PCI_SLOT(id
.pci
.devfn
), 0);
4122 *groupid
= id
.group
;
4127 static struct iommu_ops intel_iommu_ops
= {
4128 .domain_init
= intel_iommu_domain_init
,
4129 .domain_destroy
= intel_iommu_domain_destroy
,
4130 .attach_dev
= intel_iommu_attach_device
,
4131 .detach_dev
= intel_iommu_detach_device
,
4132 .map
= intel_iommu_map
,
4133 .unmap
= intel_iommu_unmap
,
4134 .iova_to_phys
= intel_iommu_iova_to_phys
,
4135 .domain_has_cap
= intel_iommu_domain_has_cap
,
4136 .device_group
= intel_iommu_device_group
,
4137 .pgsize_bitmap
= INTEL_IOMMU_PGSIZES
,
4140 static void __devinit
quirk_iommu_rwbf(struct pci_dev
*dev
)
4143 * Mobile 4 Series Chipset neglects to set RWBF capability,
4146 printk(KERN_INFO
"DMAR: Forcing write-buffer flush capability\n");
4149 /* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */
4150 if (dev
->revision
== 0x07) {
4151 printk(KERN_INFO
"DMAR: Disabling IOMMU for graphics on this chipset\n");
4156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2a40, quirk_iommu_rwbf
);
4159 #define GGC_MEMORY_SIZE_MASK (0xf << 8)
4160 #define GGC_MEMORY_SIZE_NONE (0x0 << 8)
4161 #define GGC_MEMORY_SIZE_1M (0x1 << 8)
4162 #define GGC_MEMORY_SIZE_2M (0x3 << 8)
4163 #define GGC_MEMORY_VT_ENABLED (0x8 << 8)
4164 #define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
4165 #define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
4166 #define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
4168 static void __devinit
quirk_calpella_no_shadow_gtt(struct pci_dev
*dev
)
4172 if (pci_read_config_word(dev
, GGC
, &ggc
))
4175 if (!(ggc
& GGC_MEMORY_VT_ENABLED
)) {
4176 printk(KERN_INFO
"DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
4178 } else if (dmar_map_gfx
) {
4179 /* we have to ensure the gfx device is idle before we flush */
4180 printk(KERN_INFO
"DMAR: Disabling batched IOTLB flush on Ironlake\n");
4181 intel_iommu_strict
= 1;
4184 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x0040, quirk_calpella_no_shadow_gtt
);
4185 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x0044, quirk_calpella_no_shadow_gtt
);
4186 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x0062, quirk_calpella_no_shadow_gtt
);
4187 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x006a, quirk_calpella_no_shadow_gtt
);
4189 /* On Tylersburg chipsets, some BIOSes have been known to enable the
4190 ISOCH DMAR unit for the Azalia sound device, but not give it any
4191 TLB entries, which causes it to deadlock. Check for that. We do
4192 this in a function called from init_dmars(), instead of in a PCI
4193 quirk, because we don't want to print the obnoxious "BIOS broken"
4194 message if VT-d is actually disabled.
4196 static void __init
check_tylersburg_isoch(void)
4198 struct pci_dev
*pdev
;
4199 uint32_t vtisochctrl
;
4201 /* If there's no Azalia in the system anyway, forget it. */
4202 pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
, 0x3a3e, NULL
);
4207 /* System Management Registers. Might be hidden, in which case
4208 we can't do the sanity check. But that's OK, because the
4209 known-broken BIOSes _don't_ actually hide it, so far. */
4210 pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
, 0x342e, NULL
);
4214 if (pci_read_config_dword(pdev
, 0x188, &vtisochctrl
)) {
4221 /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
4222 if (vtisochctrl
& 1)
4225 /* Drop all bits other than the number of TLB entries */
4226 vtisochctrl
&= 0x1c;
4228 /* If we have the recommended number of TLB entries (16), fine. */
4229 if (vtisochctrl
== 0x10)
4232 /* Zero TLB entries? You get to ride the short bus to school. */
4234 WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
4235 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
4236 dmi_get_system_info(DMI_BIOS_VENDOR
),
4237 dmi_get_system_info(DMI_BIOS_VERSION
),
4238 dmi_get_system_info(DMI_PRODUCT_VERSION
));
4239 iommu_identity_mapping
|= IDENTMAP_AZALIA
;
4243 printk(KERN_WARNING
"DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",