2 * omap iommu: tlb and pagetable primitives
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/err.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/platform_device.h>
20 #include <linux/iommu.h>
21 #include <linux/omap-iommu.h>
22 #include <linux/mutex.h>
23 #include <linux/spinlock.h>
25 #include <linux/pm_runtime.h>
27 #include <asm/cacheflush.h>
29 #include <linux/platform_data/iommu-omap.h>
31 #include "omap-iopgtable.h"
32 #include "omap-iommu.h"
34 #define for_each_iotlb_cr(obj, n, __i, cr) \
36 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
39 /* bitmap of the page sizes currently supported */
40 #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
43 * struct omap_iommu_domain - omap iommu domain
44 * @pgtable: the page table
45 * @iommu_dev: an omap iommu device attached to this domain. only a single
46 * iommu device can be attached for now.
47 * @dev: Device using this domain.
48 * @lock: domain lock, should be taken when attaching/detaching
50 struct omap_iommu_domain
{
52 struct omap_iommu
*iommu_dev
;
57 #define MMU_LOCK_BASE_SHIFT 10
58 #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
59 #define MMU_LOCK_BASE(x) \
60 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
62 #define MMU_LOCK_VICT_SHIFT 4
63 #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
64 #define MMU_LOCK_VICT(x) \
65 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
72 /* accommodate the difference between omap1 and omap2/3 */
73 static const struct iommu_functions
*arch_iommu
;
75 static struct platform_driver omap_iommu_driver
;
76 static struct kmem_cache
*iopte_cachep
;
79 * omap_install_iommu_arch - Install archtecure specific iommu functions
80 * @ops: a pointer to architecture specific iommu functions
82 * There are several kind of iommu algorithm(tlb, pagetable) among
83 * omap series. This interface installs such an iommu algorighm.
85 int omap_install_iommu_arch(const struct iommu_functions
*ops
)
93 EXPORT_SYMBOL_GPL(omap_install_iommu_arch
);
96 * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions
97 * @ops: a pointer to architecture specific iommu functions
99 * This interface uninstalls the iommu algorighm installed previously.
101 void omap_uninstall_iommu_arch(const struct iommu_functions
*ops
)
103 if (arch_iommu
!= ops
)
104 pr_err("%s: not your arch\n", __func__
);
108 EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch
);
111 * omap_iommu_save_ctx - Save registers for pm off-mode support
112 * @dev: client device
114 void omap_iommu_save_ctx(struct device
*dev
)
116 struct omap_iommu
*obj
= dev_to_omap_iommu(dev
);
118 arch_iommu
->save_ctx(obj
);
120 EXPORT_SYMBOL_GPL(omap_iommu_save_ctx
);
123 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
124 * @dev: client device
126 void omap_iommu_restore_ctx(struct device
*dev
)
128 struct omap_iommu
*obj
= dev_to_omap_iommu(dev
);
130 arch_iommu
->restore_ctx(obj
);
132 EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx
);
135 * omap_iommu_arch_version - Return running iommu arch version
137 u32
omap_iommu_arch_version(void)
139 return arch_iommu
->version
;
141 EXPORT_SYMBOL_GPL(omap_iommu_arch_version
);
143 static int iommu_enable(struct omap_iommu
*obj
)
146 struct platform_device
*pdev
= to_platform_device(obj
->dev
);
147 struct iommu_platform_data
*pdata
= pdev
->dev
.platform_data
;
155 if (pdata
->deassert_reset
) {
156 err
= pdata
->deassert_reset(pdev
, pdata
->reset_name
);
158 dev_err(obj
->dev
, "deassert_reset failed: %d\n", err
);
163 pm_runtime_get_sync(obj
->dev
);
165 err
= arch_iommu
->enable(obj
);
170 static void iommu_disable(struct omap_iommu
*obj
)
172 struct platform_device
*pdev
= to_platform_device(obj
->dev
);
173 struct iommu_platform_data
*pdata
= pdev
->dev
.platform_data
;
178 arch_iommu
->disable(obj
);
180 pm_runtime_put_sync(obj
->dev
);
182 if (pdata
->assert_reset
)
183 pdata
->assert_reset(pdev
, pdata
->reset_name
);
189 void omap_iotlb_cr_to_e(struct cr_regs
*cr
, struct iotlb_entry
*e
)
193 arch_iommu
->cr_to_e(cr
, e
);
195 EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e
);
197 static inline int iotlb_cr_valid(struct cr_regs
*cr
)
202 return arch_iommu
->cr_valid(cr
);
205 static inline struct cr_regs
*iotlb_alloc_cr(struct omap_iommu
*obj
,
206 struct iotlb_entry
*e
)
211 return arch_iommu
->alloc_cr(obj
, e
);
214 static u32
iotlb_cr_to_virt(struct cr_regs
*cr
)
216 return arch_iommu
->cr_to_virt(cr
);
219 static u32
get_iopte_attr(struct iotlb_entry
*e
)
221 return arch_iommu
->get_pte_attr(e
);
224 static u32
iommu_report_fault(struct omap_iommu
*obj
, u32
*da
)
226 return arch_iommu
->fault_isr(obj
, da
);
229 static void iotlb_lock_get(struct omap_iommu
*obj
, struct iotlb_lock
*l
)
233 val
= iommu_read_reg(obj
, MMU_LOCK
);
235 l
->base
= MMU_LOCK_BASE(val
);
236 l
->vict
= MMU_LOCK_VICT(val
);
240 static void iotlb_lock_set(struct omap_iommu
*obj
, struct iotlb_lock
*l
)
244 val
= (l
->base
<< MMU_LOCK_BASE_SHIFT
);
245 val
|= (l
->vict
<< MMU_LOCK_VICT_SHIFT
);
247 iommu_write_reg(obj
, val
, MMU_LOCK
);
250 static void iotlb_read_cr(struct omap_iommu
*obj
, struct cr_regs
*cr
)
252 arch_iommu
->tlb_read_cr(obj
, cr
);
255 static void iotlb_load_cr(struct omap_iommu
*obj
, struct cr_regs
*cr
)
257 arch_iommu
->tlb_load_cr(obj
, cr
);
259 iommu_write_reg(obj
, 1, MMU_FLUSH_ENTRY
);
260 iommu_write_reg(obj
, 1, MMU_LD_TLB
);
264 * iotlb_dump_cr - Dump an iommu tlb entry into buf
266 * @cr: contents of cam and ram register
267 * @buf: output buffer
269 static inline ssize_t
iotlb_dump_cr(struct omap_iommu
*obj
, struct cr_regs
*cr
,
274 return arch_iommu
->dump_cr(obj
, cr
, buf
);
277 /* only used in iotlb iteration for-loop */
278 static struct cr_regs
__iotlb_read_cr(struct omap_iommu
*obj
, int n
)
283 iotlb_lock_get(obj
, &l
);
285 iotlb_lock_set(obj
, &l
);
286 iotlb_read_cr(obj
, &cr
);
292 * load_iotlb_entry - Set an iommu tlb entry
294 * @e: an iommu tlb entry info
296 #ifdef PREFETCH_IOTLB
297 static int load_iotlb_entry(struct omap_iommu
*obj
, struct iotlb_entry
*e
)
303 if (!obj
|| !obj
->nr_tlb_entries
|| !e
)
306 pm_runtime_get_sync(obj
->dev
);
308 iotlb_lock_get(obj
, &l
);
309 if (l
.base
== obj
->nr_tlb_entries
) {
310 dev_warn(obj
->dev
, "%s: preserve entries full\n", __func__
);
318 for_each_iotlb_cr(obj
, obj
->nr_tlb_entries
, i
, tmp
)
319 if (!iotlb_cr_valid(&tmp
))
322 if (i
== obj
->nr_tlb_entries
) {
323 dev_dbg(obj
->dev
, "%s: full: no entry\n", __func__
);
328 iotlb_lock_get(obj
, &l
);
331 iotlb_lock_set(obj
, &l
);
334 cr
= iotlb_alloc_cr(obj
, e
);
336 pm_runtime_put_sync(obj
->dev
);
340 iotlb_load_cr(obj
, cr
);
345 /* increment victim for next tlb load */
346 if (++l
.vict
== obj
->nr_tlb_entries
)
348 iotlb_lock_set(obj
, &l
);
350 pm_runtime_put_sync(obj
->dev
);
354 #else /* !PREFETCH_IOTLB */
356 static int load_iotlb_entry(struct omap_iommu
*obj
, struct iotlb_entry
*e
)
361 #endif /* !PREFETCH_IOTLB */
363 static int prefetch_iotlb_entry(struct omap_iommu
*obj
, struct iotlb_entry
*e
)
365 return load_iotlb_entry(obj
, e
);
369 * flush_iotlb_page - Clear an iommu tlb entry
371 * @da: iommu device virtual address
373 * Clear an iommu tlb entry which includes 'da' address.
375 static void flush_iotlb_page(struct omap_iommu
*obj
, u32 da
)
380 pm_runtime_get_sync(obj
->dev
);
382 for_each_iotlb_cr(obj
, obj
->nr_tlb_entries
, i
, cr
) {
386 if (!iotlb_cr_valid(&cr
))
389 start
= iotlb_cr_to_virt(&cr
);
390 bytes
= iopgsz_to_bytes(cr
.cam
& 3);
392 if ((start
<= da
) && (da
< start
+ bytes
)) {
393 dev_dbg(obj
->dev
, "%s: %08x<=%08x(%x)\n",
394 __func__
, start
, da
, bytes
);
395 iotlb_load_cr(obj
, &cr
);
396 iommu_write_reg(obj
, 1, MMU_FLUSH_ENTRY
);
399 pm_runtime_put_sync(obj
->dev
);
401 if (i
== obj
->nr_tlb_entries
)
402 dev_dbg(obj
->dev
, "%s: no page for %08x\n", __func__
, da
);
406 * flush_iotlb_all - Clear all iommu tlb entries
409 static void flush_iotlb_all(struct omap_iommu
*obj
)
413 pm_runtime_get_sync(obj
->dev
);
417 iotlb_lock_set(obj
, &l
);
419 iommu_write_reg(obj
, 1, MMU_GFLUSH
);
421 pm_runtime_put_sync(obj
->dev
);
424 #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
426 ssize_t
omap_iommu_dump_ctx(struct omap_iommu
*obj
, char *buf
, ssize_t bytes
)
431 pm_runtime_get_sync(obj
->dev
);
433 bytes
= arch_iommu
->dump_ctx(obj
, buf
, bytes
);
435 pm_runtime_put_sync(obj
->dev
);
439 EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx
);
442 __dump_tlb_entries(struct omap_iommu
*obj
, struct cr_regs
*crs
, int num
)
445 struct iotlb_lock saved
;
447 struct cr_regs
*p
= crs
;
449 pm_runtime_get_sync(obj
->dev
);
450 iotlb_lock_get(obj
, &saved
);
452 for_each_iotlb_cr(obj
, num
, i
, tmp
) {
453 if (!iotlb_cr_valid(&tmp
))
458 iotlb_lock_set(obj
, &saved
);
459 pm_runtime_put_sync(obj
->dev
);
465 * omap_dump_tlb_entries - dump cr arrays to given buffer
467 * @buf: output buffer
469 size_t omap_dump_tlb_entries(struct omap_iommu
*obj
, char *buf
, ssize_t bytes
)
475 num
= bytes
/ sizeof(*cr
);
476 num
= min(obj
->nr_tlb_entries
, num
);
478 cr
= kcalloc(num
, sizeof(*cr
), GFP_KERNEL
);
482 num
= __dump_tlb_entries(obj
, cr
, num
);
483 for (i
= 0; i
< num
; i
++)
484 p
+= iotlb_dump_cr(obj
, cr
+ i
, p
);
489 EXPORT_SYMBOL_GPL(omap_dump_tlb_entries
);
491 int omap_foreach_iommu_device(void *data
, int (*fn
)(struct device
*, void *))
493 return driver_for_each_device(&omap_iommu_driver
.driver
,
496 EXPORT_SYMBOL_GPL(omap_foreach_iommu_device
);
498 #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
501 * H/W pagetable operations
503 static void flush_iopgd_range(u32
*first
, u32
*last
)
505 /* FIXME: L2 cache should be taken care of if it exists */
507 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
509 first
+= L1_CACHE_BYTES
/ sizeof(*first
);
510 } while (first
<= last
);
513 static void flush_iopte_range(u32
*first
, u32
*last
)
515 /* FIXME: L2 cache should be taken care of if it exists */
517 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
519 first
+= L1_CACHE_BYTES
/ sizeof(*first
);
520 } while (first
<= last
);
523 static void iopte_free(u32
*iopte
)
525 /* Note: freed iopte's must be clean ready for re-use */
526 kmem_cache_free(iopte_cachep
, iopte
);
529 static u32
*iopte_alloc(struct omap_iommu
*obj
, u32
*iopgd
, u32 da
)
533 /* a table has already existed */
538 * do the allocation outside the page table lock
540 spin_unlock(&obj
->page_table_lock
);
541 iopte
= kmem_cache_zalloc(iopte_cachep
, GFP_KERNEL
);
542 spin_lock(&obj
->page_table_lock
);
546 return ERR_PTR(-ENOMEM
);
548 *iopgd
= virt_to_phys(iopte
) | IOPGD_TABLE
;
549 flush_iopgd_range(iopgd
, iopgd
);
551 dev_vdbg(obj
->dev
, "%s: a new pte:%p\n", __func__
, iopte
);
553 /* We raced, free the reduniovant table */
558 iopte
= iopte_offset(iopgd
, da
);
561 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
562 __func__
, da
, iopgd
, *iopgd
, iopte
, *iopte
);
567 static int iopgd_alloc_section(struct omap_iommu
*obj
, u32 da
, u32 pa
, u32 prot
)
569 u32
*iopgd
= iopgd_offset(obj
, da
);
571 if ((da
| pa
) & ~IOSECTION_MASK
) {
572 dev_err(obj
->dev
, "%s: %08x:%08x should aligned on %08lx\n",
573 __func__
, da
, pa
, IOSECTION_SIZE
);
577 *iopgd
= (pa
& IOSECTION_MASK
) | prot
| IOPGD_SECTION
;
578 flush_iopgd_range(iopgd
, iopgd
);
582 static int iopgd_alloc_super(struct omap_iommu
*obj
, u32 da
, u32 pa
, u32 prot
)
584 u32
*iopgd
= iopgd_offset(obj
, da
);
587 if ((da
| pa
) & ~IOSUPER_MASK
) {
588 dev_err(obj
->dev
, "%s: %08x:%08x should aligned on %08lx\n",
589 __func__
, da
, pa
, IOSUPER_SIZE
);
593 for (i
= 0; i
< 16; i
++)
594 *(iopgd
+ i
) = (pa
& IOSUPER_MASK
) | prot
| IOPGD_SUPER
;
595 flush_iopgd_range(iopgd
, iopgd
+ 15);
599 static int iopte_alloc_page(struct omap_iommu
*obj
, u32 da
, u32 pa
, u32 prot
)
601 u32
*iopgd
= iopgd_offset(obj
, da
);
602 u32
*iopte
= iopte_alloc(obj
, iopgd
, da
);
605 return PTR_ERR(iopte
);
607 *iopte
= (pa
& IOPAGE_MASK
) | prot
| IOPTE_SMALL
;
608 flush_iopte_range(iopte
, iopte
);
610 dev_vdbg(obj
->dev
, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
611 __func__
, da
, pa
, iopte
, *iopte
);
616 static int iopte_alloc_large(struct omap_iommu
*obj
, u32 da
, u32 pa
, u32 prot
)
618 u32
*iopgd
= iopgd_offset(obj
, da
);
619 u32
*iopte
= iopte_alloc(obj
, iopgd
, da
);
622 if ((da
| pa
) & ~IOLARGE_MASK
) {
623 dev_err(obj
->dev
, "%s: %08x:%08x should aligned on %08lx\n",
624 __func__
, da
, pa
, IOLARGE_SIZE
);
629 return PTR_ERR(iopte
);
631 for (i
= 0; i
< 16; i
++)
632 *(iopte
+ i
) = (pa
& IOLARGE_MASK
) | prot
| IOPTE_LARGE
;
633 flush_iopte_range(iopte
, iopte
+ 15);
638 iopgtable_store_entry_core(struct omap_iommu
*obj
, struct iotlb_entry
*e
)
640 int (*fn
)(struct omap_iommu
*, u32
, u32
, u32
);
648 case MMU_CAM_PGSZ_16M
:
649 fn
= iopgd_alloc_super
;
651 case MMU_CAM_PGSZ_1M
:
652 fn
= iopgd_alloc_section
;
654 case MMU_CAM_PGSZ_64K
:
655 fn
= iopte_alloc_large
;
657 case MMU_CAM_PGSZ_4K
:
658 fn
= iopte_alloc_page
;
666 prot
= get_iopte_attr(e
);
668 spin_lock(&obj
->page_table_lock
);
669 err
= fn(obj
, e
->da
, e
->pa
, prot
);
670 spin_unlock(&obj
->page_table_lock
);
676 * omap_iopgtable_store_entry - Make an iommu pte entry
678 * @e: an iommu tlb entry info
680 int omap_iopgtable_store_entry(struct omap_iommu
*obj
, struct iotlb_entry
*e
)
684 flush_iotlb_page(obj
, e
->da
);
685 err
= iopgtable_store_entry_core(obj
, e
);
687 prefetch_iotlb_entry(obj
, e
);
690 EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry
);
693 * iopgtable_lookup_entry - Lookup an iommu pte entry
695 * @da: iommu device virtual address
696 * @ppgd: iommu pgd entry pointer to be returned
697 * @ppte: iommu pte entry pointer to be returned
700 iopgtable_lookup_entry(struct omap_iommu
*obj
, u32 da
, u32
**ppgd
, u32
**ppte
)
702 u32
*iopgd
, *iopte
= NULL
;
704 iopgd
= iopgd_offset(obj
, da
);
708 if (iopgd_is_table(*iopgd
))
709 iopte
= iopte_offset(iopgd
, da
);
715 static size_t iopgtable_clear_entry_core(struct omap_iommu
*obj
, u32 da
)
718 u32
*iopgd
= iopgd_offset(obj
, da
);
724 if (iopgd_is_table(*iopgd
)) {
726 u32
*iopte
= iopte_offset(iopgd
, da
);
729 if (*iopte
& IOPTE_LARGE
) {
731 /* rewind to the 1st entry */
732 iopte
= iopte_offset(iopgd
, (da
& IOLARGE_MASK
));
735 memset(iopte
, 0, nent
* sizeof(*iopte
));
736 flush_iopte_range(iopte
, iopte
+ (nent
- 1) * sizeof(*iopte
));
739 * do table walk to check if this table is necessary or not
741 iopte
= iopte_offset(iopgd
, 0);
742 for (i
= 0; i
< PTRS_PER_IOPTE
; i
++)
747 nent
= 1; /* for the next L1 entry */
750 if ((*iopgd
& IOPGD_SUPER
) == IOPGD_SUPER
) {
752 /* rewind to the 1st entry */
753 iopgd
= iopgd_offset(obj
, (da
& IOSUPER_MASK
));
757 memset(iopgd
, 0, nent
* sizeof(*iopgd
));
758 flush_iopgd_range(iopgd
, iopgd
+ (nent
- 1) * sizeof(*iopgd
));
764 * iopgtable_clear_entry - Remove an iommu pte entry
766 * @da: iommu device virtual address
768 static size_t iopgtable_clear_entry(struct omap_iommu
*obj
, u32 da
)
772 spin_lock(&obj
->page_table_lock
);
774 bytes
= iopgtable_clear_entry_core(obj
, da
);
775 flush_iotlb_page(obj
, da
);
777 spin_unlock(&obj
->page_table_lock
);
782 static void iopgtable_clear_entry_all(struct omap_iommu
*obj
)
786 spin_lock(&obj
->page_table_lock
);
788 for (i
= 0; i
< PTRS_PER_IOPGD
; i
++) {
792 da
= i
<< IOPGD_SHIFT
;
793 iopgd
= iopgd_offset(obj
, da
);
798 if (iopgd_is_table(*iopgd
))
799 iopte_free(iopte_offset(iopgd
, 0));
802 flush_iopgd_range(iopgd
, iopgd
);
805 flush_iotlb_all(obj
);
807 spin_unlock(&obj
->page_table_lock
);
811 * Device IOMMU generic operations
813 static irqreturn_t
iommu_fault_handler(int irq
, void *data
)
817 struct omap_iommu
*obj
= data
;
818 struct iommu_domain
*domain
= obj
->domain
;
823 errs
= iommu_report_fault(obj
, &da
);
827 /* Fault callback or TLB/PTE Dynamic loading */
828 if (!report_iommu_fault(domain
, obj
->dev
, da
, 0))
833 iopgd
= iopgd_offset(obj
, da
);
835 if (!iopgd_is_table(*iopgd
)) {
836 dev_err(obj
->dev
, "%s: errs:0x%08x da:0x%08x pgd:0x%p "
837 "*pgd:px%08x\n", obj
->name
, errs
, da
, iopgd
, *iopgd
);
841 iopte
= iopte_offset(iopgd
, da
);
843 dev_err(obj
->dev
, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x "
844 "pte:0x%p *pte:0x%08x\n", obj
->name
, errs
, da
, iopgd
, *iopgd
,
850 static int device_match_by_alias(struct device
*dev
, void *data
)
852 struct omap_iommu
*obj
= to_iommu(dev
);
853 const char *name
= data
;
855 pr_debug("%s: %s %s\n", __func__
, obj
->name
, name
);
857 return strcmp(obj
->name
, name
) == 0;
861 * omap_iommu_attach() - attach iommu device to an iommu domain
862 * @name: name of target omap iommu device
865 static struct omap_iommu
*omap_iommu_attach(const char *name
, u32
*iopgd
)
869 struct omap_iommu
*obj
;
871 dev
= driver_find_device(&omap_iommu_driver
.driver
, NULL
,
873 device_match_by_alias
);
879 spin_lock(&obj
->iommu_lock
);
881 /* an iommu device can only be attached once */
882 if (++obj
->refcount
> 1) {
883 dev_err(dev
, "%s: already attached!\n", obj
->name
);
889 err
= iommu_enable(obj
);
892 flush_iotlb_all(obj
);
894 if (!try_module_get(obj
->owner
))
897 spin_unlock(&obj
->iommu_lock
);
899 dev_dbg(obj
->dev
, "%s: %s\n", __func__
, obj
->name
);
903 if (obj
->refcount
== 1)
907 spin_unlock(&obj
->iommu_lock
);
912 * omap_iommu_detach - release iommu device
915 static void omap_iommu_detach(struct omap_iommu
*obj
)
917 if (!obj
|| IS_ERR(obj
))
920 spin_lock(&obj
->iommu_lock
);
922 if (--obj
->refcount
== 0)
925 module_put(obj
->owner
);
929 spin_unlock(&obj
->iommu_lock
);
931 dev_dbg(obj
->dev
, "%s: %s\n", __func__
, obj
->name
);
935 * OMAP Device MMU(IOMMU) detection
937 static int __devinit
omap_iommu_probe(struct platform_device
*pdev
)
941 struct omap_iommu
*obj
;
942 struct resource
*res
;
943 struct iommu_platform_data
*pdata
= pdev
->dev
.platform_data
;
945 obj
= kzalloc(sizeof(*obj
) + MMU_REG_SIZE
, GFP_KERNEL
);
949 obj
->nr_tlb_entries
= pdata
->nr_tlb_entries
;
950 obj
->name
= pdata
->name
;
951 obj
->dev
= &pdev
->dev
;
952 obj
->ctx
= (void *)obj
+ sizeof(*obj
);
953 obj
->da_start
= pdata
->da_start
;
954 obj
->da_end
= pdata
->da_end
;
956 spin_lock_init(&obj
->iommu_lock
);
957 mutex_init(&obj
->mmap_lock
);
958 spin_lock_init(&obj
->page_table_lock
);
959 INIT_LIST_HEAD(&obj
->mmap
);
961 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
967 res
= request_mem_region(res
->start
, resource_size(res
),
968 dev_name(&pdev
->dev
));
974 obj
->regbase
= ioremap(res
->start
, resource_size(res
));
980 irq
= platform_get_irq(pdev
, 0);
985 err
= request_irq(irq
, iommu_fault_handler
, IRQF_SHARED
,
986 dev_name(&pdev
->dev
), obj
);
989 platform_set_drvdata(pdev
, obj
);
991 pm_runtime_irq_safe(obj
->dev
);
992 pm_runtime_enable(obj
->dev
);
994 dev_info(&pdev
->dev
, "%s registered\n", obj
->name
);
998 iounmap(obj
->regbase
);
1000 release_mem_region(res
->start
, resource_size(res
));
1006 static int __devexit
omap_iommu_remove(struct platform_device
*pdev
)
1009 struct resource
*res
;
1010 struct omap_iommu
*obj
= platform_get_drvdata(pdev
);
1012 platform_set_drvdata(pdev
, NULL
);
1014 iopgtable_clear_entry_all(obj
);
1016 irq
= platform_get_irq(pdev
, 0);
1018 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1019 release_mem_region(res
->start
, resource_size(res
));
1020 iounmap(obj
->regbase
);
1022 pm_runtime_disable(obj
->dev
);
1024 dev_info(&pdev
->dev
, "%s removed\n", obj
->name
);
1029 static struct platform_driver omap_iommu_driver
= {
1030 .probe
= omap_iommu_probe
,
1031 .remove
= __devexit_p(omap_iommu_remove
),
1033 .name
= "omap-iommu",
1037 static void iopte_cachep_ctor(void *iopte
)
1039 clean_dcache_area(iopte
, IOPTE_TABLE_SIZE
);
1042 static u32
iotlb_init_entry(struct iotlb_entry
*e
, u32 da
, u32 pa
,
1045 memset(e
, 0, sizeof(*e
));
1050 /* FIXME: add OMAP1 support */
1051 e
->pgsz
= flags
& MMU_CAM_PGSZ_MASK
;
1052 e
->endian
= flags
& MMU_RAM_ENDIAN_MASK
;
1053 e
->elsz
= flags
& MMU_RAM_ELSZ_MASK
;
1054 e
->mixed
= flags
& MMU_RAM_MIXED_MASK
;
1056 return iopgsz_to_bytes(e
->pgsz
);
1059 static int omap_iommu_map(struct iommu_domain
*domain
, unsigned long da
,
1060 phys_addr_t pa
, size_t bytes
, int prot
)
1062 struct omap_iommu_domain
*omap_domain
= domain
->priv
;
1063 struct omap_iommu
*oiommu
= omap_domain
->iommu_dev
;
1064 struct device
*dev
= oiommu
->dev
;
1065 struct iotlb_entry e
;
1069 /* we only support mapping a single iommu page for now */
1070 omap_pgsz
= bytes_to_iopgsz(bytes
);
1071 if (omap_pgsz
< 0) {
1072 dev_err(dev
, "invalid size to map: %d\n", bytes
);
1076 dev_dbg(dev
, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da
, pa
, bytes
);
1078 flags
= omap_pgsz
| prot
;
1080 iotlb_init_entry(&e
, da
, pa
, flags
);
1082 ret
= omap_iopgtable_store_entry(oiommu
, &e
);
1084 dev_err(dev
, "omap_iopgtable_store_entry failed: %d\n", ret
);
1089 static size_t omap_iommu_unmap(struct iommu_domain
*domain
, unsigned long da
,
1092 struct omap_iommu_domain
*omap_domain
= domain
->priv
;
1093 struct omap_iommu
*oiommu
= omap_domain
->iommu_dev
;
1094 struct device
*dev
= oiommu
->dev
;
1096 dev_dbg(dev
, "unmapping da 0x%lx size %u\n", da
, size
);
1098 return iopgtable_clear_entry(oiommu
, da
);
1102 omap_iommu_attach_dev(struct iommu_domain
*domain
, struct device
*dev
)
1104 struct omap_iommu_domain
*omap_domain
= domain
->priv
;
1105 struct omap_iommu
*oiommu
;
1106 struct omap_iommu_arch_data
*arch_data
= dev
->archdata
.iommu
;
1109 spin_lock(&omap_domain
->lock
);
1111 /* only a single device is supported per domain for now */
1112 if (omap_domain
->iommu_dev
) {
1113 dev_err(dev
, "iommu domain is already attached\n");
1118 /* get a handle to and enable the omap iommu */
1119 oiommu
= omap_iommu_attach(arch_data
->name
, omap_domain
->pgtable
);
1120 if (IS_ERR(oiommu
)) {
1121 ret
= PTR_ERR(oiommu
);
1122 dev_err(dev
, "can't get omap iommu: %d\n", ret
);
1126 omap_domain
->iommu_dev
= arch_data
->iommu_dev
= oiommu
;
1127 omap_domain
->dev
= dev
;
1128 oiommu
->domain
= domain
;
1131 spin_unlock(&omap_domain
->lock
);
1135 static void _omap_iommu_detach_dev(struct omap_iommu_domain
*omap_domain
,
1138 struct omap_iommu
*oiommu
= dev_to_omap_iommu(dev
);
1139 struct omap_iommu_arch_data
*arch_data
= dev
->archdata
.iommu
;
1141 /* only a single device is supported per domain for now */
1142 if (omap_domain
->iommu_dev
!= oiommu
) {
1143 dev_err(dev
, "invalid iommu device\n");
1147 iopgtable_clear_entry_all(oiommu
);
1149 omap_iommu_detach(oiommu
);
1151 omap_domain
->iommu_dev
= arch_data
->iommu_dev
= NULL
;
1152 omap_domain
->dev
= NULL
;
1155 static void omap_iommu_detach_dev(struct iommu_domain
*domain
,
1158 struct omap_iommu_domain
*omap_domain
= domain
->priv
;
1160 spin_lock(&omap_domain
->lock
);
1161 _omap_iommu_detach_dev(omap_domain
, dev
);
1162 spin_unlock(&omap_domain
->lock
);
1165 static int omap_iommu_domain_init(struct iommu_domain
*domain
)
1167 struct omap_iommu_domain
*omap_domain
;
1169 omap_domain
= kzalloc(sizeof(*omap_domain
), GFP_KERNEL
);
1171 pr_err("kzalloc failed\n");
1175 omap_domain
->pgtable
= kzalloc(IOPGD_TABLE_SIZE
, GFP_KERNEL
);
1176 if (!omap_domain
->pgtable
) {
1177 pr_err("kzalloc failed\n");
1182 * should never fail, but please keep this around to ensure
1183 * we keep the hardware happy
1185 BUG_ON(!IS_ALIGNED((long)omap_domain
->pgtable
, IOPGD_TABLE_SIZE
));
1187 clean_dcache_area(omap_domain
->pgtable
, IOPGD_TABLE_SIZE
);
1188 spin_lock_init(&omap_domain
->lock
);
1190 domain
->priv
= omap_domain
;
1192 domain
->geometry
.aperture_start
= 0;
1193 domain
->geometry
.aperture_end
= (1ULL << 32) - 1;
1194 domain
->geometry
.force_aperture
= true;
1204 static void omap_iommu_domain_destroy(struct iommu_domain
*domain
)
1206 struct omap_iommu_domain
*omap_domain
= domain
->priv
;
1208 domain
->priv
= NULL
;
1211 * An iommu device is still attached
1212 * (currently, only one device can be attached) ?
1214 if (omap_domain
->iommu_dev
)
1215 _omap_iommu_detach_dev(omap_domain
, omap_domain
->dev
);
1217 kfree(omap_domain
->pgtable
);
1221 static phys_addr_t
omap_iommu_iova_to_phys(struct iommu_domain
*domain
,
1224 struct omap_iommu_domain
*omap_domain
= domain
->priv
;
1225 struct omap_iommu
*oiommu
= omap_domain
->iommu_dev
;
1226 struct device
*dev
= oiommu
->dev
;
1228 phys_addr_t ret
= 0;
1230 iopgtable_lookup_entry(oiommu
, da
, &pgd
, &pte
);
1233 if (iopte_is_small(*pte
))
1234 ret
= omap_iommu_translate(*pte
, da
, IOPTE_MASK
);
1235 else if (iopte_is_large(*pte
))
1236 ret
= omap_iommu_translate(*pte
, da
, IOLARGE_MASK
);
1238 dev_err(dev
, "bogus pte 0x%x, da 0x%lx", *pte
, da
);
1240 if (iopgd_is_section(*pgd
))
1241 ret
= omap_iommu_translate(*pgd
, da
, IOSECTION_MASK
);
1242 else if (iopgd_is_super(*pgd
))
1243 ret
= omap_iommu_translate(*pgd
, da
, IOSUPER_MASK
);
1245 dev_err(dev
, "bogus pgd 0x%x, da 0x%lx", *pgd
, da
);
1251 static int omap_iommu_domain_has_cap(struct iommu_domain
*domain
,
1257 static struct iommu_ops omap_iommu_ops
= {
1258 .domain_init
= omap_iommu_domain_init
,
1259 .domain_destroy
= omap_iommu_domain_destroy
,
1260 .attach_dev
= omap_iommu_attach_dev
,
1261 .detach_dev
= omap_iommu_detach_dev
,
1262 .map
= omap_iommu_map
,
1263 .unmap
= omap_iommu_unmap
,
1264 .iova_to_phys
= omap_iommu_iova_to_phys
,
1265 .domain_has_cap
= omap_iommu_domain_has_cap
,
1266 .pgsize_bitmap
= OMAP_IOMMU_PGSIZES
,
1269 static int __init
omap_iommu_init(void)
1271 struct kmem_cache
*p
;
1272 const unsigned long flags
= SLAB_HWCACHE_ALIGN
;
1273 size_t align
= 1 << 10; /* L2 pagetable alignement */
1275 p
= kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE
, align
, flags
,
1281 bus_set_iommu(&platform_bus_type
, &omap_iommu_ops
);
1283 return platform_driver_register(&omap_iommu_driver
);
1285 /* must be ready before omap3isp is probed */
1286 subsys_initcall(omap_iommu_init
);
1288 static void __exit
omap_iommu_exit(void)
1290 kmem_cache_destroy(iopte_cachep
);
1292 platform_driver_unregister(&omap_iommu_driver
);
1294 module_exit(omap_iommu_exit
);
1296 MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
1297 MODULE_ALIAS("platform:omap-iommu");
1298 MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
1299 MODULE_LICENSE("GPL v2");