drivers/iommu/omap-iommu.h

   1 /*
   2  * omap iommu: main structures
   3  *
   4  * Copyright (C) 2008-2009 Nokia Corporation
   5  *
   6  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef _OMAP_IOMMU_H
  14 #define _OMAP_IOMMU_H
  15
  16 #include <linux/bitops.h>
  17
  18 #define for_each_iotlb_cr(obj, n, __i, cr)                              \
  19         for (__i = 0;                                                   \
  20              (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true);   \
  21              __i++)
  22
  23 struct iotlb_entry {
  24         u32 da;
  25         u32 pa;
  26         u32 pgsz, prsvd, valid;
  27         u32 endian, elsz, mixed;
  28 };
  29
  30 struct omap_iommu {
  31         const char      *name;
  32         void __iomem    *regbase;
  33         struct device   *dev;
  34         struct iommu_domain *domain;
  35         struct dentry   *debug_dir;
  36
  37         spinlock_t      iommu_lock;     /* global for this whole object */
  38
  39         /*
  40          * We don't change iopgd for a situation like pgd for a task,
  41          * but share it globally for each iommu.
  42          */
  43         u32             *iopgd;
  44         spinlock_t      page_table_lock; /* protect iopgd */
  45
  46         int             nr_tlb_entries;
  47
  48         void *ctx; /* iommu context: registres saved area */
  49
  50         int has_bus_err_back;
  51 };
  52
  53 struct cr_regs {
  54         u32 cam;
  55         u32 ram;
  56 };
  57
  58 struct iotlb_lock {
  59         short base;
  60         short vict;
  61 };
  62
  63 /**
  64  * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
  65  * @dev: iommu client device
  66  */
  67 static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
  68 {
  69         struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
  70
  71         return arch_data->iommu_dev;
  72 }
  73
  74 /*
  75  * MMU Register offsets
  76  */
  77 #define MMU_REVISION            0x00
  78 #define MMU_IRQSTATUS           0x18
  79 #define MMU_IRQENABLE           0x1c
  80 #define MMU_WALKING_ST          0x40
  81 #define MMU_CNTL                0x44
  82 #define MMU_FAULT_AD            0x48
  83 #define MMU_TTB                 0x4c
  84 #define MMU_LOCK                0x50
  85 #define MMU_LD_TLB              0x54
  86 #define MMU_CAM                 0x58
  87 #define MMU_RAM                 0x5c
  88 #define MMU_GFLUSH              0x60
  89 #define MMU_FLUSH_ENTRY         0x64
  90 #define MMU_READ_CAM            0x68
  91 #define MMU_READ_RAM            0x6c
  92 #define MMU_EMU_FAULT_AD        0x70
  93 #define MMU_GP_REG              0x88
  94
  95 #define MMU_REG_SIZE            256
  96
  97 /*
  98  * MMU Register bit definitions
  99  */
 100 /* IRQSTATUS & IRQENABLE */
 101 #define MMU_IRQ_MULTIHITFAULT   BIT(4)
 102 #define MMU_IRQ_TABLEWALKFAULT  BIT(3)
 103 #define MMU_IRQ_EMUMISS         BIT(2)
 104 #define MMU_IRQ_TRANSLATIONFAULT        BIT(1)
 105 #define MMU_IRQ_TLBMISS         BIT(0)
 106
 107 #define __MMU_IRQ_FAULT         \
 108         (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
 109 #define MMU_IRQ_MASK            \
 110         (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
 111 #define MMU_IRQ_TWL_MASK        (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
 112 #define MMU_IRQ_TLB_MISS_MASK   (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
 113
 114 /* MMU_CNTL */
 115 #define MMU_CNTL_SHIFT          1
 116 #define MMU_CNTL_MASK           (7 << MMU_CNTL_SHIFT)
 117 #define MMU_CNTL_EML_TLB        BIT(3)
 118 #define MMU_CNTL_TWL_EN         BIT(2)
 119 #define MMU_CNTL_MMU_EN         BIT(1)
 120
 121 /* CAM */
 122 #define MMU_CAM_VATAG_SHIFT     12
 123 #define MMU_CAM_VATAG_MASK \
 124         ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
 125 #define MMU_CAM_P               BIT(3)
 126 #define MMU_CAM_V               BIT(2)
 127 #define MMU_CAM_PGSZ_MASK       3
 128 #define MMU_CAM_PGSZ_1M         (0 << 0)
 129 #define MMU_CAM_PGSZ_64K        (1 << 0)
 130 #define MMU_CAM_PGSZ_4K         (2 << 0)
 131 #define MMU_CAM_PGSZ_16M        (3 << 0)
 132
 133 /* RAM */
 134 #define MMU_RAM_PADDR_SHIFT     12
 135 #define MMU_RAM_PADDR_MASK \
 136         ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
 137
 138 #define MMU_RAM_ENDIAN_SHIFT    9
 139 #define MMU_RAM_ENDIAN_MASK     BIT(MMU_RAM_ENDIAN_SHIFT)
 140 #define MMU_RAM_ENDIAN_LITTLE   (0 << MMU_RAM_ENDIAN_SHIFT)
 141 #define MMU_RAM_ENDIAN_BIG      BIT(MMU_RAM_ENDIAN_SHIFT)
 142
 143 #define MMU_RAM_ELSZ_SHIFT      7
 144 #define MMU_RAM_ELSZ_MASK       (3 << MMU_RAM_ELSZ_SHIFT)
 145 #define MMU_RAM_ELSZ_8          (0 << MMU_RAM_ELSZ_SHIFT)
 146 #define MMU_RAM_ELSZ_16         (1 << MMU_RAM_ELSZ_SHIFT)
 147 #define MMU_RAM_ELSZ_32         (2 << MMU_RAM_ELSZ_SHIFT)
 148 #define MMU_RAM_ELSZ_NONE       (3 << MMU_RAM_ELSZ_SHIFT)
 149 #define MMU_RAM_MIXED_SHIFT     6
 150 #define MMU_RAM_MIXED_MASK      BIT(MMU_RAM_MIXED_SHIFT)
 151 #define MMU_RAM_MIXED           MMU_RAM_MIXED_MASK
 152
 153 #define MMU_GP_REG_BUS_ERR_BACK_EN      0x1
 154
 155 #define get_cam_va_mask(pgsz)                           \
 156         (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :    \
 157          ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :    \
 158          ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :    \
 159          ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
 160
 161 /*
 162  * utilities for super page(16MB, 1MB, 64KB and 4KB)
 163  */
 164
 165 #define iopgsz_max(bytes)                       \
 166         (((bytes) >= SZ_16M) ? SZ_16M :         \
 167          ((bytes) >= SZ_1M)  ? SZ_1M  :         \
 168          ((bytes) >= SZ_64K) ? SZ_64K :         \
 169          ((bytes) >= SZ_4K)  ? SZ_4K  : 0)
 170
 171 #define bytes_to_iopgsz(bytes)                          \
 172         (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M :       \
 173          ((bytes) == SZ_1M)  ? MMU_CAM_PGSZ_1M  :       \
 174          ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K :       \
 175          ((bytes) == SZ_4K)  ? MMU_CAM_PGSZ_4K  : -1)
 176
 177 #define iopgsz_to_bytes(iopgsz)                         \
 178         (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M :      \
 179          ((iopgsz) == MMU_CAM_PGSZ_1M)  ? SZ_1M  :      \
 180          ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K :      \
 181          ((iopgsz) == MMU_CAM_PGSZ_4K)  ? SZ_4K  : 0)
 182
 183 #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
 184
 185 /*
 186  * global functions
 187  */
 188
 189 struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n);
 190 void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l);
 191 void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l);
 192
 193 #ifdef CONFIG_OMAP_IOMMU_DEBUG
 194 void omap_iommu_debugfs_init(void);
 195 void omap_iommu_debugfs_exit(void);
 196
 197 void omap_iommu_debugfs_add(struct omap_iommu *obj);
 198 void omap_iommu_debugfs_remove(struct omap_iommu *obj);
 199 #else
 200 static inline void omap_iommu_debugfs_init(void) { }
 201 static inline void omap_iommu_debugfs_exit(void) { }
 202
 203 static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
 204 static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
 205 #endif
 206
 207 /*
 208  * register accessors
 209  */
 210 static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
 211 {
 212         return __raw_readl(obj->regbase + offs);
 213 }
 214
 215 static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
 216 {
 217         __raw_writel(val, obj->regbase + offs);
 218 }
 219
 220 static inline int iotlb_cr_valid(struct cr_regs *cr)
 221 {
 222         if (!cr)
 223                 return -EINVAL;
 224
 225         return cr->cam & MMU_CAM_V;
 226 }
 227
 228 #endif /* _OMAP_IOMMU_H */