drivers/irqchip/Kconfig

   1 config IRQCHIP
   2         def_bool y
   3         depends on OF_IRQ
   4
   5 config ARM_GIC
   6         bool
   7         select IRQ_DOMAIN
   8         select MULTI_IRQ_HANDLER
   9
  10 config GIC_NON_BANKED
  11         bool
  12
  13 config ARM_NVIC
  14         bool
  15         select IRQ_DOMAIN
  16         select GENERIC_IRQ_CHIP
  17
  18 config ARM_VIC
  19         bool
  20         select IRQ_DOMAIN
  21         select MULTI_IRQ_HANDLER
  22
  23 config ARM_VIC_NR
  24         int
  25         default 4 if ARCH_S5PV210
  26         default 3 if ARCH_S5PC100
  27         default 2
  28         depends on ARM_VIC
  29         help
  30           The maximum number of VICs available in the system, for
  31           power management.
  32
  33 config DW_APB_ICTL
  34         bool
  35         select IRQ_DOMAIN
  36
  37 config IMGPDC_IRQ
  38         bool
  39         select GENERIC_IRQ_CHIP
  40         select IRQ_DOMAIN
  41
  42 config CLPS711X_IRQCHIP
  43         bool
  44         depends on ARCH_CLPS711X
  45         select IRQ_DOMAIN
  46         select MULTI_IRQ_HANDLER
  47         select SPARSE_IRQ
  48         default y
  49
  50 config ORION_IRQCHIP
  51         bool
  52         select IRQ_DOMAIN
  53         select MULTI_IRQ_HANDLER
  54
  55 config RENESAS_INTC_IRQPIN
  56         bool
  57         select IRQ_DOMAIN
  58
  59 config RENESAS_IRQC
  60         bool
  61         select IRQ_DOMAIN
  62
  63 config TB10X_IRQC
  64         bool
  65         select IRQ_DOMAIN
  66         select GENERIC_IRQ_CHIP
  67
  68 config VERSATILE_FPGA_IRQ
  69         bool
  70         select IRQ_DOMAIN
  71
  72 config VERSATILE_FPGA_IRQ_NR
  73        int
  74        default 4
  75        depends on VERSATILE_FPGA_IRQ
  76
  77 config XTENSA_MX
  78         bool
  79         select IRQ_DOMAIN
  80
  81 config IRQ_CROSSBAR
  82         bool
  83         help
  84           Support for a CROSSBAR ip that preceeds the main interrupt controller.
  85           The primary irqchip invokes the crossbar's callback which inturn allocates
  86           a free irq and configures the IP. Thus the peripheral interrupts are
  87           routed to one of the free irqchip interrupt lines.