Merge branch 'work.const-qstr' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[deliverable/linux.git] / drivers / irqchip / Kconfig
1 config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
5 config ARM_GIC
6 bool
7 select IRQ_DOMAIN
8 select IRQ_DOMAIN_HIERARCHY
9 select MULTI_IRQ_HANDLER
10
11 config ARM_GIC_PM
12 bool
13 depends on PM
14 select ARM_GIC
15 select PM_CLK
16
17 config ARM_GIC_MAX_NR
18 int
19 default 2 if ARCH_REALVIEW
20 default 1
21
22 config ARM_GIC_V2M
23 bool
24 depends on PCI
25 select ARM_GIC
26 select PCI_MSI
27
28 config GIC_NON_BANKED
29 bool
30
31 config ARM_GIC_V3
32 bool
33 select IRQ_DOMAIN
34 select MULTI_IRQ_HANDLER
35 select IRQ_DOMAIN_HIERARCHY
36 select PARTITION_PERCPU
37
38 config ARM_GIC_V3_ITS
39 bool
40 depends on PCI
41 depends on PCI_MSI
42
43 config ARM_NVIC
44 bool
45 select IRQ_DOMAIN
46 select IRQ_DOMAIN_HIERARCHY
47 select GENERIC_IRQ_CHIP
48
49 config ARM_VIC
50 bool
51 select IRQ_DOMAIN
52 select MULTI_IRQ_HANDLER
53
54 config ARM_VIC_NR
55 int
56 default 4 if ARCH_S5PV210
57 default 2
58 depends on ARM_VIC
59 help
60 The maximum number of VICs available in the system, for
61 power management.
62
63 config ARMADA_370_XP_IRQ
64 bool
65 select GENERIC_IRQ_CHIP
66 select PCI_MSI if PCI
67
68 config ALPINE_MSI
69 bool
70 depends on PCI
71 select PCI_MSI
72 select GENERIC_IRQ_CHIP
73
74 config ATMEL_AIC_IRQ
75 bool
76 select GENERIC_IRQ_CHIP
77 select IRQ_DOMAIN
78 select MULTI_IRQ_HANDLER
79 select SPARSE_IRQ
80
81 config ATMEL_AIC5_IRQ
82 bool
83 select GENERIC_IRQ_CHIP
84 select IRQ_DOMAIN
85 select MULTI_IRQ_HANDLER
86 select SPARSE_IRQ
87
88 config I8259
89 bool
90 select IRQ_DOMAIN
91
92 config BCM6345_L1_IRQ
93 bool
94 select GENERIC_IRQ_CHIP
95 select IRQ_DOMAIN
96
97 config BCM7038_L1_IRQ
98 bool
99 select GENERIC_IRQ_CHIP
100 select IRQ_DOMAIN
101
102 config BCM7120_L2_IRQ
103 bool
104 select GENERIC_IRQ_CHIP
105 select IRQ_DOMAIN
106
107 config BRCMSTB_L2_IRQ
108 bool
109 select GENERIC_IRQ_CHIP
110 select IRQ_DOMAIN
111
112 config DW_APB_ICTL
113 bool
114 select GENERIC_IRQ_CHIP
115 select IRQ_DOMAIN
116
117 config HISILICON_IRQ_MBIGEN
118 bool
119 select ARM_GIC_V3
120 select ARM_GIC_V3_ITS
121
122 config IMGPDC_IRQ
123 bool
124 select GENERIC_IRQ_CHIP
125 select IRQ_DOMAIN
126
127 config IRQ_MIPS_CPU
128 bool
129 select GENERIC_IRQ_CHIP
130 select IRQ_DOMAIN
131
132 config CLPS711X_IRQCHIP
133 bool
134 depends on ARCH_CLPS711X
135 select IRQ_DOMAIN
136 select MULTI_IRQ_HANDLER
137 select SPARSE_IRQ
138 default y
139
140 config OR1K_PIC
141 bool
142 select IRQ_DOMAIN
143
144 config OMAP_IRQCHIP
145 bool
146 select GENERIC_IRQ_CHIP
147 select IRQ_DOMAIN
148
149 config ORION_IRQCHIP
150 bool
151 select IRQ_DOMAIN
152 select MULTI_IRQ_HANDLER
153
154 config PIC32_EVIC
155 bool
156 select GENERIC_IRQ_CHIP
157 select IRQ_DOMAIN
158
159 config RENESAS_INTC_IRQPIN
160 bool
161 select IRQ_DOMAIN
162
163 config RENESAS_IRQC
164 bool
165 select GENERIC_IRQ_CHIP
166 select IRQ_DOMAIN
167
168 config ST_IRQCHIP
169 bool
170 select REGMAP
171 select MFD_SYSCON
172 help
173 Enables SysCfg Controlled IRQs on STi based platforms.
174
175 config TANGO_IRQ
176 bool
177 select IRQ_DOMAIN
178 select GENERIC_IRQ_CHIP
179
180 config TB10X_IRQC
181 bool
182 select IRQ_DOMAIN
183 select GENERIC_IRQ_CHIP
184
185 config TS4800_IRQ
186 tristate "TS-4800 IRQ controller"
187 select IRQ_DOMAIN
188 depends on HAS_IOMEM
189 depends on SOC_IMX51 || COMPILE_TEST
190 help
191 Support for the TS-4800 FPGA IRQ controller
192
193 config VERSATILE_FPGA_IRQ
194 bool
195 select IRQ_DOMAIN
196
197 config VERSATILE_FPGA_IRQ_NR
198 int
199 default 4
200 depends on VERSATILE_FPGA_IRQ
201
202 config XTENSA_MX
203 bool
204 select IRQ_DOMAIN
205
206 config IRQ_CROSSBAR
207 bool
208 help
209 Support for a CROSSBAR ip that precedes the main interrupt controller.
210 The primary irqchip invokes the crossbar's callback which inturn allocates
211 a free irq and configures the IP. Thus the peripheral interrupts are
212 routed to one of the free irqchip interrupt lines.
213
214 config KEYSTONE_IRQ
215 tristate "Keystone 2 IRQ controller IP"
216 depends on ARCH_KEYSTONE
217 help
218 Support for Texas Instruments Keystone 2 IRQ controller IP which
219 is part of the Keystone 2 IPC mechanism
220
221 config MIPS_GIC
222 bool
223 select GENERIC_IRQ_IPI
224 select IRQ_DOMAIN_HIERARCHY
225 select MIPS_CM
226
227 config INGENIC_IRQ
228 bool
229 depends on MACH_INGENIC
230 default y
231
232 config RENESAS_H8300H_INTC
233 bool
234 select IRQ_DOMAIN
235
236 config RENESAS_H8S_INTC
237 bool
238 select IRQ_DOMAIN
239
240 config IMX_GPCV2
241 bool
242 select IRQ_DOMAIN
243 help
244 Enables the wakeup IRQs for IMX platforms with GPCv2 block
245
246 config IRQ_MXS
247 def_bool y if MACH_ASM9260 || ARCH_MXS
248 select IRQ_DOMAIN
249 select STMP_DEVICE
250
251 config MVEBU_ODMI
252 bool
253
254 config LS_SCFG_MSI
255 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
256 depends on PCI && PCI_MSI
257
258 config PARTITION_PERCPU
259 bool
260
261 config EZNPS_GIC
262 bool "NPS400 Global Interrupt Manager (GIM)"
263 depends on ARC || (COMPILE_TEST && !64BIT)
264 select IRQ_DOMAIN
265 help
266 Support the EZchip NPS400 global interrupt controller
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