2 * Marvell Armada 370 and Armada XP SoC IRQ handling
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqchip.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/cpu.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/irqdomain.h>
29 #include <linux/slab.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/msi.h>
32 #include <asm/mach/arch.h>
33 #include <asm/exception.h>
34 #include <asm/smp_plat.h>
35 #include <asm/mach/irq.h>
37 /* Interrupt Controller Registers Map */
38 #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
39 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
40 #define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
41 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
43 #define ARMADA_370_XP_INT_CONTROL (0x00)
44 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
45 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
46 #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
47 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
48 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
50 #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
51 #define ARMADA_375_PPI_CAUSE (0x10)
53 #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
54 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
55 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
57 #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
59 #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
60 #define ARMADA_370_XP_FABRIC_IRQ (3)
62 #define IPI_DOORBELL_START (0)
63 #define IPI_DOORBELL_END (8)
64 #define IPI_DOORBELL_MASK 0xFF
65 #define PCI_MSI_DOORBELL_START (16)
66 #define PCI_MSI_DOORBELL_NR (16)
67 #define PCI_MSI_DOORBELL_END (32)
68 #define PCI_MSI_DOORBELL_MASK 0xFFFF0000
70 static void __iomem
*per_cpu_int_base
;
71 static void __iomem
*main_int_base
;
72 static struct irq_domain
*armada_370_xp_mpic_domain
;
73 static u32 doorbell_mask_reg
;
74 static int parent_irq
;
76 static struct irq_domain
*armada_370_xp_msi_domain
;
77 static DECLARE_BITMAP(msi_used
, PCI_MSI_DOORBELL_NR
);
78 static DEFINE_MUTEX(msi_used_lock
);
79 static phys_addr_t msi_doorbell_addr
;
82 static inline bool is_percpu_irq(irq_hw_number_t irq
)
85 case ARMADA_370_XP_TIMER0_PER_CPU_IRQ
:
86 case ARMADA_370_XP_FABRIC_IRQ
:
95 * For shared global interrupts, mask/unmask global enable bit
96 * For CPU interrupts, mask/unmask the calling CPU's bit
98 static void armada_370_xp_irq_mask(struct irq_data
*d
)
100 irq_hw_number_t hwirq
= irqd_to_hwirq(d
);
102 if (!is_percpu_irq(hwirq
))
103 writel(hwirq
, main_int_base
+
104 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS
);
106 writel(hwirq
, per_cpu_int_base
+
107 ARMADA_370_XP_INT_SET_MASK_OFFS
);
110 static void armada_370_xp_irq_unmask(struct irq_data
*d
)
112 irq_hw_number_t hwirq
= irqd_to_hwirq(d
);
114 if (!is_percpu_irq(hwirq
))
115 writel(hwirq
, main_int_base
+
116 ARMADA_370_XP_INT_SET_ENABLE_OFFS
);
118 writel(hwirq
, per_cpu_int_base
+
119 ARMADA_370_XP_INT_CLEAR_MASK_OFFS
);
122 #ifdef CONFIG_PCI_MSI
124 static int armada_370_xp_alloc_msi(void)
128 mutex_lock(&msi_used_lock
);
129 hwirq
= find_first_zero_bit(&msi_used
, PCI_MSI_DOORBELL_NR
);
130 if (hwirq
>= PCI_MSI_DOORBELL_NR
)
133 set_bit(hwirq
, msi_used
);
134 mutex_unlock(&msi_used_lock
);
139 static void armada_370_xp_free_msi(int hwirq
)
141 mutex_lock(&msi_used_lock
);
142 if (!test_bit(hwirq
, msi_used
))
143 pr_err("trying to free unused MSI#%d\n", hwirq
);
145 clear_bit(hwirq
, msi_used
);
146 mutex_unlock(&msi_used_lock
);
149 static int armada_370_xp_setup_msi_irq(struct msi_controller
*chip
,
150 struct pci_dev
*pdev
,
151 struct msi_desc
*desc
)
156 /* We support MSI, but not MSI-X */
157 if (desc
->msi_attrib
.is_msix
)
160 hwirq
= armada_370_xp_alloc_msi();
164 virq
= irq_create_mapping(armada_370_xp_msi_domain
, hwirq
);
166 armada_370_xp_free_msi(hwirq
);
170 irq_set_msi_desc(virq
, desc
);
172 msg
.address_lo
= msi_doorbell_addr
;
174 msg
.data
= 0xf00 | (hwirq
+ 16);
176 pci_write_msi_msg(virq
, &msg
);
180 static void armada_370_xp_teardown_msi_irq(struct msi_controller
*chip
,
183 struct irq_data
*d
= irq_get_irq_data(irq
);
184 unsigned long hwirq
= d
->hwirq
;
186 irq_dispose_mapping(irq
);
187 armada_370_xp_free_msi(hwirq
);
190 static struct irq_chip armada_370_xp_msi_irq_chip
= {
191 .name
= "armada_370_xp_msi_irq",
192 .irq_enable
= pci_msi_unmask_irq
,
193 .irq_disable
= pci_msi_mask_irq
,
194 .irq_mask
= pci_msi_mask_irq
,
195 .irq_unmask
= pci_msi_unmask_irq
,
198 static int armada_370_xp_msi_map(struct irq_domain
*domain
, unsigned int virq
,
201 irq_set_chip_and_handler(virq
, &armada_370_xp_msi_irq_chip
,
207 static const struct irq_domain_ops armada_370_xp_msi_irq_ops
= {
208 .map
= armada_370_xp_msi_map
,
211 static int armada_370_xp_msi_init(struct device_node
*node
,
212 phys_addr_t main_int_phys_base
)
214 struct msi_controller
*msi_chip
;
218 msi_doorbell_addr
= main_int_phys_base
+
219 ARMADA_370_XP_SW_TRIG_INT_OFFS
;
221 msi_chip
= kzalloc(sizeof(*msi_chip
), GFP_KERNEL
);
225 msi_chip
->setup_irq
= armada_370_xp_setup_msi_irq
;
226 msi_chip
->teardown_irq
= armada_370_xp_teardown_msi_irq
;
227 msi_chip
->of_node
= node
;
229 armada_370_xp_msi_domain
=
230 irq_domain_add_linear(NULL
, PCI_MSI_DOORBELL_NR
,
231 &armada_370_xp_msi_irq_ops
,
233 if (!armada_370_xp_msi_domain
) {
238 ret
= of_pci_msi_chip_add(msi_chip
);
240 irq_domain_remove(armada_370_xp_msi_domain
);
245 reg
= readl(per_cpu_int_base
+ ARMADA_370_XP_IN_DRBEL_MSK_OFFS
)
246 | PCI_MSI_DOORBELL_MASK
;
248 writel(reg
, per_cpu_int_base
+
249 ARMADA_370_XP_IN_DRBEL_MSK_OFFS
);
251 /* Unmask IPI interrupt */
252 writel(1, per_cpu_int_base
+ ARMADA_370_XP_INT_CLEAR_MASK_OFFS
);
257 static inline int armada_370_xp_msi_init(struct device_node
*node
,
258 phys_addr_t main_int_phys_base
)
265 static DEFINE_RAW_SPINLOCK(irq_controller_lock
);
267 static int armada_xp_set_affinity(struct irq_data
*d
,
268 const struct cpumask
*mask_val
, bool force
)
270 irq_hw_number_t hwirq
= irqd_to_hwirq(d
);
271 unsigned long reg
, mask
;
274 /* Select a single core from the affinity mask which is online */
275 cpu
= cpumask_any_and(mask_val
, cpu_online_mask
);
276 mask
= 1UL << cpu_logical_map(cpu
);
278 raw_spin_lock(&irq_controller_lock
);
279 reg
= readl(main_int_base
+ ARMADA_370_XP_INT_SOURCE_CTL(hwirq
));
280 reg
= (reg
& (~ARMADA_370_XP_INT_SOURCE_CPU_MASK
)) | mask
;
281 writel(reg
, main_int_base
+ ARMADA_370_XP_INT_SOURCE_CTL(hwirq
));
282 raw_spin_unlock(&irq_controller_lock
);
284 return IRQ_SET_MASK_OK
;
288 static struct irq_chip armada_370_xp_irq_chip
= {
289 .name
= "armada_370_xp_irq",
290 .irq_mask
= armada_370_xp_irq_mask
,
291 .irq_mask_ack
= armada_370_xp_irq_mask
,
292 .irq_unmask
= armada_370_xp_irq_unmask
,
294 .irq_set_affinity
= armada_xp_set_affinity
,
296 .flags
= IRQCHIP_SKIP_SET_WAKE
| IRQCHIP_MASK_ON_SUSPEND
,
299 static int armada_370_xp_mpic_irq_map(struct irq_domain
*h
,
300 unsigned int virq
, irq_hw_number_t hw
)
302 armada_370_xp_irq_mask(irq_get_irq_data(virq
));
303 if (!is_percpu_irq(hw
))
304 writel(hw
, per_cpu_int_base
+
305 ARMADA_370_XP_INT_CLEAR_MASK_OFFS
);
307 writel(hw
, main_int_base
+ ARMADA_370_XP_INT_SET_ENABLE_OFFS
);
308 irq_set_status_flags(virq
, IRQ_LEVEL
);
310 if (is_percpu_irq(hw
)) {
311 irq_set_percpu_devid(virq
);
312 irq_set_chip_and_handler(virq
, &armada_370_xp_irq_chip
,
313 handle_percpu_devid_irq
);
316 irq_set_chip_and_handler(virq
, &armada_370_xp_irq_chip
,
324 static void armada_xp_mpic_smp_cpu_init(void)
329 control
= readl(main_int_base
+ ARMADA_370_XP_INT_CONTROL
);
330 nr_irqs
= (control
>> 2) & 0x3ff;
332 for (i
= 0; i
< nr_irqs
; i
++)
333 writel(i
, per_cpu_int_base
+ ARMADA_370_XP_INT_SET_MASK_OFFS
);
335 /* Clear pending IPIs */
336 writel(0, per_cpu_int_base
+ ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS
);
338 /* Enable first 8 IPIs */
339 writel(IPI_DOORBELL_MASK
, per_cpu_int_base
+
340 ARMADA_370_XP_IN_DRBEL_MSK_OFFS
);
342 /* Unmask IPI interrupt */
343 writel(0, per_cpu_int_base
+ ARMADA_370_XP_INT_CLEAR_MASK_OFFS
);
346 static void armada_xp_mpic_perf_init(void)
348 unsigned long cpuid
= cpu_logical_map(smp_processor_id());
350 /* Enable Performance Counter Overflow interrupts */
351 writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid
),
352 per_cpu_int_base
+ ARMADA_370_XP_INT_FABRIC_MASK_OFFS
);
356 static void armada_mpic_send_doorbell(const struct cpumask
*mask
,
360 unsigned long map
= 0;
362 /* Convert our logical CPU mask into a physical one. */
363 for_each_cpu(cpu
, mask
)
364 map
|= 1 << cpu_logical_map(cpu
);
367 * Ensure that stores to Normal memory are visible to the
368 * other CPUs before issuing the IPI.
373 writel((map
<< 8) | irq
, main_int_base
+
374 ARMADA_370_XP_SW_TRIG_INT_OFFS
);
377 static int armada_xp_mpic_secondary_init(struct notifier_block
*nfb
,
378 unsigned long action
, void *hcpu
)
380 if (action
== CPU_STARTING
|| action
== CPU_STARTING_FROZEN
) {
381 armada_xp_mpic_perf_init();
382 armada_xp_mpic_smp_cpu_init();
388 static struct notifier_block armada_370_xp_mpic_cpu_notifier
= {
389 .notifier_call
= armada_xp_mpic_secondary_init
,
393 static int mpic_cascaded_secondary_init(struct notifier_block
*nfb
,
394 unsigned long action
, void *hcpu
)
396 if (action
== CPU_STARTING
|| action
== CPU_STARTING_FROZEN
) {
397 armada_xp_mpic_perf_init();
398 enable_percpu_irq(parent_irq
, IRQ_TYPE_NONE
);
404 static struct notifier_block mpic_cascaded_cpu_notifier
= {
405 .notifier_call
= mpic_cascaded_secondary_init
,
408 #endif /* CONFIG_SMP */
410 static const struct irq_domain_ops armada_370_xp_mpic_irq_ops
= {
411 .map
= armada_370_xp_mpic_irq_map
,
412 .xlate
= irq_domain_xlate_onecell
,
415 #ifdef CONFIG_PCI_MSI
416 static void armada_370_xp_handle_msi_irq(struct pt_regs
*regs
, bool is_chained
)
420 msimask
= readl_relaxed(per_cpu_int_base
+
421 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS
)
422 & PCI_MSI_DOORBELL_MASK
;
424 writel(~msimask
, per_cpu_int_base
+
425 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS
);
427 for (msinr
= PCI_MSI_DOORBELL_START
;
428 msinr
< PCI_MSI_DOORBELL_END
; msinr
++) {
431 if (!(msimask
& BIT(msinr
)))
435 irq
= irq_find_mapping(armada_370_xp_msi_domain
,
437 generic_handle_irq(irq
);
440 handle_domain_irq(armada_370_xp_msi_domain
,
446 static void armada_370_xp_handle_msi_irq(struct pt_regs
*r
, bool b
) {}
449 static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc
*desc
)
451 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
452 unsigned long irqmap
, irqn
, irqsrc
, cpuid
;
453 unsigned int cascade_irq
;
455 chained_irq_enter(chip
, desc
);
457 irqmap
= readl_relaxed(per_cpu_int_base
+ ARMADA_375_PPI_CAUSE
);
458 cpuid
= cpu_logical_map(smp_processor_id());
460 for_each_set_bit(irqn
, &irqmap
, BITS_PER_LONG
) {
461 irqsrc
= readl_relaxed(main_int_base
+
462 ARMADA_370_XP_INT_SOURCE_CTL(irqn
));
464 /* Check if the interrupt is not masked on current CPU.
465 * Test IRQ (0-1) and FIQ (8-9) mask bits.
467 if (!(irqsrc
& ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid
)))
471 armada_370_xp_handle_msi_irq(NULL
, true);
475 cascade_irq
= irq_find_mapping(armada_370_xp_mpic_domain
, irqn
);
476 generic_handle_irq(cascade_irq
);
479 chained_irq_exit(chip
, desc
);
482 static void __exception_irq_entry
483 armada_370_xp_handle_irq(struct pt_regs
*regs
)
488 irqstat
= readl_relaxed(per_cpu_int_base
+
489 ARMADA_370_XP_CPU_INTACK_OFFS
);
490 irqnr
= irqstat
& 0x3FF;
496 handle_domain_irq(armada_370_xp_mpic_domain
,
503 armada_370_xp_handle_msi_irq(regs
, false);
510 ipimask
= readl_relaxed(per_cpu_int_base
+
511 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS
)
514 writel(~ipimask
, per_cpu_int_base
+
515 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS
);
517 /* Handle all pending doorbells */
518 for (ipinr
= IPI_DOORBELL_START
;
519 ipinr
< IPI_DOORBELL_END
; ipinr
++) {
520 if (ipimask
& (0x1 << ipinr
))
521 handle_IPI(ipinr
, regs
);
530 static int armada_370_xp_mpic_suspend(void)
532 doorbell_mask_reg
= readl(per_cpu_int_base
+
533 ARMADA_370_XP_IN_DRBEL_MSK_OFFS
);
537 static void armada_370_xp_mpic_resume(void)
542 /* Re-enable interrupts */
543 nirqs
= (readl(main_int_base
+ ARMADA_370_XP_INT_CONTROL
) >> 2) & 0x3ff;
544 for (irq
= 0; irq
< nirqs
; irq
++) {
545 struct irq_data
*data
;
548 virq
= irq_linear_revmap(armada_370_xp_mpic_domain
, irq
);
552 if (irq
!= ARMADA_370_XP_TIMER0_PER_CPU_IRQ
)
553 writel(irq
, per_cpu_int_base
+
554 ARMADA_370_XP_INT_CLEAR_MASK_OFFS
);
556 writel(irq
, main_int_base
+
557 ARMADA_370_XP_INT_SET_ENABLE_OFFS
);
559 data
= irq_get_irq_data(virq
);
560 if (!irqd_irq_disabled(data
))
561 armada_370_xp_irq_unmask(data
);
564 /* Reconfigure doorbells for IPIs and MSIs */
565 writel(doorbell_mask_reg
,
566 per_cpu_int_base
+ ARMADA_370_XP_IN_DRBEL_MSK_OFFS
);
567 if (doorbell_mask_reg
& IPI_DOORBELL_MASK
)
568 writel(0, per_cpu_int_base
+ ARMADA_370_XP_INT_CLEAR_MASK_OFFS
);
569 if (doorbell_mask_reg
& PCI_MSI_DOORBELL_MASK
)
570 writel(1, per_cpu_int_base
+ ARMADA_370_XP_INT_CLEAR_MASK_OFFS
);
573 struct syscore_ops armada_370_xp_mpic_syscore_ops
= {
574 .suspend
= armada_370_xp_mpic_suspend
,
575 .resume
= armada_370_xp_mpic_resume
,
578 static int __init
armada_370_xp_mpic_of_init(struct device_node
*node
,
579 struct device_node
*parent
)
581 struct resource main_int_res
, per_cpu_int_res
;
585 BUG_ON(of_address_to_resource(node
, 0, &main_int_res
));
586 BUG_ON(of_address_to_resource(node
, 1, &per_cpu_int_res
));
588 BUG_ON(!request_mem_region(main_int_res
.start
,
589 resource_size(&main_int_res
),
591 BUG_ON(!request_mem_region(per_cpu_int_res
.start
,
592 resource_size(&per_cpu_int_res
),
595 main_int_base
= ioremap(main_int_res
.start
,
596 resource_size(&main_int_res
));
597 BUG_ON(!main_int_base
);
599 per_cpu_int_base
= ioremap(per_cpu_int_res
.start
,
600 resource_size(&per_cpu_int_res
));
601 BUG_ON(!per_cpu_int_base
);
603 control
= readl(main_int_base
+ ARMADA_370_XP_INT_CONTROL
);
604 nr_irqs
= (control
>> 2) & 0x3ff;
606 for (i
= 0; i
< nr_irqs
; i
++)
607 writel(i
, main_int_base
+ ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS
);
609 armada_370_xp_mpic_domain
=
610 irq_domain_add_linear(node
, nr_irqs
,
611 &armada_370_xp_mpic_irq_ops
, NULL
);
613 BUG_ON(!armada_370_xp_mpic_domain
);
615 /* Setup for the boot CPU */
616 armada_xp_mpic_perf_init();
617 armada_xp_mpic_smp_cpu_init();
619 armada_370_xp_msi_init(node
, main_int_res
.start
);
621 parent_irq
= irq_of_parse_and_map(node
, 0);
622 if (parent_irq
<= 0) {
623 irq_set_default_host(armada_370_xp_mpic_domain
);
624 set_handle_irq(armada_370_xp_handle_irq
);
626 set_smp_cross_call(armada_mpic_send_doorbell
);
627 register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier
);
631 register_cpu_notifier(&mpic_cascaded_cpu_notifier
);
633 irq_set_chained_handler(parent_irq
,
634 armada_370_xp_mpic_handle_cascade_irq
);
637 register_syscore_ops(&armada_370_xp_mpic_syscore_ops
);
642 IRQCHIP_DECLARE(armada_370_xp_mpic
, "marvell,mpic", armada_370_xp_mpic_of_init
);