2 * drivers/irqchip/irq-crossbar.c
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sricharan R <r.sricharan@ti.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/err.h>
14 #include <linux/irqchip.h>
15 #include <linux/irqdomain.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/slab.h>
21 #define IRQ_RESERVED -2
23 #define GIC_IRQ_START 32
26 * struct crossbar_device - crossbar device description
27 * @lock: spinlock serializing access to @irq_map
28 * @int_max: maximum number of supported interrupts
29 * @safe_map: safe default value to initialize the crossbar
30 * @max_crossbar_sources: Maximum number of crossbar sources
31 * @irq_map: array of interrupts to crossbar number mapping
32 * @crossbar_base: crossbar base address
33 * @register_offsets: offsets for each irq number
34 * @write: register write function pointer
36 struct crossbar_device
{
40 uint max_crossbar_sources
;
42 void __iomem
*crossbar_base
;
43 int *register_offsets
;
44 void (*write
)(int, int);
47 static struct crossbar_device
*cb
;
49 static void crossbar_writel(int irq_no
, int cb_no
)
51 writel(cb_no
, cb
->crossbar_base
+ cb
->register_offsets
[irq_no
]);
54 static void crossbar_writew(int irq_no
, int cb_no
)
56 writew(cb_no
, cb
->crossbar_base
+ cb
->register_offsets
[irq_no
]);
59 static void crossbar_writeb(int irq_no
, int cb_no
)
61 writeb(cb_no
, cb
->crossbar_base
+ cb
->register_offsets
[irq_no
]);
64 static struct irq_chip crossbar_chip
= {
66 .irq_eoi
= irq_chip_eoi_parent
,
67 .irq_mask
= irq_chip_mask_parent
,
68 .irq_unmask
= irq_chip_unmask_parent
,
69 .irq_retrigger
= irq_chip_retrigger_hierarchy
,
70 .irq_set_type
= irq_chip_set_type_parent
,
71 .flags
= IRQCHIP_MASK_ON_SUSPEND
|
72 IRQCHIP_SKIP_SET_WAKE
,
74 .irq_set_affinity
= irq_chip_set_affinity_parent
,
78 static int allocate_gic_irq(struct irq_domain
*domain
, unsigned virq
,
79 irq_hw_number_t hwirq
)
81 struct of_phandle_args args
;
85 raw_spin_lock(&cb
->lock
);
86 for (i
= cb
->int_max
- 1; i
>= 0; i
--) {
87 if (cb
->irq_map
[i
] == IRQ_FREE
) {
88 cb
->irq_map
[i
] = hwirq
;
92 raw_spin_unlock(&cb
->lock
);
97 args
.np
= domain
->parent
->of_node
;
99 args
.args
[0] = 0; /* SPI */
101 args
.args
[2] = IRQ_TYPE_LEVEL_HIGH
;
103 err
= irq_domain_alloc_irqs_parent(domain
, virq
, 1, &args
);
105 cb
->irq_map
[i
] = IRQ_FREE
;
112 static int crossbar_domain_alloc(struct irq_domain
*d
, unsigned int virq
,
113 unsigned int nr_irqs
, void *data
)
115 struct of_phandle_args
*args
= data
;
116 irq_hw_number_t hwirq
;
119 if (args
->args_count
!= 3)
120 return -EINVAL
; /* Not GIC compliant */
121 if (args
->args
[0] != 0)
122 return -EINVAL
; /* No PPI should point to this domain */
124 hwirq
= args
->args
[1];
125 if ((hwirq
+ nr_irqs
) > cb
->max_crossbar_sources
)
126 return -EINVAL
; /* Can't deal with this */
128 for (i
= 0; i
< nr_irqs
; i
++) {
129 int err
= allocate_gic_irq(d
, virq
+ i
, hwirq
+ i
);
134 irq_domain_set_hwirq_and_chip(d
, virq
+ i
, hwirq
+ i
,
135 &crossbar_chip
, NULL
);
142 * crossbar_domain_free - unmap/free a crossbar<->irq connection
143 * @domain: domain of irq to unmap
145 * @nr_irqs: number of irqs to free
147 * We do not maintain a use count of total number of map/unmap
148 * calls for a particular irq to find out if a irq can be really
149 * unmapped. This is because unmap is called during irq_dispose_mapping(irq),
150 * after which irq is anyways unusable. So an explicit map has to be called
153 static void crossbar_domain_free(struct irq_domain
*domain
, unsigned int virq
,
154 unsigned int nr_irqs
)
158 raw_spin_lock(&cb
->lock
);
159 for (i
= 0; i
< nr_irqs
; i
++) {
160 struct irq_data
*d
= irq_domain_get_irq_data(domain
, virq
+ i
);
162 irq_domain_reset_irq_data(d
);
163 cb
->irq_map
[d
->hwirq
] = IRQ_FREE
;
164 cb
->write(d
->hwirq
, cb
->safe_map
);
166 raw_spin_unlock(&cb
->lock
);
169 static int crossbar_domain_xlate(struct irq_domain
*d
,
170 struct device_node
*controller
,
171 const u32
*intspec
, unsigned int intsize
,
172 unsigned long *out_hwirq
,
173 unsigned int *out_type
)
175 if (d
->of_node
!= controller
)
176 return -EINVAL
; /* Shouldn't happen, really... */
178 return -EINVAL
; /* Not GIC compliant */
180 return -EINVAL
; /* No PPI should point to this domain */
182 *out_hwirq
= intspec
[1];
183 *out_type
= intspec
[2];
187 static const struct irq_domain_ops crossbar_domain_ops
= {
188 .alloc
= crossbar_domain_alloc
,
189 .free
= crossbar_domain_free
,
190 .xlate
= crossbar_domain_xlate
,
193 static int __init
crossbar_of_init(struct device_node
*node
)
195 int i
, size
, max
= 0, reserved
= 0, entry
;
199 cb
= kzalloc(sizeof(*cb
), GFP_KERNEL
);
204 cb
->crossbar_base
= of_iomap(node
, 0);
205 if (!cb
->crossbar_base
)
208 of_property_read_u32(node
, "ti,max-crossbar-sources",
209 &cb
->max_crossbar_sources
);
210 if (!cb
->max_crossbar_sources
) {
211 pr_err("missing 'ti,max-crossbar-sources' property\n");
216 of_property_read_u32(node
, "ti,max-irqs", &max
);
218 pr_err("missing 'ti,max-irqs' property\n");
222 cb
->irq_map
= kcalloc(max
, sizeof(int), GFP_KERNEL
);
228 for (i
= 0; i
< max
; i
++)
229 cb
->irq_map
[i
] = IRQ_FREE
;
231 /* Get and mark reserved irqs */
232 irqsr
= of_get_property(node
, "ti,irqs-reserved", &size
);
234 size
/= sizeof(__be32
);
236 for (i
= 0; i
< size
; i
++) {
237 of_property_read_u32_index(node
,
241 pr_err("Invalid reserved entry\n");
245 cb
->irq_map
[entry
] = IRQ_RESERVED
;
249 /* Skip irqs hardwired to bypass the crossbar */
250 irqsr
= of_get_property(node
, "ti,irqs-skip", &size
);
252 size
/= sizeof(__be32
);
254 for (i
= 0; i
< size
; i
++) {
255 of_property_read_u32_index(node
,
259 pr_err("Invalid skip entry\n");
263 cb
->irq_map
[entry
] = IRQ_SKIP
;
268 cb
->register_offsets
= kcalloc(max
, sizeof(int), GFP_KERNEL
);
269 if (!cb
->register_offsets
)
272 of_property_read_u32(node
, "ti,reg-size", &size
);
276 cb
->write
= crossbar_writeb
;
279 cb
->write
= crossbar_writew
;
282 cb
->write
= crossbar_writel
;
285 pr_err("Invalid reg-size property\n");
292 * Register offsets are not linear because of the
293 * reserved irqs. so find and store the offsets once.
295 for (i
= 0; i
< max
; i
++) {
296 if (cb
->irq_map
[i
] == IRQ_RESERVED
)
299 cb
->register_offsets
[i
] = reserved
;
303 of_property_read_u32(node
, "ti,irqs-safe-map", &cb
->safe_map
);
304 /* Initialize the crossbar with safe map to start with */
305 for (i
= 0; i
< max
; i
++) {
306 if (cb
->irq_map
[i
] == IRQ_RESERVED
||
307 cb
->irq_map
[i
] == IRQ_SKIP
)
310 cb
->write(i
, cb
->safe_map
);
313 raw_spin_lock_init(&cb
->lock
);
318 kfree(cb
->register_offsets
);
322 iounmap(cb
->crossbar_base
);
330 static int __init
irqcrossbar_init(struct device_node
*node
,
331 struct device_node
*parent
)
333 struct irq_domain
*parent_domain
, *domain
;
337 pr_err("%s: no parent, giving up\n", node
->full_name
);
341 parent_domain
= irq_find_host(parent
);
342 if (!parent_domain
) {
343 pr_err("%s: unable to obtain parent domain\n", node
->full_name
);
347 err
= crossbar_of_init(node
);
351 domain
= irq_domain_add_hierarchy(parent_domain
, 0,
352 cb
->max_crossbar_sources
,
353 node
, &crossbar_domain_ops
,
356 pr_err("%s: failed to allocated domain\n", node
->full_name
);
363 IRQCHIP_DECLARE(ti_irqcrossbar
, "ti,irq-crossbar", irqcrossbar_init
);