drivers/irqchip/irq-gic-v3.c

   1 /*
   2  * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/cpu.h>
  19 #include <linux/cpu_pm.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/percpu.h>
  26 #include <linux/slab.h>
  27
  28 #include <linux/irqchip/arm-gic-v3.h>
  29
  30 #include <asm/cputype.h>
  31 #include <asm/exception.h>
  32 #include <asm/smp_plat.h>
  33
  34 #include "irq-gic-common.h"
  35 #include "irqchip.h"
  36
  37 struct gic_chip_data {
  38         void __iomem            *dist_base;
  39         void __iomem            **redist_base;
  40         void __iomem * __percpu *rdist;
  41         struct irq_domain       *domain;
  42         u64                     redist_stride;
  43         u32                     redist_regions;
  44         unsigned int            irq_nr;
  45 };
  46
  47 static struct gic_chip_data gic_data __read_mostly;
  48
  49 #define gic_data_rdist()                (this_cpu_ptr(gic_data.rdist))
  50 #define gic_data_rdist_rd_base()        (*gic_data_rdist())
  51 #define gic_data_rdist_sgi_base()       (gic_data_rdist_rd_base() + SZ_64K)
  52
  53 /* Our default, arbitrary priority value. Linux only uses one anyway. */
  54 #define DEFAULT_PMR_VALUE       0xf0
  55
  56 static inline unsigned int gic_irq(struct irq_data *d)
  57 {
  58         return d->hwirq;
  59 }
  60
  61 static inline int gic_irq_in_rdist(struct irq_data *d)
  62 {
  63         return gic_irq(d) < 32;
  64 }
  65
  66 static inline void __iomem *gic_dist_base(struct irq_data *d)
  67 {
  68         if (gic_irq_in_rdist(d))        /* SGI+PPI -> SGI_base for this CPU */
  69                 return gic_data_rdist_sgi_base();
  70
  71         if (d->hwirq <= 1023)           /* SPI -> dist_base */
  72                 return gic_data.dist_base;
  73
  74         if (d->hwirq >= 8192)
  75                 BUG();          /* LPI Detected!!! */
  76
  77         return NULL;
  78 }
  79
  80 static void gic_do_wait_for_rwp(void __iomem *base)
  81 {
  82         u32 count = 1000000;    /* 1s! */
  83
  84         while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
  85                 count--;
  86                 if (!count) {
  87                         pr_err_ratelimited("RWP timeout, gone fishing\n");
  88                         return;
  89                 }
  90                 cpu_relax();
  91                 udelay(1);
  92         };
  93 }
  94
  95 /* Wait for completion of a distributor change */
  96 static void gic_dist_wait_for_rwp(void)
  97 {
  98         gic_do_wait_for_rwp(gic_data.dist_base);
  99 }
 100
 101 /* Wait for completion of a redistributor change */
 102 static void gic_redist_wait_for_rwp(void)
 103 {
 104         gic_do_wait_for_rwp(gic_data_rdist_rd_base());
 105 }
 106
 107 /* Low level accessors */
 108 static u64 __maybe_unused gic_read_iar(void)
 109 {
 110         u64 irqstat;
 111
 112         asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
 113         return irqstat;
 114 }
 115
 116 static void __maybe_unused gic_write_pmr(u64 val)
 117 {
 118         asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
 119 }
 120
 121 static void __maybe_unused gic_write_ctlr(u64 val)
 122 {
 123         asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
 124         isb();
 125 }
 126
 127 static void __maybe_unused gic_write_grpen1(u64 val)
 128 {
 129         asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
 130         isb();
 131 }
 132
 133 static void __maybe_unused gic_write_sgi1r(u64 val)
 134 {
 135         asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
 136 }
 137
 138 static void gic_enable_sre(void)
 139 {
 140         u64 val;
 141
 142         asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
 143         val |= ICC_SRE_EL1_SRE;
 144         asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
 145         isb();
 146
 147         /*
 148          * Need to check that the SRE bit has actually been set. If
 149          * not, it means that SRE is disabled at EL2. We're going to
 150          * die painfully, and there is nothing we can do about it.
 151          *
 152          * Kindly inform the luser.
 153          */
 154         asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
 155         if (!(val & ICC_SRE_EL1_SRE))
 156                 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
 157 }
 158
 159 static void gic_enable_redist(bool enable)
 160 {
 161         void __iomem *rbase;
 162         u32 count = 1000000;    /* 1s! */
 163         u32 val;
 164
 165         rbase = gic_data_rdist_rd_base();
 166
 167         val = readl_relaxed(rbase + GICR_WAKER);
 168         if (enable)
 169                 /* Wake up this CPU redistributor */
 170                 val &= ~GICR_WAKER_ProcessorSleep;
 171         else
 172                 val |= GICR_WAKER_ProcessorSleep;
 173         writel_relaxed(val, rbase + GICR_WAKER);
 174
 175         if (!enable) {          /* Check that GICR_WAKER is writeable */
 176                 val = readl_relaxed(rbase + GICR_WAKER);
 177                 if (!(val & GICR_WAKER_ProcessorSleep))
 178                         return; /* No PM support in this redistributor */
 179         }
 180
 181         while (count--) {
 182                 val = readl_relaxed(rbase + GICR_WAKER);
 183                 if (enable ^ (val & GICR_WAKER_ChildrenAsleep))
 184                         break;
 185                 cpu_relax();
 186                 udelay(1);
 187         };
 188         if (!count)
 189                 pr_err_ratelimited("redistributor failed to %s...\n",
 190                                    enable ? "wakeup" : "sleep");
 191 }
 192
 193 /*
 194  * Routines to disable, enable, EOI and route interrupts
 195  */
 196 static void gic_poke_irq(struct irq_data *d, u32 offset)
 197 {
 198         u32 mask = 1 << (gic_irq(d) % 32);
 199         void (*rwp_wait)(void);
 200         void __iomem *base;
 201
 202         if (gic_irq_in_rdist(d)) {
 203                 base = gic_data_rdist_sgi_base();
 204                 rwp_wait = gic_redist_wait_for_rwp;
 205         } else {
 206                 base = gic_data.dist_base;
 207                 rwp_wait = gic_dist_wait_for_rwp;
 208         }
 209
 210         writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
 211         rwp_wait();
 212 }
 213
 214 static void gic_mask_irq(struct irq_data *d)
 215 {
 216         gic_poke_irq(d, GICD_ICENABLER);
 217 }
 218
 219 static void gic_unmask_irq(struct irq_data *d)
 220 {
 221         gic_poke_irq(d, GICD_ISENABLER);
 222 }
 223
 224 static void gic_eoi_irq(struct irq_data *d)
 225 {
 226         gic_write_eoir(gic_irq(d));
 227 }
 228
 229 static int gic_set_type(struct irq_data *d, unsigned int type)
 230 {
 231         unsigned int irq = gic_irq(d);
 232         void (*rwp_wait)(void);
 233         void __iomem *base;
 234
 235         /* Interrupt configuration for SGIs can't be changed */
 236         if (irq < 16)
 237                 return -EINVAL;
 238
 239         if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
 240                 return -EINVAL;
 241
 242         if (gic_irq_in_rdist(d)) {
 243                 base = gic_data_rdist_sgi_base();
 244                 rwp_wait = gic_redist_wait_for_rwp;
 245         } else {
 246                 base = gic_data.dist_base;
 247                 rwp_wait = gic_dist_wait_for_rwp;
 248         }
 249
 250         gic_configure_irq(irq, type, base, rwp_wait);
 251
 252         return 0;
 253 }
 254
 255 static u64 gic_mpidr_to_affinity(u64 mpidr)
 256 {
 257         u64 aff;
 258
 259         aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
 260                MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
 261                MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8  |
 262                MPIDR_AFFINITY_LEVEL(mpidr, 0));
 263
 264         return aff;
 265 }
 266
 267 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 268 {
 269         u64 irqnr;
 270
 271         do {
 272                 irqnr = gic_read_iar();
 273
 274                 if (likely(irqnr > 15 && irqnr < 1020)) {
 275                         int err;
 276                         err = handle_domain_irq(gic_data.domain, irqnr, regs);
 277                         if (err) {
 278                                 WARN_ONCE(true, "Unexpected SPI received!\n");
 279                                 gic_write_eoir(irqnr);
 280                         }
 281                         continue;
 282                 }
 283                 if (irqnr < 16) {
 284                         gic_write_eoir(irqnr);
 285 #ifdef CONFIG_SMP
 286                         handle_IPI(irqnr, regs);
 287 #else
 288                         WARN_ONCE(true, "Unexpected SGI received!\n");
 289 #endif
 290                         continue;
 291                 }
 292         } while (irqnr != ICC_IAR1_EL1_SPURIOUS);
 293 }
 294
 295 static void __init gic_dist_init(void)
 296 {
 297         unsigned int i;
 298         u64 affinity;
 299         void __iomem *base = gic_data.dist_base;
 300
 301         /* Disable the distributor */
 302         writel_relaxed(0, base + GICD_CTLR);
 303         gic_dist_wait_for_rwp();
 304
 305         gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
 306
 307         /* Enable distributor with ARE, Group1 */
 308         writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
 309                        base + GICD_CTLR);
 310
 311         /*
 312          * Set all global interrupts to the boot CPU only. ARE must be
 313          * enabled.
 314          */
 315         affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
 316         for (i = 32; i < gic_data.irq_nr; i++)
 317                 writeq_relaxed(affinity, base + GICD_IROUTER + i * 8);
 318 }
 319
 320 static int gic_populate_rdist(void)
 321 {
 322         u64 mpidr = cpu_logical_map(smp_processor_id());
 323         u64 typer;
 324         u32 aff;
 325         int i;
 326
 327         /*
 328          * Convert affinity to a 32bit value that can be matched to
 329          * GICR_TYPER bits [63:32].
 330          */
 331         aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
 332                MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
 333                MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
 334                MPIDR_AFFINITY_LEVEL(mpidr, 0));
 335
 336         for (i = 0; i < gic_data.redist_regions; i++) {
 337                 void __iomem *ptr = gic_data.redist_base[i];
 338                 u32 reg;
 339
 340                 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
 341                 if (reg != GIC_PIDR2_ARCH_GICv3 &&
 342                     reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
 343                         pr_warn("No redistributor present @%p\n", ptr);
 344                         break;
 345                 }
 346
 347                 do {
 348                         typer = readq_relaxed(ptr + GICR_TYPER);
 349                         if ((typer >> 32) == aff) {
 350                                 gic_data_rdist_rd_base() = ptr;
 351                                 pr_info("CPU%d: found redistributor %llx @%p\n",
 352                                         smp_processor_id(),
 353                                         (unsigned long long)mpidr, ptr);
 354                                 return 0;
 355                         }
 356
 357                         if (gic_data.redist_stride) {
 358                                 ptr += gic_data.redist_stride;
 359                         } else {
 360                                 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
 361                                 if (typer & GICR_TYPER_VLPIS)
 362                                         ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
 363                         }
 364                 } while (!(typer & GICR_TYPER_LAST));
 365         }
 366
 367         /* We couldn't even deal with ourselves... */
 368         WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
 369              smp_processor_id(), (unsigned long long)mpidr);
 370         return -ENODEV;
 371 }
 372
 373 static void gic_cpu_sys_reg_init(void)
 374 {
 375         /* Enable system registers */
 376         gic_enable_sre();
 377
 378         /* Set priority mask register */
 379         gic_write_pmr(DEFAULT_PMR_VALUE);
 380
 381         /* EOI deactivates interrupt too (mode 0) */
 382         gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
 383
 384         /* ... and let's hit the road... */
 385         gic_write_grpen1(1);
 386 }
 387
 388 static void gic_cpu_init(void)
 389 {
 390         void __iomem *rbase;
 391
 392         /* Register ourselves with the rest of the world */
 393         if (gic_populate_rdist())
 394                 return;
 395
 396         gic_enable_redist(true);
 397
 398         rbase = gic_data_rdist_sgi_base();
 399
 400         gic_cpu_config(rbase, gic_redist_wait_for_rwp);
 401
 402         /* initialise system registers */
 403         gic_cpu_sys_reg_init();
 404 }
 405
 406 #ifdef CONFIG_SMP
 407 static int gic_peek_irq(struct irq_data *d, u32 offset)
 408 {
 409         u32 mask = 1 << (gic_irq(d) % 32);
 410         void __iomem *base;
 411
 412         if (gic_irq_in_rdist(d))
 413                 base = gic_data_rdist_sgi_base();
 414         else
 415                 base = gic_data.dist_base;
 416
 417         return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
 418 }
 419
 420 static int gic_secondary_init(struct notifier_block *nfb,
 421                               unsigned long action, void *hcpu)
 422 {
 423         if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
 424                 gic_cpu_init();
 425         return NOTIFY_OK;
 426 }
 427
 428 /*
 429  * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
 430  * priority because the GIC needs to be up before the ARM generic timers.
 431  */
 432 static struct notifier_block gic_cpu_notifier = {
 433         .notifier_call = gic_secondary_init,
 434         .priority = 100,
 435 };
 436
 437 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
 438                                    u64 cluster_id)
 439 {
 440         int cpu = *base_cpu;
 441         u64 mpidr = cpu_logical_map(cpu);
 442         u16 tlist = 0;
 443
 444         while (cpu < nr_cpu_ids) {
 445                 /*
 446                  * If we ever get a cluster of more than 16 CPUs, just
 447                  * scream and skip that CPU.
 448                  */
 449                 if (WARN_ON((mpidr & 0xff) >= 16))
 450                         goto out;
 451
 452                 tlist |= 1 << (mpidr & 0xf);
 453
 454                 cpu = cpumask_next(cpu, mask);
 455                 if (cpu == nr_cpu_ids)
 456                         goto out;
 457
 458                 mpidr = cpu_logical_map(cpu);
 459
 460                 if (cluster_id != (mpidr & ~0xffUL)) {
 461                         cpu--;
 462                         goto out;
 463                 }
 464         }
 465 out:
 466         *base_cpu = cpu;
 467         return tlist;
 468 }
 469
 470 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
 471 {
 472         u64 val;
 473
 474         val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48        |
 475                MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32        |
 476                irq << 24                                        |
 477                MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16        |
 478                tlist);
 479
 480         pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
 481         gic_write_sgi1r(val);
 482 }
 483
 484 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 485 {
 486         int cpu;
 487
 488         if (WARN_ON(irq >= 16))
 489                 return;
 490
 491         /*
 492          * Ensure that stores to Normal memory are visible to the
 493          * other CPUs before issuing the IPI.
 494          */
 495         smp_wmb();
 496
 497         for_each_cpu_mask(cpu, *mask) {
 498                 u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL;
 499                 u16 tlist;
 500
 501                 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
 502                 gic_send_sgi(cluster_id, tlist, irq);
 503         }
 504
 505         /* Force the above writes to ICC_SGI1R_EL1 to be executed */
 506         isb();
 507 }
 508
 509 static void gic_smp_init(void)
 510 {
 511         set_smp_cross_call(gic_raise_softirq);
 512         register_cpu_notifier(&gic_cpu_notifier);
 513 }
 514
 515 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 516                             bool force)
 517 {
 518         unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
 519         void __iomem *reg;
 520         int enabled;
 521         u64 val;
 522
 523         if (gic_irq_in_rdist(d))
 524                 return -EINVAL;
 525
 526         /* If interrupt was enabled, disable it first */
 527         enabled = gic_peek_irq(d, GICD_ISENABLER);
 528         if (enabled)
 529                 gic_mask_irq(d);
 530
 531         reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
 532         val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
 533
 534         writeq_relaxed(val, reg);
 535
 536         /*
 537          * If the interrupt was enabled, enabled it again. Otherwise,
 538          * just wait for the distributor to have digested our changes.
 539          */
 540         if (enabled)
 541                 gic_unmask_irq(d);
 542         else
 543                 gic_dist_wait_for_rwp();
 544
 545         return IRQ_SET_MASK_OK;
 546 }
 547 #else
 548 #define gic_set_affinity        NULL
 549 #define gic_smp_init()          do { } while(0)
 550 #endif
 551
 552 #ifdef CONFIG_CPU_PM
 553 static int gic_cpu_pm_notifier(struct notifier_block *self,
 554                                unsigned long cmd, void *v)
 555 {
 556         if (cmd == CPU_PM_EXIT) {
 557                 gic_enable_redist(true);
 558                 gic_cpu_sys_reg_init();
 559         } else if (cmd == CPU_PM_ENTER) {
 560                 gic_write_grpen1(0);
 561                 gic_enable_redist(false);
 562         }
 563         return NOTIFY_OK;
 564 }
 565
 566 static struct notifier_block gic_cpu_pm_notifier_block = {
 567         .notifier_call = gic_cpu_pm_notifier,
 568 };
 569
 570 static void gic_cpu_pm_init(void)
 571 {
 572         cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
 573 }
 574
 575 #else
 576 static inline void gic_cpu_pm_init(void) { }
 577 #endif /* CONFIG_CPU_PM */
 578
 579 static struct irq_chip gic_chip = {
 580         .name                   = "GICv3",
 581         .irq_mask               = gic_mask_irq,
 582         .irq_unmask             = gic_unmask_irq,
 583         .irq_eoi                = gic_eoi_irq,
 584         .irq_set_type           = gic_set_type,
 585         .irq_set_affinity       = gic_set_affinity,
 586 };
 587
 588 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
 589                               irq_hw_number_t hw)
 590 {
 591         /* SGIs are private to the core kernel */
 592         if (hw < 16)
 593                 return -EPERM;
 594         /* PPIs */
 595         if (hw < 32) {
 596                 irq_set_percpu_devid(irq);
 597                 irq_set_chip_and_handler(irq, &gic_chip,
 598                                          handle_percpu_devid_irq);
 599                 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
 600         }
 601         /* SPIs */
 602         if (hw >= 32 && hw < gic_data.irq_nr) {
 603                 irq_set_chip_and_handler(irq, &gic_chip,
 604                                          handle_fasteoi_irq);
 605                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 606         }
 607         irq_set_chip_data(irq, d->host_data);
 608         return 0;
 609 }
 610
 611 static int gic_irq_domain_xlate(struct irq_domain *d,
 612                                 struct device_node *controller,
 613                                 const u32 *intspec, unsigned int intsize,
 614                                 unsigned long *out_hwirq, unsigned int *out_type)
 615 {
 616         if (d->of_node != controller)
 617                 return -EINVAL;
 618         if (intsize < 3)
 619                 return -EINVAL;
 620
 621         switch(intspec[0]) {
 622         case 0:                 /* SPI */
 623                 *out_hwirq = intspec[1] + 32;
 624                 break;
 625         case 1:                 /* PPI */
 626                 *out_hwirq = intspec[1] + 16;
 627                 break;
 628         default:
 629                 return -EINVAL;
 630         }
 631
 632         *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
 633         return 0;
 634 }
 635
 636 static const struct irq_domain_ops gic_irq_domain_ops = {
 637         .map = gic_irq_domain_map,
 638         .xlate = gic_irq_domain_xlate,
 639 };
 640
 641 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
 642 {
 643         void __iomem *dist_base;
 644         void __iomem **redist_base;
 645         u64 redist_stride;
 646         u32 redist_regions;
 647         u32 reg;
 648         int gic_irqs;
 649         int err;
 650         int i;
 651
 652         dist_base = of_iomap(node, 0);
 653         if (!dist_base) {
 654                 pr_err("%s: unable to map gic dist registers\n",
 655                         node->full_name);
 656                 return -ENXIO;
 657         }
 658
 659         reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
 660         if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
 661                 pr_err("%s: no distributor detected, giving up\n",
 662                         node->full_name);
 663                 err = -ENODEV;
 664                 goto out_unmap_dist;
 665         }
 666
 667         if (of_property_read_u32(node, "#redistributor-regions", &redist_regions))
 668                 redist_regions = 1;
 669
 670         redist_base = kzalloc(sizeof(*redist_base) * redist_regions, GFP_KERNEL);
 671         if (!redist_base) {
 672                 err = -ENOMEM;
 673                 goto out_unmap_dist;
 674         }
 675
 676         for (i = 0; i < redist_regions; i++) {
 677                 redist_base[i] = of_iomap(node, 1 + i);
 678                 if (!redist_base[i]) {
 679                         pr_err("%s: couldn't map region %d\n",
 680                                node->full_name, i);
 681                         err = -ENODEV;
 682                         goto out_unmap_rdist;
 683                 }
 684         }
 685
 686         if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
 687                 redist_stride = 0;
 688
 689         gic_data.dist_base = dist_base;
 690         gic_data.redist_base = redist_base;
 691         gic_data.redist_regions = redist_regions;
 692         gic_data.redist_stride = redist_stride;
 693
 694         /*
 695          * Find out how many interrupts are supported.
 696          * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
 697          */
 698         gic_irqs = readl_relaxed(gic_data.dist_base + GICD_TYPER) & 0x1f;
 699         gic_irqs = (gic_irqs + 1) * 32;
 700         if (gic_irqs > 1020)
 701                 gic_irqs = 1020;
 702         gic_data.irq_nr = gic_irqs;
 703
 704         gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops,
 705                                               &gic_data);
 706         gic_data.rdist = alloc_percpu(typeof(*gic_data.rdist));
 707
 708         if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdist)) {
 709                 err = -ENOMEM;
 710                 goto out_free;
 711         }
 712
 713         set_handle_irq(gic_handle_irq);
 714
 715         gic_smp_init();
 716         gic_dist_init();
 717         gic_cpu_init();
 718         gic_cpu_pm_init();
 719
 720         return 0;
 721
 722 out_free:
 723         if (gic_data.domain)
 724                 irq_domain_remove(gic_data.domain);
 725         free_percpu(gic_data.rdist);
 726 out_unmap_rdist:
 727         for (i = 0; i < redist_regions; i++)
 728                 if (redist_base[i])
 729                         iounmap(redist_base[i]);
 730         kfree(redist_base);
 731 out_unmap_dist:
 732         iounmap(dist_base);
 733         return err;
 734 }
 735
 736 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);