drivers/irqchip/irq-renesas-intc-irqpin.c

   1 /*
   2  * Renesas INTC External IRQ Pin Driver
   3  *
   4  *  Copyright (C) 2013 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/io.h>
  26 #include <linux/irq.h>
  27 #include <linux/irqdomain.h>
  28 #include <linux/err.h>
  29 #include <linux/slab.h>
  30 #include <linux/module.h>
  31 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  32
  33 #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
  34
  35 #define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
  36 #define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
  37 #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
  38 #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
  39 #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
  40 #define INTC_IRQPIN_REG_NR 5
  41
  42 /* INTC external IRQ PIN hardware register access:
  43  *
  44  * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
  45  * PRIO is read-write 32-bit with 4-bits per IRQ (**)
  46  * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
  47  * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
  48  * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
  49  *
  50  * (*) May be accessed by more than one driver instance - lock needed
  51  * (**) Read-modify-write access by one driver instance - lock needed
  52  * (***) Accessed by one driver instance only - no locking needed
  53  */
  54
  55 struct intc_irqpin_iomem {
  56         void __iomem *iomem;
  57         unsigned long (*read)(void __iomem *iomem);
  58         void (*write)(void __iomem *iomem, unsigned long data);
  59         int width;
  60 };
  61
  62 struct intc_irqpin_irq {
  63         int hw_irq;
  64         int requested_irq;
  65         int domain_irq;
  66         struct intc_irqpin_priv *p;
  67 };
  68
  69 struct intc_irqpin_priv {
  70         struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
  71         struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
  72         struct renesas_intc_irqpin_config config;
  73         unsigned int number_of_irqs;
  74         struct platform_device *pdev;
  75         struct irq_chip irq_chip;
  76         struct irq_domain *irq_domain;
  77 };
  78
  79 static unsigned long intc_irqpin_read32(void __iomem *iomem)
  80 {
  81         return ioread32(iomem);
  82 }
  83
  84 static unsigned long intc_irqpin_read8(void __iomem *iomem)
  85 {
  86         return ioread8(iomem);
  87 }
  88
  89 static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
  90 {
  91         iowrite32(data, iomem);
  92 }
  93
  94 static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
  95 {
  96         iowrite8(data, iomem);
  97 }
  98
  99 static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
 100                                              int reg)
 101 {
 102         struct intc_irqpin_iomem *i = &p->iomem[reg];
 103
 104         return i->read(i->iomem);
 105 }
 106
 107 static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
 108                                      int reg, unsigned long data)
 109 {
 110         struct intc_irqpin_iomem *i = &p->iomem[reg];
 111
 112         i->write(i->iomem, data);
 113 }
 114
 115 static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
 116                                                    int reg, int hw_irq)
 117 {
 118         return BIT((p->iomem[reg].width - 1) - hw_irq);
 119 }
 120
 121 static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
 122                                                int reg, int hw_irq)
 123 {
 124         intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
 125 }
 126
 127 static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
 128
 129 static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
 130                                           int reg, int shift,
 131                                           int width, int value)
 132 {
 133         unsigned long flags;
 134         unsigned long tmp;
 135
 136         raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
 137
 138         tmp = intc_irqpin_read(p, reg);
 139         tmp &= ~(((1 << width) - 1) << shift);
 140         tmp |= value << shift;
 141         intc_irqpin_write(p, reg, tmp);
 142
 143         raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
 144 }
 145
 146 static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
 147                                          int irq, int do_mask)
 148 {
 149         int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
 150         int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */
 151
 152         intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
 153                                       shift, bitfield_width,
 154                                       do_mask ? 0 : (1 << bitfield_width) - 1);
 155 }
 156
 157 static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
 158 {
 159         int bitfield_width = p->config.sense_bitfield_width;
 160         int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */
 161
 162         dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
 163
 164         if (value >= (1 << bitfield_width))
 165                 return -EINVAL;
 166
 167         intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
 168                                       bitfield_width, value);
 169         return 0;
 170 }
 171
 172 static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
 173 {
 174         dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
 175                 str, i->requested_irq, i->hw_irq, i->domain_irq);
 176 }
 177
 178 static void intc_irqpin_irq_enable(struct irq_data *d)
 179 {
 180         struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 181         int hw_irq = irqd_to_hwirq(d);
 182
 183         intc_irqpin_dbg(&p->irq[hw_irq], "enable");
 184         intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
 185 }
 186
 187 static void intc_irqpin_irq_disable(struct irq_data *d)
 188 {
 189         struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 190         int hw_irq = irqd_to_hwirq(d);
 191
 192         intc_irqpin_dbg(&p->irq[hw_irq], "disable");
 193         intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
 194 }
 195
 196 static void intc_irqpin_irq_enable_force(struct irq_data *d)
 197 {
 198         struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 199         int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
 200
 201         intc_irqpin_irq_enable(d);
 202
 203         /* enable interrupt through parent interrupt controller,
 204          * assumes non-shared interrupt with 1:1 mapping
 205          * needed for busted IRQs on some SoCs like sh73a0
 206          */
 207         irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
 208 }
 209
 210 static void intc_irqpin_irq_disable_force(struct irq_data *d)
 211 {
 212         struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 213         int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
 214
 215         /* disable interrupt through parent interrupt controller,
 216          * assumes non-shared interrupt with 1:1 mapping
 217          * needed for busted IRQs on some SoCs like sh73a0
 218          */
 219         irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
 220         intc_irqpin_irq_disable(d);
 221 }
 222
 223 #define INTC_IRQ_SENSE_VALID 0x10
 224 #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
 225
 226 static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
 227         [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
 228         [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
 229         [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
 230         [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
 231         [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
 232 };
 233
 234 static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
 235 {
 236         unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
 237         struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 238
 239         if (!(value & INTC_IRQ_SENSE_VALID))
 240                 return -EINVAL;
 241
 242         return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
 243                                      value ^ INTC_IRQ_SENSE_VALID);
 244 }
 245
 246 static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
 247 {
 248         struct intc_irqpin_irq *i = dev_id;
 249         struct intc_irqpin_priv *p = i->p;
 250         unsigned long bit;
 251
 252         intc_irqpin_dbg(i, "demux1");
 253         bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
 254
 255         if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
 256                 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
 257                 intc_irqpin_dbg(i, "demux2");
 258                 generic_handle_irq(i->domain_irq);
 259                 return IRQ_HANDLED;
 260         }
 261         return IRQ_NONE;
 262 }
 263
 264 static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
 265                                       irq_hw_number_t hw)
 266 {
 267         struct intc_irqpin_priv *p = h->host_data;
 268
 269         p->irq[hw].domain_irq = virq;
 270         p->irq[hw].hw_irq = hw;
 271
 272         intc_irqpin_dbg(&p->irq[hw], "map");
 273         irq_set_chip_data(virq, h->host_data);
 274         irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
 275         set_irq_flags(virq, IRQF_VALID); /* kill me now */
 276         return 0;
 277 }
 278
 279 static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
 280         .map    = intc_irqpin_irq_domain_map,
 281 };
 282
 283 static int intc_irqpin_probe(struct platform_device *pdev)
 284 {
 285         struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data;
 286         struct intc_irqpin_priv *p;
 287         struct intc_irqpin_iomem *i;
 288         struct resource *io[INTC_IRQPIN_REG_NR];
 289         struct resource *irq;
 290         struct irq_chip *irq_chip;
 291         void (*enable_fn)(struct irq_data *d);
 292         void (*disable_fn)(struct irq_data *d);
 293         const char *name = dev_name(&pdev->dev);
 294         int ret;
 295         int k;
 296
 297         p = kzalloc(sizeof(*p), GFP_KERNEL);
 298         if (!p) {
 299                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 300                 ret = -ENOMEM;
 301                 goto err0;
 302         }
 303
 304         /* deal with driver instance configuration */
 305         if (pdata)
 306                 memcpy(&p->config, pdata, sizeof(*pdata));
 307         if (!p->config.sense_bitfield_width)
 308                 p->config.sense_bitfield_width = 4; /* default to 4 bits */
 309
 310         p->pdev = pdev;
 311         platform_set_drvdata(pdev, p);
 312
 313         /* get hold of manadatory IOMEM */
 314         for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
 315                 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
 316                 if (!io[k]) {
 317                         dev_err(&pdev->dev, "not enough IOMEM resources\n");
 318                         ret = -EINVAL;
 319                         goto err1;
 320                 }
 321         }
 322
 323         /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
 324         for (k = 0; k < INTC_IRQPIN_MAX; k++) {
 325                 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
 326                 if (!irq)
 327                         break;
 328
 329                 p->irq[k].p = p;
 330                 p->irq[k].requested_irq = irq->start;
 331         }
 332
 333         p->number_of_irqs = k;
 334         if (p->number_of_irqs < 1) {
 335                 dev_err(&pdev->dev, "not enough IRQ resources\n");
 336                 ret = -EINVAL;
 337                 goto err1;
 338         }
 339
 340         /* ioremap IOMEM and setup read/write callbacks */
 341         for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
 342                 i = &p->iomem[k];
 343
 344                 switch (resource_size(io[k])) {
 345                 case 1:
 346                         i->width = 8;
 347                         i->read = intc_irqpin_read8;
 348                         i->write = intc_irqpin_write8;
 349                         break;
 350                 case 4:
 351                         i->width = 32;
 352                         i->read = intc_irqpin_read32;
 353                         i->write = intc_irqpin_write32;
 354                         break;
 355                 default:
 356                         dev_err(&pdev->dev, "IOMEM size mismatch\n");
 357                         ret = -EINVAL;
 358                         goto err2;
 359                 }
 360
 361                 i->iomem = ioremap_nocache(io[k]->start, resource_size(io[k]));
 362                 if (!i->iomem) {
 363                         dev_err(&pdev->dev, "failed to remap IOMEM\n");
 364                         ret = -ENXIO;
 365                         goto err2;
 366                 }
 367         }
 368
 369         /* mask all interrupts using priority */
 370         for (k = 0; k < p->number_of_irqs; k++)
 371                 intc_irqpin_mask_unmask_prio(p, k, 1);
 372
 373         /* use more severe masking method if requested */
 374         if (p->config.control_parent) {
 375                 enable_fn = intc_irqpin_irq_enable_force;
 376                 disable_fn = intc_irqpin_irq_disable_force;
 377         } else {
 378                 enable_fn = intc_irqpin_irq_enable;
 379                 disable_fn = intc_irqpin_irq_disable;
 380         }
 381
 382         irq_chip = &p->irq_chip;
 383         irq_chip->name = name;
 384         irq_chip->irq_mask = disable_fn;
 385         irq_chip->irq_unmask = enable_fn;
 386         irq_chip->irq_enable = enable_fn;
 387         irq_chip->irq_disable = disable_fn;
 388         irq_chip->irq_set_type = intc_irqpin_irq_set_type;
 389         irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
 390
 391         p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
 392                                               p->number_of_irqs,
 393                                               p->config.irq_base,
 394                                               &intc_irqpin_irq_domain_ops, p);
 395         if (!p->irq_domain) {
 396                 ret = -ENXIO;
 397                 dev_err(&pdev->dev, "cannot initialize irq domain\n");
 398                 goto err2;
 399         }
 400
 401         /* request and set priority on interrupts one by one */
 402         for (k = 0; k < p->number_of_irqs; k++) {
 403                 if (request_irq(p->irq[k].requested_irq,
 404                                 intc_irqpin_irq_handler,
 405                                 0, name, &p->irq[k])) {
 406                         dev_err(&pdev->dev, "failed to request low IRQ\n");
 407                         ret = -ENOENT;
 408                         goto err3;
 409                 }
 410                 intc_irqpin_mask_unmask_prio(p, k, 0);
 411         }
 412
 413         dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
 414
 415         /* warn in case of mismatch if irq base is specified */
 416         if (p->config.irq_base) {
 417                 if (p->config.irq_base != p->irq[0].domain_irq)
 418                         dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
 419                                  p->config.irq_base, p->irq[0].domain_irq);
 420         }
 421
 422         return 0;
 423
 424 err3:
 425         for (; k >= 0; k--)
 426                 free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]);
 427
 428         irq_domain_remove(p->irq_domain);
 429 err2:
 430         for (k = 0; k < INTC_IRQPIN_REG_NR; k++)
 431                 iounmap(p->iomem[k].iomem);
 432 err1:
 433         kfree(p);
 434 err0:
 435         return ret;
 436 }
 437
 438 static int intc_irqpin_remove(struct platform_device *pdev)
 439 {
 440         struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
 441         int k;
 442
 443         for (k = 0; k < p->number_of_irqs; k++)
 444                 free_irq(p->irq[k].requested_irq, &p->irq[k]);
 445
 446         irq_domain_remove(p->irq_domain);
 447
 448         for (k = 0; k < INTC_IRQPIN_REG_NR; k++)
 449                 iounmap(p->iomem[k].iomem);
 450
 451         kfree(p);
 452         return 0;
 453 }
 454
 455 static struct platform_driver intc_irqpin_device_driver = {
 456         .probe          = intc_irqpin_probe,
 457         .remove         = intc_irqpin_remove,
 458         .driver         = {
 459                 .name   = "renesas_intc_irqpin",
 460         }
 461 };
 462
 463 static int __init intc_irqpin_init(void)
 464 {
 465         return platform_driver_register(&intc_irqpin_device_driver);
 466 }
 467 postcore_initcall(intc_irqpin_init);
 468
 469 static void __exit intc_irqpin_exit(void)
 470 {
 471         platform_driver_unregister(&intc_irqpin_device_driver);
 472 }
 473 module_exit(intc_irqpin_exit);
 474
 475 MODULE_AUTHOR("Magnus Damm");
 476 MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
 477 MODULE_LICENSE("GPL v2");