4 * Copyright (C) 2013 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/clk.h>
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
27 #include <linux/irq.h>
28 #include <linux/irqdomain.h>
29 #include <linux/err.h>
30 #include <linux/slab.h>
31 #include <linux/module.h>
32 #include <linux/platform_data/irq-renesas-irqc.h>
33 #include <linux/pm_runtime.h>
35 #define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
37 #define IRQC_REQ_STS 0x00 /* Interrupt Request Status Register */
38 #define IRQC_EN_STS 0x04 /* Interrupt Enable Status Register */
39 #define IRQC_EN_SET 0x08 /* Interrupt Enable Set Register */
40 #define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
41 /* SYS-CPU vs. RT-CPU */
42 #define DETECT_STATUS 0x100 /* IRQn Detect Status Register */
43 #define MONITOR 0x104 /* IRQn Signal Level Monitor Register */
44 #define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */
45 #define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */
46 #define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */
47 #define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */
48 #define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */
49 #define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */
50 #define CHTEN_STS 0x120 /* Chattering Reduction Status Register */
51 #define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
52 /* IRQn Configuration Register */
63 void __iomem
*cpu_int_base
;
64 struct irqc_irq irq
[IRQC_IRQ_MAX
];
65 struct renesas_irqc_config config
;
66 unsigned int number_of_irqs
;
67 struct platform_device
*pdev
;
68 struct irq_chip irq_chip
;
69 struct irq_domain
*irq_domain
;
73 static void irqc_dbg(struct irqc_irq
*i
, char *str
)
75 dev_dbg(&i
->p
->pdev
->dev
, "%s (%d:%d:%d)\n",
76 str
, i
->requested_irq
, i
->hw_irq
, i
->domain_irq
);
79 static void irqc_irq_enable(struct irq_data
*d
)
81 struct irqc_priv
*p
= irq_data_get_irq_chip_data(d
);
82 int hw_irq
= irqd_to_hwirq(d
);
84 irqc_dbg(&p
->irq
[hw_irq
], "enable");
85 iowrite32(BIT(hw_irq
), p
->cpu_int_base
+ IRQC_EN_SET
);
88 static void irqc_irq_disable(struct irq_data
*d
)
90 struct irqc_priv
*p
= irq_data_get_irq_chip_data(d
);
91 int hw_irq
= irqd_to_hwirq(d
);
93 irqc_dbg(&p
->irq
[hw_irq
], "disable");
94 iowrite32(BIT(hw_irq
), p
->cpu_int_base
+ IRQC_EN_STS
);
97 static unsigned char irqc_sense
[IRQ_TYPE_SENSE_MASK
+ 1] = {
98 [IRQ_TYPE_LEVEL_LOW
] = 0x01,
99 [IRQ_TYPE_LEVEL_HIGH
] = 0x02,
100 [IRQ_TYPE_EDGE_FALLING
] = 0x04, /* Synchronous */
101 [IRQ_TYPE_EDGE_RISING
] = 0x08, /* Synchronous */
102 [IRQ_TYPE_EDGE_BOTH
] = 0x0c, /* Synchronous */
105 static int irqc_irq_set_type(struct irq_data
*d
, unsigned int type
)
107 struct irqc_priv
*p
= irq_data_get_irq_chip_data(d
);
108 int hw_irq
= irqd_to_hwirq(d
);
109 unsigned char value
= irqc_sense
[type
& IRQ_TYPE_SENSE_MASK
];
112 irqc_dbg(&p
->irq
[hw_irq
], "sense");
117 tmp
= ioread32(p
->iomem
+ IRQC_CONFIG(hw_irq
));
120 iowrite32(tmp
, p
->iomem
+ IRQC_CONFIG(hw_irq
));
124 static int irqc_irq_set_wake(struct irq_data
*d
, unsigned int on
)
126 struct irqc_priv
*p
= irq_data_get_irq_chip_data(d
);
139 static irqreturn_t
irqc_irq_handler(int irq
, void *dev_id
)
141 struct irqc_irq
*i
= dev_id
;
142 struct irqc_priv
*p
= i
->p
;
143 u32 bit
= BIT(i
->hw_irq
);
145 irqc_dbg(i
, "demux1");
147 if (ioread32(p
->iomem
+ DETECT_STATUS
) & bit
) {
148 iowrite32(bit
, p
->iomem
+ DETECT_STATUS
);
149 irqc_dbg(i
, "demux2");
150 generic_handle_irq(i
->domain_irq
);
156 static int irqc_irq_domain_map(struct irq_domain
*h
, unsigned int virq
,
159 struct irqc_priv
*p
= h
->host_data
;
161 p
->irq
[hw
].domain_irq
= virq
;
162 p
->irq
[hw
].hw_irq
= hw
;
164 irqc_dbg(&p
->irq
[hw
], "map");
165 irq_set_chip_data(virq
, h
->host_data
);
166 irq_set_chip_and_handler(virq
, &p
->irq_chip
, handle_level_irq
);
167 set_irq_flags(virq
, IRQF_VALID
); /* kill me now */
171 static struct irq_domain_ops irqc_irq_domain_ops
= {
172 .map
= irqc_irq_domain_map
,
173 .xlate
= irq_domain_xlate_twocell
,
176 static int irqc_probe(struct platform_device
*pdev
)
178 struct renesas_irqc_config
*pdata
= pdev
->dev
.platform_data
;
181 struct resource
*irq
;
182 struct irq_chip
*irq_chip
;
183 const char *name
= dev_name(&pdev
->dev
);
187 p
= kzalloc(sizeof(*p
), GFP_KERNEL
);
189 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
194 /* deal with driver instance configuration */
196 memcpy(&p
->config
, pdata
, sizeof(*pdata
));
199 platform_set_drvdata(pdev
, p
);
201 p
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
202 if (IS_ERR(p
->clk
)) {
203 dev_warn(&pdev
->dev
, "unable to get clock\n");
207 pm_runtime_enable(&pdev
->dev
);
208 pm_runtime_get_sync(&pdev
->dev
);
210 /* get hold of manadatory IOMEM */
211 io
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
213 dev_err(&pdev
->dev
, "not enough IOMEM resources\n");
218 /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
219 for (k
= 0; k
< IRQC_IRQ_MAX
; k
++) {
220 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, k
);
225 p
->irq
[k
].requested_irq
= irq
->start
;
228 p
->number_of_irqs
= k
;
229 if (p
->number_of_irqs
< 1) {
230 dev_err(&pdev
->dev
, "not enough IRQ resources\n");
235 /* ioremap IOMEM and setup read/write callbacks */
236 p
->iomem
= ioremap_nocache(io
->start
, resource_size(io
));
238 dev_err(&pdev
->dev
, "failed to remap IOMEM\n");
243 p
->cpu_int_base
= p
->iomem
+ IRQC_INT_CPU_BASE(0); /* SYS-SPI */
245 irq_chip
= &p
->irq_chip
;
246 irq_chip
->name
= name
;
247 irq_chip
->irq_mask
= irqc_irq_disable
;
248 irq_chip
->irq_unmask
= irqc_irq_enable
;
249 irq_chip
->irq_set_type
= irqc_irq_set_type
;
250 irq_chip
->irq_set_wake
= irqc_irq_set_wake
;
251 irq_chip
->flags
= IRQCHIP_MASK_ON_SUSPEND
;
253 p
->irq_domain
= irq_domain_add_simple(pdev
->dev
.of_node
,
256 &irqc_irq_domain_ops
, p
);
257 if (!p
->irq_domain
) {
259 dev_err(&pdev
->dev
, "cannot initialize irq domain\n");
263 /* request interrupts one by one */
264 for (k
= 0; k
< p
->number_of_irqs
; k
++) {
265 if (request_irq(p
->irq
[k
].requested_irq
, irqc_irq_handler
,
266 0, name
, &p
->irq
[k
])) {
267 dev_err(&pdev
->dev
, "failed to request IRQ\n");
273 dev_info(&pdev
->dev
, "driving %d irqs\n", p
->number_of_irqs
);
275 /* warn in case of mismatch if irq base is specified */
276 if (p
->config
.irq_base
) {
277 if (p
->config
.irq_base
!= p
->irq
[0].domain_irq
)
278 dev_warn(&pdev
->dev
, "irq base mismatch (%d/%d)\n",
279 p
->config
.irq_base
, p
->irq
[0].domain_irq
);
285 free_irq(p
->irq
[k
].requested_irq
, &p
->irq
[k
]);
287 irq_domain_remove(p
->irq_domain
);
291 pm_runtime_put(&pdev
->dev
);
292 pm_runtime_disable(&pdev
->dev
);
298 static int irqc_remove(struct platform_device
*pdev
)
300 struct irqc_priv
*p
= platform_get_drvdata(pdev
);
303 for (k
= 0; k
< p
->number_of_irqs
; k
++)
304 free_irq(p
->irq
[k
].requested_irq
, &p
->irq
[k
]);
306 irq_domain_remove(p
->irq_domain
);
308 pm_runtime_put(&pdev
->dev
);
309 pm_runtime_disable(&pdev
->dev
);
314 static const struct of_device_id irqc_dt_ids
[] = {
315 { .compatible
= "renesas,irqc", },
318 MODULE_DEVICE_TABLE(of
, irqc_dt_ids
);
320 static struct platform_driver irqc_device_driver
= {
322 .remove
= irqc_remove
,
324 .name
= "renesas_irqc",
325 .of_match_table
= irqc_dt_ids
,
329 static int __init
irqc_init(void)
331 return platform_driver_register(&irqc_device_driver
);
333 postcore_initcall(irqc_init
);
335 static void __exit
irqc_exit(void)
337 platform_driver_unregister(&irqc_device_driver
);
339 module_exit(irqc_exit
);
341 MODULE_AUTHOR("Magnus Damm");
342 MODULE_DESCRIPTION("Renesas IRQC Driver");
343 MODULE_LICENSE("GPL v2");