drivers/irqchip/irq-sirfsoc.c

   1 /*
   2  * interrupt controller support for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/init.h>
  10 #include <linux/io.h>
  11 #include <linux/irq.h>
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14 #include <linux/irqchip.h>
  15 #include <linux/irqdomain.h>
  16 #include <linux/syscore_ops.h>
  17 #include <asm/mach/irq.h>
  18 #include <asm/exception.h>
  19
  20 #define SIRFSOC_INT_RISC_MASK0          0x0018
  21 #define SIRFSOC_INT_RISC_MASK1          0x001C
  22 #define SIRFSOC_INT_RISC_LEVEL0         0x0020
  23 #define SIRFSOC_INT_RISC_LEVEL1         0x0024
  24 #define SIRFSOC_INIT_IRQ_ID             0x0038
  25 #define SIRFSOC_INT_BASE_OFFSET         0x0004
  26
  27 #define SIRFSOC_NUM_IRQS                64
  28 #define SIRFSOC_NUM_BANKS               (SIRFSOC_NUM_IRQS / 32)
  29
  30 static struct irq_domain *sirfsoc_irqdomain;
  31
  32 static __init void sirfsoc_alloc_gc(void __iomem *base)
  33 {
  34         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  35         unsigned int set = IRQ_LEVEL;
  36         struct irq_chip_generic *gc;
  37         struct irq_chip_type *ct;
  38         int i;
  39
  40         irq_alloc_domain_generic_chips(sirfsoc_irqdomain, 32, 1, "irq_sirfsoc",
  41                                        handle_level_irq, clr, set,
  42                                        IRQ_GC_INIT_MASK_CACHE);
  43
  44         for (i = 0; i < SIRFSOC_NUM_BANKS; i++) {
  45                 gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, i * 32);
  46                 gc->reg_base = base + i * SIRFSOC_INT_BASE_OFFSET;
  47                 ct = gc->chip_types;
  48                 ct->chip.irq_mask = irq_gc_mask_clr_bit;
  49                 ct->chip.irq_unmask = irq_gc_mask_set_bit;
  50                 ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
  51         }
  52 }
  53
  54 static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
  55 {
  56         void __iomem *base = sirfsoc_irqdomain->host_data;
  57         u32 irqstat;
  58
  59         irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
  60         handle_domain_irq(sirfsoc_irqdomain, irqstat & 0xff, regs);
  61 }
  62
  63 static int __init sirfsoc_irq_init(struct device_node *np,
  64         struct device_node *parent)
  65 {
  66         void __iomem *base = of_iomap(np, 0);
  67         if (!base)
  68                 panic("unable to map intc cpu registers\n");
  69
  70         sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
  71                                                   &irq_generic_chip_ops, base);
  72         sirfsoc_alloc_gc(base);
  73
  74         writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
  75         writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
  76
  77         writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
  78         writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
  79
  80         set_handle_irq(sirfsoc_handle_irq);
  81
  82         return 0;
  83 }
  84 IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
  85
  86 struct sirfsoc_irq_status {
  87         u32 mask0;
  88         u32 mask1;
  89         u32 level0;
  90         u32 level1;
  91 };
  92
  93 static struct sirfsoc_irq_status sirfsoc_irq_st;
  94
  95 static int sirfsoc_irq_suspend(void)
  96 {
  97         void __iomem *base = sirfsoc_irqdomain->host_data;
  98
  99         sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
 100         sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
 101         sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
 102         sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
 103
 104         return 0;
 105 }
 106
 107 static void sirfsoc_irq_resume(void)
 108 {
 109         void __iomem *base = sirfsoc_irqdomain->host_data;
 110
 111         writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
 112         writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
 113         writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
 114         writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
 115 }
 116
 117 static struct syscore_ops sirfsoc_irq_syscore_ops = {
 118         .suspend        = sirfsoc_irq_suspend,
 119         .resume         = sirfsoc_irq_resume,
 120 };
 121
 122 static int __init sirfsoc_irq_pm_init(void)
 123 {
 124         if (!sirfsoc_irqdomain)
 125                 return 0;
 126
 127         register_syscore_ops(&sirfsoc_irq_syscore_ops);
 128         return 0;
 129 }
 130 device_initcall(sirfsoc_irq_pm_init);