1 /*************************************************************************/
2 /* $Id: hfc4s8s_l1.c,v 1.10 2005/02/09 16:31:09 martinb1 Exp $ */
3 /* HFC-4S/8S low layer interface for Cologne Chip HFC-4S/8S isdn chips */
4 /* The low layer (L1) is implemented as a loadable module for usage with */
5 /* the HiSax isdn driver for passive cards. */
7 /* Author: Werner Cornelius */
8 /* (C) 2003 Cornelius Consult (werner@cornelius-consult.de) */
10 /* Driver maintained by Cologne Chip */
11 /* - Martin Bachem, support@colognechip.com */
13 /* This driver only works with chip revisions >= 1, older revision 0 */
14 /* engineering samples (only first manufacturer sample cards) will not */
15 /* work and are rejected by the driver. */
17 /* This file distributed under the GNU GPL. */
19 /* See Version History at the end of this file */
21 /*************************************************************************/
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/config.h>
26 #include <linux/pci.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/timer.h>
30 #include <linux/skbuff.h>
31 #include <linux/wait.h>
33 #include "hfc4s8s_l1.h"
35 static const char hfc4s8s_rev
[] = "Revision: 1.10";
37 /***************************************************************/
38 /* adjustable transparent mode fifo threshold */
39 /* The value defines the used fifo threshold with the equation */
41 /* notify number of bytes = 2 * 2 ^ TRANS_FIFO_THRES */
43 /* The default value is 5 which results in a buffer size of 64 */
44 /* and an interrupt rate of 8ms. */
45 /* The maximum value is 7 due to fifo size restrictions. */
46 /* Values below 3-4 are not recommended due to high interrupt */
47 /* load of the processor. For non critical applications the */
48 /* value should be raised to 7 to reduce any interrupt overhead*/
49 /***************************************************************/
50 #define TRANS_FIFO_THRES 5
55 #define CLOCKMODE_0 0 /* ext. 24.576 MhZ clk freq, int. single clock mode */
56 #define CLOCKMODE_1 1 /* ext. 49.576 MhZ clk freq, int. single clock mode */
57 #define CHIP_ID_SHIFT 4
59 #define MAX_D_FRAME_SIZE 270
60 #define MAX_B_FRAME_SIZE 1536
61 #define TRANS_TIMER_MODE (TRANS_FIFO_THRES & 0xf)
62 #define TRANS_FIFO_BYTES (2 << TRANS_FIFO_THRES)
63 #define MAX_F_CNT 0x0f
65 #define CLKDEL_NT 0x6c
70 #define L1_TIMER_T4 2 /* minimum in jiffies */
71 #define L1_TIMER_T3 (7 * HZ) /* activation timeout */
72 #define L1_TIMER_T1 ((120 * HZ) / 1000) /* NT mode deactivation timeout */
80 /* private driver_data */
88 static struct pci_device_id hfc4s8s_ids
[] = {
89 {.vendor
= PCI_VENDOR_ID_CCD
,
90 .device
= PCI_DEVICE_ID_4S
,
94 (unsigned long) &((hfc4s8s_param
) {CHIP_ID_4S
, CLOCKMODE_0
, 4,
95 "HFC-4S Evaluation Board"}),
97 {.vendor
= PCI_VENDOR_ID_CCD
,
98 .device
= PCI_DEVICE_ID_8S
,
102 (unsigned long) &((hfc4s8s_param
) {CHIP_ID_8S
, CLOCKMODE_0
, 8,
103 "HFC-8S Evaluation Board"}),
105 {.vendor
= PCI_VENDOR_ID_CCD
,
106 .device
= PCI_DEVICE_ID_4S
,
110 (unsigned long) &((hfc4s8s_param
) {CHIP_ID_4S
, CLOCKMODE_1
, 4,
113 {.vendor
= PCI_VENDOR_ID_CCD
,
114 .device
= PCI_DEVICE_ID_8S
,
118 (unsigned long) &((hfc4s8s_param
) {CHIP_ID_8S
, CLOCKMODE_1
, 8,
124 MODULE_DEVICE_TABLE(pci
, hfc4s8s_ids
);
126 MODULE_AUTHOR("Werner Cornelius, werner@cornelius-consult.de");
127 MODULE_DESCRIPTION("ISDN layer 1 for Cologne Chip HFC-4S/8S chips");
128 MODULE_LICENSE("GPL");
133 struct hfc4s8s_btype
{
135 struct hisax_b_if b_if
;
136 struct hfc4s8s_l1
*l1p
;
137 struct sk_buff_head tx_queue
;
138 struct sk_buff
*tx_skb
;
139 struct sk_buff
*rx_skb
;
150 struct _hfc4s8s_hw
*hw
; /* pointer to hardware area */
151 int l1_state
; /* actual l1 state */
152 struct timer_list l1_timer
; /* layer 1 timer structure */
153 int nt_mode
; /* set to nt mode */
154 int st_num
; /* own index */
155 int enabled
; /* interface is enabled */
156 struct sk_buff_head d_tx_queue
; /* send queue */
157 int tx_cnt
; /* bytes to send */
158 struct hisax_d_if d_if
; /* D-channel interface */
159 struct hfc4s8s_btype b_ch
[2]; /* B-channel data */
160 struct hisax_b_if
*b_table
[2];
163 /**********************/
164 /* hardware structure */
165 /**********************/
166 typedef struct _hfc4s8s_hw
{
177 hfc4s8s_param driver_data
;
180 struct work_struct tqueue
;
181 struct hfc4s8s_l1 l1
[HFC_MAX_ST
];
186 volatile u_char r_irq_statech
; /* active isdn l1 status */
187 u_char r_irqmsk_statchg
; /* enabled isdn status ints */
188 u_char r_irq_fifo_blx
[8]; /* fifo status registers */
189 u_char fifo_rx_trans_enables
[8]; /* mask for enabled transparent rx fifos */
190 u_char fifo_slow_timer_service
[8]; /* mask for fifos needing slower timer service */
191 volatile u_char r_irq_oview
; /* contents of overview register */
192 volatile u_char timer_irq
;
193 int timer_usg_cnt
; /* number of channels using timer */
199 /***************************/
200 /* inline function defines */
201 /***************************/
202 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM /* inline functions mempry mapped */
204 /* memory write and dummy IO read to avoid PCI byte merge problems */
205 #define Write_hfc8(a,b,c) {(*((volatile u_char *)(a->membase+b)) = c); inb(a->iobase+4);}
206 /* memory write without dummy IO access for fifo data access */
207 #define fWrite_hfc8(a,b,c) (*((volatile u_char *)(a->membase+b)) = c)
208 #define Read_hfc8(a,b) (*((volatile u_char *)(a->membase+b)))
209 #define Write_hfc16(a,b,c) (*((volatile unsigned short *)(a->membase+b)) = c)
210 #define Read_hfc16(a,b) (*((volatile unsigned short *)(a->membase+b)))
211 #define Write_hfc32(a,b,c) (*((volatile unsigned long *)(a->membase+b)) = c)
212 #define Read_hfc32(a,b) (*((volatile unsigned long *)(a->membase+b)))
213 #define wait_busy(a) {while ((Read_hfc8(a, R_STATUS) & M_BUSY));}
214 #define PCI_ENA_MEMIO 0x03
218 /* inline functions io mapped */
220 SetRegAddr(hfc4s8s_hw
* a
, u_char b
)
222 outb(b
, (a
->iobase
) + 4);
226 GetRegAddr(hfc4s8s_hw
* a
)
228 return (inb((volatile u_int
) (a
->iobase
+ 4)));
233 Write_hfc8(hfc4s8s_hw
* a
, u_char b
, u_char c
)
240 fWrite_hfc8(hfc4s8s_hw
* a
, u_char c
)
246 Write_hfc16(hfc4s8s_hw
* a
, u_char b
, u_short c
)
253 Write_hfc32(hfc4s8s_hw
* a
, u_char b
, u_long c
)
260 fWrite_hfc32(hfc4s8s_hw
* a
, u_long c
)
266 Read_hfc8(hfc4s8s_hw
* a
, u_char b
)
269 return (inb((volatile u_int
) a
->iobase
));
273 fRead_hfc8(hfc4s8s_hw
* a
)
275 return (inb((volatile u_int
) a
->iobase
));
279 static inline u_short
280 Read_hfc16(hfc4s8s_hw
* a
, u_char b
)
283 return (inw((volatile u_int
) a
->iobase
));
287 Read_hfc32(hfc4s8s_hw
* a
, u_char b
)
290 return (inl((volatile u_int
) a
->iobase
));
294 fRead_hfc32(hfc4s8s_hw
* a
)
296 return (inl((volatile u_int
) a
->iobase
));
300 wait_busy(hfc4s8s_hw
* a
)
302 SetRegAddr(a
, R_STATUS
);
303 while (inb((volatile u_int
) a
->iobase
) & M_BUSY
);
306 #define PCI_ENA_REGIO 0x01
308 #endif /* CONFIG_HISAX_HFC4S8S_PCIMEM */
310 /******************************************************/
311 /* function to read critical counter registers that */
312 /* may be udpated by the chip during read */
313 /******************************************************/
314 static volatile u_char
315 Read_hfc8_stable(hfc4s8s_hw
* hw
, int reg
)
319 ref8
= Read_hfc8(hw
, reg
);
320 while (((in8
= Read_hfc8(hw
, reg
)) != ref8
)) {
327 Read_hfc16_stable(hfc4s8s_hw
* hw
, int reg
)
332 ref16
= Read_hfc16(hw
, reg
);
333 while (((in16
= Read_hfc16(hw
, reg
)) != ref16
)) {
339 /*****************************/
340 /* D-channel call from HiSax */
341 /*****************************/
343 dch_l2l1(struct hisax_d_if
*iface
, int pr
, void *arg
)
345 struct hfc4s8s_l1
*l1
= iface
->ifc
.priv
;
346 struct sk_buff
*skb
= (struct sk_buff
*) arg
;
351 case (PH_DATA
| REQUEST
):
356 spin_lock_irqsave(&l1
->lock
, flags
);
357 skb_queue_tail(&l1
->d_tx_queue
, skb
);
358 if ((skb_queue_len(&l1
->d_tx_queue
) == 1) &&
360 l1
->hw
->mr
.r_irq_fifo_blx
[l1
->st_num
] |=
362 spin_unlock_irqrestore(&l1
->lock
, flags
);
363 schedule_work(&l1
->hw
->tqueue
);
365 spin_unlock_irqrestore(&l1
->lock
, flags
);
368 case (PH_ACTIVATE
| REQUEST
):
372 if (l1
->l1_state
< 6) {
373 spin_lock_irqsave(&l1
->lock
,
376 Write_hfc8(l1
->hw
, R_ST_SEL
,
378 Write_hfc8(l1
->hw
, A_ST_WR_STA
,
380 mod_timer(&l1
->l1_timer
,
381 jiffies
+ L1_TIMER_T3
);
382 spin_unlock_irqrestore(&l1
->lock
,
384 } else if (l1
->l1_state
== 7)
385 l1
->d_if
.ifc
.l1l2(&l1
->d_if
.ifc
,
390 if (l1
->l1_state
!= 3) {
391 spin_lock_irqsave(&l1
->lock
,
393 Write_hfc8(l1
->hw
, R_ST_SEL
,
395 Write_hfc8(l1
->hw
, A_ST_WR_STA
,
397 spin_unlock_irqrestore(&l1
->lock
,
399 } else if (l1
->l1_state
== 3)
400 l1
->d_if
.ifc
.l1l2(&l1
->d_if
.ifc
,
409 "HFC-4S/8S: Unknown D-chan cmd 0x%x received, ignored\n",
414 l1
->d_if
.ifc
.l1l2(&l1
->d_if
.ifc
,
415 PH_DEACTIVATE
| INDICATION
, NULL
);
418 /*****************************/
419 /* B-channel call from HiSax */
420 /*****************************/
422 bch_l2l1(struct hisax_if
*ifc
, int pr
, void *arg
)
424 struct hfc4s8s_btype
*bch
= ifc
->priv
;
425 struct hfc4s8s_l1
*l1
= bch
->l1p
;
426 struct sk_buff
*skb
= (struct sk_buff
*) arg
;
427 int mode
= (int) arg
;
432 case (PH_DATA
| REQUEST
):
433 if (!l1
->enabled
|| (bch
->mode
== L1_MODE_NULL
)) {
437 spin_lock_irqsave(&l1
->lock
, flags
);
438 skb_queue_tail(&bch
->tx_queue
, skb
);
439 if (!bch
->tx_skb
&& (bch
->tx_cnt
<= 0)) {
440 l1
->hw
->mr
.r_irq_fifo_blx
[l1
->st_num
] |=
441 ((bch
->bchan
== 1) ? 1 : 4);
442 spin_unlock_irqrestore(&l1
->lock
, flags
);
443 schedule_work(&l1
->hw
->tqueue
);
445 spin_unlock_irqrestore(&l1
->lock
, flags
);
448 case (PH_ACTIVATE
| REQUEST
):
449 case (PH_DEACTIVATE
| REQUEST
):
452 if (pr
== (PH_DEACTIVATE
| REQUEST
))
457 spin_lock_irqsave(&l1
->lock
,
459 l1
->hw
->mr
.timer_usg_cnt
++;
461 fifo_slow_timer_service
[l1
->
466 Write_hfc8(l1
->hw
, R_FIFO
,
471 Write_hfc8(l1
->hw
, A_CON_HDLC
, 0xc); /* HDLC mode, flag fill, connect ST */
472 Write_hfc8(l1
->hw
, A_SUBCH_CFG
, 0); /* 8 bits */
473 Write_hfc8(l1
->hw
, A_IRQ_MSK
, 1); /* enable TX interrupts for hdlc */
474 Write_hfc8(l1
->hw
, A_INC_RES_FIFO
, 2); /* reset fifo */
477 Write_hfc8(l1
->hw
, R_FIFO
,
482 Write_hfc8(l1
->hw
, A_CON_HDLC
, 0xc); /* HDLC mode, flag fill, connect ST */
483 Write_hfc8(l1
->hw
, A_SUBCH_CFG
, 0); /* 8 bits */
484 Write_hfc8(l1
->hw
, A_IRQ_MSK
, 1); /* enable RX interrupts for hdlc */
485 Write_hfc8(l1
->hw
, A_INC_RES_FIFO
, 2); /* reset fifo */
487 Write_hfc8(l1
->hw
, R_ST_SEL
,
489 l1
->hw
->mr
.r_ctrl0
|=
491 Write_hfc8(l1
->hw
, A_ST_CTRL0
,
493 bch
->mode
= L1_MODE_HDLC
;
494 spin_unlock_irqrestore(&l1
->lock
,
497 bch
->b_if
.ifc
.l1l2(&bch
->b_if
.ifc
,
504 spin_lock_irqsave(&l1
->lock
,
507 fifo_rx_trans_enables
[l1
->
512 l1
->hw
->mr
.timer_usg_cnt
++;
513 Write_hfc8(l1
->hw
, R_FIFO
,
518 Write_hfc8(l1
->hw
, A_CON_HDLC
, 0xf); /* Transparent mode, 1 fill, connect ST */
519 Write_hfc8(l1
->hw
, A_SUBCH_CFG
, 0); /* 8 bits */
520 Write_hfc8(l1
->hw
, A_IRQ_MSK
, 0); /* disable TX interrupts */
521 Write_hfc8(l1
->hw
, A_INC_RES_FIFO
, 2); /* reset fifo */
524 Write_hfc8(l1
->hw
, R_FIFO
,
529 Write_hfc8(l1
->hw
, A_CON_HDLC
, 0xf); /* Transparent mode, 1 fill, connect ST */
530 Write_hfc8(l1
->hw
, A_SUBCH_CFG
, 0); /* 8 bits */
531 Write_hfc8(l1
->hw
, A_IRQ_MSK
, 0); /* disable RX interrupts */
532 Write_hfc8(l1
->hw
, A_INC_RES_FIFO
, 2); /* reset fifo */
534 Write_hfc8(l1
->hw
, R_ST_SEL
,
536 l1
->hw
->mr
.r_ctrl0
|=
538 Write_hfc8(l1
->hw
, A_ST_CTRL0
,
540 bch
->mode
= L1_MODE_TRANS
;
541 spin_unlock_irqrestore(&l1
->lock
,
544 bch
->b_if
.ifc
.l1l2(&bch
->b_if
.ifc
,
551 if (bch
->mode
== L1_MODE_NULL
)
553 spin_lock_irqsave(&l1
->lock
,
556 fifo_slow_timer_service
[l1
->
562 fifo_rx_trans_enables
[l1
->
567 l1
->hw
->mr
.timer_usg_cnt
--;
568 Write_hfc8(l1
->hw
, R_FIFO
,
573 Write_hfc8(l1
->hw
, A_IRQ_MSK
, 0); /* disable TX interrupts */
575 Write_hfc8(l1
->hw
, R_FIFO
,
580 Write_hfc8(l1
->hw
, A_IRQ_MSK
, 0); /* disable RX interrupts */
581 Write_hfc8(l1
->hw
, R_ST_SEL
,
583 l1
->hw
->mr
.r_ctrl0
&=
585 Write_hfc8(l1
->hw
, A_ST_CTRL0
,
587 spin_unlock_irqrestore(&l1
->lock
,
590 bch
->mode
= L1_MODE_NULL
;
591 bch
->b_if
.ifc
.l1l2(&bch
->b_if
.ifc
,
596 dev_kfree_skb(bch
->tx_skb
);
600 dev_kfree_skb(bch
->rx_skb
);
603 skb_queue_purge(&bch
->tx_queue
);
609 /* timer is only used when at least one b channel */
610 /* is set up to transparent mode */
611 if (l1
->hw
->mr
.timer_usg_cnt
) {
612 Write_hfc8(l1
->hw
, R_IRQMSK_MISC
,
615 Write_hfc8(l1
->hw
, R_IRQMSK_MISC
, 0);
622 "HFC-4S/8S: Unknown B-chan cmd 0x%x received, ignored\n",
627 bch
->b_if
.ifc
.l1l2(&bch
->b_if
.ifc
,
628 PH_DEACTIVATE
| INDICATION
, NULL
);
631 /**************************/
632 /* layer 1 timer function */
633 /**************************/
635 hfc_l1_timer(struct hfc4s8s_l1
*l1
)
642 spin_lock_irqsave(&l1
->lock
, flags
);
645 Write_hfc8(l1
->hw
, R_ST_SEL
, l1
->st_num
);
646 Write_hfc8(l1
->hw
, A_ST_WR_STA
, 0x11);
647 spin_unlock_irqrestore(&l1
->lock
, flags
);
648 l1
->d_if
.ifc
.l1l2(&l1
->d_if
.ifc
,
649 PH_DEACTIVATE
| INDICATION
, NULL
);
650 spin_lock_irqsave(&l1
->lock
, flags
);
652 Write_hfc8(l1
->hw
, A_ST_WR_STA
, 0x1);
653 spin_unlock_irqrestore(&l1
->lock
, flags
);
655 /* activation timed out */
656 Write_hfc8(l1
->hw
, R_ST_SEL
, l1
->st_num
);
657 Write_hfc8(l1
->hw
, A_ST_WR_STA
, 0x13);
658 spin_unlock_irqrestore(&l1
->lock
, flags
);
659 l1
->d_if
.ifc
.l1l2(&l1
->d_if
.ifc
,
660 PH_DEACTIVATE
| INDICATION
, NULL
);
661 spin_lock_irqsave(&l1
->lock
, flags
);
662 Write_hfc8(l1
->hw
, R_ST_SEL
, l1
->st_num
);
663 Write_hfc8(l1
->hw
, A_ST_WR_STA
, 0x3);
664 spin_unlock_irqrestore(&l1
->lock
, flags
);
668 /****************************************/
669 /* a complete D-frame has been received */
670 /****************************************/
672 rx_d_frame(struct hfc4s8s_l1
*l1p
, int ech
)
684 Write_hfc8(l1p
->hw
, R_FIFO
,
685 (l1p
->st_num
* 8 + ((ech
) ? 7 : 5)));
688 f1
= Read_hfc8_stable(l1p
->hw
, A_F1
);
689 f2
= Read_hfc8(l1p
->hw
, A_F2
);
692 df
= f1
- f2
+ MAX_F_CNT
+ 1;
696 return; /* no complete frame in fifo */
699 z1
= Read_hfc16_stable(l1p
->hw
, A_Z1
);
700 z2
= Read_hfc16(l1p
->hw
, A_Z2
);
706 if (!(skb
= dev_alloc_skb(MAX_D_FRAME_SIZE
))) {
708 "HFC-4S/8S: Could not allocate D/E "
709 "channel receive buffer");
710 Write_hfc8(l1p
->hw
, A_INC_RES_FIFO
, 2);
715 if (((z1
< 4) || (z1
> MAX_D_FRAME_SIZE
))) {
718 /* remove errornous D frame */
721 Write_hfc8(l1p
->hw
, A_INC_RES_FIFO
, 2);
725 /* read errornous D frame */
727 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
728 SetRegAddr(l1p
->hw
, A_FIFO_DATA0
);
732 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
733 Read_hfc32(l1p
->hw
, A_FIFO_DATA0
);
735 fRead_hfc32(l1p
->hw
);
741 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
742 Read_hfc8(l1p
->hw
, A_FIFO_DATA0
);
747 Write_hfc8(l1p
->hw
, A_INC_RES_FIFO
, 1);
755 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
756 SetRegAddr(l1p
->hw
, A_FIFO_DATA0
);
760 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
761 *((unsigned long *) cp
) =
762 Read_hfc32(l1p
->hw
, A_FIFO_DATA0
);
764 *((unsigned long *) cp
) = fRead_hfc32(l1p
->hw
);
771 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
772 *cp
++ = Read_hfc8(l1p
->hw
, A_FIFO_DATA0
);
774 *cp
++ = fRead_hfc8(l1p
->hw
);
777 Write_hfc8(l1p
->hw
, A_INC_RES_FIFO
, 1); /* increment f counter */
783 skb
->len
= (cp
- skb
->data
) - 2;
785 l1p
->d_if
.ifc
.l1l2(&l1p
->d_if
.ifc
,
786 PH_DATA_E
| INDICATION
,
789 l1p
->d_if
.ifc
.l1l2(&l1p
->d_if
.ifc
,
790 PH_DATA
| INDICATION
,
796 /*************************************************************/
797 /* a B-frame has been received (perhaps not fully completed) */
798 /*************************************************************/
800 rx_b_frame(struct hfc4s8s_btype
*bch
)
802 int z1
, z2
, hdlc_complete
;
804 struct hfc4s8s_l1
*l1
= bch
->l1p
;
807 if (!l1
->enabled
|| (bch
->mode
== L1_MODE_NULL
))
812 Write_hfc8(l1
->hw
, R_FIFO
,
813 (l1
->st_num
* 8 + ((bch
->bchan
== 1) ? 1 : 3)));
816 if (bch
->mode
== L1_MODE_HDLC
) {
817 f1
= Read_hfc8_stable(l1
->hw
, A_F1
);
818 f2
= Read_hfc8(l1
->hw
, A_F2
);
819 hdlc_complete
= ((f1
^ f2
) & MAX_F_CNT
);
822 z1
= Read_hfc16_stable(l1
->hw
, A_Z1
);
823 z2
= Read_hfc16(l1
->hw
, A_Z2
);
833 if (!(skb
= bch
->rx_skb
)) {
836 dev_alloc_skb((bch
->mode
==
838 : (MAX_B_FRAME_SIZE
+ 3)))) {
840 "HFC-4S/8S: Could not allocate B "
841 "channel receive buffer");
844 bch
->rx_ptr
= skb
->data
;
848 skb
->len
= (bch
->rx_ptr
- skb
->data
) + z1
;
850 /* HDLC length check */
851 if ((bch
->mode
== L1_MODE_HDLC
) &&
852 ((hdlc_complete
&& (skb
->len
< 4)) ||
853 (skb
->len
> (MAX_B_FRAME_SIZE
+ 3)))) {
856 bch
->rx_ptr
= skb
->data
;
857 Write_hfc8(l1
->hw
, A_INC_RES_FIFO
, 2); /* reset fifo */
861 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
862 SetRegAddr(l1
->hw
, A_FIFO_DATA0
);
866 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
867 *((unsigned long *) bch
->rx_ptr
) =
868 Read_hfc32(l1
->hw
, A_FIFO_DATA0
);
870 *((unsigned long *) bch
->rx_ptr
) =
878 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
879 *(bch
->rx_ptr
++) = Read_hfc8(l1
->hw
, A_FIFO_DATA0
);
881 *(bch
->rx_ptr
++) = fRead_hfc8(l1
->hw
);
885 /* increment f counter */
886 Write_hfc8(l1
->hw
, A_INC_RES_FIFO
, 1);
893 bch
->rx_ptr
= skb
->data
;
898 if (hdlc_complete
|| (bch
->mode
== L1_MODE_TRANS
)) {
901 bch
->b_if
.ifc
.l1l2(&bch
->b_if
.ifc
,
902 PH_DATA
| INDICATION
, skb
);
908 /********************************************/
909 /* a D-frame has been/should be transmitted */
910 /********************************************/
912 tx_d_frame(struct hfc4s8s_l1
*l1p
)
919 if (l1p
->l1_state
!= 7)
923 Write_hfc8(l1p
->hw
, R_FIFO
, (l1p
->st_num
* 8 + 4));
926 f1
= Read_hfc8(l1p
->hw
, A_F1
);
927 f2
= Read_hfc8_stable(l1p
->hw
, A_F2
);
929 if ((f1
^ f2
) & MAX_F_CNT
)
930 return; /* fifo is still filled */
932 if (l1p
->tx_cnt
> 0) {
935 l1p
->d_if
.ifc
.l1l2(&l1p
->d_if
.ifc
, PH_DATA
| CONFIRM
,
939 if ((skb
= skb_dequeue(&l1p
->d_tx_queue
))) {
942 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
943 SetRegAddr(l1p
->hw
, A_FIFO_DATA0
);
947 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
948 fWrite_hfc32(l1p
->hw
, A_FIFO_DATA0
,
949 *(unsigned long *) cp
);
951 SetRegAddr(l1p
->hw
, A_FIFO_DATA0
);
952 fWrite_hfc32(l1p
->hw
, *(unsigned long *) cp
);
958 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
960 fWrite_hfc8(l1p
->hw
, A_FIFO_DATA0
, *cp
++);
963 fWrite_hfc8(l1p
->hw
, *cp
++);
966 l1p
->tx_cnt
= skb
->truesize
;
967 Write_hfc8(l1p
->hw
, A_INC_RES_FIFO
, 1); /* increment f counter */
974 /******************************************************/
975 /* a B-frame may be transmitted (or is not completed) */
976 /******************************************************/
978 tx_b_frame(struct hfc4s8s_btype
*bch
)
981 struct hfc4s8s_l1
*l1
= bch
->l1p
;
983 int cnt
, max
, hdlc_num
, ack_len
= 0;
985 if (!l1
->enabled
|| (bch
->mode
== L1_MODE_NULL
))
989 Write_hfc8(l1
->hw
, R_FIFO
,
990 (l1
->st_num
* 8 + ((bch
->bchan
== 1) ? 0 : 2)));
994 if (bch
->mode
== L1_MODE_HDLC
) {
995 hdlc_num
= Read_hfc8(l1
->hw
, A_F1
) & MAX_F_CNT
;
997 (Read_hfc8_stable(l1
->hw
, A_F2
) & MAX_F_CNT
);
1001 break; /* fifo still filled up with hdlc frames */
1005 if (!(skb
= bch
->tx_skb
)) {
1006 if (!(skb
= skb_dequeue(&bch
->tx_queue
))) {
1007 l1
->hw
->mr
.fifo_slow_timer_service
[l1
->
1009 &= ~((bch
->bchan
== 1) ? 1 : 4);
1010 break; /* list empty */
1017 l1
->hw
->mr
.fifo_slow_timer_service
[l1
->st_num
] |=
1018 ((bch
->bchan
== 1) ? 1 : 4);
1020 l1
->hw
->mr
.fifo_slow_timer_service
[l1
->st_num
] &=
1021 ~((bch
->bchan
== 1) ? 1 : 4);
1023 max
= Read_hfc16_stable(l1
->hw
, A_Z2
);
1024 max
-= Read_hfc16(l1
->hw
, A_Z1
);
1030 break; /* don't write to small amounts of bytes */
1032 cnt
= skb
->len
- bch
->tx_cnt
;
1035 cp
= skb
->data
+ bch
->tx_cnt
;
1038 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
1039 SetRegAddr(l1
->hw
, A_FIFO_DATA0
);
1042 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
1043 fWrite_hfc32(l1
->hw
, A_FIFO_DATA0
,
1044 *(unsigned long *) cp
);
1046 fWrite_hfc32(l1
->hw
, *(unsigned long *) cp
);
1053 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
1054 fWrite_hfc8(l1
->hw
, A_FIFO_DATA0
, *cp
++);
1056 fWrite_hfc8(l1
->hw
, *cp
++);
1059 if (bch
->tx_cnt
>= skb
->len
) {
1060 if (bch
->mode
== L1_MODE_HDLC
) {
1061 /* increment f counter */
1062 Write_hfc8(l1
->hw
, A_INC_RES_FIFO
, 1);
1064 ack_len
+= skb
->truesize
;
1070 Write_hfc8(l1
->hw
, R_FIFO
,
1072 ((bch
->bchan
== 1) ? 0 : 2)));
1077 bch
->b_if
.ifc
.l1l2((struct hisax_if
*) &bch
->b_if
,
1078 PH_DATA
| CONFIRM
, (void *) ack_len
);
1081 /*************************************/
1082 /* bottom half handler for interrupt */
1083 /*************************************/
1085 hfc4s8s_bh(hfc4s8s_hw
* hw
)
1088 struct hfc4s8s_l1
*l1p
;
1089 volatile u_char
*fifo_stat
;
1092 /* handle layer 1 state changes */
1096 if ((b
& hw
->mr
.r_irq_statech
)) {
1097 /* reset l1 event */
1098 hw
->mr
.r_irq_statech
&= ~b
;
1101 u_char oldstate
= l1p
->l1_state
;
1103 Write_hfc8(l1p
->hw
, R_ST_SEL
,
1110 && (l1p
->l1_state
!= 3))
1111 l1p
->d_if
.ifc
.l1l2(&l1p
->
1119 if (l1p
->l1_state
!= 2) {
1120 del_timer(&l1p
->l1_timer
);
1121 if (l1p
->l1_state
== 3) {
1131 /* allow transition */
1132 Write_hfc8(hw
, A_ST_WR_STA
,
1134 mod_timer(&l1p
->l1_timer
,
1139 "HFC-4S/8S: NT ch %d l1 state %d -> %d\n",
1140 l1p
->st_num
, oldstate
,
1143 u_char oldstate
= l1p
->l1_state
;
1145 Write_hfc8(l1p
->hw
, R_ST_SEL
,
1151 if (((l1p
->l1_state
== 3) &&
1153 (oldstate
== 8))) ||
1156 && (l1p
->l1_state
== 8))) {
1157 mod_timer(&l1p
->l1_timer
,
1161 if (l1p
->l1_state
== 7) {
1173 if (l1p
->l1_state
== 3) {
1188 "HFC-4S/8S: TE %d ch %d l1 state %d -> %d\n",
1190 l1p
->st_num
, oldstate
,
1199 /* now handle the fifos */
1201 fifo_stat
= hw
->mr
.r_irq_fifo_blx
;
1203 while (idx
< hw
->driver_data
.max_st_ports
) {
1205 if (hw
->mr
.timer_irq
) {
1206 *fifo_stat
|= hw
->mr
.fifo_rx_trans_enables
[idx
];
1207 if (hw
->fifo_sched_cnt
<= 0) {
1209 hw
->mr
.fifo_slow_timer_service
[l1p
->
1213 /* ignore fifo 6 (TX E fifo) */
1214 *fifo_stat
&= 0xff - 0x40;
1216 while (*fifo_stat
) {
1218 if (!l1p
->nt_mode
) {
1219 /* RX Fifo has data to read */
1220 if ((*fifo_stat
& 0x20)) {
1221 *fifo_stat
&= ~0x20;
1224 /* E Fifo has data to read */
1225 if ((*fifo_stat
& 0x80)) {
1226 *fifo_stat
&= ~0x80;
1229 /* TX Fifo completed send */
1230 if ((*fifo_stat
& 0x10)) {
1231 *fifo_stat
&= ~0x10;
1235 /* B1 RX Fifo has data to read */
1236 if ((*fifo_stat
& 0x2)) {
1238 rx_b_frame(l1p
->b_ch
);
1240 /* B1 TX Fifo has send completed */
1241 if ((*fifo_stat
& 0x1)) {
1243 tx_b_frame(l1p
->b_ch
);
1245 /* B2 RX Fifo has data to read */
1246 if ((*fifo_stat
& 0x8)) {
1248 rx_b_frame(l1p
->b_ch
+ 1);
1250 /* B2 TX Fifo has send completed */
1251 if ((*fifo_stat
& 0x4)) {
1253 tx_b_frame(l1p
->b_ch
+ 1);
1261 if (hw
->fifo_sched_cnt
<= 0)
1262 hw
->fifo_sched_cnt
+= (1 << (7 - TRANS_TIMER_MODE
));
1263 hw
->mr
.timer_irq
= 0; /* clear requested timer irq */
1266 /*********************/
1267 /* interrupt handler */
1268 /*********************/
1270 hfc4s8s_interrupt(int intno
, void *dev_id
, struct pt_regs
*regs
)
1272 hfc4s8s_hw
*hw
= dev_id
;
1274 volatile u_char
*ovp
;
1278 if (!hw
|| !(hw
->mr
.r_irq_ctrl
& M_GLOB_IRQ_EN
))
1281 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
1282 /* read current selected regsister */
1283 old_ioreg
= GetRegAddr(hw
);
1286 /* Layer 1 State change */
1287 hw
->mr
.r_irq_statech
|=
1288 (Read_hfc8(hw
, R_SCI
) & hw
->mr
.r_irqmsk_statchg
);
1290 (b
= (Read_hfc8(hw
, R_STATUS
) & (M_MISC_IRQSTA
| M_FR_IRQSTA
)))
1291 && !hw
->mr
.r_irq_statech
) {
1292 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
1293 SetRegAddr(hw
, old_ioreg
);
1299 if (Read_hfc8(hw
, R_IRQ_MISC
) & M_TI_IRQ
) {
1300 hw
->mr
.timer_irq
= 1;
1301 hw
->fifo_sched_cnt
--;
1305 if ((ovr
= Read_hfc8(hw
, R_IRQ_OVIEW
))) {
1306 hw
->mr
.r_irq_oview
|= ovr
;
1307 idx
= R_IRQ_FIFO_BL0
;
1308 ovp
= hw
->mr
.r_irq_fifo_blx
;
1311 *ovp
|= Read_hfc8(hw
, idx
);
1319 /* queue the request to allow other cards to interrupt */
1320 schedule_work(&hw
->tqueue
);
1322 #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM
1323 SetRegAddr(hw
, old_ioreg
);
1326 } /* hfc4s8s_interrupt */
1328 /***********************************************************************/
1329 /* reset the complete chip, don't release the chips irq but disable it */
1330 /***********************************************************************/
1332 chipreset(hfc4s8s_hw
* hw
)
1336 spin_lock_irqsave(&hw
->lock
, flags
);
1337 Write_hfc8(hw
, R_CTRL
, 0); /* use internal RAM */
1338 Write_hfc8(hw
, R_RAM_MISC
, 0); /* 32k*8 RAM */
1339 Write_hfc8(hw
, R_FIFO_MD
, 0); /* fifo mode 386 byte/fifo simple mode */
1340 Write_hfc8(hw
, R_CIRM
, M_SRES
); /* reset chip */
1341 hw
->mr
.r_irq_ctrl
= 0; /* interrupt is inactive */
1342 spin_unlock_irqrestore(&hw
->lock
, flags
);
1345 Write_hfc8(hw
, R_CIRM
, 0); /* disable reset */
1348 Write_hfc8(hw
, R_PCM_MD0
, M_PCM_MD
); /* master mode */
1349 Write_hfc8(hw
, R_RAM_MISC
, M_FZ_MD
); /* transmit fifo option */
1350 if (hw
->driver_data
.clock_mode
== 1)
1351 Write_hfc8(hw
, R_BRG_PCM_CFG
, M_PCM_CLK
); /* PCM clk / 2 */
1352 Write_hfc8(hw
, R_TI_WD
, TRANS_TIMER_MODE
); /* timer interval */
1354 memset(&hw
->mr
, 0, sizeof(hw
->mr
));
1357 /********************************************/
1358 /* disable/enable hardware in nt or te mode */
1359 /********************************************/
1361 hfc_hardware_enable(hfc4s8s_hw
* hw
, int enable
, int nt_mode
)
1368 /* save system vars */
1369 hw
->nt_mode
= nt_mode
;
1371 /* enable fifo and state irqs, but not global irq enable */
1372 hw
->mr
.r_irq_ctrl
= M_FIFO_IRQ
;
1373 Write_hfc8(hw
, R_IRQ_CTRL
, hw
->mr
.r_irq_ctrl
);
1374 hw
->mr
.r_irqmsk_statchg
= 0;
1375 Write_hfc8(hw
, R_SCI_MSK
, hw
->mr
.r_irqmsk_statchg
);
1376 Write_hfc8(hw
, R_PWM_MD
, 0x80);
1377 Write_hfc8(hw
, R_PWM1
, 26);
1379 Write_hfc8(hw
, R_ST_SYNC
, M_AUTO_SYNC
);
1381 /* enable the line interfaces and fifos */
1382 for (i
= 0; i
< hw
->driver_data
.max_st_ports
; i
++) {
1383 hw
->mr
.r_irqmsk_statchg
|= (1 << i
);
1384 Write_hfc8(hw
, R_SCI_MSK
, hw
->mr
.r_irqmsk_statchg
);
1385 Write_hfc8(hw
, R_ST_SEL
, i
);
1386 Write_hfc8(hw
, A_ST_CLK_DLY
,
1387 ((nt_mode
) ? CLKDEL_NT
: CLKDEL_TE
));
1388 hw
->mr
.r_ctrl0
= ((nt_mode
) ? CTRL0_NT
: CTRL0_TE
);
1389 Write_hfc8(hw
, A_ST_CTRL0
, hw
->mr
.r_ctrl0
);
1390 Write_hfc8(hw
, A_ST_CTRL2
, 3);
1391 Write_hfc8(hw
, A_ST_WR_STA
, 0); /* enable state machine */
1393 hw
->l1
[i
].enabled
= 1;
1394 hw
->l1
[i
].nt_mode
= nt_mode
;
1398 Write_hfc8(hw
, R_FIFO
, i
* 8 + 7); /* E fifo */
1400 Write_hfc8(hw
, A_CON_HDLC
, 0x11); /* HDLC mode, 1 fill, connect ST */
1401 Write_hfc8(hw
, A_SUBCH_CFG
, 2); /* only 2 bits */
1402 Write_hfc8(hw
, A_IRQ_MSK
, 1); /* enable interrupt */
1403 Write_hfc8(hw
, A_INC_RES_FIFO
, 2); /* reset fifo */
1406 /* setup D RX-fifo */
1407 Write_hfc8(hw
, R_FIFO
, i
* 8 + 5); /* RX fifo */
1409 Write_hfc8(hw
, A_CON_HDLC
, 0x11); /* HDLC mode, 1 fill, connect ST */
1410 Write_hfc8(hw
, A_SUBCH_CFG
, 2); /* only 2 bits */
1411 Write_hfc8(hw
, A_IRQ_MSK
, 1); /* enable interrupt */
1412 Write_hfc8(hw
, A_INC_RES_FIFO
, 2); /* reset fifo */
1415 /* setup D TX-fifo */
1416 Write_hfc8(hw
, R_FIFO
, i
* 8 + 4); /* TX fifo */
1418 Write_hfc8(hw
, A_CON_HDLC
, 0x11); /* HDLC mode, 1 fill, connect ST */
1419 Write_hfc8(hw
, A_SUBCH_CFG
, 2); /* only 2 bits */
1420 Write_hfc8(hw
, A_IRQ_MSK
, 1); /* enable interrupt */
1421 Write_hfc8(hw
, A_INC_RES_FIFO
, 2); /* reset fifo */
1425 sprintf(if_name
, "hfc4s8s_%d%d_", hw
->cardnum
, i
);
1428 (&hw
->l1
[i
].d_if
, hw
->l1
[i
].b_table
, if_name
,
1429 ((nt_mode
) ? 3 : 2))) {
1431 hw
->l1
[i
].enabled
= 0;
1432 hw
->mr
.r_irqmsk_statchg
&= ~(1 << i
);
1433 Write_hfc8(hw
, R_SCI_MSK
,
1434 hw
->mr
.r_irqmsk_statchg
);
1436 "HFC-4S/8S: Unable to register S/T device %s, break\n",
1441 spin_lock_irqsave(&hw
->lock
, flags
);
1442 hw
->mr
.r_irq_ctrl
|= M_GLOB_IRQ_EN
;
1443 Write_hfc8(hw
, R_IRQ_CTRL
, hw
->mr
.r_irq_ctrl
);
1444 spin_unlock_irqrestore(&hw
->lock
, flags
);
1446 /* disable hardware */
1447 spin_lock_irqsave(&hw
->lock
, flags
);
1448 hw
->mr
.r_irq_ctrl
&= ~M_GLOB_IRQ_EN
;
1449 Write_hfc8(hw
, R_IRQ_CTRL
, hw
->mr
.r_irq_ctrl
);
1450 spin_unlock_irqrestore(&hw
->lock
, flags
);
1452 for (i
= hw
->driver_data
.max_st_ports
- 1; i
>= 0; i
--) {
1453 hw
->l1
[i
].enabled
= 0;
1454 hisax_unregister(&hw
->l1
[i
].d_if
);
1455 del_timer(&hw
->l1
[i
].l1_timer
);
1456 skb_queue_purge(&hw
->l1
[i
].d_tx_queue
);
1457 skb_queue_purge(&hw
->l1
[i
].b_ch
[0].tx_queue
);
1458 skb_queue_purge(&hw
->l1
[i
].b_ch
[1].tx_queue
);
1462 } /* hfc_hardware_enable */
1464 /******************************************/
1465 /* disable memory mapped ports / io ports */
1466 /******************************************/
1468 release_pci_ports(hfc4s8s_hw
* hw
)
1470 pci_write_config_word(hw
->pdev
, PCI_COMMAND
, 0);
1471 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
1473 iounmap((void *) hw
->membase
);
1476 release_region(hw
->iobase
, 8);
1480 /*****************************************/
1481 /* enable memory mapped ports / io ports */
1482 /*****************************************/
1484 enable_pci_ports(hfc4s8s_hw
* hw
)
1486 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
1487 pci_write_config_word(hw
->pdev
, PCI_COMMAND
, PCI_ENA_MEMIO
);
1489 pci_write_config_word(hw
->pdev
, PCI_COMMAND
, PCI_ENA_REGIO
);
1493 /*************************************/
1494 /* initialise the HFC-4s/8s hardware */
1495 /* return 0 on success. */
1496 /*************************************/
1497 static int __devinit
1498 setup_instance(hfc4s8s_hw
* hw
)
1503 for (i
= 0; i
< HFC_MAX_ST
; i
++) {
1504 struct hfc4s8s_l1
*l1p
;
1507 spin_lock_init(&l1p
->lock
);
1509 l1p
->l1_timer
.function
= (void *) hfc_l1_timer
;
1510 l1p
->l1_timer
.data
= (long) (l1p
);
1511 init_timer(&l1p
->l1_timer
);
1513 skb_queue_head_init(&l1p
->d_tx_queue
);
1514 l1p
->d_if
.ifc
.priv
= hw
->l1
+ i
;
1515 l1p
->d_if
.ifc
.l2l1
= (void *) dch_l2l1
;
1517 spin_lock_init(&l1p
->b_ch
[0].lock
);
1518 l1p
->b_ch
[0].b_if
.ifc
.l2l1
= (void *) bch_l2l1
;
1519 l1p
->b_ch
[0].b_if
.ifc
.priv
= (void *) &l1p
->b_ch
[0];
1520 l1p
->b_ch
[0].l1p
= hw
->l1
+ i
;
1521 l1p
->b_ch
[0].bchan
= 1;
1522 l1p
->b_table
[0] = &l1p
->b_ch
[0].b_if
;
1523 skb_queue_head_init(&l1p
->b_ch
[0].tx_queue
);
1525 spin_lock_init(&l1p
->b_ch
[1].lock
);
1526 l1p
->b_ch
[1].b_if
.ifc
.l2l1
= (void *) bch_l2l1
;
1527 l1p
->b_ch
[1].b_if
.ifc
.priv
= (void *) &l1p
->b_ch
[1];
1528 l1p
->b_ch
[1].l1p
= hw
->l1
+ i
;
1529 l1p
->b_ch
[1].bchan
= 2;
1530 l1p
->b_table
[1] = &l1p
->b_ch
[1].b_if
;
1531 skb_queue_head_init(&l1p
->b_ch
[1].tx_queue
);
1534 enable_pci_ports(hw
);
1537 i
= Read_hfc8(hw
, R_CHIP_ID
) >> CHIP_ID_SHIFT
;
1538 if (i
!= hw
->driver_data
.chip_id
) {
1540 "HFC-4S/8S: invalid chip id 0x%x instead of 0x%x, card ignored\n",
1541 i
, hw
->driver_data
.chip_id
);
1545 i
= Read_hfc8(hw
, R_CHIP_RV
) & 0xf;
1548 "HFC-4S/8S: chip revision 0 not supported, card ignored\n");
1552 INIT_WORK(&hw
->tqueue
, (void *) (void *) hfc4s8s_bh
, hw
);
1555 (hw
->irq
, hfc4s8s_interrupt
, SA_SHIRQ
, hw
->card_name
, hw
)) {
1557 "HFC-4S/8S: unable to alloc irq %d, card ignored\n",
1561 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
1563 "HFC-4S/8S: found PCI card at membase 0x%p, irq %d\n",
1564 hw
->hw_membase
, hw
->irq
);
1567 "HFC-4S/8S: found PCI card at iobase 0x%x, irq %d\n",
1568 hw
->iobase
, hw
->irq
);
1571 hfc_hardware_enable(hw
, 1, 0);
1577 release_pci_ports(hw
);
1582 /*****************************************/
1583 /* PCI hotplug interface: probe new card */
1584 /*****************************************/
1585 static int __devinit
1586 hfc4s8s_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1589 hfc4s8s_param
*driver_data
= (hfc4s8s_param
*) ent
->driver_data
;
1592 if (!(hw
= kmalloc(sizeof(hfc4s8s_hw
), GFP_ATOMIC
))) {
1593 printk(KERN_ERR
"No kmem for HFC-4S/8S card\n");
1596 memset(hw
, 0, sizeof(hfc4s8s_hw
));
1599 err
= pci_enable_device(pdev
);
1604 hw
->cardnum
= card_cnt
;
1605 sprintf(hw
->card_name
, "hfc4s8s_%d", hw
->cardnum
);
1606 printk(KERN_INFO
"HFC-4S/8S: found adapter %s (%s) at %s\n",
1607 driver_data
->device_name
, hw
->card_name
, pci_name(pdev
));
1609 spin_lock_init(&hw
->lock
);
1611 hw
->driver_data
= *driver_data
;
1612 hw
->irq
= pdev
->irq
;
1613 hw
->iobase
= pci_resource_start(pdev
, 0);
1615 #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM
1616 hw
->hw_membase
= (u_char
*) pci_resource_start(pdev
, 1);
1617 hw
->membase
= ioremap((ulong
) hw
->hw_membase
, 256);
1619 if (!request_region(hw
->iobase
, 8, hw
->card_name
)) {
1621 "HFC-4S/8S: failed to rquest address space at 0x%04x\n",
1627 pci_set_drvdata(pdev
, hw
);
1628 err
= setup_instance(hw
);
1638 /**************************************/
1639 /* PCI hotplug interface: remove card */
1640 /**************************************/
1641 static void __devexit
1642 hfc4s8s_remove(struct pci_dev
*pdev
)
1644 hfc4s8s_hw
*hw
= pci_get_drvdata(pdev
);
1646 printk(KERN_INFO
"HFC-4S/8S: removing card %d\n", hw
->cardnum
);
1647 hfc_hardware_enable(hw
, 0, 0);
1650 free_irq(hw
->irq
, hw
);
1652 release_pci_ports(hw
);
1655 pci_disable_device(pdev
);
1660 static struct pci_driver hfc4s8s_driver
= {
1662 probe
:hfc4s8s_probe
,
1663 remove
:__devexit_p(hfc4s8s_remove
),
1664 id_table
:hfc4s8s_ids
,
1667 /**********************/
1668 /* driver Module init */
1669 /**********************/
1671 hfc4s8s_module_init(void)
1676 "HFC-4S/8S: Layer 1 driver module for HFC-4S/8S isdn chips, %s\n",
1679 "HFC-4S/8S: (C) 2003 Cornelius Consult, www.cornelius-consult.de\n");
1683 err
= pci_register_driver(&hfc4s8s_driver
);
1687 printk(KERN_INFO
"HFC-4S/8S: found %d cards\n", card_cnt
);
1689 #if !defined(CONFIG_HOTPLUG)
1692 pci_unregister_driver(&hfc4s8s_driver
);
1700 } /* hfc4s8s_init_hw */
1702 /*************************************/
1703 /* driver module exit : */
1704 /* release the HFC-4s/8s hardware */
1705 /*************************************/
1707 hfc4s8s_module_exit(void)
1709 pci_unregister_driver(&hfc4s8s_driver
);
1710 printk(KERN_INFO
"HFC-4S/8S: module removed\n");
1711 } /* hfc4s8s_release_hw */
1713 module_init(hfc4s8s_module_init
);
1714 module_exit(hfc4s8s_module_exit
);