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[deliverable/linux.git] / drivers / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "kvm.h"
19 #include "vmx.h"
20 #include "kvm_vmx.h"
21 #include <linux/module.h>
22 #include <linux/mm.h>
23 #include <linux/highmem.h>
24 #include <asm/io.h>
25 #include <asm/desc.h>
26
27 #include "segment_descriptor.h"
28
29
30 MODULE_AUTHOR("Qumranet");
31 MODULE_LICENSE("GPL");
32
33 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
34 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
35
36 #ifdef CONFIG_X86_64
37 #define HOST_IS_64 1
38 #else
39 #define HOST_IS_64 0
40 #endif
41
42 static struct vmcs_descriptor {
43 int size;
44 int order;
45 u32 revision_id;
46 } vmcs_descriptor;
47
48 #define VMX_SEGMENT_FIELD(seg) \
49 [VCPU_SREG_##seg] = { \
50 .selector = GUEST_##seg##_SELECTOR, \
51 .base = GUEST_##seg##_BASE, \
52 .limit = GUEST_##seg##_LIMIT, \
53 .ar_bytes = GUEST_##seg##_AR_BYTES, \
54 }
55
56 static struct kvm_vmx_segment_field {
57 unsigned selector;
58 unsigned base;
59 unsigned limit;
60 unsigned ar_bytes;
61 } kvm_vmx_segment_fields[] = {
62 VMX_SEGMENT_FIELD(CS),
63 VMX_SEGMENT_FIELD(DS),
64 VMX_SEGMENT_FIELD(ES),
65 VMX_SEGMENT_FIELD(FS),
66 VMX_SEGMENT_FIELD(GS),
67 VMX_SEGMENT_FIELD(SS),
68 VMX_SEGMENT_FIELD(TR),
69 VMX_SEGMENT_FIELD(LDTR),
70 };
71
72 static const u32 vmx_msr_index[] = {
73 #ifdef CONFIG_X86_64
74 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
75 #endif
76 MSR_EFER, MSR_K6_STAR,
77 };
78 #define NR_VMX_MSR (sizeof(vmx_msr_index) / sizeof(*vmx_msr_index))
79
80 static inline int is_page_fault(u32 intr_info)
81 {
82 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
83 INTR_INFO_VALID_MASK)) ==
84 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
85 }
86
87 static inline int is_external_interrupt(u32 intr_info)
88 {
89 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
90 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
91 }
92
93 static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr)
94 {
95 int i;
96
97 for (i = 0; i < vcpu->nmsrs; ++i)
98 if (vcpu->guest_msrs[i].index == msr)
99 return &vcpu->guest_msrs[i];
100 return 0;
101 }
102
103 static void vmcs_clear(struct vmcs *vmcs)
104 {
105 u64 phys_addr = __pa(vmcs);
106 u8 error;
107
108 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
109 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
110 : "cc", "memory");
111 if (error)
112 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
113 vmcs, phys_addr);
114 }
115
116 static void __vcpu_clear(void *arg)
117 {
118 struct kvm_vcpu *vcpu = arg;
119 int cpu = smp_processor_id();
120
121 if (vcpu->cpu == cpu)
122 vmcs_clear(vcpu->vmcs);
123 if (per_cpu(current_vmcs, cpu) == vcpu->vmcs)
124 per_cpu(current_vmcs, cpu) = NULL;
125 }
126
127 static unsigned long vmcs_readl(unsigned long field)
128 {
129 unsigned long value;
130
131 asm volatile (ASM_VMX_VMREAD_RDX_RAX
132 : "=a"(value) : "d"(field) : "cc");
133 return value;
134 }
135
136 static u16 vmcs_read16(unsigned long field)
137 {
138 return vmcs_readl(field);
139 }
140
141 static u32 vmcs_read32(unsigned long field)
142 {
143 return vmcs_readl(field);
144 }
145
146 static u64 vmcs_read64(unsigned long field)
147 {
148 #ifdef CONFIG_X86_64
149 return vmcs_readl(field);
150 #else
151 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
152 #endif
153 }
154
155 static void vmcs_writel(unsigned long field, unsigned long value)
156 {
157 u8 error;
158
159 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
160 : "=q"(error) : "a"(value), "d"(field) : "cc" );
161 if (error)
162 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
163 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
164 }
165
166 static void vmcs_write16(unsigned long field, u16 value)
167 {
168 vmcs_writel(field, value);
169 }
170
171 static void vmcs_write32(unsigned long field, u32 value)
172 {
173 vmcs_writel(field, value);
174 }
175
176 static void vmcs_write64(unsigned long field, u64 value)
177 {
178 #ifdef CONFIG_X86_64
179 vmcs_writel(field, value);
180 #else
181 vmcs_writel(field, value);
182 asm volatile ("");
183 vmcs_writel(field+1, value >> 32);
184 #endif
185 }
186
187 /*
188 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
189 * vcpu mutex is already taken.
190 */
191 static struct kvm_vcpu *vmx_vcpu_load(struct kvm_vcpu *vcpu)
192 {
193 u64 phys_addr = __pa(vcpu->vmcs);
194 int cpu;
195
196 cpu = get_cpu();
197
198 if (vcpu->cpu != cpu) {
199 smp_call_function(__vcpu_clear, vcpu, 0, 1);
200 vcpu->launched = 0;
201 }
202
203 if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) {
204 u8 error;
205
206 per_cpu(current_vmcs, cpu) = vcpu->vmcs;
207 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
208 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
209 : "cc");
210 if (error)
211 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
212 vcpu->vmcs, phys_addr);
213 }
214
215 if (vcpu->cpu != cpu) {
216 struct descriptor_table dt;
217 unsigned long sysenter_esp;
218
219 vcpu->cpu = cpu;
220 /*
221 * Linux uses per-cpu TSS and GDT, so set these when switching
222 * processors.
223 */
224 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
225 get_gdt(&dt);
226 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
227
228 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
229 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
230 }
231 return vcpu;
232 }
233
234 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
235 {
236 put_cpu();
237 }
238
239 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
240 {
241 return vmcs_readl(GUEST_RFLAGS);
242 }
243
244 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
245 {
246 vmcs_writel(GUEST_RFLAGS, rflags);
247 }
248
249 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
250 {
251 unsigned long rip;
252 u32 interruptibility;
253
254 rip = vmcs_readl(GUEST_RIP);
255 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
256 vmcs_writel(GUEST_RIP, rip);
257
258 /*
259 * We emulated an instruction, so temporary interrupt blocking
260 * should be removed, if set.
261 */
262 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
263 if (interruptibility & 3)
264 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
265 interruptibility & ~3);
266 }
267
268 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
269 {
270 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
271 vmcs_readl(GUEST_RIP));
272 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
273 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
274 GP_VECTOR |
275 INTR_TYPE_EXCEPTION |
276 INTR_INFO_DELIEVER_CODE_MASK |
277 INTR_INFO_VALID_MASK);
278 }
279
280 /*
281 * reads and returns guest's timestamp counter "register"
282 * guest_tsc = host_tsc + tsc_offset -- 21.3
283 */
284 static u64 guest_read_tsc(void)
285 {
286 u64 host_tsc, tsc_offset;
287
288 rdtscll(host_tsc);
289 tsc_offset = vmcs_read64(TSC_OFFSET);
290 return host_tsc + tsc_offset;
291 }
292
293 /*
294 * writes 'guest_tsc' into guest's timestamp counter "register"
295 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
296 */
297 static void guest_write_tsc(u64 guest_tsc)
298 {
299 u64 host_tsc;
300
301 rdtscll(host_tsc);
302 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
303 }
304
305 static void reload_tss(void)
306 {
307 #ifndef CONFIG_X86_64
308
309 /*
310 * VT restores TR but not its size. Useless.
311 */
312 struct descriptor_table gdt;
313 struct segment_descriptor *descs;
314
315 get_gdt(&gdt);
316 descs = (void *)gdt.base;
317 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
318 load_TR_desc();
319 #endif
320 }
321
322 /*
323 * Reads an msr value (of 'msr_index') into 'pdata'.
324 * Returns 0 on success, non-0 otherwise.
325 * Assumes vcpu_load() was already called.
326 */
327 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
328 {
329 u64 data;
330 struct vmx_msr_entry *msr;
331
332 if (!pdata) {
333 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
334 return -EINVAL;
335 }
336
337 switch (msr_index) {
338 #ifdef CONFIG_X86_64
339 case MSR_FS_BASE:
340 data = vmcs_readl(GUEST_FS_BASE);
341 break;
342 case MSR_GS_BASE:
343 data = vmcs_readl(GUEST_GS_BASE);
344 break;
345 case MSR_EFER:
346 return kvm_get_msr_common(vcpu, msr_index, pdata);
347 #endif
348 case MSR_IA32_TIME_STAMP_COUNTER:
349 data = guest_read_tsc();
350 break;
351 case MSR_IA32_SYSENTER_CS:
352 data = vmcs_read32(GUEST_SYSENTER_CS);
353 break;
354 case MSR_IA32_SYSENTER_EIP:
355 data = vmcs_read32(GUEST_SYSENTER_EIP);
356 break;
357 case MSR_IA32_SYSENTER_ESP:
358 data = vmcs_read32(GUEST_SYSENTER_ESP);
359 break;
360 default:
361 msr = find_msr_entry(vcpu, msr_index);
362 if (msr) {
363 data = msr->data;
364 break;
365 }
366 return kvm_get_msr_common(vcpu, msr_index, pdata);
367 }
368
369 *pdata = data;
370 return 0;
371 }
372
373 /*
374 * Writes msr value into into the appropriate "register".
375 * Returns 0 on success, non-0 otherwise.
376 * Assumes vcpu_load() was already called.
377 */
378 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
379 {
380 struct vmx_msr_entry *msr;
381 switch (msr_index) {
382 #ifdef CONFIG_X86_64
383 case MSR_EFER:
384 return kvm_set_msr_common(vcpu, msr_index, data);
385 case MSR_FS_BASE:
386 vmcs_writel(GUEST_FS_BASE, data);
387 break;
388 case MSR_GS_BASE:
389 vmcs_writel(GUEST_GS_BASE, data);
390 break;
391 #endif
392 case MSR_IA32_SYSENTER_CS:
393 vmcs_write32(GUEST_SYSENTER_CS, data);
394 break;
395 case MSR_IA32_SYSENTER_EIP:
396 vmcs_write32(GUEST_SYSENTER_EIP, data);
397 break;
398 case MSR_IA32_SYSENTER_ESP:
399 vmcs_write32(GUEST_SYSENTER_ESP, data);
400 break;
401 case MSR_IA32_TIME_STAMP_COUNTER: {
402 guest_write_tsc(data);
403 break;
404 }
405 default:
406 msr = find_msr_entry(vcpu, msr_index);
407 if (msr) {
408 msr->data = data;
409 break;
410 }
411 return kvm_set_msr_common(vcpu, msr_index, data);
412 msr->data = data;
413 break;
414 }
415
416 return 0;
417 }
418
419 /*
420 * Sync the rsp and rip registers into the vcpu structure. This allows
421 * registers to be accessed by indexing vcpu->regs.
422 */
423 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
424 {
425 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
426 vcpu->rip = vmcs_readl(GUEST_RIP);
427 }
428
429 /*
430 * Syncs rsp and rip back into the vmcs. Should be called after possible
431 * modification.
432 */
433 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
434 {
435 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
436 vmcs_writel(GUEST_RIP, vcpu->rip);
437 }
438
439 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
440 {
441 unsigned long dr7 = 0x400;
442 u32 exception_bitmap;
443 int old_singlestep;
444
445 exception_bitmap = vmcs_read32(EXCEPTION_BITMAP);
446 old_singlestep = vcpu->guest_debug.singlestep;
447
448 vcpu->guest_debug.enabled = dbg->enabled;
449 if (vcpu->guest_debug.enabled) {
450 int i;
451
452 dr7 |= 0x200; /* exact */
453 for (i = 0; i < 4; ++i) {
454 if (!dbg->breakpoints[i].enabled)
455 continue;
456 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
457 dr7 |= 2 << (i*2); /* global enable */
458 dr7 |= 0 << (i*4+16); /* execution breakpoint */
459 }
460
461 exception_bitmap |= (1u << 1); /* Trap debug exceptions */
462
463 vcpu->guest_debug.singlestep = dbg->singlestep;
464 } else {
465 exception_bitmap &= ~(1u << 1); /* Ignore debug exceptions */
466 vcpu->guest_debug.singlestep = 0;
467 }
468
469 if (old_singlestep && !vcpu->guest_debug.singlestep) {
470 unsigned long flags;
471
472 flags = vmcs_readl(GUEST_RFLAGS);
473 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
474 vmcs_writel(GUEST_RFLAGS, flags);
475 }
476
477 vmcs_write32(EXCEPTION_BITMAP, exception_bitmap);
478 vmcs_writel(GUEST_DR7, dr7);
479
480 return 0;
481 }
482
483 static __init int cpu_has_kvm_support(void)
484 {
485 unsigned long ecx = cpuid_ecx(1);
486 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
487 }
488
489 static __init int vmx_disabled_by_bios(void)
490 {
491 u64 msr;
492
493 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
494 return (msr & 5) == 1; /* locked but not enabled */
495 }
496
497 static __init void hardware_enable(void *garbage)
498 {
499 int cpu = raw_smp_processor_id();
500 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
501 u64 old;
502
503 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
504 if ((old & 5) != 5)
505 /* enable and lock */
506 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5);
507 write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */
508 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
509 : "memory", "cc");
510 }
511
512 static void hardware_disable(void *garbage)
513 {
514 asm volatile (ASM_VMX_VMXOFF : : : "cc");
515 }
516
517 static __init void setup_vmcs_descriptor(void)
518 {
519 u32 vmx_msr_low, vmx_msr_high;
520
521 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
522 vmcs_descriptor.size = vmx_msr_high & 0x1fff;
523 vmcs_descriptor.order = get_order(vmcs_descriptor.size);
524 vmcs_descriptor.revision_id = vmx_msr_low;
525 }
526
527 static struct vmcs *alloc_vmcs_cpu(int cpu)
528 {
529 int node = cpu_to_node(cpu);
530 struct page *pages;
531 struct vmcs *vmcs;
532
533 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
534 if (!pages)
535 return NULL;
536 vmcs = page_address(pages);
537 memset(vmcs, 0, vmcs_descriptor.size);
538 vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
539 return vmcs;
540 }
541
542 static struct vmcs *alloc_vmcs(void)
543 {
544 return alloc_vmcs_cpu(smp_processor_id());
545 }
546
547 static void free_vmcs(struct vmcs *vmcs)
548 {
549 free_pages((unsigned long)vmcs, vmcs_descriptor.order);
550 }
551
552 static __exit void free_kvm_area(void)
553 {
554 int cpu;
555
556 for_each_online_cpu(cpu)
557 free_vmcs(per_cpu(vmxarea, cpu));
558 }
559
560 extern struct vmcs *alloc_vmcs_cpu(int cpu);
561
562 static __init int alloc_kvm_area(void)
563 {
564 int cpu;
565
566 for_each_online_cpu(cpu) {
567 struct vmcs *vmcs;
568
569 vmcs = alloc_vmcs_cpu(cpu);
570 if (!vmcs) {
571 free_kvm_area();
572 return -ENOMEM;
573 }
574
575 per_cpu(vmxarea, cpu) = vmcs;
576 }
577 return 0;
578 }
579
580 static __init int hardware_setup(void)
581 {
582 setup_vmcs_descriptor();
583 return alloc_kvm_area();
584 }
585
586 static __exit void hardware_unsetup(void)
587 {
588 free_kvm_area();
589 }
590
591 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
592 {
593 if (vcpu->rmode.active)
594 vmcs_write32(EXCEPTION_BITMAP, ~0);
595 else
596 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
597 }
598
599 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
600 {
601 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
602
603 if (vmcs_readl(sf->base) == save->base) {
604 vmcs_write16(sf->selector, save->selector);
605 vmcs_writel(sf->base, save->base);
606 vmcs_write32(sf->limit, save->limit);
607 vmcs_write32(sf->ar_bytes, save->ar);
608 } else {
609 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
610 << AR_DPL_SHIFT;
611 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
612 }
613 }
614
615 static void enter_pmode(struct kvm_vcpu *vcpu)
616 {
617 unsigned long flags;
618
619 vcpu->rmode.active = 0;
620
621 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
622 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
623 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
624
625 flags = vmcs_readl(GUEST_RFLAGS);
626 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
627 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
628 vmcs_writel(GUEST_RFLAGS, flags);
629
630 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) |
631 (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK));
632
633 update_exception_bitmap(vcpu);
634
635 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
636 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
637 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
638 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
639
640 vmcs_write16(GUEST_SS_SELECTOR, 0);
641 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
642
643 vmcs_write16(GUEST_CS_SELECTOR,
644 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
645 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
646 }
647
648 static int rmode_tss_base(struct kvm* kvm)
649 {
650 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
651 return base_gfn << PAGE_SHIFT;
652 }
653
654 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
655 {
656 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
657
658 save->selector = vmcs_read16(sf->selector);
659 save->base = vmcs_readl(sf->base);
660 save->limit = vmcs_read32(sf->limit);
661 save->ar = vmcs_read32(sf->ar_bytes);
662 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
663 vmcs_write32(sf->limit, 0xffff);
664 vmcs_write32(sf->ar_bytes, 0xf3);
665 }
666
667 static void enter_rmode(struct kvm_vcpu *vcpu)
668 {
669 unsigned long flags;
670
671 vcpu->rmode.active = 1;
672
673 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
674 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
675
676 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
677 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
678
679 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
680 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
681
682 flags = vmcs_readl(GUEST_RFLAGS);
683 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
684
685 flags |= IOPL_MASK | X86_EFLAGS_VM;
686
687 vmcs_writel(GUEST_RFLAGS, flags);
688 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK);
689 update_exception_bitmap(vcpu);
690
691 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
692 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
693 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
694
695 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
696 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
697 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
698
699 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
700 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
701 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
702 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
703 }
704
705 #ifdef CONFIG_X86_64
706
707 static void enter_lmode(struct kvm_vcpu *vcpu)
708 {
709 u32 guest_tr_ar;
710
711 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
712 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
713 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
714 __FUNCTION__);
715 vmcs_write32(GUEST_TR_AR_BYTES,
716 (guest_tr_ar & ~AR_TYPE_MASK)
717 | AR_TYPE_BUSY_64_TSS);
718 }
719
720 vcpu->shadow_efer |= EFER_LMA;
721
722 find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
723 vmcs_write32(VM_ENTRY_CONTROLS,
724 vmcs_read32(VM_ENTRY_CONTROLS)
725 | VM_ENTRY_CONTROLS_IA32E_MASK);
726 }
727
728 static void exit_lmode(struct kvm_vcpu *vcpu)
729 {
730 vcpu->shadow_efer &= ~EFER_LMA;
731
732 vmcs_write32(VM_ENTRY_CONTROLS,
733 vmcs_read32(VM_ENTRY_CONTROLS)
734 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
735 }
736
737 #endif
738
739 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
740 {
741 if (vcpu->rmode.active && (cr0 & CR0_PE_MASK))
742 enter_pmode(vcpu);
743
744 if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK))
745 enter_rmode(vcpu);
746
747 #ifdef CONFIG_X86_64
748 if (vcpu->shadow_efer & EFER_LME) {
749 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK))
750 enter_lmode(vcpu);
751 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK))
752 exit_lmode(vcpu);
753 }
754 #endif
755
756 vmcs_writel(CR0_READ_SHADOW, cr0);
757 vmcs_writel(GUEST_CR0,
758 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
759 vcpu->cr0 = cr0;
760 }
761
762 /*
763 * Used when restoring the VM to avoid corrupting segment registers
764 */
765 static void vmx_set_cr0_no_modeswitch(struct kvm_vcpu *vcpu, unsigned long cr0)
766 {
767 vcpu->rmode.active = ((cr0 & CR0_PE_MASK) == 0);
768 update_exception_bitmap(vcpu);
769 vmcs_writel(CR0_READ_SHADOW, cr0);
770 vmcs_writel(GUEST_CR0,
771 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
772 vcpu->cr0 = cr0;
773 }
774
775 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
776 {
777 vmcs_writel(GUEST_CR3, cr3);
778 }
779
780 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
781 {
782 vmcs_writel(CR4_READ_SHADOW, cr4);
783 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
784 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
785 vcpu->cr4 = cr4;
786 }
787
788 #ifdef CONFIG_X86_64
789
790 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
791 {
792 struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
793
794 vcpu->shadow_efer = efer;
795 if (efer & EFER_LMA) {
796 vmcs_write32(VM_ENTRY_CONTROLS,
797 vmcs_read32(VM_ENTRY_CONTROLS) |
798 VM_ENTRY_CONTROLS_IA32E_MASK);
799 msr->data = efer;
800
801 } else {
802 vmcs_write32(VM_ENTRY_CONTROLS,
803 vmcs_read32(VM_ENTRY_CONTROLS) &
804 ~VM_ENTRY_CONTROLS_IA32E_MASK);
805
806 msr->data = efer & ~EFER_LME;
807 }
808 }
809
810 #endif
811
812 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
813 {
814 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
815
816 return vmcs_readl(sf->base);
817 }
818
819 static void vmx_get_segment(struct kvm_vcpu *vcpu,
820 struct kvm_segment *var, int seg)
821 {
822 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
823 u32 ar;
824
825 var->base = vmcs_readl(sf->base);
826 var->limit = vmcs_read32(sf->limit);
827 var->selector = vmcs_read16(sf->selector);
828 ar = vmcs_read32(sf->ar_bytes);
829 if (ar & AR_UNUSABLE_MASK)
830 ar = 0;
831 var->type = ar & 15;
832 var->s = (ar >> 4) & 1;
833 var->dpl = (ar >> 5) & 3;
834 var->present = (ar >> 7) & 1;
835 var->avl = (ar >> 12) & 1;
836 var->l = (ar >> 13) & 1;
837 var->db = (ar >> 14) & 1;
838 var->g = (ar >> 15) & 1;
839 var->unusable = (ar >> 16) & 1;
840 }
841
842 static void vmx_set_segment(struct kvm_vcpu *vcpu,
843 struct kvm_segment *var, int seg)
844 {
845 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
846 u32 ar;
847
848 vmcs_writel(sf->base, var->base);
849 vmcs_write32(sf->limit, var->limit);
850 vmcs_write16(sf->selector, var->selector);
851 if (var->unusable)
852 ar = 1 << 16;
853 else {
854 ar = var->type & 15;
855 ar |= (var->s & 1) << 4;
856 ar |= (var->dpl & 3) << 5;
857 ar |= (var->present & 1) << 7;
858 ar |= (var->avl & 1) << 12;
859 ar |= (var->l & 1) << 13;
860 ar |= (var->db & 1) << 14;
861 ar |= (var->g & 1) << 15;
862 }
863 if (ar == 0) /* a 0 value means unusable */
864 ar = AR_UNUSABLE_MASK;
865 vmcs_write32(sf->ar_bytes, ar);
866 }
867
868 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
869 {
870 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
871
872 *db = (ar >> 14) & 1;
873 *l = (ar >> 13) & 1;
874 }
875
876 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
877 {
878 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
879 dt->base = vmcs_readl(GUEST_IDTR_BASE);
880 }
881
882 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
883 {
884 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
885 vmcs_writel(GUEST_IDTR_BASE, dt->base);
886 }
887
888 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
889 {
890 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
891 dt->base = vmcs_readl(GUEST_GDTR_BASE);
892 }
893
894 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
895 {
896 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
897 vmcs_writel(GUEST_GDTR_BASE, dt->base);
898 }
899
900 static int init_rmode_tss(struct kvm* kvm)
901 {
902 struct page *p1, *p2, *p3;
903 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
904 char *page;
905
906 p1 = _gfn_to_page(kvm, fn++);
907 p2 = _gfn_to_page(kvm, fn++);
908 p3 = _gfn_to_page(kvm, fn);
909
910 if (!p1 || !p2 || !p3) {
911 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
912 return 0;
913 }
914
915 page = kmap_atomic(p1, KM_USER0);
916 memset(page, 0, PAGE_SIZE);
917 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
918 kunmap_atomic(page, KM_USER0);
919
920 page = kmap_atomic(p2, KM_USER0);
921 memset(page, 0, PAGE_SIZE);
922 kunmap_atomic(page, KM_USER0);
923
924 page = kmap_atomic(p3, KM_USER0);
925 memset(page, 0, PAGE_SIZE);
926 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
927 kunmap_atomic(page, KM_USER0);
928
929 return 1;
930 }
931
932 static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
933 {
934 u32 msr_high, msr_low;
935
936 rdmsr(msr, msr_low, msr_high);
937
938 val &= msr_high;
939 val |= msr_low;
940 vmcs_write32(vmcs_field, val);
941 }
942
943 static void seg_setup(int seg)
944 {
945 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
946
947 vmcs_write16(sf->selector, 0);
948 vmcs_writel(sf->base, 0);
949 vmcs_write32(sf->limit, 0xffff);
950 vmcs_write32(sf->ar_bytes, 0x93);
951 }
952
953 /*
954 * Sets up the vmcs for emulated real mode.
955 */
956 static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
957 {
958 u32 host_sysenter_cs;
959 u32 junk;
960 unsigned long a;
961 struct descriptor_table dt;
962 int i;
963 int ret = 0;
964 int nr_good_msrs;
965 extern asmlinkage void kvm_vmx_return(void);
966
967 if (!init_rmode_tss(vcpu->kvm)) {
968 ret = -ENOMEM;
969 goto out;
970 }
971
972 memset(vcpu->regs, 0, sizeof(vcpu->regs));
973 vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
974 vcpu->cr8 = 0;
975 vcpu->apic_base = 0xfee00000 |
976 /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
977 MSR_IA32_APICBASE_ENABLE;
978
979 fx_init(vcpu);
980
981 /*
982 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
983 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
984 */
985 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
986 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
987 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
988 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
989
990 seg_setup(VCPU_SREG_DS);
991 seg_setup(VCPU_SREG_ES);
992 seg_setup(VCPU_SREG_FS);
993 seg_setup(VCPU_SREG_GS);
994 seg_setup(VCPU_SREG_SS);
995
996 vmcs_write16(GUEST_TR_SELECTOR, 0);
997 vmcs_writel(GUEST_TR_BASE, 0);
998 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
999 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1000
1001 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1002 vmcs_writel(GUEST_LDTR_BASE, 0);
1003 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1004 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1005
1006 vmcs_write32(GUEST_SYSENTER_CS, 0);
1007 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1008 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1009
1010 vmcs_writel(GUEST_RFLAGS, 0x02);
1011 vmcs_writel(GUEST_RIP, 0xfff0);
1012 vmcs_writel(GUEST_RSP, 0);
1013
1014 vmcs_writel(GUEST_CR3, 0);
1015
1016 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1017 vmcs_writel(GUEST_DR7, 0x400);
1018
1019 vmcs_writel(GUEST_GDTR_BASE, 0);
1020 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1021
1022 vmcs_writel(GUEST_IDTR_BASE, 0);
1023 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1024
1025 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1026 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1027 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1028
1029 /* I/O */
1030 vmcs_write64(IO_BITMAP_A, 0);
1031 vmcs_write64(IO_BITMAP_B, 0);
1032
1033 guest_write_tsc(0);
1034
1035 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1036
1037 /* Special registers */
1038 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1039
1040 /* Control */
1041 vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS,
1042 PIN_BASED_VM_EXEC_CONTROL,
1043 PIN_BASED_EXT_INTR_MASK /* 20.6.1 */
1044 | PIN_BASED_NMI_EXITING /* 20.6.1 */
1045 );
1046 vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS,
1047 CPU_BASED_VM_EXEC_CONTROL,
1048 CPU_BASED_HLT_EXITING /* 20.6.2 */
1049 | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */
1050 | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */
1051 | CPU_BASED_UNCOND_IO_EXITING /* 20.6.2 */
1052 | CPU_BASED_INVDPG_EXITING
1053 | CPU_BASED_MOV_DR_EXITING
1054 | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */
1055 );
1056
1057 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
1058 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1059 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1060 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1061
1062 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1063 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1064 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1065
1066 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1067 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1068 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1069 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1070 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1071 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1072 #ifdef CONFIG_X86_64
1073 rdmsrl(MSR_FS_BASE, a);
1074 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1075 rdmsrl(MSR_GS_BASE, a);
1076 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1077 #else
1078 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1079 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1080 #endif
1081
1082 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1083
1084 get_idt(&dt);
1085 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1086
1087
1088 vmcs_writel(HOST_RIP, (unsigned long)kvm_vmx_return); /* 22.2.5 */
1089
1090 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1091 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1092 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1093 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1094 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1095 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1096
1097 for (i = 0; i < NR_VMX_MSR; ++i) {
1098 u32 index = vmx_msr_index[i];
1099 u32 data_low, data_high;
1100 u64 data;
1101 int j = vcpu->nmsrs;
1102
1103 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1104 continue;
1105 data = data_low | ((u64)data_high << 32);
1106 vcpu->host_msrs[j].index = index;
1107 vcpu->host_msrs[j].reserved = 0;
1108 vcpu->host_msrs[j].data = data;
1109 vcpu->guest_msrs[j] = vcpu->host_msrs[j];
1110 ++vcpu->nmsrs;
1111 }
1112 printk(KERN_DEBUG "kvm: msrs: %d\n", vcpu->nmsrs);
1113
1114 nr_good_msrs = vcpu->nmsrs - NR_BAD_MSRS;
1115 vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR,
1116 virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1117 vmcs_writel(VM_EXIT_MSR_STORE_ADDR,
1118 virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1119 vmcs_writel(VM_EXIT_MSR_LOAD_ADDR,
1120 virt_to_phys(vcpu->host_msrs + NR_BAD_MSRS));
1121 vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS, VM_EXIT_CONTROLS,
1122 (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */
1123 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, nr_good_msrs); /* 22.2.2 */
1124 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1125 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1126
1127
1128 /* 22.2.1, 20.8.1 */
1129 vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS,
1130 VM_ENTRY_CONTROLS, 0);
1131 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1132
1133 #ifdef CONFIG_X86_64
1134 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1135 vmcs_writel(TPR_THRESHOLD, 0);
1136 #endif
1137
1138 vmcs_writel(CR0_GUEST_HOST_MASK, KVM_GUEST_CR0_MASK);
1139 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1140
1141 vcpu->cr0 = 0x60000010;
1142 vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1143 vmx_set_cr4(vcpu, 0);
1144 #ifdef CONFIG_X86_64
1145 vmx_set_efer(vcpu, 0);
1146 #endif
1147
1148 return 0;
1149
1150 out:
1151 return ret;
1152 }
1153
1154 static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1155 {
1156 u16 ent[2];
1157 u16 cs;
1158 u16 ip;
1159 unsigned long flags;
1160 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1161 u16 sp = vmcs_readl(GUEST_RSP);
1162 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1163
1164 if (sp > ss_limit || sp - 6 > sp) {
1165 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1166 __FUNCTION__,
1167 vmcs_readl(GUEST_RSP),
1168 vmcs_readl(GUEST_SS_BASE),
1169 vmcs_read32(GUEST_SS_LIMIT));
1170 return;
1171 }
1172
1173 if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1174 sizeof(ent)) {
1175 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1176 return;
1177 }
1178
1179 flags = vmcs_readl(GUEST_RFLAGS);
1180 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1181 ip = vmcs_readl(GUEST_RIP);
1182
1183
1184 if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1185 kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1186 kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1187 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1188 return;
1189 }
1190
1191 vmcs_writel(GUEST_RFLAGS, flags &
1192 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1193 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1194 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1195 vmcs_writel(GUEST_RIP, ent[0]);
1196 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1197 }
1198
1199 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1200 {
1201 int word_index = __ffs(vcpu->irq_summary);
1202 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1203 int irq = word_index * BITS_PER_LONG + bit_index;
1204
1205 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1206 if (!vcpu->irq_pending[word_index])
1207 clear_bit(word_index, &vcpu->irq_summary);
1208
1209 if (vcpu->rmode.active) {
1210 inject_rmode_irq(vcpu, irq);
1211 return;
1212 }
1213 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1214 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1215 }
1216
1217 static void kvm_try_inject_irq(struct kvm_vcpu *vcpu)
1218 {
1219 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF)
1220 && (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0)
1221 /*
1222 * Interrupts enabled, and not blocked by sti or mov ss. Good.
1223 */
1224 kvm_do_inject_irq(vcpu);
1225 else
1226 /*
1227 * Interrupts blocked. Wait for unblock.
1228 */
1229 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1230 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL)
1231 | CPU_BASED_VIRTUAL_INTR_PENDING);
1232 }
1233
1234 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1235 {
1236 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1237
1238 set_debugreg(dbg->bp[0], 0);
1239 set_debugreg(dbg->bp[1], 1);
1240 set_debugreg(dbg->bp[2], 2);
1241 set_debugreg(dbg->bp[3], 3);
1242
1243 if (dbg->singlestep) {
1244 unsigned long flags;
1245
1246 flags = vmcs_readl(GUEST_RFLAGS);
1247 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1248 vmcs_writel(GUEST_RFLAGS, flags);
1249 }
1250 }
1251
1252 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1253 int vec, u32 err_code)
1254 {
1255 if (!vcpu->rmode.active)
1256 return 0;
1257
1258 if (vec == GP_VECTOR && err_code == 0)
1259 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1260 return 1;
1261 return 0;
1262 }
1263
1264 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1265 {
1266 u32 intr_info, error_code;
1267 unsigned long cr2, rip;
1268 u32 vect_info;
1269 enum emulation_result er;
1270
1271 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1272 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1273
1274 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1275 !is_page_fault(intr_info)) {
1276 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1277 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1278 }
1279
1280 if (is_external_interrupt(vect_info)) {
1281 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1282 set_bit(irq, vcpu->irq_pending);
1283 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1284 }
1285
1286 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1287 asm ("int $2");
1288 return 1;
1289 }
1290 error_code = 0;
1291 rip = vmcs_readl(GUEST_RIP);
1292 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1293 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1294 if (is_page_fault(intr_info)) {
1295 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1296
1297 spin_lock(&vcpu->kvm->lock);
1298 if (!vcpu->mmu.page_fault(vcpu, cr2, error_code)) {
1299 spin_unlock(&vcpu->kvm->lock);
1300 return 1;
1301 }
1302
1303 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1304 spin_unlock(&vcpu->kvm->lock);
1305
1306 switch (er) {
1307 case EMULATE_DONE:
1308 return 1;
1309 case EMULATE_DO_MMIO:
1310 ++kvm_stat.mmio_exits;
1311 kvm_run->exit_reason = KVM_EXIT_MMIO;
1312 return 0;
1313 case EMULATE_FAIL:
1314 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1315 break;
1316 default:
1317 BUG();
1318 }
1319 }
1320
1321 if (vcpu->rmode.active &&
1322 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1323 error_code))
1324 return 1;
1325
1326 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1327 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1328 return 0;
1329 }
1330 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1331 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1332 kvm_run->ex.error_code = error_code;
1333 return 0;
1334 }
1335
1336 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1337 struct kvm_run *kvm_run)
1338 {
1339 ++kvm_stat.irq_exits;
1340 return 1;
1341 }
1342
1343
1344 static int get_io_count(struct kvm_vcpu *vcpu, u64 *count)
1345 {
1346 u64 inst;
1347 gva_t rip;
1348 int countr_size;
1349 int i, n;
1350
1351 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1352 countr_size = 2;
1353 } else {
1354 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1355
1356 countr_size = (cs_ar & AR_L_MASK) ? 8:
1357 (cs_ar & AR_DB_MASK) ? 4: 2;
1358 }
1359
1360 rip = vmcs_readl(GUEST_RIP);
1361 if (countr_size != 8)
1362 rip += vmcs_readl(GUEST_CS_BASE);
1363
1364 n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1365
1366 for (i = 0; i < n; i++) {
1367 switch (((u8*)&inst)[i]) {
1368 case 0xf0:
1369 case 0xf2:
1370 case 0xf3:
1371 case 0x2e:
1372 case 0x36:
1373 case 0x3e:
1374 case 0x26:
1375 case 0x64:
1376 case 0x65:
1377 case 0x66:
1378 break;
1379 case 0x67:
1380 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1381 default:
1382 goto done;
1383 }
1384 }
1385 return 0;
1386 done:
1387 countr_size *= 8;
1388 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
1389 return 1;
1390 }
1391
1392 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1393 {
1394 u64 exit_qualification;
1395
1396 ++kvm_stat.io_exits;
1397 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1398 kvm_run->exit_reason = KVM_EXIT_IO;
1399 if (exit_qualification & 8)
1400 kvm_run->io.direction = KVM_EXIT_IO_IN;
1401 else
1402 kvm_run->io.direction = KVM_EXIT_IO_OUT;
1403 kvm_run->io.size = (exit_qualification & 7) + 1;
1404 kvm_run->io.string = (exit_qualification & 16) != 0;
1405 kvm_run->io.string_down
1406 = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1407 kvm_run->io.rep = (exit_qualification & 32) != 0;
1408 kvm_run->io.port = exit_qualification >> 16;
1409 if (kvm_run->io.string) {
1410 if (!get_io_count(vcpu, &kvm_run->io.count))
1411 return 1;
1412 kvm_run->io.address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1413 } else
1414 kvm_run->io.value = vcpu->regs[VCPU_REGS_RAX]; /* rax */
1415 return 0;
1416 }
1417
1418 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1419 {
1420 u64 address = vmcs_read64(EXIT_QUALIFICATION);
1421 int instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1422 spin_lock(&vcpu->kvm->lock);
1423 vcpu->mmu.inval_page(vcpu, address);
1424 spin_unlock(&vcpu->kvm->lock);
1425 vmcs_writel(GUEST_RIP, vmcs_readl(GUEST_RIP) + instruction_length);
1426 return 1;
1427 }
1428
1429 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1430 {
1431 u64 exit_qualification;
1432 int cr;
1433 int reg;
1434
1435 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1436 cr = exit_qualification & 15;
1437 reg = (exit_qualification >> 8) & 15;
1438 switch ((exit_qualification >> 4) & 3) {
1439 case 0: /* mov to cr */
1440 switch (cr) {
1441 case 0:
1442 vcpu_load_rsp_rip(vcpu);
1443 set_cr0(vcpu, vcpu->regs[reg]);
1444 skip_emulated_instruction(vcpu);
1445 return 1;
1446 case 3:
1447 vcpu_load_rsp_rip(vcpu);
1448 set_cr3(vcpu, vcpu->regs[reg]);
1449 skip_emulated_instruction(vcpu);
1450 return 1;
1451 case 4:
1452 vcpu_load_rsp_rip(vcpu);
1453 set_cr4(vcpu, vcpu->regs[reg]);
1454 skip_emulated_instruction(vcpu);
1455 return 1;
1456 case 8:
1457 vcpu_load_rsp_rip(vcpu);
1458 set_cr8(vcpu, vcpu->regs[reg]);
1459 skip_emulated_instruction(vcpu);
1460 return 1;
1461 };
1462 break;
1463 case 1: /*mov from cr*/
1464 switch (cr) {
1465 case 3:
1466 vcpu_load_rsp_rip(vcpu);
1467 vcpu->regs[reg] = vcpu->cr3;
1468 vcpu_put_rsp_rip(vcpu);
1469 skip_emulated_instruction(vcpu);
1470 return 1;
1471 case 8:
1472 printk(KERN_DEBUG "handle_cr: read CR8 "
1473 "cpu erratum AA15\n");
1474 vcpu_load_rsp_rip(vcpu);
1475 vcpu->regs[reg] = vcpu->cr8;
1476 vcpu_put_rsp_rip(vcpu);
1477 skip_emulated_instruction(vcpu);
1478 return 1;
1479 }
1480 break;
1481 case 3: /* lmsw */
1482 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1483
1484 skip_emulated_instruction(vcpu);
1485 return 1;
1486 default:
1487 break;
1488 }
1489 kvm_run->exit_reason = 0;
1490 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1491 (int)(exit_qualification >> 4) & 3, cr);
1492 return 0;
1493 }
1494
1495 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1496 {
1497 u64 exit_qualification;
1498 unsigned long val;
1499 int dr, reg;
1500
1501 /*
1502 * FIXME: this code assumes the host is debugging the guest.
1503 * need to deal with guest debugging itself too.
1504 */
1505 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1506 dr = exit_qualification & 7;
1507 reg = (exit_qualification >> 8) & 15;
1508 vcpu_load_rsp_rip(vcpu);
1509 if (exit_qualification & 16) {
1510 /* mov from dr */
1511 switch (dr) {
1512 case 6:
1513 val = 0xffff0ff0;
1514 break;
1515 case 7:
1516 val = 0x400;
1517 break;
1518 default:
1519 val = 0;
1520 }
1521 vcpu->regs[reg] = val;
1522 } else {
1523 /* mov to dr */
1524 }
1525 vcpu_put_rsp_rip(vcpu);
1526 skip_emulated_instruction(vcpu);
1527 return 1;
1528 }
1529
1530 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1531 {
1532 kvm_run->exit_reason = KVM_EXIT_CPUID;
1533 return 0;
1534 }
1535
1536 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1537 {
1538 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1539 u64 data;
1540
1541 if (vmx_get_msr(vcpu, ecx, &data)) {
1542 vmx_inject_gp(vcpu, 0);
1543 return 1;
1544 }
1545
1546 /* FIXME: handling of bits 32:63 of rax, rdx */
1547 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1548 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1549 skip_emulated_instruction(vcpu);
1550 return 1;
1551 }
1552
1553 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1554 {
1555 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1556 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1557 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1558
1559 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1560 vmx_inject_gp(vcpu, 0);
1561 return 1;
1562 }
1563
1564 skip_emulated_instruction(vcpu);
1565 return 1;
1566 }
1567
1568 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1569 struct kvm_run *kvm_run)
1570 {
1571 /* Turn off interrupt window reporting. */
1572 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1573 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL)
1574 & ~CPU_BASED_VIRTUAL_INTR_PENDING);
1575 return 1;
1576 }
1577
1578 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1579 {
1580 skip_emulated_instruction(vcpu);
1581 if (vcpu->irq_summary && (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF))
1582 return 1;
1583
1584 kvm_run->exit_reason = KVM_EXIT_HLT;
1585 return 0;
1586 }
1587
1588 /*
1589 * The exit handlers return 1 if the exit was handled fully and guest execution
1590 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1591 * to be done to userspace and return 0.
1592 */
1593 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1594 struct kvm_run *kvm_run) = {
1595 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
1596 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
1597 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
1598 [EXIT_REASON_INVLPG] = handle_invlpg,
1599 [EXIT_REASON_CR_ACCESS] = handle_cr,
1600 [EXIT_REASON_DR_ACCESS] = handle_dr,
1601 [EXIT_REASON_CPUID] = handle_cpuid,
1602 [EXIT_REASON_MSR_READ] = handle_rdmsr,
1603 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
1604 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
1605 [EXIT_REASON_HLT] = handle_halt,
1606 };
1607
1608 static const int kvm_vmx_max_exit_handlers =
1609 sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers);
1610
1611 /*
1612 * The guest has exited. See if we can fix it or if we need userspace
1613 * assistance.
1614 */
1615 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1616 {
1617 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1618 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
1619
1620 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
1621 exit_reason != EXIT_REASON_EXCEPTION_NMI )
1622 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
1623 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
1624 kvm_run->instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1625 if (exit_reason < kvm_vmx_max_exit_handlers
1626 && kvm_vmx_exit_handlers[exit_reason])
1627 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
1628 else {
1629 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1630 kvm_run->hw.hardware_exit_reason = exit_reason;
1631 }
1632 return 0;
1633 }
1634
1635 static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1636 {
1637 u8 fail;
1638 u16 fs_sel, gs_sel, ldt_sel;
1639 int fs_gs_ldt_reload_needed;
1640
1641 again:
1642 /*
1643 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1644 * allow segment selectors with cpl > 0 or ti == 1.
1645 */
1646 fs_sel = read_fs();
1647 gs_sel = read_gs();
1648 ldt_sel = read_ldt();
1649 fs_gs_ldt_reload_needed = (fs_sel & 7) | (gs_sel & 7) | ldt_sel;
1650 if (!fs_gs_ldt_reload_needed) {
1651 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1652 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1653 } else {
1654 vmcs_write16(HOST_FS_SELECTOR, 0);
1655 vmcs_write16(HOST_GS_SELECTOR, 0);
1656 }
1657
1658 #ifdef CONFIG_X86_64
1659 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1660 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1661 #else
1662 vmcs_writel(HOST_FS_BASE, segment_base(fs_sel));
1663 vmcs_writel(HOST_GS_BASE, segment_base(gs_sel));
1664 #endif
1665
1666 if (vcpu->irq_summary &&
1667 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1668 kvm_try_inject_irq(vcpu);
1669
1670 if (vcpu->guest_debug.enabled)
1671 kvm_guest_debug_pre(vcpu);
1672
1673 fx_save(vcpu->host_fx_image);
1674 fx_restore(vcpu->guest_fx_image);
1675
1676 save_msrs(vcpu->host_msrs, vcpu->nmsrs);
1677 load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1678
1679 asm (
1680 /* Store host registers */
1681 "pushf \n\t"
1682 #ifdef CONFIG_X86_64
1683 "push %%rax; push %%rbx; push %%rdx;"
1684 "push %%rsi; push %%rdi; push %%rbp;"
1685 "push %%r8; push %%r9; push %%r10; push %%r11;"
1686 "push %%r12; push %%r13; push %%r14; push %%r15;"
1687 "push %%rcx \n\t"
1688 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1689 #else
1690 "pusha; push %%ecx \n\t"
1691 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1692 #endif
1693 /* Check if vmlaunch of vmresume is needed */
1694 "cmp $0, %1 \n\t"
1695 /* Load guest registers. Don't clobber flags. */
1696 #ifdef CONFIG_X86_64
1697 "mov %c[cr2](%3), %%rax \n\t"
1698 "mov %%rax, %%cr2 \n\t"
1699 "mov %c[rax](%3), %%rax \n\t"
1700 "mov %c[rbx](%3), %%rbx \n\t"
1701 "mov %c[rdx](%3), %%rdx \n\t"
1702 "mov %c[rsi](%3), %%rsi \n\t"
1703 "mov %c[rdi](%3), %%rdi \n\t"
1704 "mov %c[rbp](%3), %%rbp \n\t"
1705 "mov %c[r8](%3), %%r8 \n\t"
1706 "mov %c[r9](%3), %%r9 \n\t"
1707 "mov %c[r10](%3), %%r10 \n\t"
1708 "mov %c[r11](%3), %%r11 \n\t"
1709 "mov %c[r12](%3), %%r12 \n\t"
1710 "mov %c[r13](%3), %%r13 \n\t"
1711 "mov %c[r14](%3), %%r14 \n\t"
1712 "mov %c[r15](%3), %%r15 \n\t"
1713 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
1714 #else
1715 "mov %c[cr2](%3), %%eax \n\t"
1716 "mov %%eax, %%cr2 \n\t"
1717 "mov %c[rax](%3), %%eax \n\t"
1718 "mov %c[rbx](%3), %%ebx \n\t"
1719 "mov %c[rdx](%3), %%edx \n\t"
1720 "mov %c[rsi](%3), %%esi \n\t"
1721 "mov %c[rdi](%3), %%edi \n\t"
1722 "mov %c[rbp](%3), %%ebp \n\t"
1723 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
1724 #endif
1725 /* Enter guest mode */
1726 "jne launched \n\t"
1727 ASM_VMX_VMLAUNCH "\n\t"
1728 "jmp kvm_vmx_return \n\t"
1729 "launched: " ASM_VMX_VMRESUME "\n\t"
1730 ".globl kvm_vmx_return \n\t"
1731 "kvm_vmx_return: "
1732 /* Save guest registers, load host registers, keep flags */
1733 #ifdef CONFIG_X86_64
1734 "xchg %3, 0(%%rsp) \n\t"
1735 "mov %%rax, %c[rax](%3) \n\t"
1736 "mov %%rbx, %c[rbx](%3) \n\t"
1737 "pushq 0(%%rsp); popq %c[rcx](%3) \n\t"
1738 "mov %%rdx, %c[rdx](%3) \n\t"
1739 "mov %%rsi, %c[rsi](%3) \n\t"
1740 "mov %%rdi, %c[rdi](%3) \n\t"
1741 "mov %%rbp, %c[rbp](%3) \n\t"
1742 "mov %%r8, %c[r8](%3) \n\t"
1743 "mov %%r9, %c[r9](%3) \n\t"
1744 "mov %%r10, %c[r10](%3) \n\t"
1745 "mov %%r11, %c[r11](%3) \n\t"
1746 "mov %%r12, %c[r12](%3) \n\t"
1747 "mov %%r13, %c[r13](%3) \n\t"
1748 "mov %%r14, %c[r14](%3) \n\t"
1749 "mov %%r15, %c[r15](%3) \n\t"
1750 "mov %%cr2, %%rax \n\t"
1751 "mov %%rax, %c[cr2](%3) \n\t"
1752 "mov 0(%%rsp), %3 \n\t"
1753
1754 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1755 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1756 "pop %%rbp; pop %%rdi; pop %%rsi;"
1757 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
1758 #else
1759 "xchg %3, 0(%%esp) \n\t"
1760 "mov %%eax, %c[rax](%3) \n\t"
1761 "mov %%ebx, %c[rbx](%3) \n\t"
1762 "pushl 0(%%esp); popl %c[rcx](%3) \n\t"
1763 "mov %%edx, %c[rdx](%3) \n\t"
1764 "mov %%esi, %c[rsi](%3) \n\t"
1765 "mov %%edi, %c[rdi](%3) \n\t"
1766 "mov %%ebp, %c[rbp](%3) \n\t"
1767 "mov %%cr2, %%eax \n\t"
1768 "mov %%eax, %c[cr2](%3) \n\t"
1769 "mov 0(%%esp), %3 \n\t"
1770
1771 "pop %%ecx; popa \n\t"
1772 #endif
1773 "setbe %0 \n\t"
1774 "popf \n\t"
1775 : "=g" (fail)
1776 : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP),
1777 "c"(vcpu),
1778 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
1779 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1780 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1781 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1782 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1783 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1784 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
1785 #ifdef CONFIG_X86_64
1786 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1787 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1788 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1789 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1790 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1791 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1792 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1793 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
1794 #endif
1795 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
1796 : "cc", "memory" );
1797
1798 ++kvm_stat.exits;
1799
1800 save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1801 load_msrs(vcpu->host_msrs, NR_BAD_MSRS);
1802
1803 fx_save(vcpu->guest_fx_image);
1804 fx_restore(vcpu->host_fx_image);
1805
1806 #ifndef CONFIG_X86_64
1807 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
1808 #endif
1809
1810 kvm_run->exit_type = 0;
1811 if (fail) {
1812 kvm_run->exit_type = KVM_EXIT_TYPE_FAIL_ENTRY;
1813 kvm_run->exit_reason = vmcs_read32(VM_INSTRUCTION_ERROR);
1814 } else {
1815 if (fs_gs_ldt_reload_needed) {
1816 load_ldt(ldt_sel);
1817 load_fs(fs_sel);
1818 /*
1819 * If we have to reload gs, we must take care to
1820 * preserve our gs base.
1821 */
1822 local_irq_disable();
1823 load_gs(gs_sel);
1824 #ifdef CONFIG_X86_64
1825 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
1826 #endif
1827 local_irq_enable();
1828
1829 reload_tss();
1830 }
1831 vcpu->launched = 1;
1832 kvm_run->exit_type = KVM_EXIT_TYPE_VM_EXIT;
1833 if (kvm_handle_exit(kvm_run, vcpu)) {
1834 /* Give scheduler a change to reschedule. */
1835 if (signal_pending(current)) {
1836 ++kvm_stat.signal_exits;
1837 return -EINTR;
1838 }
1839 kvm_resched(vcpu);
1840 goto again;
1841 }
1842 }
1843 return 0;
1844 }
1845
1846 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1847 {
1848 vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3));
1849 }
1850
1851 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
1852 unsigned long addr,
1853 u32 err_code)
1854 {
1855 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1856
1857 ++kvm_stat.pf_guest;
1858
1859 if (is_page_fault(vect_info)) {
1860 printk(KERN_DEBUG "inject_page_fault: "
1861 "double fault 0x%lx @ 0x%lx\n",
1862 addr, vmcs_readl(GUEST_RIP));
1863 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
1864 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1865 DF_VECTOR |
1866 INTR_TYPE_EXCEPTION |
1867 INTR_INFO_DELIEVER_CODE_MASK |
1868 INTR_INFO_VALID_MASK);
1869 return;
1870 }
1871 vcpu->cr2 = addr;
1872 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
1873 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1874 PF_VECTOR |
1875 INTR_TYPE_EXCEPTION |
1876 INTR_INFO_DELIEVER_CODE_MASK |
1877 INTR_INFO_VALID_MASK);
1878
1879 }
1880
1881 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
1882 {
1883 if (vcpu->vmcs) {
1884 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
1885 free_vmcs(vcpu->vmcs);
1886 vcpu->vmcs = NULL;
1887 }
1888 }
1889
1890 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
1891 {
1892 vmx_free_vmcs(vcpu);
1893 }
1894
1895 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
1896 {
1897 struct vmcs *vmcs;
1898
1899 vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1900 if (!vcpu->guest_msrs)
1901 return -ENOMEM;
1902
1903 vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1904 if (!vcpu->host_msrs)
1905 goto out_free_guest_msrs;
1906
1907 vmcs = alloc_vmcs();
1908 if (!vmcs)
1909 goto out_free_msrs;
1910
1911 vmcs_clear(vmcs);
1912 vcpu->vmcs = vmcs;
1913 vcpu->launched = 0;
1914
1915 return 0;
1916
1917 out_free_msrs:
1918 kfree(vcpu->host_msrs);
1919 vcpu->host_msrs = NULL;
1920
1921 out_free_guest_msrs:
1922 kfree(vcpu->guest_msrs);
1923 vcpu->guest_msrs = NULL;
1924
1925 return -ENOMEM;
1926 }
1927
1928 static struct kvm_arch_ops vmx_arch_ops = {
1929 .cpu_has_kvm_support = cpu_has_kvm_support,
1930 .disabled_by_bios = vmx_disabled_by_bios,
1931 .hardware_setup = hardware_setup,
1932 .hardware_unsetup = hardware_unsetup,
1933 .hardware_enable = hardware_enable,
1934 .hardware_disable = hardware_disable,
1935
1936 .vcpu_create = vmx_create_vcpu,
1937 .vcpu_free = vmx_free_vcpu,
1938
1939 .vcpu_load = vmx_vcpu_load,
1940 .vcpu_put = vmx_vcpu_put,
1941
1942 .set_guest_debug = set_guest_debug,
1943 .get_msr = vmx_get_msr,
1944 .set_msr = vmx_set_msr,
1945 .get_segment_base = vmx_get_segment_base,
1946 .get_segment = vmx_get_segment,
1947 .set_segment = vmx_set_segment,
1948 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
1949 .set_cr0 = vmx_set_cr0,
1950 .set_cr0_no_modeswitch = vmx_set_cr0_no_modeswitch,
1951 .set_cr3 = vmx_set_cr3,
1952 .set_cr4 = vmx_set_cr4,
1953 #ifdef CONFIG_X86_64
1954 .set_efer = vmx_set_efer,
1955 #endif
1956 .get_idt = vmx_get_idt,
1957 .set_idt = vmx_set_idt,
1958 .get_gdt = vmx_get_gdt,
1959 .set_gdt = vmx_set_gdt,
1960 .cache_regs = vcpu_load_rsp_rip,
1961 .decache_regs = vcpu_put_rsp_rip,
1962 .get_rflags = vmx_get_rflags,
1963 .set_rflags = vmx_set_rflags,
1964
1965 .tlb_flush = vmx_flush_tlb,
1966 .inject_page_fault = vmx_inject_page_fault,
1967
1968 .inject_gp = vmx_inject_gp,
1969
1970 .run = vmx_vcpu_run,
1971 .skip_emulated_instruction = skip_emulated_instruction,
1972 .vcpu_setup = vmx_vcpu_setup,
1973 };
1974
1975 static int __init vmx_init(void)
1976 {
1977 return kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
1978 }
1979
1980 static void __exit vmx_exit(void)
1981 {
1982 kvm_exit_arch();
1983 }
1984
1985 module_init(vmx_init)
1986 module_exit(vmx_exit)
Linux kernel - Deliverables
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