2 Driver for Philips tda1004xh OFDM Demodulator
4 (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * This driver needs external firmware. Please use the commands
24 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
25 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
26 * download/extract them, and then copy them to /usr/lib/hotplug/firmware.
28 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
29 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
31 #include <linux/init.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/device.h>
35 #include "dvb_frontend.h"
39 TDA1004X_DEMOD_TDA10045
,
40 TDA1004X_DEMOD_TDA10046
,
43 struct tda1004x_state
{
44 struct i2c_adapter
* i2c
;
45 struct dvb_frontend_ops ops
;
46 const struct tda1004x_config
* config
;
47 struct dvb_frontend frontend
;
49 /* private demod data */
51 enum tda1004x_demod demod_type
;
55 #define dprintk(args...) \
57 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
60 #define TDA1004X_CHIPID 0x00
61 #define TDA1004X_AUTO 0x01
62 #define TDA1004X_IN_CONF1 0x02
63 #define TDA1004X_IN_CONF2 0x03
64 #define TDA1004X_OUT_CONF1 0x04
65 #define TDA1004X_OUT_CONF2 0x05
66 #define TDA1004X_STATUS_CD 0x06
67 #define TDA1004X_CONFC4 0x07
68 #define TDA1004X_DSSPARE2 0x0C
69 #define TDA10045H_CODE_IN 0x0D
70 #define TDA10045H_FWPAGE 0x0E
71 #define TDA1004X_SCAN_CPT 0x10
72 #define TDA1004X_DSP_CMD 0x11
73 #define TDA1004X_DSP_ARG 0x12
74 #define TDA1004X_DSP_DATA1 0x13
75 #define TDA1004X_DSP_DATA2 0x14
76 #define TDA1004X_CONFADC1 0x15
77 #define TDA1004X_CONFC1 0x16
78 #define TDA10045H_S_AGC 0x1a
79 #define TDA10046H_AGC_TUN_LEVEL 0x1a
80 #define TDA1004X_SNR 0x1c
81 #define TDA1004X_CONF_TS1 0x1e
82 #define TDA1004X_CONF_TS2 0x1f
83 #define TDA1004X_CBER_RESET 0x20
84 #define TDA1004X_CBER_MSB 0x21
85 #define TDA1004X_CBER_LSB 0x22
86 #define TDA1004X_CVBER_LUT 0x23
87 #define TDA1004X_VBER_MSB 0x24
88 #define TDA1004X_VBER_MID 0x25
89 #define TDA1004X_VBER_LSB 0x26
90 #define TDA1004X_UNCOR 0x27
92 #define TDA10045H_CONFPLL_P 0x2D
93 #define TDA10045H_CONFPLL_M_MSB 0x2E
94 #define TDA10045H_CONFPLL_M_LSB 0x2F
95 #define TDA10045H_CONFPLL_N 0x30
97 #define TDA10046H_CONFPLL1 0x2D
98 #define TDA10046H_CONFPLL2 0x2F
99 #define TDA10046H_CONFPLL3 0x30
100 #define TDA10046H_TIME_WREF1 0x31
101 #define TDA10046H_TIME_WREF2 0x32
102 #define TDA10046H_TIME_WREF3 0x33
103 #define TDA10046H_TIME_WREF4 0x34
104 #define TDA10046H_TIME_WREF5 0x35
106 #define TDA10045H_UNSURW_MSB 0x31
107 #define TDA10045H_UNSURW_LSB 0x32
108 #define TDA10045H_WREF_MSB 0x33
109 #define TDA10045H_WREF_MID 0x34
110 #define TDA10045H_WREF_LSB 0x35
111 #define TDA10045H_MUXOUT 0x36
112 #define TDA1004X_CONFADC2 0x37
114 #define TDA10045H_IOFFSET 0x38
116 #define TDA10046H_CONF_TRISTATE1 0x3B
117 #define TDA10046H_CONF_TRISTATE2 0x3C
118 #define TDA10046H_CONF_POLARITY 0x3D
119 #define TDA10046H_FREQ_OFFSET 0x3E
120 #define TDA10046H_GPIO_OUT_SEL 0x41
121 #define TDA10046H_GPIO_SELECT 0x42
122 #define TDA10046H_AGC_CONF 0x43
123 #define TDA10046H_AGC_GAINS 0x46
124 #define TDA10046H_AGC_TUN_MIN 0x47
125 #define TDA10046H_AGC_TUN_MAX 0x48
126 #define TDA10046H_AGC_IF_MIN 0x49
127 #define TDA10046H_AGC_IF_MAX 0x4A
129 #define TDA10046H_FREQ_PHY2_MSB 0x4D
130 #define TDA10046H_FREQ_PHY2_LSB 0x4E
132 #define TDA10046H_CVBER_CTRL 0x4F
133 #define TDA10046H_AGC_IF_LEVEL 0x52
134 #define TDA10046H_CODE_CPT 0x57
135 #define TDA10046H_CODE_IN 0x58
138 static int tda1004x_write_byteI(struct tda1004x_state
*state
, int reg
, int data
)
141 u8 buf
[] = { reg
, data
};
142 struct i2c_msg msg
= { .flags
= 0, .buf
= buf
, .len
= 2 };
144 dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__
, reg
, data
);
146 msg
.addr
= state
->config
->demod_address
;
147 ret
= i2c_transfer(state
->i2c
, &msg
, 1);
150 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
151 __FUNCTION__
, reg
, data
, ret
);
153 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__
,
155 return (ret
!= 1) ? -1 : 0;
158 static int tda1004x_read_byte(struct tda1004x_state
*state
, int reg
)
163 struct i2c_msg msg
[] = {{ .flags
= 0, .buf
= b0
, .len
= 1 },
164 { .flags
= I2C_M_RD
, .buf
= b1
, .len
= 1 }};
166 dprintk("%s: reg=0x%x\n", __FUNCTION__
, reg
);
168 msg
[0].addr
= state
->config
->demod_address
;
169 msg
[1].addr
= state
->config
->demod_address
;
170 ret
= i2c_transfer(state
->i2c
, msg
, 2);
173 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__
, reg
,
178 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__
,
183 static int tda1004x_write_mask(struct tda1004x_state
*state
, int reg
, int mask
, int data
)
186 dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__
, reg
,
189 // read a byte and check
190 val
= tda1004x_read_byte(state
, reg
);
198 // write it out again
199 return tda1004x_write_byteI(state
, reg
, val
);
202 static int tda1004x_write_buf(struct tda1004x_state
*state
, int reg
, unsigned char *buf
, int len
)
207 dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__
, reg
, len
);
210 for (i
= 0; i
< len
; i
++) {
211 result
= tda1004x_write_byteI(state
, reg
+ i
, buf
[i
]);
219 static int tda1004x_enable_tuner_i2c(struct tda1004x_state
*state
)
222 dprintk("%s\n", __FUNCTION__
);
224 result
= tda1004x_write_mask(state
, TDA1004X_CONFC4
, 2, 2);
229 static int tda1004x_disable_tuner_i2c(struct tda1004x_state
*state
)
231 dprintk("%s\n", __FUNCTION__
);
233 return tda1004x_write_mask(state
, TDA1004X_CONFC4
, 2, 0);
236 static int tda10045h_set_bandwidth(struct tda1004x_state
*state
,
237 fe_bandwidth_t bandwidth
)
239 static u8 bandwidth_6mhz
[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
240 static u8 bandwidth_7mhz
[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
241 static u8 bandwidth_8mhz
[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
244 case BANDWIDTH_6_MHZ
:
245 tda1004x_write_buf(state
, TDA10045H_CONFPLL_P
, bandwidth_6mhz
, sizeof(bandwidth_6mhz
));
248 case BANDWIDTH_7_MHZ
:
249 tda1004x_write_buf(state
, TDA10045H_CONFPLL_P
, bandwidth_7mhz
, sizeof(bandwidth_7mhz
));
252 case BANDWIDTH_8_MHZ
:
253 tda1004x_write_buf(state
, TDA10045H_CONFPLL_P
, bandwidth_8mhz
, sizeof(bandwidth_8mhz
));
260 tda1004x_write_byteI(state
, TDA10045H_IOFFSET
, 0);
265 static int tda10046h_set_bandwidth(struct tda1004x_state
*state
,
266 fe_bandwidth_t bandwidth
)
268 static u8 bandwidth_6mhz
[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
269 static u8 bandwidth_7mhz
[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
270 static u8 bandwidth_8mhz
[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
273 case BANDWIDTH_6_MHZ
:
274 tda1004x_write_buf(state
, TDA10046H_TIME_WREF1
, bandwidth_6mhz
, sizeof(bandwidth_6mhz
));
277 case BANDWIDTH_7_MHZ
:
278 tda1004x_write_buf(state
, TDA10046H_TIME_WREF1
, bandwidth_7mhz
, sizeof(bandwidth_7mhz
));
281 case BANDWIDTH_8_MHZ
:
282 tda1004x_write_buf(state
, TDA10046H_TIME_WREF1
, bandwidth_8mhz
, sizeof(bandwidth_8mhz
));
292 static int tda1004x_do_upload(struct tda1004x_state
*state
,
293 unsigned char *mem
, unsigned int len
,
294 u8 dspCodeCounterReg
, u8 dspCodeInReg
)
297 struct i2c_msg fw_msg
= { .flags
= 0, .buf
= buf
, .len
= 0 };
301 /* clear code counter */
302 tda1004x_write_byteI(state
, dspCodeCounterReg
, 0);
303 fw_msg
.addr
= state
->config
->demod_address
;
305 buf
[0] = dspCodeInReg
;
307 // work out how much to send this time
313 memcpy(buf
+ 1, mem
+ pos
, tx_size
);
314 fw_msg
.len
= tx_size
+ 1;
315 if (i2c_transfer(state
->i2c
, &fw_msg
, 1) != 1) {
316 printk(KERN_ERR
"tda1004x: Error during firmware upload\n");
321 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__
, pos
);
323 // give the DSP a chance to settle 03/10/05 Hac
329 static int tda1004x_check_upload_ok(struct tda1004x_state
*state
)
332 unsigned long timeout
;
334 if (state
->demod_type
== TDA1004X_DEMOD_TDA10046
) {
335 timeout
= jiffies
+ 2 * HZ
;
336 while(!(tda1004x_read_byte(state
, TDA1004X_STATUS_CD
) & 0x20)) {
337 if (time_after(jiffies
, timeout
)) {
338 printk(KERN_ERR
"tda1004x: timeout waiting for DSP ready\n");
346 // check upload was OK
347 tda1004x_write_mask(state
, TDA1004X_CONFC4
, 0x10, 0); // we want to read from the DSP
348 tda1004x_write_byteI(state
, TDA1004X_DSP_CMD
, 0x67);
350 data1
= tda1004x_read_byte(state
, TDA1004X_DSP_DATA1
);
351 data2
= tda1004x_read_byte(state
, TDA1004X_DSP_DATA2
);
352 if (data1
!= 0x67 || data2
< 0x20 || data2
> 0x2a) {
353 printk(KERN_INFO
"tda1004x: found firmware revision %x -- invalid\n", data2
);
356 printk(KERN_INFO
"tda1004x: found firmware revision %x -- ok\n", data2
);
360 static int tda10045_fwupload(struct dvb_frontend
* fe
)
362 struct tda1004x_state
* state
= fe
->demodulator_priv
;
364 const struct firmware
*fw
;
366 /* don't re-upload unless necessary */
367 if (tda1004x_check_upload_ok(state
) == 0)
370 /* request the firmware, this will block until someone uploads it */
371 printk(KERN_INFO
"tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE
);
372 ret
= state
->config
->request_firmware(fe
, &fw
, TDA10045_DEFAULT_FIRMWARE
);
374 printk(KERN_ERR
"tda1004x: no firmware upload (timeout or file not found?)\n");
379 tda1004x_write_mask(state
, TDA1004X_CONFC4
, 0x10, 0);
380 tda1004x_write_mask(state
, TDA1004X_CONFC4
, 8, 8);
381 tda1004x_write_mask(state
, TDA1004X_CONFC4
, 8, 0);
385 tda10045h_set_bandwidth(state
, BANDWIDTH_8_MHZ
);
387 ret
= tda1004x_do_upload(state
, fw
->data
, fw
->size
, TDA10045H_FWPAGE
, TDA10045H_CODE_IN
);
390 printk(KERN_INFO
"tda1004x: firmware upload complete\n");
392 /* wait for DSP to initialise */
393 /* DSPREADY doesn't seem to work on the TDA10045H */
396 return tda1004x_check_upload_ok(state
);
399 static void tda10046_init_plls(struct dvb_frontend
* fe
)
401 struct tda1004x_state
* state
= fe
->demodulator_priv
;
403 tda1004x_write_byteI(state
, TDA10046H_CONFPLL1
, 0xf0);
404 tda1004x_write_byteI(state
, TDA10046H_CONFPLL2
, 10); // PLL M = 10
405 if (state
->config
->xtal_freq
== TDA10046_XTAL_4M
) {
406 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__
);
407 tda1004x_write_byteI(state
, TDA10046H_CONFPLL3
, 0); // PLL P = N = 0
409 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__
);
410 tda1004x_write_byteI(state
, TDA10046H_CONFPLL3
, 3); // PLL P = 0, N = 3
412 tda1004x_write_byteI(state
, TDA10046H_FREQ_OFFSET
, 99);
413 switch (state
->config
->if_freq
) {
414 case TDA10046_FREQ_3617
:
415 tda1004x_write_byteI(state
, TDA10046H_FREQ_PHY2_MSB
, 0xd4);
416 tda1004x_write_byteI(state
, TDA10046H_FREQ_PHY2_LSB
, 0x2c);
418 case TDA10046_FREQ_3613
:
419 tda1004x_write_byteI(state
, TDA10046H_FREQ_PHY2_MSB
, 0xd4);
420 tda1004x_write_byteI(state
, TDA10046H_FREQ_PHY2_LSB
, 0x13);
423 tda10046h_set_bandwidth(state
, BANDWIDTH_8_MHZ
); // default bandwidth 8 MHz
426 static int tda10046_fwupload(struct dvb_frontend
* fe
)
428 struct tda1004x_state
* state
= fe
->demodulator_priv
;
430 const struct firmware
*fw
;
432 /* reset + wake up chip */
433 tda1004x_write_byteI(state
, TDA1004X_CONFC4
, 0);
434 tda1004x_write_mask(state
, TDA10046H_CONF_TRISTATE1
, 1, 0);
435 /* let the clocks recover from sleep */
438 /* don't re-upload unless necessary */
439 if (tda1004x_check_upload_ok(state
) == 0)
443 tda10046_init_plls(fe
);
445 if (state
->config
->request_firmware
!= NULL
) {
446 /* request the firmware, this will block until someone uploads it */
447 printk(KERN_INFO
"tda1004x: waiting for firmware upload...\n");
448 ret
= state
->config
->request_firmware(fe
, &fw
, TDA10046_DEFAULT_FIRMWARE
);
450 printk(KERN_ERR
"tda1004x: no firmware upload (timeout or file not found?)\n");
453 tda1004x_write_mask(state
, TDA1004X_CONFC4
, 8, 8); // going to boot from HOST
454 ret
= tda1004x_do_upload(state
, fw
->data
, fw
->size
, TDA10046H_CODE_CPT
, TDA10046H_CODE_IN
);
458 /* boot from firmware eeprom */
459 /* Hac Note: we might need to do some GPIO Magic here */
460 printk(KERN_INFO
"tda1004x: booting from eeprom\n");
461 tda1004x_write_mask(state
, TDA1004X_CONFC4
, 4, 4);
464 return tda1004x_check_upload_ok(state
);
467 static int tda1004x_encode_fec(int fec
)
469 // convert known FEC values
487 static int tda1004x_decode_fec(int tdafec
)
489 // convert known FEC values
507 int tda1004x_write_byte(struct dvb_frontend
* fe
, int reg
, int data
)
509 struct tda1004x_state
* state
= fe
->demodulator_priv
;
511 return tda1004x_write_byteI(state
, reg
, data
);
514 static int tda10045_init(struct dvb_frontend
* fe
)
516 struct tda1004x_state
* state
= fe
->demodulator_priv
;
518 dprintk("%s\n", __FUNCTION__
);
520 if (state
->initialised
)
523 if (tda10045_fwupload(fe
)) {
524 printk("tda1004x: firmware upload failed\n");
528 tda1004x_write_mask(state
, TDA1004X_CONFADC1
, 0x10, 0); // wake up the ADC
531 if (state
->config
->pll_init
) {
532 tda1004x_enable_tuner_i2c(state
);
533 state
->config
->pll_init(fe
);
534 tda1004x_disable_tuner_i2c(state
);
538 tda1004x_write_mask(state
, TDA1004X_CONFC4
, 0x20, 0); // disable DSP watchdog timer
539 tda1004x_write_mask(state
, TDA1004X_AUTO
, 8, 0); // select HP stream
540 tda1004x_write_mask(state
, TDA1004X_CONFC1
, 0x40, 0); // set polarity of VAGC signal
541 tda1004x_write_mask(state
, TDA1004X_CONFC1
, 0x80, 0x80); // enable pulse killer
542 tda1004x_write_mask(state
, TDA1004X_AUTO
, 0x10, 0x10); // enable auto offset
543 tda1004x_write_mask(state
, TDA1004X_IN_CONF2
, 0xC0, 0x0); // no frequency offset
544 tda1004x_write_byteI(state
, TDA1004X_CONF_TS1
, 0); // setup MPEG2 TS interface
545 tda1004x_write_byteI(state
, TDA1004X_CONF_TS2
, 0); // setup MPEG2 TS interface
546 tda1004x_write_mask(state
, TDA1004X_VBER_MSB
, 0xe0, 0xa0); // 10^6 VBER measurement bits
547 tda1004x_write_mask(state
, TDA1004X_CONFC1
, 0x10, 0); // VAGC polarity
548 tda1004x_write_byteI(state
, TDA1004X_CONFADC1
, 0x2e);
550 tda1004x_write_mask(state
, 0x1f, 0x01, state
->config
->invert_oclk
);
552 state
->initialised
= 1;
556 static int tda10046_init(struct dvb_frontend
* fe
)
558 struct tda1004x_state
* state
= fe
->demodulator_priv
;
559 dprintk("%s\n", __FUNCTION__
);
561 if (state
->initialised
)
564 if (tda10046_fwupload(fe
)) {
565 printk("tda1004x: firmware upload failed\n");
569 // Init the tuner PLL
570 if (state
->config
->pll_init
) {
571 tda1004x_enable_tuner_i2c(state
);
572 state
->config
->pll_init(fe
);
573 tda1004x_disable_tuner_i2c(state
);
577 tda1004x_write_mask(state
, TDA1004X_CONFC4
, 0x20, 0); // disable DSP watchdog timer
578 tda1004x_write_byteI(state
, TDA1004X_AUTO
, 7); // select HP stream
579 tda1004x_write_byteI(state
, TDA1004X_CONFC1
, 8); // disable pulse killer
581 tda10046_init_plls(fe
);
582 switch (state
->config
->agc_config
) {
583 case TDA10046_AGC_DEFAULT
:
584 tda1004x_write_byteI(state
, TDA10046H_AGC_CONF
, 0x00); // AGC setup
585 tda1004x_write_byteI(state
, TDA10046H_CONF_POLARITY
, 0x60); // set AGC polarities
587 case TDA10046_AGC_IFO_AUTO_NEG
:
588 tda1004x_write_byteI(state
, TDA10046H_AGC_CONF
, 0x0a); // AGC setup
589 tda1004x_write_byteI(state
, TDA10046H_CONF_POLARITY
, 0x60); // set AGC polarities
592 tda1004x_write_byteI(state
, TDA10046H_CONF_TRISTATE1
, 0x61); // Turn both AGC outputs on
593 tda1004x_write_byteI(state
, TDA10046H_AGC_TUN_MIN
, 0); // }
594 tda1004x_write_byteI(state
, TDA10046H_AGC_TUN_MAX
, 0xff); // } AGC min/max values
595 tda1004x_write_byteI(state
, TDA10046H_AGC_IF_MIN
, 0); // }
596 tda1004x_write_byteI(state
, TDA10046H_AGC_IF_MAX
, 0xff); // }
597 tda1004x_write_byteI(state
, TDA10046H_AGC_GAINS
, 1); // IF gain 2, TUN gain 1
598 tda1004x_write_byteI(state
, TDA10046H_CVBER_CTRL
, 0x1a); // 10^6 VBER measurement bits
599 tda1004x_write_byteI(state
, TDA1004X_CONF_TS1
, 7); // MPEG2 interface config
600 tda1004x_write_byteI(state
, TDA1004X_CONF_TS2
, 0xc0); // MPEG2 interface config
601 tda1004x_write_mask(state
, 0x3a, 0x80, state
->config
->invert_oclk
<< 7);
603 tda1004x_write_byteI(state
, TDA10046H_CONF_TRISTATE2
, 0xe1); // tristate setup
604 tda1004x_write_byteI(state
, TDA10046H_GPIO_OUT_SEL
, 0xcc); // GPIO output config
605 tda1004x_write_byteI(state
, TDA10046H_GPIO_SELECT
, 8); // GPIO select
607 state
->initialised
= 1;
611 static int tda1004x_set_fe(struct dvb_frontend
* fe
,
612 struct dvb_frontend_parameters
*fe_params
)
614 struct tda1004x_state
* state
= fe
->demodulator_priv
;
618 dprintk("%s\n", __FUNCTION__
);
620 if (state
->demod_type
== TDA1004X_DEMOD_TDA10046
) {
622 tda1004x_write_mask(state
, TDA1004X_AUTO
, 0x10, 0x10);
623 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x80, 0);
624 tda1004x_write_mask(state
, TDA1004X_IN_CONF2
, 0xC0, 0);
626 // disable agc_conf[2]
627 tda1004x_write_mask(state
, TDA10046H_AGC_CONF
, 4, 0);
631 tda1004x_enable_tuner_i2c(state
);
632 state
->config
->pll_set(fe
, fe_params
);
633 tda1004x_disable_tuner_i2c(state
);
635 // Hardcoded to use auto as much as possible on the TDA10045 as it
636 // is very unreliable if AUTO mode is _not_ used.
637 if (state
->demod_type
== TDA1004X_DEMOD_TDA10045
) {
638 fe_params
->u
.ofdm
.code_rate_HP
= FEC_AUTO
;
639 fe_params
->u
.ofdm
.guard_interval
= GUARD_INTERVAL_AUTO
;
640 fe_params
->u
.ofdm
.transmission_mode
= TRANSMISSION_MODE_AUTO
;
643 // Set standard params.. or put them to auto
644 if ((fe_params
->u
.ofdm
.code_rate_HP
== FEC_AUTO
) ||
645 (fe_params
->u
.ofdm
.code_rate_LP
== FEC_AUTO
) ||
646 (fe_params
->u
.ofdm
.constellation
== QAM_AUTO
) ||
647 (fe_params
->u
.ofdm
.hierarchy_information
== HIERARCHY_AUTO
)) {
648 tda1004x_write_mask(state
, TDA1004X_AUTO
, 1, 1); // enable auto
649 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x03, 0); // turn off constellation bits
650 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x60, 0); // turn off hierarchy bits
651 tda1004x_write_mask(state
, TDA1004X_IN_CONF2
, 0x3f, 0); // turn off FEC bits
653 tda1004x_write_mask(state
, TDA1004X_AUTO
, 1, 0); // disable auto
656 tmp
= tda1004x_encode_fec(fe_params
->u
.ofdm
.code_rate_HP
);
659 tda1004x_write_mask(state
, TDA1004X_IN_CONF2
, 7, tmp
);
662 tmp
= tda1004x_encode_fec(fe_params
->u
.ofdm
.code_rate_LP
);
665 tda1004x_write_mask(state
, TDA1004X_IN_CONF2
, 0x38, tmp
<< 3);
668 switch (fe_params
->u
.ofdm
.constellation
) {
670 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 3, 0);
674 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 3, 1);
678 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 3, 2);
686 switch (fe_params
->u
.ofdm
.hierarchy_information
) {
688 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x60, 0 << 5);
692 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x60, 1 << 5);
696 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x60, 2 << 5);
700 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x60, 3 << 5);
709 switch (state
->demod_type
) {
710 case TDA1004X_DEMOD_TDA10045
:
711 tda10045h_set_bandwidth(state
, fe_params
->u
.ofdm
.bandwidth
);
714 case TDA1004X_DEMOD_TDA10046
:
715 tda10046h_set_bandwidth(state
, fe_params
->u
.ofdm
.bandwidth
);
720 inversion
= fe_params
->inversion
;
721 if (state
->config
->invert
)
722 inversion
= inversion
? INVERSION_OFF
: INVERSION_ON
;
725 tda1004x_write_mask(state
, TDA1004X_CONFC1
, 0x20, 0);
729 tda1004x_write_mask(state
, TDA1004X_CONFC1
, 0x20, 0x20);
736 // set guard interval
737 switch (fe_params
->u
.ofdm
.guard_interval
) {
738 case GUARD_INTERVAL_1_32
:
739 tda1004x_write_mask(state
, TDA1004X_AUTO
, 2, 0);
740 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x0c, 0 << 2);
743 case GUARD_INTERVAL_1_16
:
744 tda1004x_write_mask(state
, TDA1004X_AUTO
, 2, 0);
745 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x0c, 1 << 2);
748 case GUARD_INTERVAL_1_8
:
749 tda1004x_write_mask(state
, TDA1004X_AUTO
, 2, 0);
750 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x0c, 2 << 2);
753 case GUARD_INTERVAL_1_4
:
754 tda1004x_write_mask(state
, TDA1004X_AUTO
, 2, 0);
755 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x0c, 3 << 2);
758 case GUARD_INTERVAL_AUTO
:
759 tda1004x_write_mask(state
, TDA1004X_AUTO
, 2, 2);
760 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x0c, 0 << 2);
767 // set transmission mode
768 switch (fe_params
->u
.ofdm
.transmission_mode
) {
769 case TRANSMISSION_MODE_2K
:
770 tda1004x_write_mask(state
, TDA1004X_AUTO
, 4, 0);
771 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x10, 0 << 4);
774 case TRANSMISSION_MODE_8K
:
775 tda1004x_write_mask(state
, TDA1004X_AUTO
, 4, 0);
776 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x10, 1 << 4);
779 case TRANSMISSION_MODE_AUTO
:
780 tda1004x_write_mask(state
, TDA1004X_AUTO
, 4, 4);
781 tda1004x_write_mask(state
, TDA1004X_IN_CONF1
, 0x10, 0);
789 switch (state
->demod_type
) {
790 case TDA1004X_DEMOD_TDA10045
:
791 tda1004x_write_mask(state
, TDA1004X_CONFC4
, 8, 8);
792 tda1004x_write_mask(state
, TDA1004X_CONFC4
, 8, 0);
795 case TDA1004X_DEMOD_TDA10046
:
796 tda1004x_write_mask(state
, TDA1004X_AUTO
, 0x40, 0x40);
805 static int tda1004x_get_fe(struct dvb_frontend
* fe
, struct dvb_frontend_parameters
*fe_params
)
807 struct tda1004x_state
* state
= fe
->demodulator_priv
;
808 dprintk("%s\n", __FUNCTION__
);
811 fe_params
->inversion
= INVERSION_OFF
;
812 if (tda1004x_read_byte(state
, TDA1004X_CONFC1
) & 0x20)
813 fe_params
->inversion
= INVERSION_ON
;
814 if (state
->config
->invert
)
815 fe_params
->inversion
= fe_params
->inversion
? INVERSION_OFF
: INVERSION_ON
;
818 switch (state
->demod_type
) {
819 case TDA1004X_DEMOD_TDA10045
:
820 switch (tda1004x_read_byte(state
, TDA10045H_WREF_LSB
)) {
822 fe_params
->u
.ofdm
.bandwidth
= BANDWIDTH_8_MHZ
;
825 fe_params
->u
.ofdm
.bandwidth
= BANDWIDTH_7_MHZ
;
828 fe_params
->u
.ofdm
.bandwidth
= BANDWIDTH_6_MHZ
;
833 case TDA1004X_DEMOD_TDA10046
:
834 switch (tda1004x_read_byte(state
, TDA10046H_TIME_WREF1
)) {
836 fe_params
->u
.ofdm
.bandwidth
= BANDWIDTH_8_MHZ
;
839 fe_params
->u
.ofdm
.bandwidth
= BANDWIDTH_7_MHZ
;
842 fe_params
->u
.ofdm
.bandwidth
= BANDWIDTH_6_MHZ
;
849 fe_params
->u
.ofdm
.code_rate_HP
=
850 tda1004x_decode_fec(tda1004x_read_byte(state
, TDA1004X_OUT_CONF2
) & 7);
851 fe_params
->u
.ofdm
.code_rate_LP
=
852 tda1004x_decode_fec((tda1004x_read_byte(state
, TDA1004X_OUT_CONF2
) >> 3) & 7);
855 switch (tda1004x_read_byte(state
, TDA1004X_OUT_CONF1
) & 3) {
857 fe_params
->u
.ofdm
.constellation
= QPSK
;
860 fe_params
->u
.ofdm
.constellation
= QAM_16
;
863 fe_params
->u
.ofdm
.constellation
= QAM_64
;
868 fe_params
->u
.ofdm
.transmission_mode
= TRANSMISSION_MODE_2K
;
869 if (tda1004x_read_byte(state
, TDA1004X_OUT_CONF1
) & 0x10)
870 fe_params
->u
.ofdm
.transmission_mode
= TRANSMISSION_MODE_8K
;
873 switch ((tda1004x_read_byte(state
, TDA1004X_OUT_CONF1
) & 0x0c) >> 2) {
875 fe_params
->u
.ofdm
.guard_interval
= GUARD_INTERVAL_1_32
;
878 fe_params
->u
.ofdm
.guard_interval
= GUARD_INTERVAL_1_16
;
881 fe_params
->u
.ofdm
.guard_interval
= GUARD_INTERVAL_1_8
;
884 fe_params
->u
.ofdm
.guard_interval
= GUARD_INTERVAL_1_4
;
889 switch ((tda1004x_read_byte(state
, TDA1004X_OUT_CONF1
) & 0x60) >> 5) {
891 fe_params
->u
.ofdm
.hierarchy_information
= HIERARCHY_NONE
;
894 fe_params
->u
.ofdm
.hierarchy_information
= HIERARCHY_1
;
897 fe_params
->u
.ofdm
.hierarchy_information
= HIERARCHY_2
;
900 fe_params
->u
.ofdm
.hierarchy_information
= HIERARCHY_4
;
907 static int tda1004x_read_status(struct dvb_frontend
* fe
, fe_status_t
* fe_status
)
909 struct tda1004x_state
* state
= fe
->demodulator_priv
;
914 dprintk("%s\n", __FUNCTION__
);
917 status
= tda1004x_read_byte(state
, TDA1004X_STATUS_CD
);
924 *fe_status
|= FE_HAS_SIGNAL
;
926 *fe_status
|= FE_HAS_CARRIER
;
928 *fe_status
|= FE_HAS_VITERBI
| FE_HAS_SYNC
| FE_HAS_LOCK
;
930 // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
931 // is getting anything valid
932 if (!(*fe_status
& FE_HAS_VITERBI
)) {
934 cber
= tda1004x_read_byte(state
, TDA1004X_CBER_LSB
);
937 status
= tda1004x_read_byte(state
, TDA1004X_CBER_MSB
);
940 cber
|= (status
<< 8);
941 tda1004x_read_byte(state
, TDA1004X_CBER_RESET
);
944 *fe_status
|= FE_HAS_VITERBI
;
947 // if we DO have some valid VITERBI output, but don't already have SYNC
948 // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
949 if ((*fe_status
& FE_HAS_VITERBI
) && (!(*fe_status
& FE_HAS_SYNC
))) {
951 vber
= tda1004x_read_byte(state
, TDA1004X_VBER_LSB
);
954 status
= tda1004x_read_byte(state
, TDA1004X_VBER_MID
);
957 vber
|= (status
<< 8);
958 status
= tda1004x_read_byte(state
, TDA1004X_VBER_MSB
);
961 vber
|= ((status
<< 16) & 0x0f);
962 tda1004x_read_byte(state
, TDA1004X_CVBER_LUT
);
964 // if RS has passed some valid TS packets, then we must be
965 // getting some SYNC bytes
967 *fe_status
|= FE_HAS_SYNC
;
971 dprintk("%s: fe_status=0x%x\n", __FUNCTION__
, *fe_status
);
975 static int tda1004x_read_signal_strength(struct dvb_frontend
* fe
, u16
* signal
)
977 struct tda1004x_state
* state
= fe
->demodulator_priv
;
981 dprintk("%s\n", __FUNCTION__
);
983 // determine the register to use
984 switch (state
->demod_type
) {
985 case TDA1004X_DEMOD_TDA10045
:
986 reg
= TDA10045H_S_AGC
;
989 case TDA1004X_DEMOD_TDA10046
:
990 reg
= TDA10046H_AGC_IF_LEVEL
;
995 tmp
= tda1004x_read_byte(state
, reg
);
999 *signal
= (tmp
<< 8) | tmp
;
1000 dprintk("%s: signal=0x%x\n", __FUNCTION__
, *signal
);
1004 static int tda1004x_read_snr(struct dvb_frontend
* fe
, u16
* snr
)
1006 struct tda1004x_state
* state
= fe
->demodulator_priv
;
1009 dprintk("%s\n", __FUNCTION__
);
1012 tmp
= tda1004x_read_byte(state
, TDA1004X_SNR
);
1018 *snr
= ((tmp
<< 8) | tmp
);
1019 dprintk("%s: snr=0x%x\n", __FUNCTION__
, *snr
);
1023 static int tda1004x_read_ucblocks(struct dvb_frontend
* fe
, u32
* ucblocks
)
1025 struct tda1004x_state
* state
= fe
->demodulator_priv
;
1030 dprintk("%s\n", __FUNCTION__
);
1032 // read the UCBLOCKS and reset
1034 tmp
= tda1004x_read_byte(state
, TDA1004X_UNCOR
);
1038 while (counter
++ < 5) {
1039 tda1004x_write_mask(state
, TDA1004X_UNCOR
, 0x80, 0);
1040 tda1004x_write_mask(state
, TDA1004X_UNCOR
, 0x80, 0);
1041 tda1004x_write_mask(state
, TDA1004X_UNCOR
, 0x80, 0);
1043 tmp2
= tda1004x_read_byte(state
, TDA1004X_UNCOR
);
1047 if ((tmp2
< tmp
) || (tmp2
== 0))
1054 *ucblocks
= 0xffffffff;
1056 dprintk("%s: ucblocks=0x%x\n", __FUNCTION__
, *ucblocks
);
1060 static int tda1004x_read_ber(struct dvb_frontend
* fe
, u32
* ber
)
1062 struct tda1004x_state
* state
= fe
->demodulator_priv
;
1065 dprintk("%s\n", __FUNCTION__
);
1068 tmp
= tda1004x_read_byte(state
, TDA1004X_CBER_LSB
);
1072 tmp
= tda1004x_read_byte(state
, TDA1004X_CBER_MSB
);
1076 tda1004x_read_byte(state
, TDA1004X_CBER_RESET
);
1078 dprintk("%s: ber=0x%x\n", __FUNCTION__
, *ber
);
1082 static int tda1004x_sleep(struct dvb_frontend
* fe
)
1084 struct tda1004x_state
* state
= fe
->demodulator_priv
;
1086 switch (state
->demod_type
) {
1087 case TDA1004X_DEMOD_TDA10045
:
1088 tda1004x_write_mask(state
, TDA1004X_CONFADC1
, 0x10, 0x10);
1091 case TDA1004X_DEMOD_TDA10046
:
1092 tda1004x_write_mask(state
, TDA1004X_CONFC4
, 1, 1);
1093 if (state
->config
->pll_sleep
!= NULL
)
1094 state
->config
->pll_sleep(fe
);
1097 state
->initialised
= 0;
1102 static int tda1004x_get_tune_settings(struct dvb_frontend
* fe
, struct dvb_frontend_tune_settings
* fesettings
)
1104 fesettings
->min_delay_ms
= 800;
1105 fesettings
->step_size
= 166667;
1106 fesettings
->max_drift
= 166667*2;
1110 static void tda1004x_release(struct dvb_frontend
* fe
)
1112 struct tda1004x_state
*state
= fe
->demodulator_priv
;
1116 static struct dvb_frontend_ops tda10045_ops
= {
1118 .name
= "Philips TDA10045H DVB-T",
1120 .frequency_min
= 51000000,
1121 .frequency_max
= 858000000,
1122 .frequency_stepsize
= 166667,
1124 FE_CAN_FEC_1_2
| FE_CAN_FEC_2_3
| FE_CAN_FEC_3_4
|
1125 FE_CAN_FEC_5_6
| FE_CAN_FEC_7_8
| FE_CAN_FEC_AUTO
|
1126 FE_CAN_QPSK
| FE_CAN_QAM_16
| FE_CAN_QAM_64
| FE_CAN_QAM_AUTO
|
1127 FE_CAN_TRANSMISSION_MODE_AUTO
| FE_CAN_GUARD_INTERVAL_AUTO
1130 .release
= tda1004x_release
,
1132 .init
= tda10045_init
,
1133 .sleep
= tda1004x_sleep
,
1135 .set_frontend
= tda1004x_set_fe
,
1136 .get_frontend
= tda1004x_get_fe
,
1137 .get_tune_settings
= tda1004x_get_tune_settings
,
1139 .read_status
= tda1004x_read_status
,
1140 .read_ber
= tda1004x_read_ber
,
1141 .read_signal_strength
= tda1004x_read_signal_strength
,
1142 .read_snr
= tda1004x_read_snr
,
1143 .read_ucblocks
= tda1004x_read_ucblocks
,
1146 struct dvb_frontend
* tda10045_attach(const struct tda1004x_config
* config
,
1147 struct i2c_adapter
* i2c
)
1149 struct tda1004x_state
*state
;
1151 /* allocate memory for the internal state */
1152 state
= kmalloc(sizeof(struct tda1004x_state
), GFP_KERNEL
);
1156 /* setup the state */
1157 state
->config
= config
;
1159 memcpy(&state
->ops
, &tda10045_ops
, sizeof(struct dvb_frontend_ops
));
1160 state
->initialised
= 0;
1161 state
->demod_type
= TDA1004X_DEMOD_TDA10045
;
1163 /* check if the demod is there */
1164 if (tda1004x_read_byte(state
, TDA1004X_CHIPID
) != 0x25) {
1169 /* create dvb_frontend */
1170 state
->frontend
.ops
= &state
->ops
;
1171 state
->frontend
.demodulator_priv
= state
;
1172 return &state
->frontend
;
1175 static struct dvb_frontend_ops tda10046_ops
= {
1177 .name
= "Philips TDA10046H DVB-T",
1179 .frequency_min
= 51000000,
1180 .frequency_max
= 858000000,
1181 .frequency_stepsize
= 166667,
1183 FE_CAN_FEC_1_2
| FE_CAN_FEC_2_3
| FE_CAN_FEC_3_4
|
1184 FE_CAN_FEC_5_6
| FE_CAN_FEC_7_8
| FE_CAN_FEC_AUTO
|
1185 FE_CAN_QPSK
| FE_CAN_QAM_16
| FE_CAN_QAM_64
| FE_CAN_QAM_AUTO
|
1186 FE_CAN_TRANSMISSION_MODE_AUTO
| FE_CAN_GUARD_INTERVAL_AUTO
1189 .release
= tda1004x_release
,
1191 .init
= tda10046_init
,
1192 .sleep
= tda1004x_sleep
,
1194 .set_frontend
= tda1004x_set_fe
,
1195 .get_frontend
= tda1004x_get_fe
,
1196 .get_tune_settings
= tda1004x_get_tune_settings
,
1198 .read_status
= tda1004x_read_status
,
1199 .read_ber
= tda1004x_read_ber
,
1200 .read_signal_strength
= tda1004x_read_signal_strength
,
1201 .read_snr
= tda1004x_read_snr
,
1202 .read_ucblocks
= tda1004x_read_ucblocks
,
1205 struct dvb_frontend
* tda10046_attach(const struct tda1004x_config
* config
,
1206 struct i2c_adapter
* i2c
)
1208 struct tda1004x_state
*state
;
1210 /* allocate memory for the internal state */
1211 state
= kmalloc(sizeof(struct tda1004x_state
), GFP_KERNEL
);
1215 /* setup the state */
1216 state
->config
= config
;
1218 memcpy(&state
->ops
, &tda10046_ops
, sizeof(struct dvb_frontend_ops
));
1219 state
->initialised
= 0;
1220 state
->demod_type
= TDA1004X_DEMOD_TDA10046
;
1222 /* check if the demod is there */
1223 if (tda1004x_read_byte(state
, TDA1004X_CHIPID
) != 0x46) {
1228 /* create dvb_frontend */
1229 state
->frontend
.ops
= &state
->ops
;
1230 state
->frontend
.demodulator_priv
= state
;
1231 return &state
->frontend
;
1234 module_param(debug
, int, 0644);
1235 MODULE_PARM_DESC(debug
, "Turn on/off frontend debugging (default:off).");
1237 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1238 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1239 MODULE_LICENSE("GPL");
1241 EXPORT_SYMBOL(tda10045_attach
);
1242 EXPORT_SYMBOL(tda10046_attach
);
1243 EXPORT_SYMBOL(tda1004x_write_byte
);