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V4L/DVB (6925): tda18271: move state structures to tda18271-priv.h
[deliverable/linux.git] / drivers / media / dvb / frontends / tda18271-fe.c
1 /*
2 tda18271-fe.c - driver for the Philips / NXP TDA18271 silicon tuner
3
4 Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org)
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21 #include <linux/delay.h>
22 #include <linux/videodev2.h>
23 #include "tda18271-priv.h"
24
25 int tda18271_debug;
26 module_param_named(debug, tda18271_debug, int, 0644);
27 MODULE_PARM_DESC(debug, "set debug level (info=1, map=2, reg=4 (or-able))");
28
29 /*---------------------------------------------------------------------*/
30
31 static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
32 {
33 struct tda18271_priv *priv = fe->tuner_priv;
34 enum tda18271_i2c_gate gate;
35 int ret = 0;
36
37 switch (priv->gate) {
38 case TDA18271_GATE_DIGITAL:
39 case TDA18271_GATE_ANALOG:
40 gate = priv->gate;
41 break;
42 case TDA18271_GATE_AUTO:
43 default:
44 switch (priv->mode) {
45 case TDA18271_DIGITAL:
46 gate = TDA18271_GATE_DIGITAL;
47 break;
48 case TDA18271_ANALOG:
49 default:
50 gate = TDA18271_GATE_ANALOG;
51 break;
52 }
53 }
54
55 switch (gate) {
56 case TDA18271_GATE_ANALOG:
57 if (fe->ops.analog_ops.i2c_gate_ctrl)
58 ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable);
59 break;
60 case TDA18271_GATE_DIGITAL:
61 if (fe->ops.i2c_gate_ctrl)
62 ret = fe->ops.i2c_gate_ctrl(fe, enable);
63 break;
64 default:
65 ret = -EINVAL;
66 break;
67 }
68
69 return ret;
70 };
71
72 /*---------------------------------------------------------------------*/
73
74 static void tda18271_dump_regs(struct dvb_frontend *fe)
75 {
76 struct tda18271_priv *priv = fe->tuner_priv;
77 unsigned char *regs = priv->tda18271_regs;
78
79 dbg_reg("=== TDA18271 REG DUMP ===\n");
80 dbg_reg("ID_BYTE = 0x%02x\n", 0xff & regs[R_ID]);
81 dbg_reg("THERMO_BYTE = 0x%02x\n", 0xff & regs[R_TM]);
82 dbg_reg("POWER_LEVEL_BYTE = 0x%02x\n", 0xff & regs[R_PL]);
83 dbg_reg("EASY_PROG_BYTE_1 = 0x%02x\n", 0xff & regs[R_EP1]);
84 dbg_reg("EASY_PROG_BYTE_2 = 0x%02x\n", 0xff & regs[R_EP2]);
85 dbg_reg("EASY_PROG_BYTE_3 = 0x%02x\n", 0xff & regs[R_EP3]);
86 dbg_reg("EASY_PROG_BYTE_4 = 0x%02x\n", 0xff & regs[R_EP4]);
87 dbg_reg("EASY_PROG_BYTE_5 = 0x%02x\n", 0xff & regs[R_EP5]);
88 dbg_reg("CAL_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_CPD]);
89 dbg_reg("CAL_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_CD1]);
90 dbg_reg("CAL_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_CD2]);
91 dbg_reg("CAL_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_CD3]);
92 dbg_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
93 dbg_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]);
94 dbg_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]);
95 dbg_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]);
96 }
97
98 static void tda18271_read_regs(struct dvb_frontend *fe)
99 {
100 struct tda18271_priv *priv = fe->tuner_priv;
101 unsigned char *regs = priv->tda18271_regs;
102 unsigned char buf = 0x00;
103 int ret;
104 struct i2c_msg msg[] = {
105 { .addr = priv->i2c_addr, .flags = 0,
106 .buf = &buf, .len = 1 },
107 { .addr = priv->i2c_addr, .flags = I2C_M_RD,
108 .buf = regs, .len = 16 }
109 };
110
111 tda18271_i2c_gate_ctrl(fe, 1);
112
113 /* read all registers */
114 ret = i2c_transfer(priv->i2c_adap, msg, 2);
115
116 tda18271_i2c_gate_ctrl(fe, 0);
117
118 if (ret != 2)
119 printk("ERROR: %s: i2c_transfer returned: %d\n",
120 __FUNCTION__, ret);
121
122 if (tda18271_debug & DBG_REG)
123 tda18271_dump_regs(fe);
124 }
125
126 static void tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
127 {
128 struct tda18271_priv *priv = fe->tuner_priv;
129 unsigned char *regs = priv->tda18271_regs;
130 unsigned char buf[TDA18271_NUM_REGS+1];
131 struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
132 .buf = buf, .len = len+1 };
133 int i, ret;
134
135 BUG_ON((len == 0) || (idx+len > sizeof(buf)));
136
137 buf[0] = idx;
138 for (i = 1; i <= len; i++) {
139 buf[i] = regs[idx-1+i];
140 }
141
142 tda18271_i2c_gate_ctrl(fe, 1);
143
144 /* write registers */
145 ret = i2c_transfer(priv->i2c_adap, &msg, 1);
146
147 tda18271_i2c_gate_ctrl(fe, 0);
148
149 if (ret != 1)
150 printk(KERN_WARNING "ERROR: %s: i2c_transfer returned: %d\n",
151 __FUNCTION__, ret);
152 }
153
154 /*---------------------------------------------------------------------*/
155
156 static int tda18271_init_regs(struct dvb_frontend *fe)
157 {
158 struct tda18271_priv *priv = fe->tuner_priv;
159 unsigned char *regs = priv->tda18271_regs;
160
161 printk(KERN_INFO "tda18271: initializing registers\n");
162
163 /* initialize registers */
164 regs[R_ID] = 0x83;
165 regs[R_TM] = 0x08;
166 regs[R_PL] = 0x80;
167 regs[R_EP1] = 0xc6;
168 regs[R_EP2] = 0xdf;
169 regs[R_EP3] = 0x16;
170 regs[R_EP4] = 0x60;
171 regs[R_EP5] = 0x80;
172 regs[R_CPD] = 0x80;
173 regs[R_CD1] = 0x00;
174 regs[R_CD2] = 0x00;
175 regs[R_CD3] = 0x00;
176 regs[R_MPD] = 0x00;
177 regs[R_MD1] = 0x00;
178 regs[R_MD2] = 0x00;
179 regs[R_MD3] = 0x00;
180 regs[R_EB1] = 0xff;
181 regs[R_EB2] = 0x01;
182 regs[R_EB3] = 0x84;
183 regs[R_EB4] = 0x41;
184 regs[R_EB5] = 0x01;
185 regs[R_EB6] = 0x84;
186 regs[R_EB7] = 0x40;
187 regs[R_EB8] = 0x07;
188 regs[R_EB9] = 0x00;
189 regs[R_EB10] = 0x00;
190 regs[R_EB11] = 0x96;
191 regs[R_EB12] = 0x0f;
192 regs[R_EB13] = 0xc1;
193 regs[R_EB14] = 0x00;
194 regs[R_EB15] = 0x8f;
195 regs[R_EB16] = 0x00;
196 regs[R_EB17] = 0x00;
197 regs[R_EB18] = 0x00;
198 regs[R_EB19] = 0x00;
199 regs[R_EB20] = 0x20;
200 regs[R_EB21] = 0x33;
201 regs[R_EB22] = 0x48;
202 regs[R_EB23] = 0xb0;
203
204 tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
205 /* setup AGC1 & AGC2 */
206 regs[R_EB17] = 0x00;
207 tda18271_write_regs(fe, R_EB17, 1);
208 regs[R_EB17] = 0x03;
209 tda18271_write_regs(fe, R_EB17, 1);
210 regs[R_EB17] = 0x43;
211 tda18271_write_regs(fe, R_EB17, 1);
212 regs[R_EB17] = 0x4c;
213 tda18271_write_regs(fe, R_EB17, 1);
214
215 regs[R_EB20] = 0xa0;
216 tda18271_write_regs(fe, R_EB20, 1);
217 regs[R_EB20] = 0xa7;
218 tda18271_write_regs(fe, R_EB20, 1);
219 regs[R_EB20] = 0xe7;
220 tda18271_write_regs(fe, R_EB20, 1);
221 regs[R_EB20] = 0xec;
222 tda18271_write_regs(fe, R_EB20, 1);
223
224 /* image rejection calibration */
225
226 /* low-band */
227 regs[R_EP3] = 0x1f;
228 regs[R_EP4] = 0x66;
229 regs[R_EP5] = 0x81;
230 regs[R_CPD] = 0xcc;
231 regs[R_CD1] = 0x6c;
232 regs[R_CD2] = 0x00;
233 regs[R_CD3] = 0x00;
234 regs[R_MPD] = 0xcd;
235 regs[R_MD1] = 0x77;
236 regs[R_MD2] = 0x08;
237 regs[R_MD3] = 0x00;
238
239 tda18271_write_regs(fe, R_EP3, 11);
240 msleep(5); /* pll locking */
241
242 regs[R_EP1] = 0xc6;
243 tda18271_write_regs(fe, R_EP1, 1);
244 msleep(5); /* wanted low measurement */
245
246 regs[R_EP3] = 0x1f;
247 regs[R_EP4] = 0x66;
248 regs[R_EP5] = 0x85;
249 regs[R_CPD] = 0xcb;
250 regs[R_CD1] = 0x66;
251 regs[R_CD2] = 0x70;
252 regs[R_CD3] = 0x00;
253
254 tda18271_write_regs(fe, R_EP3, 7);
255 msleep(5); /* pll locking */
256
257 regs[R_EP2] = 0xdf;
258 tda18271_write_regs(fe, R_EP2, 1);
259 msleep(30); /* image low optimization completion */
260
261 /* mid-band */
262 regs[R_EP3] = 0x1f;
263 regs[R_EP4] = 0x66;
264 regs[R_EP5] = 0x82;
265 regs[R_CPD] = 0xa8;
266 regs[R_CD1] = 0x66;
267 regs[R_CD2] = 0x00;
268 regs[R_CD3] = 0x00;
269 regs[R_MPD] = 0xa9;
270 regs[R_MD1] = 0x73;
271 regs[R_MD2] = 0x1a;
272 regs[R_MD3] = 0x00;
273
274 tda18271_write_regs(fe, R_EP3, 11);
275 msleep(5); /* pll locking */
276
277 regs[R_EP1] = 0xc6;
278 tda18271_write_regs(fe, R_EP1, 1);
279 msleep(5); /* wanted mid measurement */
280
281 regs[R_EP3] = 0x1f;
282 regs[R_EP4] = 0x66;
283 regs[R_EP5] = 0x86;
284 regs[R_CPD] = 0xa8;
285 regs[R_CD1] = 0x66;
286 regs[R_CD2] = 0xa0;
287 regs[R_CD3] = 0x00;
288
289 tda18271_write_regs(fe, R_EP3, 7);
290 msleep(5); /* pll locking */
291
292 regs[R_EP2] = 0xdf;
293 tda18271_write_regs(fe, R_EP2, 1);
294 msleep(30); /* image mid optimization completion */
295
296 /* high-band */
297 regs[R_EP3] = 0x1f;
298 regs[R_EP4] = 0x66;
299 regs[R_EP5] = 0x83;
300 regs[R_CPD] = 0x98;
301 regs[R_CD1] = 0x65;
302 regs[R_CD2] = 0x00;
303 regs[R_CD3] = 0x00;
304 regs[R_MPD] = 0x99;
305 regs[R_MD1] = 0x71;
306 regs[R_MD2] = 0xcd;
307 regs[R_MD3] = 0x00;
308
309 tda18271_write_regs(fe, R_EP3, 11);
310 msleep(5); /* pll locking */
311
312 regs[R_EP1] = 0xc6;
313 tda18271_write_regs(fe, R_EP1, 1);
314 msleep(5); /* wanted high measurement */
315
316 regs[R_EP3] = 0x1f;
317 regs[R_EP4] = 0x66;
318 regs[R_EP5] = 0x87;
319 regs[R_CPD] = 0x98;
320 regs[R_CD1] = 0x65;
321 regs[R_CD2] = 0x50;
322 regs[R_CD3] = 0x00;
323
324 tda18271_write_regs(fe, R_EP3, 7);
325 msleep(5); /* pll locking */
326
327 regs[R_EP2] = 0xdf;
328
329 tda18271_write_regs(fe, R_EP2, 1);
330 msleep(30); /* image high optimization completion */
331
332 regs[R_EP4] = 0x64;
333 tda18271_write_regs(fe, R_EP4, 1);
334
335 regs[R_EP1] = 0xc6;
336 tda18271_write_regs(fe, R_EP1, 1);
337
338 return 0;
339 }
340
341 static int tda18271_init(struct dvb_frontend *fe)
342 {
343 struct tda18271_priv *priv = fe->tuner_priv;
344 unsigned char *regs = priv->tda18271_regs;
345
346 tda18271_read_regs(fe);
347
348 /* test IR_CAL_OK to see if we need init */
349 if ((regs[R_EP1] & 0x08) == 0)
350 tda18271_init_regs(fe);
351
352 return 0;
353 }
354
355 static int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
356 {
357 /* Sets Main Post-Divider & Divider bytes, but does not write them */
358 struct tda18271_priv *priv = fe->tuner_priv;
359 unsigned char *regs = priv->tda18271_regs;
360 u8 d, pd;
361 u32 div;
362
363 tda18271_lookup_main_pll(&freq, &pd, &d);
364
365 regs[R_MPD] = (0x77 & pd);
366
367 switch (priv->mode) {
368 case TDA18271_ANALOG:
369 regs[R_MPD] &= ~0x08;
370 break;
371 case TDA18271_DIGITAL:
372 regs[R_MPD] |= 0x08;
373 break;
374 }
375
376 div = ((d * (freq / 1000)) << 7) / 125;
377
378 regs[R_MD1] = 0x7f & (div >> 16);
379 regs[R_MD2] = 0xff & (div >> 8);
380 regs[R_MD3] = 0xff & div;
381
382 return 0;
383 }
384
385 static int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
386 {
387 /* Sets Cal Post-Divider & Divider bytes, but does not write them */
388 struct tda18271_priv *priv = fe->tuner_priv;
389 unsigned char *regs = priv->tda18271_regs;
390 u8 d, pd;
391 u32 div;
392
393 tda18271_lookup_cal_pll(&freq, &pd, &d);
394
395 regs[R_CPD] = pd;
396
397 div = ((d * (freq / 1000)) << 7) / 125;
398
399 regs[R_CD1] = 0x7f & (div >> 16);
400 regs[R_CD2] = 0xff & (div >> 8);
401 regs[R_CD3] = 0xff & div;
402
403 return 0;
404 }
405
406 static int tda18271_tune(struct dvb_frontend *fe,
407 u32 ifc, u32 freq, u32 bw, u8 std)
408 {
409 struct tda18271_priv *priv = fe->tuner_priv;
410 unsigned char *regs = priv->tda18271_regs;
411 u32 N = 0;
412 u8 val;
413
414 tda18271_init(fe);
415
416 dbg_info("freq = %d, ifc = %d\n", freq, ifc);
417
418 /* RF tracking filter calibration */
419
420 /* calculate BP_Filter */
421 tda18271_lookup_bp_filter(&freq, &val);
422
423 regs[R_EP1] &= ~0x07; /* clear bp filter bits */
424 regs[R_EP1] |= val;
425 tda18271_write_regs(fe, R_EP1, 1);
426
427 regs[R_EB4] &= 0x07;
428 regs[R_EB4] |= 0x60;
429 tda18271_write_regs(fe, R_EB4, 1);
430
431 regs[R_EB7] = 0x60;
432 tda18271_write_regs(fe, R_EB7, 1);
433
434 regs[R_EB14] = 0x00;
435 tda18271_write_regs(fe, R_EB14, 1);
436
437 regs[R_EB20] = 0xcc;
438 tda18271_write_regs(fe, R_EB20, 1);
439
440 /* set CAL mode to RF tracking filter calibration */
441 regs[R_EP4] |= 0x03;
442
443 /* calculate CAL PLL */
444
445 switch (priv->mode) {
446 case TDA18271_ANALOG:
447 N = freq - 1250000;
448 break;
449 case TDA18271_DIGITAL:
450 N = freq + bw / 2;
451 break;
452 }
453
454 tda18271_calc_cal_pll(fe, N);
455
456 /* calculate MAIN PLL */
457
458 switch (priv->mode) {
459 case TDA18271_ANALOG:
460 N = freq - 250000;
461 break;
462 case TDA18271_DIGITAL:
463 N = freq + bw / 2 + 1000000;
464 break;
465 }
466
467 tda18271_calc_main_pll(fe, N);
468
469 tda18271_write_regs(fe, R_EP3, 11);
470 msleep(5); /* RF tracking filter calibration initialization */
471
472 /* search for K,M,CO for RF Calibration */
473 tda18271_lookup_km(&freq, &val);
474
475 regs[R_EB13] &= 0x83;
476 regs[R_EB13] |= val;
477 tda18271_write_regs(fe, R_EB13, 1);
478
479 /* search for RF_BAND */
480 tda18271_lookup_rf_band(&freq, &val);
481
482 regs[R_EP2] &= ~0xe0; /* clear rf band bits */
483 regs[R_EP2] |= (val << 5);
484
485 /* search for Gain_Taper */
486 tda18271_lookup_gain_taper(&freq, &val);
487
488 regs[R_EP2] &= ~0x1f; /* clear gain taper bits */
489 regs[R_EP2] |= val;
490
491 tda18271_write_regs(fe, R_EP2, 1);
492 tda18271_write_regs(fe, R_EP1, 1);
493 tda18271_write_regs(fe, R_EP2, 1);
494 tda18271_write_regs(fe, R_EP1, 1);
495
496 regs[R_EB4] &= 0x07;
497 regs[R_EB4] |= 0x40;
498 tda18271_write_regs(fe, R_EB4, 1);
499
500 regs[R_EB7] = 0x40;
501 tda18271_write_regs(fe, R_EB7, 1);
502 msleep(10);
503
504 regs[R_EB20] = 0xec;
505 tda18271_write_regs(fe, R_EB20, 1);
506 msleep(60); /* RF tracking filter calibration completion */
507
508 regs[R_EP4] &= ~0x03; /* set cal mode to normal */
509 tda18271_write_regs(fe, R_EP4, 1);
510
511 tda18271_write_regs(fe, R_EP1, 1);
512
513 /* RF tracking filer correction for VHF_Low band */
514 tda18271_lookup_rf_cal(&freq, &val);
515
516 /* VHF_Low band only */
517 if (val != 0) {
518 regs[R_EB14] = val;
519 tda18271_write_regs(fe, R_EB14, 1);
520 }
521
522 /* Channel Configuration */
523
524 switch (priv->mode) {
525 case TDA18271_ANALOG:
526 regs[R_EB22] = 0x2c;
527 break;
528 case TDA18271_DIGITAL:
529 regs[R_EB22] = 0x37;
530 break;
531 }
532 tda18271_write_regs(fe, R_EB22, 1);
533
534 regs[R_EP1] |= 0x40; /* set dis power level on */
535
536 /* set standard */
537 regs[R_EP3] &= ~0x1f; /* clear std bits */
538
539 /* see table 22 */
540 regs[R_EP3] |= std;
541
542 regs[R_EP4] &= ~0x03; /* set cal mode to normal */
543
544 regs[R_EP4] &= ~0x1c; /* clear if level bits */
545 switch (priv->mode) {
546 case TDA18271_ANALOG:
547 regs[R_MPD] &= ~0x80; /* IF notch = 0 */
548 break;
549 case TDA18271_DIGITAL:
550 regs[R_EP4] |= 0x04;
551 regs[R_MPD] |= 0x80;
552 break;
553 }
554
555 regs[R_EP4] &= ~0x80; /* turn this bit on only for fm */
556
557 /* image rejection validity EP5[2:0] */
558 tda18271_lookup_ir_measure(&freq, &val);
559
560 regs[R_EP5] &= ~0x07;
561 regs[R_EP5] |= val;
562
563 /* calculate MAIN PLL */
564 N = freq + ifc;
565
566 tda18271_calc_main_pll(fe, N);
567
568 tda18271_write_regs(fe, R_TM, 15);
569 msleep(5);
570
571 return 0;
572 }
573
574 /* ------------------------------------------------------------------ */
575
576 static int tda18271_set_params(struct dvb_frontend *fe,
577 struct dvb_frontend_parameters *params)
578 {
579 struct tda18271_priv *priv = fe->tuner_priv;
580 u8 std;
581 u32 bw, sgIF = 0;
582
583 u32 freq = params->frequency;
584
585 priv->mode = TDA18271_DIGITAL;
586
587 /* see table 22 */
588 if (fe->ops.info.type == FE_ATSC) {
589 switch (params->u.vsb.modulation) {
590 case VSB_8:
591 case VSB_16:
592 std = 0x1b; /* device-specific (spec says 0x1c) */
593 sgIF = 5380000;
594 break;
595 case QAM_64:
596 case QAM_256:
597 std = 0x18; /* device-specific (spec says 0x1d) */
598 sgIF = 4000000;
599 break;
600 default:
601 printk(KERN_WARNING "%s: modulation not set!\n",
602 __FUNCTION__);
603 return -EINVAL;
604 }
605 #if 0
606 /* userspace request is already center adjusted */
607 freq += 1750000; /* Adjust to center (+1.75MHZ) */
608 #endif
609 bw = 6000000;
610 } else if (fe->ops.info.type == FE_OFDM) {
611 switch (params->u.ofdm.bandwidth) {
612 case BANDWIDTH_6_MHZ:
613 std = 0x1b; /* device-specific (spec says 0x1c) */
614 bw = 6000000;
615 sgIF = 3300000;
616 break;
617 case BANDWIDTH_7_MHZ:
618 std = 0x19; /* device-specific (spec says 0x1d) */
619 bw = 7000000;
620 sgIF = 3800000;
621 break;
622 case BANDWIDTH_8_MHZ:
623 std = 0x1a; /* device-specific (spec says 0x1e) */
624 bw = 8000000;
625 sgIF = 4300000;
626 break;
627 default:
628 printk(KERN_WARNING "%s: bandwidth not set!\n",
629 __FUNCTION__);
630 return -EINVAL;
631 }
632 } else {
633 printk(KERN_WARNING "%s: modulation type not supported!\n",
634 __FUNCTION__);
635 return -EINVAL;
636 }
637
638 return tda18271_tune(fe, sgIF, freq, bw, std);
639 }
640
641 static int tda18271_set_analog_params(struct dvb_frontend *fe,
642 struct analog_parameters *params)
643 {
644 struct tda18271_priv *priv = fe->tuner_priv;
645 u8 std;
646 unsigned int sgIF;
647 char *mode;
648
649 priv->mode = TDA18271_ANALOG;
650
651 /* see table 22 */
652 if (params->std & V4L2_STD_MN) {
653 std = 0x0d;
654 sgIF = 92;
655 mode = "MN";
656 } else if (params->std & V4L2_STD_B) {
657 std = 0x0e;
658 sgIF = 108;
659 mode = "B";
660 } else if (params->std & V4L2_STD_GH) {
661 std = 0x0f;
662 sgIF = 124;
663 mode = "GH";
664 } else if (params->std & V4L2_STD_PAL_I) {
665 std = 0x0f;
666 sgIF = 124;
667 mode = "I";
668 } else if (params->std & V4L2_STD_DK) {
669 std = 0x0f;
670 sgIF = 124;
671 mode = "DK";
672 } else if (params->std & V4L2_STD_SECAM_L) {
673 std = 0x0f;
674 sgIF = 124;
675 mode = "L";
676 } else if (params->std & V4L2_STD_SECAM_LC) {
677 std = 0x0f;
678 sgIF = 20;
679 mode = "LC";
680 } else {
681 std = 0x0f;
682 sgIF = 124;
683 mode = "xx";
684 }
685
686 if (params->mode == V4L2_TUNER_RADIO)
687 sgIF = 88; /* if frequency is 5.5 MHz */
688
689 dbg_info("setting tda18271 to system %s\n", mode);
690
691 return tda18271_tune(fe, sgIF * 62500, params->frequency * 62500,
692 0, std);
693 }
694
695 static int tda18271_release(struct dvb_frontend *fe)
696 {
697 kfree(fe->tuner_priv);
698 fe->tuner_priv = NULL;
699 return 0;
700 }
701
702 static int tda18271_get_frequency(struct dvb_frontend *fe, u32 *frequency)
703 {
704 struct tda18271_priv *priv = fe->tuner_priv;
705 *frequency = priv->frequency;
706 return 0;
707 }
708
709 static int tda18271_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
710 {
711 struct tda18271_priv *priv = fe->tuner_priv;
712 *bandwidth = priv->bandwidth;
713 return 0;
714 }
715
716 static int tda18271_get_id(struct dvb_frontend *fe)
717 {
718 struct tda18271_priv *priv = fe->tuner_priv;
719 unsigned char *regs = priv->tda18271_regs;
720 char *name;
721 int ret = 0;
722
723 tda18271_read_regs(fe);
724
725 switch (regs[R_ID] & 0x7f) {
726 case 3:
727 name = "TDA18271HD/C1";
728 break;
729 case 4:
730 name = "TDA18271HD/C2";
731 ret = -EPROTONOSUPPORT;
732 break;
733 default:
734 name = "Unknown device";
735 ret = -EINVAL;
736 break;
737 }
738
739 dbg_info("%s detected @ %d-%04x%s\n", name,
740 i2c_adapter_id(priv->i2c_adap), priv->i2c_addr,
741 (0 == ret) ? "" : ", device not supported.");
742
743 return ret;
744 }
745
746 static struct dvb_tuner_ops tda18271_tuner_ops = {
747 .info = {
748 .name = "NXP TDA18271HD",
749 .frequency_min = 45000000,
750 .frequency_max = 864000000,
751 .frequency_step = 62500
752 },
753 .init = tda18271_init,
754 .set_params = tda18271_set_params,
755 .set_analog_params = tda18271_set_analog_params,
756 .release = tda18271_release,
757 .get_frequency = tda18271_get_frequency,
758 .get_bandwidth = tda18271_get_bandwidth,
759 };
760
761 struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
762 struct i2c_adapter *i2c,
763 enum tda18271_i2c_gate gate)
764 {
765 struct tda18271_priv *priv = NULL;
766
767 priv = kzalloc(sizeof(struct tda18271_priv), GFP_KERNEL);
768 if (priv == NULL)
769 return NULL;
770
771 priv->i2c_addr = addr;
772 priv->i2c_adap = i2c;
773 priv->gate = gate;
774
775 fe->tuner_priv = priv;
776
777 if (tda18271_get_id(fe) < 0)
778 goto fail;
779
780 memcpy(&fe->ops.tuner_ops, &tda18271_tuner_ops,
781 sizeof(struct dvb_tuner_ops));
782
783 tda18271_init_regs(fe);
784
785 return fe;
786 fail:
787 tda18271_release(fe);
788 return NULL;
789 }
790 EXPORT_SYMBOL_GPL(tda18271_attach);
791 MODULE_DESCRIPTION("NXP TDA18271HD analog / digital tuner driver");
792 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
793 MODULE_LICENSE("GPL");
794
795 /*
796 * Overrides for Emacs so that we follow Linus's tabbing style.
797 * ---------------------------------------------------------------------------
798 * Local variables:
799 * c-basic-offset: 8
800 * End:
801 */
Linux kernel - Deliverables
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