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Merge remote-tracking branch 'asoc/fix/intel' into asoc-linus
[deliverable/linux.git] / drivers / media / dvb-frontends / stv0367.c
1 /*
2 * stv0367.c
3 *
4 * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
5 *
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2010,2011 NetUP Inc.
8 * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/string.h>
29 #include <linux/slab.h>
30 #include <linux/i2c.h>
31
32 #include "stv0367.h"
33 #include "stv0367_regs.h"
34 #include "stv0367_priv.h"
35
36 /* Max transfer size done by I2C transfer functions */
37 #define MAX_XFER_SIZE 64
38
39 static int stvdebug;
40 module_param_named(debug, stvdebug, int, 0644);
41
42 static int i2cdebug;
43 module_param_named(i2c_debug, i2cdebug, int, 0644);
44
45 #define dprintk(args...) \
46 do { \
47 if (stvdebug) \
48 printk(KERN_DEBUG args); \
49 } while (0)
50 /* DVB-C */
51
52 struct stv0367cab_state {
53 enum stv0367_cab_signal_type state;
54 u32 mclk;
55 u32 adc_clk;
56 s32 search_range;
57 s32 derot_offset;
58 /* results */
59 int locked; /* channel found */
60 u32 freq_khz; /* found frequency (in kHz) */
61 u32 symbol_rate; /* found symbol rate (in Bds) */
62 fe_spectral_inversion_t spect_inv; /* Spectrum Inversion */
63 };
64
65 struct stv0367ter_state {
66 /* DVB-T */
67 enum stv0367_ter_signal_type state;
68 enum stv0367_ter_if_iq_mode if_iq_mode;
69 enum stv0367_ter_mode mode;/* mode 2K or 8K */
70 fe_guard_interval_t guard;
71 enum stv0367_ter_hierarchy hierarchy;
72 u32 frequency;
73 fe_spectral_inversion_t sense; /* current search spectrum */
74 u8 force; /* force mode/guard */
75 u8 bw; /* channel width 6, 7 or 8 in MHz */
76 u8 pBW; /* channel width used during previous lock */
77 u32 pBER;
78 u32 pPER;
79 u32 ucblocks;
80 s8 echo_pos; /* echo position */
81 u8 first_lock;
82 u8 unlock_counter;
83 u32 agc_val;
84 };
85
86 struct stv0367_state {
87 struct dvb_frontend fe;
88 struct i2c_adapter *i2c;
89 /* config settings */
90 const struct stv0367_config *config;
91 u8 chip_id;
92 /* DVB-C */
93 struct stv0367cab_state *cab_state;
94 /* DVB-T */
95 struct stv0367ter_state *ter_state;
96 };
97
98 struct st_register {
99 u16 addr;
100 u8 value;
101 };
102
103 /* values for STV4100 XTAL=30M int clk=53.125M*/
104 static struct st_register def0367ter[STV0367TER_NBREGS] = {
105 {R367TER_ID, 0x60},
106 {R367TER_I2CRPT, 0xa0},
107 /* {R367TER_I2CRPT, 0x22},*/
108 {R367TER_TOPCTRL, 0x00},/* for xc5000; was 0x02 */
109 {R367TER_IOCFG0, 0x40},
110 {R367TER_DAC0R, 0x00},
111 {R367TER_IOCFG1, 0x00},
112 {R367TER_DAC1R, 0x00},
113 {R367TER_IOCFG2, 0x62},
114 {R367TER_SDFR, 0x00},
115 {R367TER_STATUS, 0xf8},
116 {R367TER_AUX_CLK, 0x0a},
117 {R367TER_FREESYS1, 0x00},
118 {R367TER_FREESYS2, 0x00},
119 {R367TER_FREESYS3, 0x00},
120 {R367TER_GPIO_CFG, 0x55},
121 {R367TER_GPIO_CMD, 0x00},
122 {R367TER_AGC2MAX, 0xff},
123 {R367TER_AGC2MIN, 0x00},
124 {R367TER_AGC1MAX, 0xff},
125 {R367TER_AGC1MIN, 0x00},
126 {R367TER_AGCR, 0xbc},
127 {R367TER_AGC2TH, 0x00},
128 {R367TER_AGC12C, 0x00},
129 {R367TER_AGCCTRL1, 0x85},
130 {R367TER_AGCCTRL2, 0x1f},
131 {R367TER_AGC1VAL1, 0x00},
132 {R367TER_AGC1VAL2, 0x00},
133 {R367TER_AGC2VAL1, 0x6f},
134 {R367TER_AGC2VAL2, 0x05},
135 {R367TER_AGC2PGA, 0x00},
136 {R367TER_OVF_RATE1, 0x00},
137 {R367TER_OVF_RATE2, 0x00},
138 {R367TER_GAIN_SRC1, 0xaa},/* for xc5000; was 0x2b */
139 {R367TER_GAIN_SRC2, 0xd6},/* for xc5000; was 0x04 */
140 {R367TER_INC_DEROT1, 0x55},
141 {R367TER_INC_DEROT2, 0x55},
142 {R367TER_PPM_CPAMP_DIR, 0x2c},
143 {R367TER_PPM_CPAMP_INV, 0x00},
144 {R367TER_FREESTFE_1, 0x00},
145 {R367TER_FREESTFE_2, 0x1c},
146 {R367TER_DCOFFSET, 0x00},
147 {R367TER_EN_PROCESS, 0x05},
148 {R367TER_SDI_SMOOTHER, 0x80},
149 {R367TER_FE_LOOP_OPEN, 0x1c},
150 {R367TER_FREQOFF1, 0x00},
151 {R367TER_FREQOFF2, 0x00},
152 {R367TER_FREQOFF3, 0x00},
153 {R367TER_TIMOFF1, 0x00},
154 {R367TER_TIMOFF2, 0x00},
155 {R367TER_EPQ, 0x02},
156 {R367TER_EPQAUTO, 0x01},
157 {R367TER_SYR_UPDATE, 0xf5},
158 {R367TER_CHPFREE, 0x00},
159 {R367TER_PPM_STATE_MAC, 0x23},
160 {R367TER_INR_THRESHOLD, 0xff},
161 {R367TER_EPQ_TPS_ID_CELL, 0xf9},
162 {R367TER_EPQ_CFG, 0x00},
163 {R367TER_EPQ_STATUS, 0x01},
164 {R367TER_AUTORELOCK, 0x81},
165 {R367TER_BER_THR_VMSB, 0x00},
166 {R367TER_BER_THR_MSB, 0x00},
167 {R367TER_BER_THR_LSB, 0x00},
168 {R367TER_CCD, 0x83},
169 {R367TER_SPECTR_CFG, 0x00},
170 {R367TER_CHC_DUMMY, 0x18},
171 {R367TER_INC_CTL, 0x88},
172 {R367TER_INCTHRES_COR1, 0xb4},
173 {R367TER_INCTHRES_COR2, 0x96},
174 {R367TER_INCTHRES_DET1, 0x0e},
175 {R367TER_INCTHRES_DET2, 0x11},
176 {R367TER_IIR_CELLNB, 0x8d},
177 {R367TER_IIRCX_COEFF1_MSB, 0x00},
178 {R367TER_IIRCX_COEFF1_LSB, 0x00},
179 {R367TER_IIRCX_COEFF2_MSB, 0x09},
180 {R367TER_IIRCX_COEFF2_LSB, 0x18},
181 {R367TER_IIRCX_COEFF3_MSB, 0x14},
182 {R367TER_IIRCX_COEFF3_LSB, 0x9c},
183 {R367TER_IIRCX_COEFF4_MSB, 0x00},
184 {R367TER_IIRCX_COEFF4_LSB, 0x00},
185 {R367TER_IIRCX_COEFF5_MSB, 0x36},
186 {R367TER_IIRCX_COEFF5_LSB, 0x42},
187 {R367TER_FEPATH_CFG, 0x00},
188 {R367TER_PMC1_FUNC, 0x65},
189 {R367TER_PMC1_FOR, 0x00},
190 {R367TER_PMC2_FUNC, 0x00},
191 {R367TER_STATUS_ERR_DA, 0xe0},
192 {R367TER_DIG_AGC_R, 0xfe},
193 {R367TER_COMAGC_TARMSB, 0x0b},
194 {R367TER_COM_AGC_TAR_ENMODE, 0x41},
195 {R367TER_COM_AGC_CFG, 0x3e},
196 {R367TER_COM_AGC_GAIN1, 0x39},
197 {R367TER_AUT_AGC_TARGETMSB, 0x0b},
198 {R367TER_LOCK_DET_MSB, 0x01},
199 {R367TER_AGCTAR_LOCK_LSBS, 0x40},
200 {R367TER_AUT_GAIN_EN, 0xf4},
201 {R367TER_AUT_CFG, 0xf0},
202 {R367TER_LOCKN, 0x23},
203 {R367TER_INT_X_3, 0x00},
204 {R367TER_INT_X_2, 0x03},
205 {R367TER_INT_X_1, 0x8d},
206 {R367TER_INT_X_0, 0xa0},
207 {R367TER_MIN_ERRX_MSB, 0x00},
208 {R367TER_COR_CTL, 0x23},
209 {R367TER_COR_STAT, 0xf6},
210 {R367TER_COR_INTEN, 0x00},
211 {R367TER_COR_INTSTAT, 0x3f},
212 {R367TER_COR_MODEGUARD, 0x03},
213 {R367TER_AGC_CTL, 0x08},
214 {R367TER_AGC_MANUAL1, 0x00},
215 {R367TER_AGC_MANUAL2, 0x00},
216 {R367TER_AGC_TARG, 0x16},
217 {R367TER_AGC_GAIN1, 0x53},
218 {R367TER_AGC_GAIN2, 0x1d},
219 {R367TER_RESERVED_1, 0x00},
220 {R367TER_RESERVED_2, 0x00},
221 {R367TER_RESERVED_3, 0x00},
222 {R367TER_CAS_CTL, 0x44},
223 {R367TER_CAS_FREQ, 0xb3},
224 {R367TER_CAS_DAGCGAIN, 0x12},
225 {R367TER_SYR_CTL, 0x04},
226 {R367TER_SYR_STAT, 0x10},
227 {R367TER_SYR_NCO1, 0x00},
228 {R367TER_SYR_NCO2, 0x00},
229 {R367TER_SYR_OFFSET1, 0x00},
230 {R367TER_SYR_OFFSET2, 0x00},
231 {R367TER_FFT_CTL, 0x00},
232 {R367TER_SCR_CTL, 0x70},
233 {R367TER_PPM_CTL1, 0xf8},
234 {R367TER_TRL_CTL, 0x14},/* for xc5000; was 0xac */
235 {R367TER_TRL_NOMRATE1, 0xae},/* for xc5000; was 0x1e */
236 {R367TER_TRL_NOMRATE2, 0x56},/* for xc5000; was 0x58 */
237 {R367TER_TRL_TIME1, 0x1d},
238 {R367TER_TRL_TIME2, 0xfc},
239 {R367TER_CRL_CTL, 0x24},
240 {R367TER_CRL_FREQ1, 0xad},
241 {R367TER_CRL_FREQ2, 0x9d},
242 {R367TER_CRL_FREQ3, 0xff},
243 {R367TER_CHC_CTL, 0x01},
244 {R367TER_CHC_SNR, 0xf0},
245 {R367TER_BDI_CTL, 0x00},
246 {R367TER_DMP_CTL, 0x00},
247 {R367TER_TPS_RCVD1, 0x30},
248 {R367TER_TPS_RCVD2, 0x02},
249 {R367TER_TPS_RCVD3, 0x01},
250 {R367TER_TPS_RCVD4, 0x00},
251 {R367TER_TPS_ID_CELL1, 0x00},
252 {R367TER_TPS_ID_CELL2, 0x00},
253 {R367TER_TPS_RCVD5_SET1, 0x02},
254 {R367TER_TPS_SET2, 0x02},
255 {R367TER_TPS_SET3, 0x01},
256 {R367TER_TPS_CTL, 0x00},
257 {R367TER_CTL_FFTOSNUM, 0x34},
258 {R367TER_TESTSELECT, 0x09},
259 {R367TER_MSC_REV, 0x0a},
260 {R367TER_PIR_CTL, 0x00},
261 {R367TER_SNR_CARRIER1, 0xa1},
262 {R367TER_SNR_CARRIER2, 0x9a},
263 {R367TER_PPM_CPAMP, 0x2c},
264 {R367TER_TSM_AP0, 0x00},
265 {R367TER_TSM_AP1, 0x00},
266 {R367TER_TSM_AP2 , 0x00},
267 {R367TER_TSM_AP3, 0x00},
268 {R367TER_TSM_AP4, 0x00},
269 {R367TER_TSM_AP5, 0x00},
270 {R367TER_TSM_AP6, 0x00},
271 {R367TER_TSM_AP7, 0x00},
272 {R367TER_TSTRES, 0x00},
273 {R367TER_ANACTRL, 0x0D},/* PLL stoped, restart at init!!! */
274 {R367TER_TSTBUS, 0x00},
275 {R367TER_TSTRATE, 0x00},
276 {R367TER_CONSTMODE, 0x01},
277 {R367TER_CONSTCARR1, 0x00},
278 {R367TER_CONSTCARR2, 0x00},
279 {R367TER_ICONSTEL, 0x0a},
280 {R367TER_QCONSTEL, 0x15},
281 {R367TER_TSTBISTRES0, 0x00},
282 {R367TER_TSTBISTRES1, 0x00},
283 {R367TER_TSTBISTRES2, 0x28},
284 {R367TER_TSTBISTRES3, 0x00},
285 {R367TER_RF_AGC1, 0xff},
286 {R367TER_RF_AGC2, 0x83},
287 {R367TER_ANADIGCTRL, 0x19},
288 {R367TER_PLLMDIV, 0x01},/* for xc5000; was 0x0c */
289 {R367TER_PLLNDIV, 0x06},/* for xc5000; was 0x55 */
290 {R367TER_PLLSETUP, 0x18},
291 {R367TER_DUAL_AD12, 0x0C},/* for xc5000 AGC voltage 1.6V */
292 {R367TER_TSTBIST, 0x00},
293 {R367TER_PAD_COMP_CTRL, 0x00},
294 {R367TER_PAD_COMP_WR, 0x00},
295 {R367TER_PAD_COMP_RD, 0xe0},
296 {R367TER_SYR_TARGET_FFTADJT_MSB, 0x00},
297 {R367TER_SYR_TARGET_FFTADJT_LSB, 0x00},
298 {R367TER_SYR_TARGET_CHCADJT_MSB, 0x00},
299 {R367TER_SYR_TARGET_CHCADJT_LSB, 0x00},
300 {R367TER_SYR_FLAG, 0x00},
301 {R367TER_CRL_TARGET1, 0x00},
302 {R367TER_CRL_TARGET2, 0x00},
303 {R367TER_CRL_TARGET3, 0x00},
304 {R367TER_CRL_TARGET4, 0x00},
305 {R367TER_CRL_FLAG, 0x00},
306 {R367TER_TRL_TARGET1, 0x00},
307 {R367TER_TRL_TARGET2, 0x00},
308 {R367TER_TRL_CHC, 0x00},
309 {R367TER_CHC_SNR_TARG, 0x00},
310 {R367TER_TOP_TRACK, 0x00},
311 {R367TER_TRACKER_FREE1, 0x00},
312 {R367TER_ERROR_CRL1, 0x00},
313 {R367TER_ERROR_CRL2, 0x00},
314 {R367TER_ERROR_CRL3, 0x00},
315 {R367TER_ERROR_CRL4, 0x00},
316 {R367TER_DEC_NCO1, 0x2c},
317 {R367TER_DEC_NCO2, 0x0f},
318 {R367TER_DEC_NCO3, 0x20},
319 {R367TER_SNR, 0xf1},
320 {R367TER_SYR_FFTADJ1, 0x00},
321 {R367TER_SYR_FFTADJ2, 0x00},
322 {R367TER_SYR_CHCADJ1, 0x00},
323 {R367TER_SYR_CHCADJ2, 0x00},
324 {R367TER_SYR_OFF, 0x00},
325 {R367TER_PPM_OFFSET1, 0x00},
326 {R367TER_PPM_OFFSET2, 0x03},
327 {R367TER_TRACKER_FREE2, 0x00},
328 {R367TER_DEBG_LT10, 0x00},
329 {R367TER_DEBG_LT11, 0x00},
330 {R367TER_DEBG_LT12, 0x00},
331 {R367TER_DEBG_LT13, 0x00},
332 {R367TER_DEBG_LT14, 0x00},
333 {R367TER_DEBG_LT15, 0x00},
334 {R367TER_DEBG_LT16, 0x00},
335 {R367TER_DEBG_LT17, 0x00},
336 {R367TER_DEBG_LT18, 0x00},
337 {R367TER_DEBG_LT19, 0x00},
338 {R367TER_DEBG_LT1A, 0x00},
339 {R367TER_DEBG_LT1B, 0x00},
340 {R367TER_DEBG_LT1C, 0x00},
341 {R367TER_DEBG_LT1D, 0x00},
342 {R367TER_DEBG_LT1E, 0x00},
343 {R367TER_DEBG_LT1F, 0x00},
344 {R367TER_RCCFGH, 0x00},
345 {R367TER_RCCFGM, 0x00},
346 {R367TER_RCCFGL, 0x00},
347 {R367TER_RCINSDELH, 0x00},
348 {R367TER_RCINSDELM, 0x00},
349 {R367TER_RCINSDELL, 0x00},
350 {R367TER_RCSTATUS, 0x00},
351 {R367TER_RCSPEED, 0x6f},
352 {R367TER_RCDEBUGM, 0xe7},
353 {R367TER_RCDEBUGL, 0x9b},
354 {R367TER_RCOBSCFG, 0x00},
355 {R367TER_RCOBSM, 0x00},
356 {R367TER_RCOBSL, 0x00},
357 {R367TER_RCFECSPY, 0x00},
358 {R367TER_RCFSPYCFG, 0x00},
359 {R367TER_RCFSPYDATA, 0x00},
360 {R367TER_RCFSPYOUT, 0x00},
361 {R367TER_RCFSTATUS, 0x00},
362 {R367TER_RCFGOODPACK, 0x00},
363 {R367TER_RCFPACKCNT, 0x00},
364 {R367TER_RCFSPYMISC, 0x00},
365 {R367TER_RCFBERCPT4, 0x00},
366 {R367TER_RCFBERCPT3, 0x00},
367 {R367TER_RCFBERCPT2, 0x00},
368 {R367TER_RCFBERCPT1, 0x00},
369 {R367TER_RCFBERCPT0, 0x00},
370 {R367TER_RCFBERERR2, 0x00},
371 {R367TER_RCFBERERR1, 0x00},
372 {R367TER_RCFBERERR0, 0x00},
373 {R367TER_RCFSTATESM, 0x00},
374 {R367TER_RCFSTATESL, 0x00},
375 {R367TER_RCFSPYBER, 0x00},
376 {R367TER_RCFSPYDISTM, 0x00},
377 {R367TER_RCFSPYDISTL, 0x00},
378 {R367TER_RCFSPYOBS7, 0x00},
379 {R367TER_RCFSPYOBS6, 0x00},
380 {R367TER_RCFSPYOBS5, 0x00},
381 {R367TER_RCFSPYOBS4, 0x00},
382 {R367TER_RCFSPYOBS3, 0x00},
383 {R367TER_RCFSPYOBS2, 0x00},
384 {R367TER_RCFSPYOBS1, 0x00},
385 {R367TER_RCFSPYOBS0, 0x00},
386 {R367TER_TSGENERAL, 0x00},
387 {R367TER_RC1SPEED, 0x6f},
388 {R367TER_TSGSTATUS, 0x18},
389 {R367TER_FECM, 0x01},
390 {R367TER_VTH12, 0xff},
391 {R367TER_VTH23, 0xa1},
392 {R367TER_VTH34, 0x64},
393 {R367TER_VTH56, 0x40},
394 {R367TER_VTH67, 0x00},
395 {R367TER_VTH78, 0x2c},
396 {R367TER_VITCURPUN, 0x12},
397 {R367TER_VERROR, 0x01},
398 {R367TER_PRVIT, 0x3f},
399 {R367TER_VAVSRVIT, 0x00},
400 {R367TER_VSTATUSVIT, 0xbd},
401 {R367TER_VTHINUSE, 0xa1},
402 {R367TER_KDIV12, 0x20},
403 {R367TER_KDIV23, 0x40},
404 {R367TER_KDIV34, 0x20},
405 {R367TER_KDIV56, 0x30},
406 {R367TER_KDIV67, 0x00},
407 {R367TER_KDIV78, 0x30},
408 {R367TER_SIGPOWER, 0x54},
409 {R367TER_DEMAPVIT, 0x40},
410 {R367TER_VITSCALE, 0x00},
411 {R367TER_FFEC1PRG, 0x00},
412 {R367TER_FVITCURPUN, 0x12},
413 {R367TER_FVERROR, 0x01},
414 {R367TER_FVSTATUSVIT, 0xbd},
415 {R367TER_DEBUG_LT1, 0x00},
416 {R367TER_DEBUG_LT2, 0x00},
417 {R367TER_DEBUG_LT3, 0x00},
418 {R367TER_TSTSFMET, 0x00},
419 {R367TER_SELOUT, 0x00},
420 {R367TER_TSYNC, 0x00},
421 {R367TER_TSTERR, 0x00},
422 {R367TER_TSFSYNC, 0x00},
423 {R367TER_TSTSFERR, 0x00},
424 {R367TER_TSTTSSF1, 0x01},
425 {R367TER_TSTTSSF2, 0x1f},
426 {R367TER_TSTTSSF3, 0x00},
427 {R367TER_TSTTS1, 0x00},
428 {R367TER_TSTTS2, 0x1f},
429 {R367TER_TSTTS3, 0x01},
430 {R367TER_TSTTS4, 0x00},
431 {R367TER_TSTTSRC, 0x00},
432 {R367TER_TSTTSRS, 0x00},
433 {R367TER_TSSTATEM, 0xb0},
434 {R367TER_TSSTATEL, 0x40},
435 {R367TER_TSCFGH, 0xC0},
436 {R367TER_TSCFGM, 0xc0},/* for xc5000; was 0x00 */
437 {R367TER_TSCFGL, 0x20},
438 {R367TER_TSSYNC, 0x00},
439 {R367TER_TSINSDELH, 0x00},
440 {R367TER_TSINSDELM, 0x00},
441 {R367TER_TSINSDELL, 0x00},
442 {R367TER_TSDIVN, 0x03},
443 {R367TER_TSDIVPM, 0x00},
444 {R367TER_TSDIVPL, 0x00},
445 {R367TER_TSDIVQM, 0x00},
446 {R367TER_TSDIVQL, 0x00},
447 {R367TER_TSDILSTKM, 0x00},
448 {R367TER_TSDILSTKL, 0x00},
449 {R367TER_TSSPEED, 0x40},/* for xc5000; was 0x6f */
450 {R367TER_TSSTATUS, 0x81},
451 {R367TER_TSSTATUS2, 0x6a},
452 {R367TER_TSBITRATEM, 0x0f},
453 {R367TER_TSBITRATEL, 0xc6},
454 {R367TER_TSPACKLENM, 0x00},
455 {R367TER_TSPACKLENL, 0xfc},
456 {R367TER_TSBLOCLENM, 0x0a},
457 {R367TER_TSBLOCLENL, 0x80},
458 {R367TER_TSDLYH, 0x90},
459 {R367TER_TSDLYM, 0x68},
460 {R367TER_TSDLYL, 0x01},
461 {R367TER_TSNPDAV, 0x00},
462 {R367TER_TSBUFSTATH, 0x00},
463 {R367TER_TSBUFSTATM, 0x00},
464 {R367TER_TSBUFSTATL, 0x00},
465 {R367TER_TSDEBUGM, 0xcf},
466 {R367TER_TSDEBUGL, 0x1e},
467 {R367TER_TSDLYSETH, 0x00},
468 {R367TER_TSDLYSETM, 0x68},
469 {R367TER_TSDLYSETL, 0x00},
470 {R367TER_TSOBSCFG, 0x00},
471 {R367TER_TSOBSM, 0x47},
472 {R367TER_TSOBSL, 0x1f},
473 {R367TER_ERRCTRL1, 0x95},
474 {R367TER_ERRCNT1H, 0x80},
475 {R367TER_ERRCNT1M, 0x00},
476 {R367TER_ERRCNT1L, 0x00},
477 {R367TER_ERRCTRL2, 0x95},
478 {R367TER_ERRCNT2H, 0x00},
479 {R367TER_ERRCNT2M, 0x00},
480 {R367TER_ERRCNT2L, 0x00},
481 {R367TER_FECSPY, 0x88},
482 {R367TER_FSPYCFG, 0x2c},
483 {R367TER_FSPYDATA, 0x3a},
484 {R367TER_FSPYOUT, 0x06},
485 {R367TER_FSTATUS, 0x61},
486 {R367TER_FGOODPACK, 0xff},
487 {R367TER_FPACKCNT, 0xff},
488 {R367TER_FSPYMISC, 0x66},
489 {R367TER_FBERCPT4, 0x00},
490 {R367TER_FBERCPT3, 0x00},
491 {R367TER_FBERCPT2, 0x36},
492 {R367TER_FBERCPT1, 0x36},
493 {R367TER_FBERCPT0, 0x14},
494 {R367TER_FBERERR2, 0x00},
495 {R367TER_FBERERR1, 0x03},
496 {R367TER_FBERERR0, 0x28},
497 {R367TER_FSTATESM, 0x00},
498 {R367TER_FSTATESL, 0x02},
499 {R367TER_FSPYBER, 0x00},
500 {R367TER_FSPYDISTM, 0x01},
501 {R367TER_FSPYDISTL, 0x9f},
502 {R367TER_FSPYOBS7, 0xc9},
503 {R367TER_FSPYOBS6, 0x99},
504 {R367TER_FSPYOBS5, 0x08},
505 {R367TER_FSPYOBS4, 0xec},
506 {R367TER_FSPYOBS3, 0x01},
507 {R367TER_FSPYOBS2, 0x0f},
508 {R367TER_FSPYOBS1, 0xf5},
509 {R367TER_FSPYOBS0, 0x08},
510 {R367TER_SFDEMAP, 0x40},
511 {R367TER_SFERROR, 0x00},
512 {R367TER_SFAVSR, 0x30},
513 {R367TER_SFECSTATUS, 0xcc},
514 {R367TER_SFKDIV12, 0x20},
515 {R367TER_SFKDIV23, 0x40},
516 {R367TER_SFKDIV34, 0x20},
517 {R367TER_SFKDIV56, 0x20},
518 {R367TER_SFKDIV67, 0x00},
519 {R367TER_SFKDIV78, 0x20},
520 {R367TER_SFDILSTKM, 0x00},
521 {R367TER_SFDILSTKL, 0x00},
522 {R367TER_SFSTATUS, 0xb5},
523 {R367TER_SFDLYH, 0x90},
524 {R367TER_SFDLYM, 0x60},
525 {R367TER_SFDLYL, 0x01},
526 {R367TER_SFDLYSETH, 0xc0},
527 {R367TER_SFDLYSETM, 0x60},
528 {R367TER_SFDLYSETL, 0x00},
529 {R367TER_SFOBSCFG, 0x00},
530 {R367TER_SFOBSM, 0x47},
531 {R367TER_SFOBSL, 0x05},
532 {R367TER_SFECINFO, 0x40},
533 {R367TER_SFERRCTRL, 0x74},
534 {R367TER_SFERRCNTH, 0x80},
535 {R367TER_SFERRCNTM , 0x00},
536 {R367TER_SFERRCNTL, 0x00},
537 {R367TER_SYMBRATEM, 0x2f},
538 {R367TER_SYMBRATEL, 0x50},
539 {R367TER_SYMBSTATUS, 0x7f},
540 {R367TER_SYMBCFG, 0x00},
541 {R367TER_SYMBFIFOM, 0xf4},
542 {R367TER_SYMBFIFOL, 0x0d},
543 {R367TER_SYMBOFFSM, 0xf0},
544 {R367TER_SYMBOFFSL, 0x2d},
545 {R367TER_DEBUG_LT4, 0x00},
546 {R367TER_DEBUG_LT5, 0x00},
547 {R367TER_DEBUG_LT6, 0x00},
548 {R367TER_DEBUG_LT7, 0x00},
549 {R367TER_DEBUG_LT8, 0x00},
550 {R367TER_DEBUG_LT9, 0x00},
551 };
552
553 #define RF_LOOKUP_TABLE_SIZE 31
554 #define RF_LOOKUP_TABLE2_SIZE 16
555 /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
556 static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
557 {/*AGC1*/
558 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
559 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
560 76, 77, 78, 80, 83, 85, 88,
561 }, {/*RF(dbm)*/
562 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
563 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
564 49, 50, 52, 53, 54, 55, 56,
565 }
566 };
567 /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
568 static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
569 {/*AGC2*/
570 28, 29, 31, 32, 34, 35, 36, 37,
571 38, 39, 40, 41, 42, 43, 44, 45,
572 }, {/*RF(dbm)*/
573 57, 58, 59, 60, 61, 62, 63, 64,
574 65, 66, 67, 68, 69, 70, 71, 72,
575 }
576 };
577
578 static struct st_register def0367cab[STV0367CAB_NBREGS] = {
579 {R367CAB_ID, 0x60},
580 {R367CAB_I2CRPT, 0xa0},
581 /*{R367CAB_I2CRPT, 0x22},*/
582 {R367CAB_TOPCTRL, 0x10},
583 {R367CAB_IOCFG0, 0x80},
584 {R367CAB_DAC0R, 0x00},
585 {R367CAB_IOCFG1, 0x00},
586 {R367CAB_DAC1R, 0x00},
587 {R367CAB_IOCFG2, 0x00},
588 {R367CAB_SDFR, 0x00},
589 {R367CAB_AUX_CLK, 0x00},
590 {R367CAB_FREESYS1, 0x00},
591 {R367CAB_FREESYS2, 0x00},
592 {R367CAB_FREESYS3, 0x00},
593 {R367CAB_GPIO_CFG, 0x55},
594 {R367CAB_GPIO_CMD, 0x01},
595 {R367CAB_TSTRES, 0x00},
596 {R367CAB_ANACTRL, 0x0d},/* was 0x00 need to check - I.M.L.*/
597 {R367CAB_TSTBUS, 0x00},
598 {R367CAB_RF_AGC1, 0xea},
599 {R367CAB_RF_AGC2, 0x82},
600 {R367CAB_ANADIGCTRL, 0x0b},
601 {R367CAB_PLLMDIV, 0x01},
602 {R367CAB_PLLNDIV, 0x08},
603 {R367CAB_PLLSETUP, 0x18},
604 {R367CAB_DUAL_AD12, 0x0C}, /* for xc5000 AGC voltage 1.6V */
605 {R367CAB_TSTBIST, 0x00},
606 {R367CAB_CTRL_1, 0x00},
607 {R367CAB_CTRL_2, 0x03},
608 {R367CAB_IT_STATUS1, 0x2b},
609 {R367CAB_IT_STATUS2, 0x08},
610 {R367CAB_IT_EN1, 0x00},
611 {R367CAB_IT_EN2, 0x00},
612 {R367CAB_CTRL_STATUS, 0x04},
613 {R367CAB_TEST_CTL, 0x00},
614 {R367CAB_AGC_CTL, 0x73},
615 {R367CAB_AGC_IF_CFG, 0x50},
616 {R367CAB_AGC_RF_CFG, 0x00},
617 {R367CAB_AGC_PWM_CFG, 0x03},
618 {R367CAB_AGC_PWR_REF_L, 0x5a},
619 {R367CAB_AGC_PWR_REF_H, 0x00},
620 {R367CAB_AGC_RF_TH_L, 0xff},
621 {R367CAB_AGC_RF_TH_H, 0x07},
622 {R367CAB_AGC_IF_LTH_L, 0x00},
623 {R367CAB_AGC_IF_LTH_H, 0x08},
624 {R367CAB_AGC_IF_HTH_L, 0xff},
625 {R367CAB_AGC_IF_HTH_H, 0x07},
626 {R367CAB_AGC_PWR_RD_L, 0xa0},
627 {R367CAB_AGC_PWR_RD_M, 0xe9},
628 {R367CAB_AGC_PWR_RD_H, 0x03},
629 {R367CAB_AGC_PWM_IFCMD_L, 0xe4},
630 {R367CAB_AGC_PWM_IFCMD_H, 0x00},
631 {R367CAB_AGC_PWM_RFCMD_L, 0xff},
632 {R367CAB_AGC_PWM_RFCMD_H, 0x07},
633 {R367CAB_IQDEM_CFG, 0x01},
634 {R367CAB_MIX_NCO_LL, 0x22},
635 {R367CAB_MIX_NCO_HL, 0x96},
636 {R367CAB_MIX_NCO_HH, 0x55},
637 {R367CAB_SRC_NCO_LL, 0xff},
638 {R367CAB_SRC_NCO_LH, 0x0c},
639 {R367CAB_SRC_NCO_HL, 0xf5},
640 {R367CAB_SRC_NCO_HH, 0x20},
641 {R367CAB_IQDEM_GAIN_SRC_L, 0x06},
642 {R367CAB_IQDEM_GAIN_SRC_H, 0x01},
643 {R367CAB_IQDEM_DCRM_CFG_LL, 0xfe},
644 {R367CAB_IQDEM_DCRM_CFG_LH, 0xff},
645 {R367CAB_IQDEM_DCRM_CFG_HL, 0x0f},
646 {R367CAB_IQDEM_DCRM_CFG_HH, 0x00},
647 {R367CAB_IQDEM_ADJ_COEFF0, 0x34},
648 {R367CAB_IQDEM_ADJ_COEFF1, 0xae},
649 {R367CAB_IQDEM_ADJ_COEFF2, 0x46},
650 {R367CAB_IQDEM_ADJ_COEFF3, 0x77},
651 {R367CAB_IQDEM_ADJ_COEFF4, 0x96},
652 {R367CAB_IQDEM_ADJ_COEFF5, 0x69},
653 {R367CAB_IQDEM_ADJ_COEFF6, 0xc7},
654 {R367CAB_IQDEM_ADJ_COEFF7, 0x01},
655 {R367CAB_IQDEM_ADJ_EN, 0x04},
656 {R367CAB_IQDEM_ADJ_AGC_REF, 0x94},
657 {R367CAB_ALLPASSFILT1, 0xc9},
658 {R367CAB_ALLPASSFILT2, 0x2d},
659 {R367CAB_ALLPASSFILT3, 0xa3},
660 {R367CAB_ALLPASSFILT4, 0xfb},
661 {R367CAB_ALLPASSFILT5, 0xf6},
662 {R367CAB_ALLPASSFILT6, 0x45},
663 {R367CAB_ALLPASSFILT7, 0x6f},
664 {R367CAB_ALLPASSFILT8, 0x7e},
665 {R367CAB_ALLPASSFILT9, 0x05},
666 {R367CAB_ALLPASSFILT10, 0x0a},
667 {R367CAB_ALLPASSFILT11, 0x51},
668 {R367CAB_TRL_AGC_CFG, 0x20},
669 {R367CAB_TRL_LPF_CFG, 0x28},
670 {R367CAB_TRL_LPF_ACQ_GAIN, 0x44},
671 {R367CAB_TRL_LPF_TRK_GAIN, 0x22},
672 {R367CAB_TRL_LPF_OUT_GAIN, 0x03},
673 {R367CAB_TRL_LOCKDET_LTH, 0x04},
674 {R367CAB_TRL_LOCKDET_HTH, 0x11},
675 {R367CAB_TRL_LOCKDET_TRGVAL, 0x20},
676 {R367CAB_IQ_QAM, 0x01},
677 {R367CAB_FSM_STATE, 0xa0},
678 {R367CAB_FSM_CTL, 0x08},
679 {R367CAB_FSM_STS, 0x0c},
680 {R367CAB_FSM_SNR0_HTH, 0x00},
681 {R367CAB_FSM_SNR1_HTH, 0x00},
682 {R367CAB_FSM_SNR2_HTH, 0x23},/* 0x00 */
683 {R367CAB_FSM_SNR0_LTH, 0x00},
684 {R367CAB_FSM_SNR1_LTH, 0x00},
685 {R367CAB_FSM_EQA1_HTH, 0x00},
686 {R367CAB_FSM_TEMPO, 0x32},
687 {R367CAB_FSM_CONFIG, 0x03},
688 {R367CAB_EQU_I_TESTTAP_L, 0x11},
689 {R367CAB_EQU_I_TESTTAP_M, 0x00},
690 {R367CAB_EQU_I_TESTTAP_H, 0x00},
691 {R367CAB_EQU_TESTAP_CFG, 0x00},
692 {R367CAB_EQU_Q_TESTTAP_L, 0xff},
693 {R367CAB_EQU_Q_TESTTAP_M, 0x00},
694 {R367CAB_EQU_Q_TESTTAP_H, 0x00},
695 {R367CAB_EQU_TAP_CTRL, 0x00},
696 {R367CAB_EQU_CTR_CRL_CONTROL_L, 0x11},
697 {R367CAB_EQU_CTR_CRL_CONTROL_H, 0x05},
698 {R367CAB_EQU_CTR_HIPOW_L, 0x00},
699 {R367CAB_EQU_CTR_HIPOW_H, 0x00},
700 {R367CAB_EQU_I_EQU_LO, 0xef},
701 {R367CAB_EQU_I_EQU_HI, 0x00},
702 {R367CAB_EQU_Q_EQU_LO, 0xee},
703 {R367CAB_EQU_Q_EQU_HI, 0x00},
704 {R367CAB_EQU_MAPPER, 0xc5},
705 {R367CAB_EQU_SWEEP_RATE, 0x80},
706 {R367CAB_EQU_SNR_LO, 0x64},
707 {R367CAB_EQU_SNR_HI, 0x03},
708 {R367CAB_EQU_GAMMA_LO, 0x00},
709 {R367CAB_EQU_GAMMA_HI, 0x00},
710 {R367CAB_EQU_ERR_GAIN, 0x36},
711 {R367CAB_EQU_RADIUS, 0xaa},
712 {R367CAB_EQU_FFE_MAINTAP, 0x00},
713 {R367CAB_EQU_FFE_LEAKAGE, 0x63},
714 {R367CAB_EQU_FFE_MAINTAP_POS, 0xdf},
715 {R367CAB_EQU_GAIN_WIDE, 0x88},
716 {R367CAB_EQU_GAIN_NARROW, 0x41},
717 {R367CAB_EQU_CTR_LPF_GAIN, 0xd1},
718 {R367CAB_EQU_CRL_LPF_GAIN, 0xa7},
719 {R367CAB_EQU_GLOBAL_GAIN, 0x06},
720 {R367CAB_EQU_CRL_LD_SEN, 0x85},
721 {R367CAB_EQU_CRL_LD_VAL, 0xe2},
722 {R367CAB_EQU_CRL_TFR, 0x20},
723 {R367CAB_EQU_CRL_BISTH_LO, 0x00},
724 {R367CAB_EQU_CRL_BISTH_HI, 0x00},
725 {R367CAB_EQU_SWEEP_RANGE_LO, 0x00},
726 {R367CAB_EQU_SWEEP_RANGE_HI, 0x00},
727 {R367CAB_EQU_CRL_LIMITER, 0x40},
728 {R367CAB_EQU_MODULUS_MAP, 0x90},
729 {R367CAB_EQU_PNT_GAIN, 0xa7},
730 {R367CAB_FEC_AC_CTR_0, 0x16},
731 {R367CAB_FEC_AC_CTR_1, 0x0b},
732 {R367CAB_FEC_AC_CTR_2, 0x88},
733 {R367CAB_FEC_AC_CTR_3, 0x02},
734 {R367CAB_FEC_STATUS, 0x12},
735 {R367CAB_RS_COUNTER_0, 0x7d},
736 {R367CAB_RS_COUNTER_1, 0xd0},
737 {R367CAB_RS_COUNTER_2, 0x19},
738 {R367CAB_RS_COUNTER_3, 0x0b},
739 {R367CAB_RS_COUNTER_4, 0xa3},
740 {R367CAB_RS_COUNTER_5, 0x00},
741 {R367CAB_BERT_0, 0x01},
742 {R367CAB_BERT_1, 0x25},
743 {R367CAB_BERT_2, 0x41},
744 {R367CAB_BERT_3, 0x39},
745 {R367CAB_OUTFORMAT_0, 0xc2},
746 {R367CAB_OUTFORMAT_1, 0x22},
747 {R367CAB_SMOOTHER_2, 0x28},
748 {R367CAB_TSMF_CTRL_0, 0x01},
749 {R367CAB_TSMF_CTRL_1, 0xc6},
750 {R367CAB_TSMF_CTRL_3, 0x43},
751 {R367CAB_TS_ON_ID_0, 0x00},
752 {R367CAB_TS_ON_ID_1, 0x00},
753 {R367CAB_TS_ON_ID_2, 0x00},
754 {R367CAB_TS_ON_ID_3, 0x00},
755 {R367CAB_RE_STATUS_0, 0x00},
756 {R367CAB_RE_STATUS_1, 0x00},
757 {R367CAB_RE_STATUS_2, 0x00},
758 {R367CAB_RE_STATUS_3, 0x00},
759 {R367CAB_TS_STATUS_0, 0x00},
760 {R367CAB_TS_STATUS_1, 0x00},
761 {R367CAB_TS_STATUS_2, 0xa0},
762 {R367CAB_TS_STATUS_3, 0x00},
763 {R367CAB_T_O_ID_0, 0x00},
764 {R367CAB_T_O_ID_1, 0x00},
765 {R367CAB_T_O_ID_2, 0x00},
766 {R367CAB_T_O_ID_3, 0x00},
767 };
768
769 static
770 int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
771 {
772 u8 buf[MAX_XFER_SIZE];
773 struct i2c_msg msg = {
774 .addr = state->config->demod_address,
775 .flags = 0,
776 .buf = buf,
777 .len = len + 2
778 };
779 int ret;
780
781 if (2 + len > sizeof(buf)) {
782 printk(KERN_WARNING
783 "%s: i2c wr reg=%04x: len=%d is too big!\n",
784 KBUILD_MODNAME, reg, len);
785 return -EINVAL;
786 }
787
788
789 buf[0] = MSB(reg);
790 buf[1] = LSB(reg);
791 memcpy(buf + 2, data, len);
792
793 if (i2cdebug)
794 printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, buf[2]);
795
796 ret = i2c_transfer(state->i2c, &msg, 1);
797 if (ret != 1)
798 printk(KERN_ERR "%s: i2c write error!\n", __func__);
799
800 return (ret != 1) ? -EREMOTEIO : 0;
801 }
802
803 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
804 {
805 return stv0367_writeregs(state, reg, &data, 1);
806 }
807
808 static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
809 {
810 u8 b0[] = { 0, 0 };
811 u8 b1[] = { 0 };
812 struct i2c_msg msg[] = {
813 {
814 .addr = state->config->demod_address,
815 .flags = 0,
816 .buf = b0,
817 .len = 2
818 }, {
819 .addr = state->config->demod_address,
820 .flags = I2C_M_RD,
821 .buf = b1,
822 .len = 1
823 }
824 };
825 int ret;
826
827 b0[0] = MSB(reg);
828 b0[1] = LSB(reg);
829
830 ret = i2c_transfer(state->i2c, msg, 2);
831 if (ret != 2)
832 printk(KERN_ERR "%s: i2c read error\n", __func__);
833
834 if (i2cdebug)
835 printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, b1[0]);
836
837 return b1[0];
838 }
839
840 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
841 {
842 u8 position = 0, i = 0;
843
844 (*mask) = label & 0xff;
845
846 while ((position == 0) && (i < 8)) {
847 position = ((*mask) >> i) & 0x01;
848 i++;
849 }
850
851 (*pos) = (i - 1);
852 }
853
854 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
855 {
856 u8 reg, mask, pos;
857
858 reg = stv0367_readreg(state, (label >> 16) & 0xffff);
859 extract_mask_pos(label, &mask, &pos);
860
861 val = mask & (val << pos);
862
863 reg = (reg & (~mask)) | val;
864 stv0367_writereg(state, (label >> 16) & 0xffff, reg);
865
866 }
867
868 static void stv0367_setbits(u8 *reg, u32 label, u8 val)
869 {
870 u8 mask, pos;
871
872 extract_mask_pos(label, &mask, &pos);
873
874 val = mask & (val << pos);
875
876 (*reg) = ((*reg) & (~mask)) | val;
877 }
878
879 static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
880 {
881 u8 val = 0xff;
882 u8 mask, pos;
883
884 extract_mask_pos(label, &mask, &pos);
885
886 val = stv0367_readreg(state, label >> 16);
887 val = (val & mask) >> pos;
888
889 return val;
890 }
891
892 #if 0 /* Currently, unused */
893 static u8 stv0367_getbits(u8 reg, u32 label)
894 {
895 u8 mask, pos;
896
897 extract_mask_pos(label, &mask, &pos);
898
899 return (reg & mask) >> pos;
900 }
901 #endif
902 static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
903 {
904 struct stv0367_state *state = fe->demodulator_priv;
905 u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
906
907 dprintk("%s:\n", __func__);
908
909 if (enable) {
910 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
911 stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
912 } else {
913 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
914 stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
915 }
916
917 stv0367_writereg(state, R367TER_I2CRPT, tmp);
918
919 return 0;
920 }
921
922 static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
923 {
924 struct dvb_frontend_ops *frontend_ops = &fe->ops;
925 struct dvb_tuner_ops *tuner_ops = &frontend_ops->tuner_ops;
926 u32 freq = 0;
927 int err = 0;
928
929 dprintk("%s:\n", __func__);
930
931 if (tuner_ops->get_frequency) {
932 err = tuner_ops->get_frequency(fe, &freq);
933 if (err < 0) {
934 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
935 return err;
936 }
937
938 dprintk("%s: frequency=%d\n", __func__, freq);
939
940 } else
941 return -1;
942
943 return freq;
944 }
945
946 static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
947 {
948 {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
949 {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
950 {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
951 {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
952 {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
953 {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
954 }, {
955 {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
956 {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
957 {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
958 {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
959 {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
960 {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
961 }, {
962 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
963 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
964 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
965 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
966 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
967 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
968 }
969 };
970
971 static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
972 {
973 {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
974 {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
975 {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
976 {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
977 {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
978 {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
979 }, {
980 {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
981 {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
982 {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
983 {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
984 {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
985 {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
986 }, {
987 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
988 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
989 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
990 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
991 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
992 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
993 }
994 };
995
996 static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
997 {
998 {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
999 {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
1000 {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
1001 {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
1002 {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
1003 {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
1004 }, {
1005 {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
1006 {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
1007 {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
1008 {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
1009 {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
1010 {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
1011
1012 }, {
1013 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
1014 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1015 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1016 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1017 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1018 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
1019 }
1020 };
1021
1022 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
1023 {
1024 u32 mclk_Hz = 0; /* master clock frequency (Hz) */
1025 u32 m, n, p;
1026
1027 dprintk("%s:\n", __func__);
1028
1029 if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
1030 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
1031 if (n == 0)
1032 n = n + 1;
1033
1034 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
1035 if (m == 0)
1036 m = m + 1;
1037
1038 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
1039 if (p > 5)
1040 p = 5;
1041
1042 mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
1043
1044 dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
1045 n, m, p, mclk_Hz, ExtClk_Hz);
1046 } else
1047 mclk_Hz = ExtClk_Hz;
1048
1049 dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
1050
1051 return mclk_Hz;
1052 }
1053
1054 static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
1055 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
1056 {
1057 int i, j, k, freq;
1058
1059 dprintk("%s:\n", __func__);
1060
1061 freq = stv0367ter_get_mclk(state, DemodXtal);
1062
1063 if (freq == 53125000)
1064 k = 1; /* equivalent to Xtal 25M on 362*/
1065 else if (freq == 54000000)
1066 k = 0; /* equivalent to Xtal 27M on 362*/
1067 else if (freq == 52500000)
1068 k = 2; /* equivalent to Xtal 30M on 362*/
1069 else
1070 return 0;
1071
1072 for (i = 1; i <= 6; i++) {
1073 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
1074
1075 for (j = 1; j <= 5; j++) {
1076 stv0367_writereg(state,
1077 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
1078 MSB(CellsCoeffs[k][i-1][j-1]));
1079 stv0367_writereg(state,
1080 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
1081 LSB(CellsCoeffs[k][i-1][j-1]));
1082 }
1083 }
1084
1085 return 1;
1086
1087 }
1088
1089 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
1090 {
1091 dprintk("%s:\n", __func__);
1092
1093 stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
1094
1095 /* Lock detect 1 */
1096 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
1097 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1098 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1099
1100 /* Lock detect 2 */
1101 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
1102 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1103 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1104
1105 /* Lock detect 3 */
1106 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
1107 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1108 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1109
1110 /* Lock detect 4 */
1111 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
1112 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1113 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1114
1115 }
1116
1117 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
1118 u32 DemodXtalValue)
1119 {
1120 dprintk("%s:\n", __func__);
1121
1122 stv0367_writebits(state, F367TER_NRST_IIR, 0);
1123
1124 switch (Bandwidth) {
1125 case 6:
1126 if (!stv0367ter_filt_coeff_init(state,
1127 CellsCoeffs_6MHz_367cofdm,
1128 DemodXtalValue))
1129 return 0;
1130 break;
1131 case 7:
1132 if (!stv0367ter_filt_coeff_init(state,
1133 CellsCoeffs_7MHz_367cofdm,
1134 DemodXtalValue))
1135 return 0;
1136 break;
1137 case 8:
1138 if (!stv0367ter_filt_coeff_init(state,
1139 CellsCoeffs_8MHz_367cofdm,
1140 DemodXtalValue))
1141 return 0;
1142 break;
1143 default:
1144 return 0;
1145 }
1146
1147 stv0367_writebits(state, F367TER_NRST_IIR, 1);
1148
1149 return 1;
1150 }
1151
1152 static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
1153 {
1154
1155 u8 com_n;
1156
1157 dprintk("%s:\n", __func__);
1158
1159 com_n = stv0367_readbits(state, F367TER_COM_N);
1160
1161 stv0367_writebits(state, F367TER_COM_N, 0x07);
1162
1163 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
1164 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
1165
1166 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
1167 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
1168
1169 stv0367_writebits(state, F367TER_COM_N, com_n);
1170
1171 }
1172
1173 static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
1174 {
1175 int local_tempo = 0;
1176 switch (mode) {
1177 case 0:
1178 local_tempo = tempo1;
1179 break;
1180 case 1:
1181 local_tempo = tempo2;
1182 break ;
1183
1184 case 2:
1185 local_tempo = tempo3;
1186 break;
1187
1188 default:
1189 break;
1190 }
1191 /* msleep(local_tempo); */
1192 return local_tempo;
1193 }
1194
1195 static enum
1196 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
1197 {
1198 int wd = 100;
1199 unsigned short int SYR_var;
1200 s32 SYRStatus;
1201
1202 dprintk("%s:\n", __func__);
1203
1204 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1205
1206 while ((!SYR_var) && (wd > 0)) {
1207 usleep_range(2000, 3000);
1208 wd -= 2;
1209 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1210 }
1211
1212 if (!SYR_var)
1213 SYRStatus = FE_TER_NOSYMBOL;
1214 else
1215 SYRStatus = FE_TER_SYMBOLOK;
1216
1217 dprintk("stv0367ter_check_syr SYRStatus %s\n",
1218 SYR_var == 0 ? "No Symbol" : "OK");
1219
1220 return SYRStatus;
1221 }
1222
1223 static enum
1224 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
1225 s32 FFTmode)
1226 {
1227
1228 s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
1229 int wd = 0;
1230
1231 dprintk("%s:\n", __func__);
1232
1233 switch (FFTmode) {
1234 case 0: /*2k mode*/
1235 CPAMPMin = 20;
1236 wd = 10;
1237 break;
1238 case 1: /*8k mode*/
1239 CPAMPMin = 80;
1240 wd = 55;
1241 break;
1242 case 2: /*4k mode*/
1243 CPAMPMin = 40;
1244 wd = 30;
1245 break;
1246 default:
1247 CPAMPMin = 0xffff; /*drives to NOCPAMP */
1248 break;
1249 }
1250
1251 dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
1252
1253 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1254 while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
1255 usleep_range(1000, 2000);
1256 wd -= 1;
1257 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1258 /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
1259 }
1260 dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
1261 if (CPAMPvalue < CPAMPMin) {
1262 CPAMPStatus = FE_TER_NOCPAMP;
1263 printk(KERN_ERR "CPAMP failed\n");
1264 } else {
1265 printk(KERN_ERR "CPAMP OK !\n");
1266 CPAMPStatus = FE_TER_CPAMPOK;
1267 }
1268
1269 return CPAMPStatus;
1270 }
1271
1272 static enum stv0367_ter_signal_type
1273 stv0367ter_lock_algo(struct stv0367_state *state)
1274 {
1275 enum stv0367_ter_signal_type ret_flag;
1276 short int wd, tempo;
1277 u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
1278 u8 tmp, tmp2;
1279
1280 dprintk("%s:\n", __func__);
1281
1282 if (state == NULL)
1283 return FE_TER_SWNOK;
1284
1285 try = 0;
1286 do {
1287 ret_flag = FE_TER_LOCKOK;
1288
1289 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1290
1291 if (state->config->if_iq_mode != 0)
1292 stv0367_writebits(state, F367TER_COM_N, 0x07);
1293
1294 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
1295 stv0367_writebits(state, F367TER_MODE, 0);
1296 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
1297 usleep_range(5000, 10000);
1298
1299 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1300
1301
1302 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
1303 return FE_TER_NOSYMBOL;
1304 else { /*
1305 if chip locked on wrong mode first try,
1306 it must lock correctly second try */
1307 mode = stv0367_readbits(state, F367TER_SYR_MODE);
1308 if (stv0367ter_check_cpamp(state, mode) ==
1309 FE_TER_NOCPAMP) {
1310 if (try == 0)
1311 ret_flag = FE_TER_NOCPAMP;
1312
1313 }
1314 }
1315
1316 try++;
1317 } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
1318
1319 tmp = stv0367_readreg(state, R367TER_SYR_STAT);
1320 tmp2 = stv0367_readreg(state, R367TER_STATUS);
1321 dprintk("state=%p\n", state);
1322 dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
1323 mode, tmp, tmp2);
1324
1325 tmp = stv0367_readreg(state, R367TER_PRVIT);
1326 tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
1327 dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
1328
1329 tmp = stv0367_readreg(state, R367TER_GAIN_SRC1);
1330 dprintk("GAIN_SRC1=0x%x\n", tmp);
1331
1332 if ((mode != 0) && (mode != 1) && (mode != 2))
1333 return FE_TER_SWNOK;
1334
1335 /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
1336
1337 /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
1338 and set channel predictor in automatic */
1339 #if 0
1340 switch (guard) {
1341
1342 case 0:
1343 case 1:
1344 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1345 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
1346 break;
1347 case 2:
1348 case 3:
1349 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1350 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1351 break;
1352
1353 default:
1354 return FE_TER_SWNOK;
1355 }
1356 #endif
1357
1358 /*reset fec an reedsolo FOR 367 only*/
1359 stv0367_writebits(state, F367TER_RST_SFEC, 1);
1360 stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
1361 usleep_range(1000, 2000);
1362 stv0367_writebits(state, F367TER_RST_SFEC, 0);
1363 stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
1364
1365 u_var1 = stv0367_readbits(state, F367TER_LK);
1366 u_var2 = stv0367_readbits(state, F367TER_PRF);
1367 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1368 /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
1369
1370 wd = stv0367ter_duration(mode, 125, 500, 250);
1371 tempo = stv0367ter_duration(mode, 4, 16, 8);
1372
1373 /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */
1374 while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
1375 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1376 wd -= tempo;
1377 u_var1 = stv0367_readbits(state, F367TER_LK);
1378 u_var2 = stv0367_readbits(state, F367TER_PRF);
1379 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1380 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
1381 }
1382
1383 if (!u_var1)
1384 return FE_TER_NOLOCK;
1385
1386
1387 if (!u_var2)
1388 return FE_TER_NOPRFOUND;
1389
1390 if (!u_var3)
1391 return FE_TER_NOTPS;
1392
1393 guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1394 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1395 switch (guard) {
1396 case 0:
1397 case 1:
1398 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1399 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
1400 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
1401 break;
1402 case 2:
1403 case 3:
1404 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1405 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
1406 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
1407 break;
1408
1409 default:
1410 return FE_TER_SWNOK;
1411 }
1412
1413 /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
1414 if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
1415 (mode == 1) &&
1416 (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
1417 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
1418 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
1419 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
1420 } else
1421 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
1422
1423 wd = stv0367ter_duration(mode, 125, 500, 250);
1424 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1425
1426 while ((!u_var4) && (wd >= 0)) {
1427 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1428 wd -= tempo;
1429 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1430 }
1431
1432 if (!u_var4)
1433 return FE_TER_NOLOCK;
1434
1435 /* for 367 leave COM_N at 0x7 for IQ_mode*/
1436 /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
1437 tempo=0;
1438 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
1439 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
1440 ChipWaitOrAbort(state,1);
1441 tempo+=1;
1442 }
1443
1444 stv0367_writebits(state,F367TER_COM_N,0x17);
1445 } */
1446
1447 stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
1448
1449 dprintk("FE_TER_LOCKOK !!!\n");
1450
1451 return FE_TER_LOCKOK;
1452
1453 }
1454
1455 static void stv0367ter_set_ts_mode(struct stv0367_state *state,
1456 enum stv0367_ts_mode PathTS)
1457 {
1458
1459 dprintk("%s:\n", __func__);
1460
1461 if (state == NULL)
1462 return;
1463
1464 stv0367_writebits(state, F367TER_TS_DIS, 0);
1465 switch (PathTS) {
1466 default:
1467 /*for removing warning :default we can assume in parallel mode*/
1468 case STV0367_PARALLEL_PUNCT_CLOCK:
1469 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
1470 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
1471 break;
1472 case STV0367_SERIAL_PUNCT_CLOCK:
1473 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
1474 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
1475 break;
1476 }
1477 }
1478
1479 static void stv0367ter_set_clk_pol(struct stv0367_state *state,
1480 enum stv0367_clk_pol clock)
1481 {
1482
1483 dprintk("%s:\n", __func__);
1484
1485 if (state == NULL)
1486 return;
1487
1488 switch (clock) {
1489 case STV0367_RISINGEDGE_CLOCK:
1490 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
1491 break;
1492 case STV0367_FALLINGEDGE_CLOCK:
1493 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1494 break;
1495 /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
1496 default:
1497 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1498 break;
1499 }
1500 }
1501
1502 #if 0
1503 static void stv0367ter_core_sw(struct stv0367_state *state)
1504 {
1505
1506 dprintk("%s:\n", __func__);
1507
1508 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1509 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1510 msleep(350);
1511 }
1512 #endif
1513 static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
1514 {
1515 struct stv0367_state *state = fe->demodulator_priv;
1516
1517 dprintk("%s:\n", __func__);
1518
1519 if (standby_on) {
1520 stv0367_writebits(state, F367TER_STDBY, 1);
1521 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
1522 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
1523 } else {
1524 stv0367_writebits(state, F367TER_STDBY, 0);
1525 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
1526 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
1527 }
1528
1529 return 0;
1530 }
1531
1532 static int stv0367ter_sleep(struct dvb_frontend *fe)
1533 {
1534 return stv0367ter_standby(fe, 1);
1535 }
1536
1537 static int stv0367ter_init(struct dvb_frontend *fe)
1538 {
1539 struct stv0367_state *state = fe->demodulator_priv;
1540 struct stv0367ter_state *ter_state = state->ter_state;
1541 int i;
1542
1543 dprintk("%s:\n", __func__);
1544
1545 ter_state->pBER = 0;
1546
1547 for (i = 0; i < STV0367TER_NBREGS; i++)
1548 stv0367_writereg(state, def0367ter[i].addr,
1549 def0367ter[i].value);
1550
1551 switch (state->config->xtal) {
1552 /*set internal freq to 53.125MHz */
1553 case 25000000:
1554 stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
1555 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1556 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1557 break;
1558 default:
1559 case 27000000:
1560 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
1561 stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
1562 stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
1563 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1564 break;
1565 case 30000000:
1566 stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
1567 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1568 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1569 break;
1570 }
1571
1572 stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
1573 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
1574
1575 /*Set TS1 and TS2 to serial or parallel mode */
1576 stv0367ter_set_ts_mode(state, state->config->ts_mode);
1577 stv0367ter_set_clk_pol(state, state->config->clk_pol);
1578
1579 state->chip_id = stv0367_readreg(state, R367TER_ID);
1580 ter_state->first_lock = 0;
1581 ter_state->unlock_counter = 2;
1582
1583 return 0;
1584 }
1585
1586 static int stv0367ter_algo(struct dvb_frontend *fe)
1587 {
1588 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1589 struct stv0367_state *state = fe->demodulator_priv;
1590 struct stv0367ter_state *ter_state = state->ter_state;
1591 int offset = 0, tempo = 0;
1592 u8 u_var;
1593 u8 /*constell,*/ counter;
1594 s8 step;
1595 s32 timing_offset = 0;
1596 u32 trl_nomrate = 0, InternalFreq = 0, temp = 0;
1597
1598 dprintk("%s:\n", __func__);
1599
1600 ter_state->frequency = p->frequency;
1601 ter_state->force = FE_TER_FORCENONE
1602 + stv0367_readbits(state, F367TER_FORCE) * 2;
1603 ter_state->if_iq_mode = state->config->if_iq_mode;
1604 switch (state->config->if_iq_mode) {
1605 case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */
1606 dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1607 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1608 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1609 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1610 break;
1611 case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */
1612 dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1613 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1614 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1615 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1616 break;
1617 case FE_TER_IQ_TUNER: /* IQ mode */
1618 dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1619 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1620 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1621 break;
1622 default:
1623 printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1624 return -EINVAL;
1625 }
1626
1627 usleep_range(5000, 7000);
1628
1629 switch (p->inversion) {
1630 case INVERSION_AUTO:
1631 default:
1632 dprintk("%s: inversion AUTO\n", __func__);
1633 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1634 stv0367_writebits(state, F367TER_IQ_INVERT,
1635 ter_state->sense);
1636 else
1637 stv0367_writebits(state, F367TER_INV_SPECTR,
1638 ter_state->sense);
1639
1640 break;
1641 case INVERSION_ON:
1642 case INVERSION_OFF:
1643 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1644 stv0367_writebits(state, F367TER_IQ_INVERT,
1645 p->inversion);
1646 else
1647 stv0367_writebits(state, F367TER_INV_SPECTR,
1648 p->inversion);
1649
1650 break;
1651 }
1652
1653 if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1654 (ter_state->pBW != ter_state->bw)) {
1655 stv0367ter_agc_iir_lock_detect_set(state);
1656
1657 /*set fine agc target to 180 for LPIF or IQ mode*/
1658 /* set Q_AGCTarget */
1659 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1660 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1661 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1662
1663 /* set Q_AGCTarget */
1664 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1665 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1666 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1667
1668 if (!stv0367_iir_filt_init(state, ter_state->bw,
1669 state->config->xtal))
1670 return -EINVAL;
1671 /*set IIR filter once for 6,7 or 8MHz BW*/
1672 ter_state->pBW = ter_state->bw;
1673
1674 stv0367ter_agc_iir_rst(state);
1675 }
1676
1677 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1678 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1679 else
1680 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1681
1682 InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1683 temp = (int)
1684 ((((ter_state->bw * 64 * (1 << 15) * 100)
1685 / (InternalFreq)) * 10) / 7);
1686
1687 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1688 temp = temp / 2;
1689 stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1690 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1691
1692 temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1693 stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1694 stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1695 temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1696 stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1697 stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1698 temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1699 stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1700
1701 temp = (int)
1702 ((InternalFreq - state->config->if_khz) * (1 << 16)
1703 / (InternalFreq));
1704
1705 dprintk("DEROT temp=0x%x\n", temp);
1706 stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1707 stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1708
1709 ter_state->echo_pos = 0;
1710 ter_state->ucblocks = 0; /* liplianin */
1711 ter_state->pBER = 0; /* liplianin */
1712 stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1713
1714 if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1715 return 0;
1716
1717 ter_state->state = FE_TER_LOCKOK;
1718
1719 ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1720 ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1721
1722 ter_state->first_lock = 1; /* we know sense now :) */
1723
1724 ter_state->agc_val =
1725 (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1726 (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1727 stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1728 (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1729
1730 /* Carrier offset calculation */
1731 stv0367_writebits(state, F367TER_FREEZE, 1);
1732 offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1733 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1734 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1735 stv0367_writebits(state, F367TER_FREEZE, 0);
1736 if (offset > 8388607)
1737 offset -= 16777216;
1738
1739 offset = offset * 2 / 16384;
1740
1741 if (ter_state->mode == FE_TER_MODE_2K)
1742 offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1743 else if (ter_state->mode == FE_TER_MODE_4K)
1744 offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1745 else if (ter_state->mode == FE_TER_MODE_8K)
1746 offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1747
1748 if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1749 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1750 (stv0367_readbits(state,
1751 F367TER_STATUS_INV_SPECRUM) == 1)))
1752 offset = offset * -1;
1753 }
1754
1755 if (ter_state->bw == 6)
1756 offset = (offset * 6) / 8;
1757 else if (ter_state->bw == 7)
1758 offset = (offset * 7) / 8;
1759
1760 ter_state->frequency += offset;
1761
1762 tempo = 10; /* exit even if timing_offset stays null */
1763 while ((timing_offset == 0) && (tempo > 0)) {
1764 usleep_range(10000, 20000); /*was 20ms */
1765 /* fine tuning of timing offset if required */
1766 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1767 + 256 * stv0367_readbits(state,
1768 F367TER_TRL_TOFFSET_HI);
1769 if (timing_offset >= 32768)
1770 timing_offset -= 65536;
1771 trl_nomrate = (512 * stv0367_readbits(state,
1772 F367TER_TRL_NOMRATE_HI)
1773 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1774 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1775
1776 timing_offset = ((signed)(1000000 / trl_nomrate) *
1777 timing_offset) / 2048;
1778 tempo--;
1779 }
1780
1781 if (timing_offset <= 0) {
1782 timing_offset = (timing_offset - 11) / 22;
1783 step = -1;
1784 } else {
1785 timing_offset = (timing_offset + 11) / 22;
1786 step = 1;
1787 }
1788
1789 for (counter = 0; counter < abs(timing_offset); counter++) {
1790 trl_nomrate += step;
1791 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1792 trl_nomrate % 2);
1793 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1794 trl_nomrate / 2);
1795 usleep_range(1000, 2000);
1796 }
1797
1798 usleep_range(5000, 6000);
1799 /* unlocks could happen in case of trl centring big step,
1800 then a core off/on restarts demod */
1801 u_var = stv0367_readbits(state, F367TER_LK);
1802
1803 if (!u_var) {
1804 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1805 msleep(20);
1806 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1807 }
1808
1809 return 0;
1810 }
1811
1812 static int stv0367ter_set_frontend(struct dvb_frontend *fe)
1813 {
1814 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1815 struct stv0367_state *state = fe->demodulator_priv;
1816 struct stv0367ter_state *ter_state = state->ter_state;
1817
1818 /*u8 trials[2]; */
1819 s8 num_trials, index;
1820 u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1821
1822 stv0367ter_init(fe);
1823
1824 if (fe->ops.tuner_ops.set_params) {
1825 if (fe->ops.i2c_gate_ctrl)
1826 fe->ops.i2c_gate_ctrl(fe, 1);
1827 fe->ops.tuner_ops.set_params(fe);
1828 if (fe->ops.i2c_gate_ctrl)
1829 fe->ops.i2c_gate_ctrl(fe, 0);
1830 }
1831
1832 switch (p->transmission_mode) {
1833 default:
1834 case TRANSMISSION_MODE_AUTO:
1835 case TRANSMISSION_MODE_2K:
1836 ter_state->mode = FE_TER_MODE_2K;
1837 break;
1838 /* case TRANSMISSION_MODE_4K:
1839 pLook.mode = FE_TER_MODE_4K;
1840 break;*/
1841 case TRANSMISSION_MODE_8K:
1842 ter_state->mode = FE_TER_MODE_8K;
1843 break;
1844 }
1845
1846 switch (p->guard_interval) {
1847 default:
1848 case GUARD_INTERVAL_1_32:
1849 case GUARD_INTERVAL_1_16:
1850 case GUARD_INTERVAL_1_8:
1851 case GUARD_INTERVAL_1_4:
1852 ter_state->guard = p->guard_interval;
1853 break;
1854 case GUARD_INTERVAL_AUTO:
1855 ter_state->guard = GUARD_INTERVAL_1_32;
1856 break;
1857 }
1858
1859 switch (p->bandwidth_hz) {
1860 case 6000000:
1861 ter_state->bw = FE_TER_CHAN_BW_6M;
1862 break;
1863 case 7000000:
1864 ter_state->bw = FE_TER_CHAN_BW_7M;
1865 break;
1866 case 8000000:
1867 default:
1868 ter_state->bw = FE_TER_CHAN_BW_8M;
1869 }
1870
1871 ter_state->hierarchy = FE_TER_HIER_NONE;
1872
1873 switch (p->inversion) {
1874 case INVERSION_OFF:
1875 case INVERSION_ON:
1876 num_trials = 1;
1877 break;
1878 default:
1879 num_trials = 2;
1880 if (ter_state->first_lock)
1881 num_trials = 1;
1882 break;
1883 }
1884
1885 ter_state->state = FE_TER_NOLOCK;
1886 index = 0;
1887
1888 while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1889 if (!ter_state->first_lock) {
1890 if (p->inversion == INVERSION_AUTO)
1891 ter_state->sense = SenseTrials[index];
1892
1893 }
1894 stv0367ter_algo(fe);
1895
1896 if ((ter_state->state == FE_TER_LOCKOK) &&
1897 (p->inversion == INVERSION_AUTO) &&
1898 (index == 1)) {
1899 /* invert spectrum sense */
1900 SenseTrials[index] = SenseTrials[0];
1901 SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1902 }
1903
1904 index++;
1905 }
1906
1907 return 0;
1908 }
1909
1910 static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1911 {
1912 struct stv0367_state *state = fe->demodulator_priv;
1913 struct stv0367ter_state *ter_state = state->ter_state;
1914 u32 errs = 0;
1915
1916 /*wait for counting completion*/
1917 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1918 errs =
1919 ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1920 * (1 << 16))
1921 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1922 * (1 << 8))
1923 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1924 ter_state->ucblocks = errs;
1925 }
1926
1927 (*ucblocks) = ter_state->ucblocks;
1928
1929 return 0;
1930 }
1931
1932 static int stv0367ter_get_frontend(struct dvb_frontend *fe)
1933 {
1934 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1935 struct stv0367_state *state = fe->demodulator_priv;
1936 struct stv0367ter_state *ter_state = state->ter_state;
1937 enum stv0367_ter_mode mode;
1938 int constell = 0,/* snr = 0,*/ Data = 0;
1939
1940 p->frequency = stv0367_get_tuner_freq(fe);
1941 if ((int)p->frequency < 0)
1942 p->frequency = -p->frequency;
1943
1944 constell = stv0367_readbits(state, F367TER_TPS_CONST);
1945 if (constell == 0)
1946 p->modulation = QPSK;
1947 else if (constell == 1)
1948 p->modulation = QAM_16;
1949 else
1950 p->modulation = QAM_64;
1951
1952 p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1953
1954 /* Get the Hierarchical mode */
1955 Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1956
1957 switch (Data) {
1958 case 0:
1959 p->hierarchy = HIERARCHY_NONE;
1960 break;
1961 case 1:
1962 p->hierarchy = HIERARCHY_1;
1963 break;
1964 case 2:
1965 p->hierarchy = HIERARCHY_2;
1966 break;
1967 case 3:
1968 p->hierarchy = HIERARCHY_4;
1969 break;
1970 default:
1971 p->hierarchy = HIERARCHY_AUTO;
1972 break; /* error */
1973 }
1974
1975 /* Get the FEC Rate */
1976 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1977 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1978 else
1979 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1980
1981 switch (Data) {
1982 case 0:
1983 p->code_rate_HP = FEC_1_2;
1984 break;
1985 case 1:
1986 p->code_rate_HP = FEC_2_3;
1987 break;
1988 case 2:
1989 p->code_rate_HP = FEC_3_4;
1990 break;
1991 case 3:
1992 p->code_rate_HP = FEC_5_6;
1993 break;
1994 case 4:
1995 p->code_rate_HP = FEC_7_8;
1996 break;
1997 default:
1998 p->code_rate_HP = FEC_AUTO;
1999 break; /* error */
2000 }
2001
2002 mode = stv0367_readbits(state, F367TER_SYR_MODE);
2003
2004 switch (mode) {
2005 case FE_TER_MODE_2K:
2006 p->transmission_mode = TRANSMISSION_MODE_2K;
2007 break;
2008 /* case FE_TER_MODE_4K:
2009 p->transmission_mode = TRANSMISSION_MODE_4K;
2010 break;*/
2011 case FE_TER_MODE_8K:
2012 p->transmission_mode = TRANSMISSION_MODE_8K;
2013 break;
2014 default:
2015 p->transmission_mode = TRANSMISSION_MODE_AUTO;
2016 }
2017
2018 p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
2019
2020 return 0;
2021 }
2022
2023 static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
2024 {
2025 struct stv0367_state *state = fe->demodulator_priv;
2026 u32 snru32 = 0;
2027 int cpt = 0;
2028 u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
2029
2030 while (cpt < 10) {
2031 usleep_range(2000, 3000);
2032 if (cut == 0x50) /*cut 1.0 cut 1.1*/
2033 snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
2034 else /*cu2.0*/
2035 snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
2036
2037 cpt++;
2038 }
2039
2040 snru32 /= 10;/*average on 10 values*/
2041
2042 *snr = snru32 / 1000;
2043
2044 return 0;
2045 }
2046
2047 #if 0
2048 static int stv0367ter_status(struct dvb_frontend *fe)
2049 {
2050
2051 struct stv0367_state *state = fe->demodulator_priv;
2052 struct stv0367ter_state *ter_state = state->ter_state;
2053 int locked = FALSE;
2054
2055 locked = (stv0367_readbits(state, F367TER_LK));
2056 if (!locked)
2057 ter_state->unlock_counter += 1;
2058 else
2059 ter_state->unlock_counter = 0;
2060
2061 if (ter_state->unlock_counter > 2) {
2062 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
2063 (!stv0367_readbits(state, F367TER_LK))) {
2064 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
2065 usleep_range(2000, 3000);
2066 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
2067 msleep(350);
2068 locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
2069 (stv0367_readbits(state, F367TER_LK));
2070 }
2071
2072 }
2073
2074 return locked;
2075 }
2076 #endif
2077 static int stv0367ter_read_status(struct dvb_frontend *fe, fe_status_t *status)
2078 {
2079 struct stv0367_state *state = fe->demodulator_priv;
2080
2081 dprintk("%s:\n", __func__);
2082
2083 *status = 0;
2084
2085 if (stv0367_readbits(state, F367TER_LK)) {
2086 *status |= FE_HAS_LOCK;
2087 dprintk("%s: stv0367 has locked\n", __func__);
2088 }
2089
2090 return 0;
2091 }
2092
2093 static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
2094 {
2095 struct stv0367_state *state = fe->demodulator_priv;
2096 struct stv0367ter_state *ter_state = state->ter_state;
2097 u32 Errors = 0, tber = 0, temporary = 0;
2098 int abc = 0, def = 0;
2099
2100
2101 /*wait for counting completion*/
2102 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
2103 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
2104 * (1 << 16))
2105 + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
2106 * (1 << 8))
2107 + ((u32)stv0367_readbits(state,
2108 F367TER_SFEC_ERR_CNT_LO));
2109 /*measurement not completed, load previous value*/
2110 else {
2111 tber = ter_state->pBER;
2112 return 0;
2113 }
2114
2115 abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
2116 def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
2117
2118 if (Errors == 0) {
2119 tber = 0;
2120 } else if (abc == 0x7) {
2121 if (Errors <= 4) {
2122 temporary = (Errors * 1000000000) / (8 * (1 << 14));
2123 temporary = temporary;
2124 } else if (Errors <= 42) {
2125 temporary = (Errors * 100000000) / (8 * (1 << 14));
2126 temporary = temporary * 10;
2127 } else if (Errors <= 429) {
2128 temporary = (Errors * 10000000) / (8 * (1 << 14));
2129 temporary = temporary * 100;
2130 } else if (Errors <= 4294) {
2131 temporary = (Errors * 1000000) / (8 * (1 << 14));
2132 temporary = temporary * 1000;
2133 } else if (Errors <= 42949) {
2134 temporary = (Errors * 100000) / (8 * (1 << 14));
2135 temporary = temporary * 10000;
2136 } else if (Errors <= 429496) {
2137 temporary = (Errors * 10000) / (8 * (1 << 14));
2138 temporary = temporary * 100000;
2139 } else { /*if (Errors<4294967) 2^22 max error*/
2140 temporary = (Errors * 1000) / (8 * (1 << 14));
2141 temporary = temporary * 100000; /* still to *10 */
2142 }
2143
2144 /* Byte error*/
2145 if (def == 2)
2146 /*tber=Errors/(8*(1 <<14));*/
2147 tber = temporary;
2148 else if (def == 3)
2149 /*tber=Errors/(8*(1 <<16));*/
2150 tber = temporary / 4;
2151 else if (def == 4)
2152 /*tber=Errors/(8*(1 <<18));*/
2153 tber = temporary / 16;
2154 else if (def == 5)
2155 /*tber=Errors/(8*(1 <<20));*/
2156 tber = temporary / 64;
2157 else if (def == 6)
2158 /*tber=Errors/(8*(1 <<22));*/
2159 tber = temporary / 256;
2160 else
2161 /* should not pass here*/
2162 tber = 0;
2163
2164 if ((Errors < 4294967) && (Errors > 429496))
2165 tber *= 10;
2166
2167 }
2168
2169 /* save actual value */
2170 ter_state->pBER = tber;
2171
2172 (*ber) = tber;
2173
2174 return 0;
2175 }
2176 #if 0
2177 static u32 stv0367ter_get_per(struct stv0367_state *state)
2178 {
2179 struct stv0367ter_state *ter_state = state->ter_state;
2180 u32 Errors = 0, Per = 0, temporary = 0;
2181 int abc = 0, def = 0, cpt = 0;
2182
2183 while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
2184 (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
2185 usleep_range(1000, 2000);
2186 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
2187 * (1 << 16))
2188 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
2189 * (1 << 8))
2190 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
2191 cpt++;
2192 }
2193 abc = stv0367_readbits(state, F367TER_ERR_SRC1);
2194 def = stv0367_readbits(state, F367TER_NUM_EVT1);
2195
2196 if (Errors == 0)
2197 Per = 0;
2198 else if (abc == 0x9) {
2199 if (Errors <= 4) {
2200 temporary = (Errors * 1000000000) / (8 * (1 << 8));
2201 temporary = temporary;
2202 } else if (Errors <= 42) {
2203 temporary = (Errors * 100000000) / (8 * (1 << 8));
2204 temporary = temporary * 10;
2205 } else if (Errors <= 429) {
2206 temporary = (Errors * 10000000) / (8 * (1 << 8));
2207 temporary = temporary * 100;
2208 } else if (Errors <= 4294) {
2209 temporary = (Errors * 1000000) / (8 * (1 << 8));
2210 temporary = temporary * 1000;
2211 } else if (Errors <= 42949) {
2212 temporary = (Errors * 100000) / (8 * (1 << 8));
2213 temporary = temporary * 10000;
2214 } else { /*if(Errors<=429496) 2^16 errors max*/
2215 temporary = (Errors * 10000) / (8 * (1 << 8));
2216 temporary = temporary * 100000;
2217 }
2218
2219 /* pkt error*/
2220 if (def == 2)
2221 /*Per=Errors/(1 << 8);*/
2222 Per = temporary;
2223 else if (def == 3)
2224 /*Per=Errors/(1 << 10);*/
2225 Per = temporary / 4;
2226 else if (def == 4)
2227 /*Per=Errors/(1 << 12);*/
2228 Per = temporary / 16;
2229 else if (def == 5)
2230 /*Per=Errors/(1 << 14);*/
2231 Per = temporary / 64;
2232 else if (def == 6)
2233 /*Per=Errors/(1 << 16);*/
2234 Per = temporary / 256;
2235 else
2236 Per = 0;
2237
2238 }
2239 /* save actual value */
2240 ter_state->pPER = Per;
2241
2242 return Per;
2243 }
2244 #endif
2245 static int stv0367_get_tune_settings(struct dvb_frontend *fe,
2246 struct dvb_frontend_tune_settings
2247 *fe_tune_settings)
2248 {
2249 fe_tune_settings->min_delay_ms = 1000;
2250 fe_tune_settings->step_size = 0;
2251 fe_tune_settings->max_drift = 0;
2252
2253 return 0;
2254 }
2255
2256 static void stv0367_release(struct dvb_frontend *fe)
2257 {
2258 struct stv0367_state *state = fe->demodulator_priv;
2259
2260 kfree(state->ter_state);
2261 kfree(state->cab_state);
2262 kfree(state);
2263 }
2264
2265 static struct dvb_frontend_ops stv0367ter_ops = {
2266 .delsys = { SYS_DVBT },
2267 .info = {
2268 .name = "ST STV0367 DVB-T",
2269 .frequency_min = 47000000,
2270 .frequency_max = 862000000,
2271 .frequency_stepsize = 15625,
2272 .frequency_tolerance = 0,
2273 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2274 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2275 FE_CAN_FEC_AUTO |
2276 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2277 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
2278 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
2279 FE_CAN_INVERSION_AUTO |
2280 FE_CAN_MUTE_TS
2281 },
2282 .release = stv0367_release,
2283 .init = stv0367ter_init,
2284 .sleep = stv0367ter_sleep,
2285 .i2c_gate_ctrl = stv0367ter_gate_ctrl,
2286 .set_frontend = stv0367ter_set_frontend,
2287 .get_frontend = stv0367ter_get_frontend,
2288 .get_tune_settings = stv0367_get_tune_settings,
2289 .read_status = stv0367ter_read_status,
2290 .read_ber = stv0367ter_read_ber,/* too slow */
2291 /* .read_signal_strength = stv0367_read_signal_strength,*/
2292 .read_snr = stv0367ter_read_snr,
2293 .read_ucblocks = stv0367ter_read_ucblocks,
2294 };
2295
2296 struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
2297 struct i2c_adapter *i2c)
2298 {
2299 struct stv0367_state *state = NULL;
2300 struct stv0367ter_state *ter_state = NULL;
2301
2302 /* allocate memory for the internal state */
2303 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2304 if (state == NULL)
2305 goto error;
2306 ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
2307 if (ter_state == NULL)
2308 goto error;
2309
2310 /* setup the state */
2311 state->i2c = i2c;
2312 state->config = config;
2313 state->ter_state = ter_state;
2314 state->fe.ops = stv0367ter_ops;
2315 state->fe.demodulator_priv = state;
2316 state->chip_id = stv0367_readreg(state, 0xf000);
2317
2318 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2319
2320 /* check if the demod is there */
2321 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2322 goto error;
2323
2324 return &state->fe;
2325
2326 error:
2327 kfree(ter_state);
2328 kfree(state);
2329 return NULL;
2330 }
2331 EXPORT_SYMBOL(stv0367ter_attach);
2332
2333 static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
2334 {
2335 struct stv0367_state *state = fe->demodulator_priv;
2336
2337 dprintk("%s:\n", __func__);
2338
2339 stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
2340
2341 return 0;
2342 }
2343
2344 static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
2345 {
2346 struct stv0367_state *state = fe->demodulator_priv;
2347 u32 mclk_Hz = 0;/* master clock frequency (Hz) */
2348 u32 M, N, P;
2349
2350
2351 if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
2352 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
2353 if (N == 0)
2354 N = N + 1;
2355
2356 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
2357 if (M == 0)
2358 M = M + 1;
2359
2360 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
2361
2362 if (P > 5)
2363 P = 5;
2364
2365 mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
2366 dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
2367 mclk_Hz);
2368 } else
2369 mclk_Hz = ExtClk_Hz;
2370
2371 dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
2372
2373 return mclk_Hz;
2374 }
2375
2376 static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
2377 {
2378 u32 ADCClk_Hz = ExtClk_Hz;
2379
2380 ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
2381
2382 return ADCClk_Hz;
2383 }
2384
2385 static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
2386 u32 SymbolRate,
2387 enum stv0367cab_mod QAMSize)
2388 {
2389 /* Set QAM size */
2390 stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
2391
2392 /* Set Registers settings specific to the QAM size */
2393 switch (QAMSize) {
2394 case FE_CAB_MOD_QAM4:
2395 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2396 break;
2397 case FE_CAB_MOD_QAM16:
2398 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
2399 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2400 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2401 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2402 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2403 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2404 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2405 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
2406 break;
2407 case FE_CAB_MOD_QAM32:
2408 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2409 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
2410 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2411 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2412 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
2413 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
2414 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2415 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2416 break;
2417 case FE_CAB_MOD_QAM64:
2418 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
2419 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2420 if (SymbolRate > 45000000) {
2421 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2422 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2423 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
2424 } else if (SymbolRate > 25000000) {
2425 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2426 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2427 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2428 } else {
2429 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2430 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2431 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2432 }
2433 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2434 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2435 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
2436 break;
2437 case FE_CAB_MOD_QAM128:
2438 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2439 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
2440 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2441 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
2442 if (SymbolRate > 45000000)
2443 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2444 else if (SymbolRate > 25000000)
2445 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2446 else
2447 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
2448
2449 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
2450 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2451 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2452 break;
2453 case FE_CAB_MOD_QAM256:
2454 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
2455 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2456 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2457 if (SymbolRate > 45000000)
2458 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2459 else if (SymbolRate > 25000000)
2460 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2461 else
2462 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2463
2464 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2465 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
2466 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2467 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2468 break;
2469 case FE_CAB_MOD_QAM512:
2470 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2471 break;
2472 case FE_CAB_MOD_QAM1024:
2473 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2474 break;
2475 default:
2476 break;
2477 }
2478
2479 return QAMSize;
2480 }
2481
2482 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
2483 u32 adc_hz, s32 derot_hz)
2484 {
2485 u32 sampled_if = 0;
2486 u32 adc_khz;
2487
2488 adc_khz = adc_hz / 1000;
2489
2490 dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
2491
2492 if (adc_khz != 0) {
2493 if (derot_hz < 1000000)
2494 derot_hz = adc_hz / 4; /* ZIF operation */
2495 if (derot_hz > adc_hz)
2496 derot_hz = derot_hz - adc_hz;
2497 sampled_if = (u32)derot_hz / 1000;
2498 sampled_if *= 32768;
2499 sampled_if /= adc_khz;
2500 sampled_if *= 256;
2501 }
2502
2503 if (sampled_if > 8388607)
2504 sampled_if = 8388607;
2505
2506 dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
2507
2508 stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
2509 stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
2510 stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
2511
2512 return derot_hz;
2513 }
2514
2515 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
2516 {
2517 u32 sampled_if;
2518
2519 sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
2520 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
2521 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
2522
2523 sampled_if /= 256;
2524 sampled_if *= (adc_hz / 1000);
2525 sampled_if += 1;
2526 sampled_if /= 32768;
2527
2528 return sampled_if;
2529 }
2530
2531 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
2532 u32 mclk_hz, u32 SymbolRate,
2533 enum stv0367cab_mod QAMSize)
2534 {
2535 u32 QamSizeCorr = 0;
2536 u32 u32_tmp = 0, u32_tmp1 = 0;
2537 u32 adp_khz;
2538
2539 dprintk("%s:\n", __func__);
2540
2541 /* Set Correction factor of SRC gain */
2542 switch (QAMSize) {
2543 case FE_CAB_MOD_QAM4:
2544 QamSizeCorr = 1110;
2545 break;
2546 case FE_CAB_MOD_QAM16:
2547 QamSizeCorr = 1032;
2548 break;
2549 case FE_CAB_MOD_QAM32:
2550 QamSizeCorr = 954;
2551 break;
2552 case FE_CAB_MOD_QAM64:
2553 QamSizeCorr = 983;
2554 break;
2555 case FE_CAB_MOD_QAM128:
2556 QamSizeCorr = 957;
2557 break;
2558 case FE_CAB_MOD_QAM256:
2559 QamSizeCorr = 948;
2560 break;
2561 case FE_CAB_MOD_QAM512:
2562 QamSizeCorr = 0;
2563 break;
2564 case FE_CAB_MOD_QAM1024:
2565 QamSizeCorr = 944;
2566 break;
2567 default:
2568 break;
2569 }
2570
2571 /* Transfer ratio calculation */
2572 if (adc_hz != 0) {
2573 u32_tmp = 256 * SymbolRate;
2574 u32_tmp = u32_tmp / adc_hz;
2575 }
2576 stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2577
2578 /* Symbol rate and SRC gain calculation */
2579 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2580 if (adp_khz != 0) {
2581 u32_tmp = SymbolRate;
2582 u32_tmp1 = SymbolRate;
2583
2584 if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2585 /* Symbol rate calculation */
2586 u32_tmp *= 2048; /* 2048 = 2^11 */
2587 u32_tmp = u32_tmp / adp_khz;
2588 u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2589 u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2590 u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2591
2592 /* SRC Gain Calculation */
2593 u32_tmp1 *= 2048; /* *2*2^10 */
2594 u32_tmp1 /= 439; /* *2/878 */
2595 u32_tmp1 *= 256; /* *2^8 */
2596 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2597 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2598 u32_tmp1 = u32_tmp1 / 10000000;
2599
2600 } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2601 /* Symbol rate calculation */
2602 u32_tmp *= 1024 ; /* 1024 = 2**10 */
2603 u32_tmp = u32_tmp / adp_khz;
2604 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2605 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2606 u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2607
2608 /* SRC Gain Calculation */
2609 u32_tmp1 *= 1024; /* *2*2^9 */
2610 u32_tmp1 /= 439; /* *2/878 */
2611 u32_tmp1 *= 256; /* *2^8 */
2612 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2613 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2614 u32_tmp1 = u32_tmp1 / 5000000;
2615 } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2616 /* Symbol rate calculation */
2617 u32_tmp *= 512 ; /* 512 = 2**9 */
2618 u32_tmp = u32_tmp / adp_khz;
2619 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2620 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2621 u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2622
2623 /* SRC Gain Calculation */
2624 u32_tmp1 *= 512; /* *2*2^8 */
2625 u32_tmp1 /= 439; /* *2/878 */
2626 u32_tmp1 *= 256; /* *2^8 */
2627 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2628 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2629 u32_tmp1 = u32_tmp1 / 2500000;
2630 } else {
2631 /* Symbol rate calculation */
2632 u32_tmp *= 256 ; /* 256 = 2**8 */
2633 u32_tmp = u32_tmp / adp_khz;
2634 u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2635 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2636 u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2637
2638 /* SRC Gain Calculation */
2639 u32_tmp1 *= 256; /* 2*2^7 */
2640 u32_tmp1 /= 439; /* *2/878 */
2641 u32_tmp1 *= 256; /* *2^8 */
2642 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2643 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2644 u32_tmp1 = u32_tmp1 / 1250000;
2645 }
2646 }
2647 #if 0
2648 /* Filters' coefficients are calculated and written
2649 into registers only if the filters are enabled */
2650 if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2651 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2652 SymbolRate);
2653 /* AllPass filter must be enabled
2654 when the adjacents filter is used */
2655 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2656 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2657 } else
2658 /* AllPass filter must be disabled
2659 when the adjacents filter is not used */
2660 #endif
2661 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2662
2663 stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2664 stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2665 stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2666 stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2667
2668 stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2669 stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2670
2671 return SymbolRate ;
2672 }
2673
2674 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2675 {
2676 u32 regsym;
2677 u32 adp_khz;
2678
2679 regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2680 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2681 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2682 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2683
2684 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2685
2686 if (regsym < 134217728) { /* 134217728L = 2**27*/
2687 regsym = regsym * 32; /* 32 = 2**5 */
2688 regsym = regsym / 32768; /* 32768L = 2**15 */
2689 regsym = adp_khz * regsym; /* AdpClk in kHz */
2690 regsym = regsym / 128; /* 128 = 2**7 */
2691 regsym *= 125 ; /* 125 = 1000/2**3 */
2692 regsym /= 2048 ; /* 2048 = 2**11 */
2693 } else if (regsym < 268435456) { /* 268435456L = 2**28 */
2694 regsym = regsym * 16; /* 16 = 2**4 */
2695 regsym = regsym / 32768; /* 32768L = 2**15 */
2696 regsym = adp_khz * regsym; /* AdpClk in kHz */
2697 regsym = regsym / 128; /* 128 = 2**7 */
2698 regsym *= 125 ; /* 125 = 1000/2**3*/
2699 regsym /= 1024 ; /* 256 = 2**10*/
2700 } else if (regsym < 536870912) { /* 536870912L = 2**29*/
2701 regsym = regsym * 8; /* 8 = 2**3 */
2702 regsym = regsym / 32768; /* 32768L = 2**15 */
2703 regsym = adp_khz * regsym; /* AdpClk in kHz */
2704 regsym = regsym / 128; /* 128 = 2**7 */
2705 regsym *= 125 ; /* 125 = 1000/2**3 */
2706 regsym /= 512 ; /* 128 = 2**9 */
2707 } else {
2708 regsym = regsym * 4; /* 4 = 2**2 */
2709 regsym = regsym / 32768; /* 32768L = 2**15 */
2710 regsym = adp_khz * regsym; /* AdpClk in kHz */
2711 regsym = regsym / 128; /* 128 = 2**7 */
2712 regsym *= 125 ; /* 125 = 1000/2**3 */
2713 regsym /= 256 ; /* 64 = 2**8 */
2714 }
2715
2716 return regsym;
2717 }
2718
2719 static int stv0367cab_read_status(struct dvb_frontend *fe, fe_status_t *status)
2720 {
2721 struct stv0367_state *state = fe->demodulator_priv;
2722
2723 dprintk("%s:\n", __func__);
2724
2725 *status = 0;
2726
2727 if (stv0367_readbits(state, F367CAB_QAMFEC_LOCK)) {
2728 *status |= FE_HAS_LOCK;
2729 dprintk("%s: stv0367 has locked\n", __func__);
2730 }
2731
2732 return 0;
2733 }
2734
2735 static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2736 {
2737 struct stv0367_state *state = fe->demodulator_priv;
2738
2739 dprintk("%s:\n", __func__);
2740
2741 if (standby_on) {
2742 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2743 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2744 stv0367_writebits(state, F367CAB_STDBY, 1);
2745 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2746 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2747 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2748 stv0367_writebits(state, F367CAB_POFFQ, 1);
2749 stv0367_writebits(state, F367CAB_POFFI, 1);
2750 } else {
2751 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2752 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2753 stv0367_writebits(state, F367CAB_STDBY, 0);
2754 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2755 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2756 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2757 stv0367_writebits(state, F367CAB_POFFQ, 0);
2758 stv0367_writebits(state, F367CAB_POFFI, 0);
2759 }
2760
2761 return 0;
2762 }
2763
2764 static int stv0367cab_sleep(struct dvb_frontend *fe)
2765 {
2766 return stv0367cab_standby(fe, 1);
2767 }
2768
2769 static int stv0367cab_init(struct dvb_frontend *fe)
2770 {
2771 struct stv0367_state *state = fe->demodulator_priv;
2772 struct stv0367cab_state *cab_state = state->cab_state;
2773 int i;
2774
2775 dprintk("%s:\n", __func__);
2776
2777 for (i = 0; i < STV0367CAB_NBREGS; i++)
2778 stv0367_writereg(state, def0367cab[i].addr,
2779 def0367cab[i].value);
2780
2781 switch (state->config->ts_mode) {
2782 case STV0367_DVBCI_CLOCK:
2783 dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2784 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2785 break;
2786 case STV0367_SERIAL_PUNCT_CLOCK:
2787 case STV0367_SERIAL_CONT_CLOCK:
2788 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2789 break;
2790 case STV0367_PARALLEL_PUNCT_CLOCK:
2791 case STV0367_OUTPUTMODE_DEFAULT:
2792 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2793 break;
2794 }
2795
2796 switch (state->config->clk_pol) {
2797 case STV0367_RISINGEDGE_CLOCK:
2798 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2799 break;
2800 case STV0367_FALLINGEDGE_CLOCK:
2801 case STV0367_CLOCKPOLARITY_DEFAULT:
2802 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2803 break;
2804 }
2805
2806 stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2807
2808 stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2809
2810 stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2811
2812 stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2813
2814 stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2815
2816 cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2817 cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2818
2819 return 0;
2820 }
2821 static
2822 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2823 struct dtv_frontend_properties *p)
2824 {
2825 struct stv0367cab_state *cab_state = state->cab_state;
2826 enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2827 u32 QAMFEC_Lock, QAM_Lock, u32_tmp,
2828 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2829 CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2830 u8 TrackAGCAccum;
2831 s32 tmp;
2832
2833 dprintk("%s:\n", __func__);
2834
2835 /* Timeouts calculation */
2836 /* A max lock time of 25 ms is allowed for delayed AGC */
2837 AGCTimeOut = 25;
2838 /* 100000 symbols needed by the TRL as a maximum value */
2839 TRLTimeOut = 100000000 / p->symbol_rate;
2840 /* CRLSymbols is the needed number of symbols to achieve a lock
2841 within [-4%, +4%] of the symbol rate.
2842 CRL timeout is calculated
2843 for a lock within [-search_range, +search_range].
2844 EQL timeout can be changed depending on
2845 the micro-reflections we want to handle.
2846 A characterization must be performed
2847 with these echoes to get new timeout values.
2848 */
2849 switch (p->modulation) {
2850 case QAM_16:
2851 CRLSymbols = 150000;
2852 EQLTimeOut = 100;
2853 break;
2854 case QAM_32:
2855 CRLSymbols = 250000;
2856 EQLTimeOut = 100;
2857 break;
2858 case QAM_64:
2859 CRLSymbols = 200000;
2860 EQLTimeOut = 100;
2861 break;
2862 case QAM_128:
2863 CRLSymbols = 250000;
2864 EQLTimeOut = 100;
2865 break;
2866 case QAM_256:
2867 CRLSymbols = 250000;
2868 EQLTimeOut = 100;
2869 break;
2870 default:
2871 CRLSymbols = 200000;
2872 EQLTimeOut = 100;
2873 break;
2874 }
2875 #if 0
2876 if (pIntParams->search_range < 0) {
2877 CRLTimeOut = (25 * CRLSymbols *
2878 (-pIntParams->search_range / 1000)) /
2879 (pIntParams->symbol_rate / 1000);
2880 } else
2881 #endif
2882 CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2883 (p->symbol_rate / 1000);
2884
2885 CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
2886 /* Timeouts below 50ms are coerced */
2887 if (CRLTimeOut < 50)
2888 CRLTimeOut = 50;
2889 /* A maximum of 100 TS packets is needed to get FEC lock even in case
2890 the spectrum inversion needs to be changed.
2891 This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2892 */
2893 FECTimeOut = 20;
2894 DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2895
2896 dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2897
2898 /* Reset the TRL to ensure nothing starts until the
2899 AGC is stable which ensures a better lock time
2900 */
2901 stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2902 /* Set AGC accumulation time to minimum and lock threshold to maximum
2903 in order to speed up the AGC lock */
2904 TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2905 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2906 /* Modulus Mapper is disabled */
2907 stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2908 /* Disable the sweep function */
2909 stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2910 /* The sweep function is never used, Sweep rate must be set to 0 */
2911 /* Set the derotator frequency in Hz */
2912 stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2913 (1000 * (s32)state->config->if_khz + cab_state->derot_offset));
2914 /* Disable the Allpass Filter when the symbol rate is out of range */
2915 if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
2916 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2917 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2918 }
2919 #if 0
2920 /* Check if the tuner is locked */
2921 tuner_lock = stv0367cab_tuner_get_status(fe);
2922 if (tuner_lock == 0)
2923 return FE_367CAB_NOTUNER;
2924 #endif
2925 /* Release the TRL to start demodulator acquisition */
2926 /* Wait for QAM lock */
2927 LockTime = 0;
2928 stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2929 do {
2930 QAM_Lock = stv0367_readbits(state, F367CAB_FSM_STATUS);
2931 if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2932 (QAM_Lock == 0x04))
2933 /*
2934 * We don't wait longer, the frequency/phase offset
2935 * must be too big
2936 */
2937 LockTime = DemodTimeOut;
2938 else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2939 (QAM_Lock == 0x02))
2940 /*
2941 * We don't wait longer, either there is no signal or
2942 * it is not the right symbol rate or it is an analog
2943 * carrier
2944 */
2945 {
2946 LockTime = DemodTimeOut;
2947 u32_tmp = stv0367_readbits(state,
2948 F367CAB_AGC_PWR_WORD_LO) +
2949 (stv0367_readbits(state,
2950 F367CAB_AGC_PWR_WORD_ME) << 8) +
2951 (stv0367_readbits(state,
2952 F367CAB_AGC_PWR_WORD_HI) << 16);
2953 if (u32_tmp >= 131072)
2954 u32_tmp = 262144 - u32_tmp;
2955 u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2956 F367CAB_AGC_IF_BWSEL)));
2957
2958 if (u32_tmp < stv0367_readbits(state,
2959 F367CAB_AGC_PWRREF_LO) +
2960 256 * stv0367_readbits(state,
2961 F367CAB_AGC_PWRREF_HI) - 10)
2962 QAM_Lock = 0x0f;
2963 } else {
2964 usleep_range(10000, 20000);
2965 LockTime += 10;
2966 }
2967 dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2968 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2969
2970 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2971
2972 } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2973 (LockTime < DemodTimeOut));
2974
2975 dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2976
2977 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2978 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2979 tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2980 dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2981
2982 tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2983 dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2984
2985 if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2986 /* Wait for FEC lock */
2987 LockTime = 0;
2988 do {
2989 usleep_range(5000, 7000);
2990 LockTime += 5;
2991 QAMFEC_Lock = stv0367_readbits(state,
2992 F367CAB_QAMFEC_LOCK);
2993 } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
2994 } else
2995 QAMFEC_Lock = 0;
2996
2997 if (QAMFEC_Lock) {
2998 signalType = FE_CAB_DATAOK;
2999 cab_state->spect_inv = stv0367_readbits(state,
3000 F367CAB_QUAD_INV);
3001 #if 0
3002 /* not clear for me */
3003 if (state->config->if_khz != 0) {
3004 if (state->config->if_khz > cab_state->adc_clk / 1000) {
3005 cab_state->freq_khz =
3006 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3007 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3008 - cab_state->adc_clk / 1000 + state->config->if_khz;
3009 } else {
3010 cab_state->freq_khz =
3011 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3012 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3013 + state->config->if_khz;
3014 }
3015 } else {
3016 cab_state->freq_khz =
3017 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
3018 stv0367cab_get_derot_freq(state,
3019 cab_state->adc_clk) -
3020 cab_state->adc_clk / 4000;
3021 }
3022 #endif
3023 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
3024 cab_state->mclk);
3025 cab_state->locked = 1;
3026
3027 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
3028 } else {
3029 switch (QAM_Lock) {
3030 case 1:
3031 signalType = FE_CAB_NOAGC;
3032 break;
3033 case 2:
3034 signalType = FE_CAB_NOTIMING;
3035 break;
3036 case 3:
3037 signalType = FE_CAB_TIMINGOK;
3038 break;
3039 case 4:
3040 signalType = FE_CAB_NOCARRIER;
3041 break;
3042 case 5:
3043 signalType = FE_CAB_CARRIEROK;
3044 break;
3045 case 7:
3046 signalType = FE_CAB_NOBLIND;
3047 break;
3048 case 8:
3049 signalType = FE_CAB_BLINDOK;
3050 break;
3051 case 10:
3052 signalType = FE_CAB_NODEMOD;
3053 break;
3054 case 11:
3055 signalType = FE_CAB_DEMODOK;
3056 break;
3057 case 12:
3058 signalType = FE_CAB_DEMODOK;
3059 break;
3060 case 13:
3061 signalType = FE_CAB_NODEMOD;
3062 break;
3063 case 14:
3064 signalType = FE_CAB_NOBLIND;
3065 break;
3066 case 15:
3067 signalType = FE_CAB_NOSIGNAL;
3068 break;
3069 default:
3070 break;
3071 }
3072
3073 }
3074
3075 /* Set the AGC control values to tracking values */
3076 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
3077 return signalType;
3078 }
3079
3080 static int stv0367cab_set_frontend(struct dvb_frontend *fe)
3081 {
3082 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3083 struct stv0367_state *state = fe->demodulator_priv;
3084 struct stv0367cab_state *cab_state = state->cab_state;
3085 enum stv0367cab_mod QAMSize = 0;
3086
3087 dprintk("%s: freq = %d, srate = %d\n", __func__,
3088 p->frequency, p->symbol_rate);
3089
3090 cab_state->derot_offset = 0;
3091
3092 switch (p->modulation) {
3093 case QAM_16:
3094 QAMSize = FE_CAB_MOD_QAM16;
3095 break;
3096 case QAM_32:
3097 QAMSize = FE_CAB_MOD_QAM32;
3098 break;
3099 case QAM_64:
3100 QAMSize = FE_CAB_MOD_QAM64;
3101 break;
3102 case QAM_128:
3103 QAMSize = FE_CAB_MOD_QAM128;
3104 break;
3105 case QAM_256:
3106 QAMSize = FE_CAB_MOD_QAM256;
3107 break;
3108 default:
3109 break;
3110 }
3111
3112 stv0367cab_init(fe);
3113
3114 /* Tuner Frequency Setting */
3115 if (fe->ops.tuner_ops.set_params) {
3116 if (fe->ops.i2c_gate_ctrl)
3117 fe->ops.i2c_gate_ctrl(fe, 1);
3118 fe->ops.tuner_ops.set_params(fe);
3119 if (fe->ops.i2c_gate_ctrl)
3120 fe->ops.i2c_gate_ctrl(fe, 0);
3121 }
3122
3123 stv0367cab_SetQamSize(
3124 state,
3125 p->symbol_rate,
3126 QAMSize);
3127
3128 stv0367cab_set_srate(state,
3129 cab_state->adc_clk,
3130 cab_state->mclk,
3131 p->symbol_rate,
3132 QAMSize);
3133 /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
3134 cab_state->state = stv0367cab_algo(state, p);
3135 return 0;
3136 }
3137
3138 static int stv0367cab_get_frontend(struct dvb_frontend *fe)
3139 {
3140 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3141 struct stv0367_state *state = fe->demodulator_priv;
3142 struct stv0367cab_state *cab_state = state->cab_state;
3143
3144 enum stv0367cab_mod QAMSize;
3145
3146 dprintk("%s:\n", __func__);
3147
3148 p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
3149
3150 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3151 switch (QAMSize) {
3152 case FE_CAB_MOD_QAM16:
3153 p->modulation = QAM_16;
3154 break;
3155 case FE_CAB_MOD_QAM32:
3156 p->modulation = QAM_32;
3157 break;
3158 case FE_CAB_MOD_QAM64:
3159 p->modulation = QAM_64;
3160 break;
3161 case FE_CAB_MOD_QAM128:
3162 p->modulation = QAM_128;
3163 break;
3164 case FE_CAB_MOD_QAM256:
3165 p->modulation = QAM_256;
3166 break;
3167 default:
3168 break;
3169 }
3170
3171 p->frequency = stv0367_get_tuner_freq(fe);
3172
3173 dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
3174
3175 if (state->config->if_khz == 0) {
3176 p->frequency +=
3177 (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
3178 cab_state->adc_clk / 4000);
3179 return 0;
3180 }
3181
3182 if (state->config->if_khz > cab_state->adc_clk / 1000)
3183 p->frequency += (state->config->if_khz
3184 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3185 - cab_state->adc_clk / 1000);
3186 else
3187 p->frequency += (state->config->if_khz
3188 - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
3189
3190 return 0;
3191 }
3192
3193 #if 0
3194 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
3195 u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
3196 {
3197 stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
3198 stv0367cab_GetPacketsCount(state, Monitor_results);
3199
3200 return;
3201 }
3202
3203 static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
3204 {
3205 struct stv0367_state *state = fe->demodulator_priv;
3206
3207 return 0;
3208 }
3209 #endif
3210 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
3211 {
3212 s32 rfLevel = 0;
3213 s32 RfAgcPwm = 0, IfAgcPwm = 0;
3214 u8 i;
3215
3216 stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
3217
3218 RfAgcPwm =
3219 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
3220 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
3221 RfAgcPwm = 100 * RfAgcPwm / 1023;
3222
3223 IfAgcPwm =
3224 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
3225 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
3226 if (IfAgcPwm >= 2048)
3227 IfAgcPwm -= 2048;
3228 else
3229 IfAgcPwm += 2048;
3230
3231 IfAgcPwm = 100 * IfAgcPwm / 4095;
3232
3233 /* For DTT75467 on NIM */
3234 if (RfAgcPwm < 90 && IfAgcPwm < 28) {
3235 for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
3236 if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
3237 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
3238 break;
3239 }
3240 }
3241 if (i == RF_LOOKUP_TABLE_SIZE)
3242 rfLevel = -56;
3243 } else { /*if IF AGC>10*/
3244 for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
3245 if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
3246 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
3247 break;
3248 }
3249 }
3250 if (i == RF_LOOKUP_TABLE2_SIZE)
3251 rfLevel = -72;
3252 }
3253 return rfLevel;
3254 }
3255
3256 static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
3257 {
3258 struct stv0367_state *state = fe->demodulator_priv;
3259
3260 s32 signal = stv0367cab_get_rf_lvl(state);
3261
3262 dprintk("%s: signal=%d dBm\n", __func__, signal);
3263
3264 if (signal <= -72)
3265 *strength = 65535;
3266 else
3267 *strength = (22 + signal) * (-1311);
3268
3269 dprintk("%s: strength=%d\n", __func__, (*strength));
3270
3271 return 0;
3272 }
3273
3274 static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
3275 {
3276 struct stv0367_state *state = fe->demodulator_priv;
3277 u32 noisepercentage;
3278 enum stv0367cab_mod QAMSize;
3279 u32 regval = 0, temp = 0;
3280 int power, i;
3281
3282 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3283 switch (QAMSize) {
3284 case FE_CAB_MOD_QAM4:
3285 power = 21904;
3286 break;
3287 case FE_CAB_MOD_QAM16:
3288 power = 20480;
3289 break;
3290 case FE_CAB_MOD_QAM32:
3291 power = 23040;
3292 break;
3293 case FE_CAB_MOD_QAM64:
3294 power = 21504;
3295 break;
3296 case FE_CAB_MOD_QAM128:
3297 power = 23616;
3298 break;
3299 case FE_CAB_MOD_QAM256:
3300 power = 21760;
3301 break;
3302 case FE_CAB_MOD_QAM512:
3303 power = 1;
3304 break;
3305 case FE_CAB_MOD_QAM1024:
3306 power = 21280;
3307 break;
3308 default:
3309 power = 1;
3310 break;
3311 }
3312
3313 for (i = 0; i < 10; i++) {
3314 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
3315 + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
3316 }
3317
3318 regval /= 10; /*for average over 10 times in for loop above*/
3319 if (regval != 0) {
3320 temp = power
3321 * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
3322 temp /= regval;
3323 }
3324
3325 /* table values, not needed to calculate logarithms */
3326 if (temp >= 5012)
3327 noisepercentage = 100;
3328 else if (temp >= 3981)
3329 noisepercentage = 93;
3330 else if (temp >= 3162)
3331 noisepercentage = 86;
3332 else if (temp >= 2512)
3333 noisepercentage = 79;
3334 else if (temp >= 1995)
3335 noisepercentage = 72;
3336 else if (temp >= 1585)
3337 noisepercentage = 65;
3338 else if (temp >= 1259)
3339 noisepercentage = 58;
3340 else if (temp >= 1000)
3341 noisepercentage = 50;
3342 else if (temp >= 794)
3343 noisepercentage = 43;
3344 else if (temp >= 501)
3345 noisepercentage = 36;
3346 else if (temp >= 316)
3347 noisepercentage = 29;
3348 else if (temp >= 200)
3349 noisepercentage = 22;
3350 else if (temp >= 158)
3351 noisepercentage = 14;
3352 else if (temp >= 126)
3353 noisepercentage = 7;
3354 else
3355 noisepercentage = 0;
3356
3357 dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
3358
3359 *snr = (noisepercentage * 65535) / 100;
3360
3361 return 0;
3362 }
3363
3364 static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
3365 {
3366 struct stv0367_state *state = fe->demodulator_priv;
3367 int corrected, tscount;
3368
3369 *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
3370 | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
3371 corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
3372 | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
3373 tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
3374 | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
3375
3376 dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
3377 __func__, *ucblocks, corrected, tscount);
3378
3379 return 0;
3380 };
3381
3382 static struct dvb_frontend_ops stv0367cab_ops = {
3383 .delsys = { SYS_DVBC_ANNEX_A },
3384 .info = {
3385 .name = "ST STV0367 DVB-C",
3386 .frequency_min = 47000000,
3387 .frequency_max = 862000000,
3388 .frequency_stepsize = 62500,
3389 .symbol_rate_min = 870000,
3390 .symbol_rate_max = 11700000,
3391 .caps = 0x400 |/* FE_CAN_QAM_4 */
3392 FE_CAN_QAM_16 | FE_CAN_QAM_32 |
3393 FE_CAN_QAM_64 | FE_CAN_QAM_128 |
3394 FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
3395 },
3396 .release = stv0367_release,
3397 .init = stv0367cab_init,
3398 .sleep = stv0367cab_sleep,
3399 .i2c_gate_ctrl = stv0367cab_gate_ctrl,
3400 .set_frontend = stv0367cab_set_frontend,
3401 .get_frontend = stv0367cab_get_frontend,
3402 .read_status = stv0367cab_read_status,
3403 /* .read_ber = stv0367cab_read_ber, */
3404 .read_signal_strength = stv0367cab_read_strength,
3405 .read_snr = stv0367cab_read_snr,
3406 .read_ucblocks = stv0367cab_read_ucblcks,
3407 .get_tune_settings = stv0367_get_tune_settings,
3408 };
3409
3410 struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
3411 struct i2c_adapter *i2c)
3412 {
3413 struct stv0367_state *state = NULL;
3414 struct stv0367cab_state *cab_state = NULL;
3415
3416 /* allocate memory for the internal state */
3417 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3418 if (state == NULL)
3419 goto error;
3420 cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3421 if (cab_state == NULL)
3422 goto error;
3423
3424 /* setup the state */
3425 state->i2c = i2c;
3426 state->config = config;
3427 cab_state->search_range = 280000;
3428 state->cab_state = cab_state;
3429 state->fe.ops = stv0367cab_ops;
3430 state->fe.demodulator_priv = state;
3431 state->chip_id = stv0367_readreg(state, 0xf000);
3432
3433 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3434
3435 /* check if the demod is there */
3436 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3437 goto error;
3438
3439 return &state->fe;
3440
3441 error:
3442 kfree(cab_state);
3443 kfree(state);
3444 return NULL;
3445 }
3446 EXPORT_SYMBOL(stv0367cab_attach);
3447
3448 MODULE_PARM_DESC(debug, "Set debug");
3449 MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3450
3451 MODULE_AUTHOR("Igor M. Liplianin");
3452 MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3453 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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