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Merge remote-tracking branch 'regulator/topic/tps65910' into regulator-next
[deliverable/linux.git] / drivers / media / i2c / adv7842.c
1 /*
2 * adv7842 - Analog Devices ADV7842 video decoder driver
3 *
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21 /*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7842, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 */
28
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/slab.h>
33 #include <linux/i2c.h>
34 #include <linux/delay.h>
35 #include <linux/videodev2.h>
36 #include <linux/workqueue.h>
37 #include <linux/v4l2-dv-timings.h>
38 #include <media/v4l2-device.h>
39 #include <media/v4l2-ctrls.h>
40 #include <media/v4l2-dv-timings.h>
41 #include <media/adv7842.h>
42
43 static int debug;
44 module_param(debug, int, 0644);
45 MODULE_PARM_DESC(debug, "debug level (0-2)");
46
47 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
48 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
49 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
50 MODULE_LICENSE("GPL");
51
52 /* ADV7842 system clock frequency */
53 #define ADV7842_fsc (28636360)
54
55 /*
56 **********************************************************************
57 *
58 * Arrays with configuration parameters for the ADV7842
59 *
60 **********************************************************************
61 */
62
63 struct adv7842_state {
64 struct v4l2_subdev sd;
65 struct media_pad pad;
66 struct v4l2_ctrl_handler hdl;
67 enum adv7842_mode mode;
68 struct v4l2_dv_timings timings;
69 enum adv7842_vid_std_select vid_std_select;
70 v4l2_std_id norm;
71 struct {
72 u8 edid[256];
73 u32 present;
74 } hdmi_edid;
75 struct {
76 u8 edid[256];
77 u32 present;
78 } vga_edid;
79 struct v4l2_fract aspect_ratio;
80 u32 rgb_quantization_range;
81 bool is_cea_format;
82 struct workqueue_struct *work_queues;
83 struct delayed_work delayed_work_enable_hotplug;
84 bool connector_hdmi;
85 bool hdmi_port_a;
86
87 /* i2c clients */
88 struct i2c_client *i2c_sdp_io;
89 struct i2c_client *i2c_sdp;
90 struct i2c_client *i2c_cp;
91 struct i2c_client *i2c_vdp;
92 struct i2c_client *i2c_afe;
93 struct i2c_client *i2c_hdmi;
94 struct i2c_client *i2c_repeater;
95 struct i2c_client *i2c_edid;
96 struct i2c_client *i2c_infoframe;
97 struct i2c_client *i2c_cec;
98 struct i2c_client *i2c_avlink;
99
100 /* controls */
101 struct v4l2_ctrl *detect_tx_5v_ctrl;
102 struct v4l2_ctrl *analog_sampling_phase_ctrl;
103 struct v4l2_ctrl *free_run_color_ctrl_manual;
104 struct v4l2_ctrl *free_run_color_ctrl;
105 struct v4l2_ctrl *rgb_quantization_range_ctrl;
106 };
107
108 /* Unsupported timings. This device cannot support 720p30. */
109 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
110 V4L2_DV_BT_CEA_1280X720P30,
111 { }
112 };
113
114 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
115 {
116 int i;
117
118 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
119 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0))
120 return false;
121 return true;
122 }
123
124 struct adv7842_video_standards {
125 struct v4l2_dv_timings timings;
126 u8 vid_std;
127 u8 v_freq;
128 };
129
130 /* sorted by number of lines */
131 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
132 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
133 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
134 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
135 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
136 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
137 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
138 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
139 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
140 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
141 /* TODO add 1920x1080P60_RB (CVT timing) */
142 { },
143 };
144
145 /* sorted by number of lines */
146 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
147 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
148 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
149 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
150 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
151 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
152 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
153 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
154 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
155 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
156 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
157 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
158 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
159 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
160 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
161 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
162 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
163 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
164 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
165 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
166 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
167 /* TODO add 1600X1200P60_RB (not a DMT timing) */
168 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
169 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
170 { },
171 };
172
173 /* sorted by number of lines */
174 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
175 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
176 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
177 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
178 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
179 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
180 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
181 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
182 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
183 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
184 { },
185 };
186
187 /* sorted by number of lines */
188 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
189 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
190 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
191 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
192 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
193 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
194 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
195 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
198 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
199 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
200 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
202 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
203 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
204 { },
205 };
206
207 /* ----------------------------------------------------------------------- */
208
209 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
210 {
211 return container_of(sd, struct adv7842_state, sd);
212 }
213
214 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
215 {
216 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
217 }
218
219 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
220 {
221 return V4L2_DV_BT_BLANKING_WIDTH(t);
222 }
223
224 static inline unsigned htotal(const struct v4l2_bt_timings *t)
225 {
226 return V4L2_DV_BT_FRAME_WIDTH(t);
227 }
228
229 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
230 {
231 return V4L2_DV_BT_BLANKING_HEIGHT(t);
232 }
233
234 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
235 {
236 return V4L2_DV_BT_FRAME_HEIGHT(t);
237 }
238
239
240 /* ----------------------------------------------------------------------- */
241
242 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
243 u8 command, bool check)
244 {
245 union i2c_smbus_data data;
246
247 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
248 I2C_SMBUS_READ, command,
249 I2C_SMBUS_BYTE_DATA, &data))
250 return data.byte;
251 if (check)
252 v4l_err(client, "error reading %02x, %02x\n",
253 client->addr, command);
254 return -EIO;
255 }
256
257 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
258 {
259 int i;
260
261 for (i = 0; i < 3; i++) {
262 int ret = adv_smbus_read_byte_data_check(client, command, true);
263
264 if (ret >= 0) {
265 if (i)
266 v4l_err(client, "read ok after %d retries\n", i);
267 return ret;
268 }
269 }
270 v4l_err(client, "read failed\n");
271 return -EIO;
272 }
273
274 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
275 u8 command, u8 value)
276 {
277 union i2c_smbus_data data;
278 int err;
279 int i;
280
281 data.byte = value;
282 for (i = 0; i < 3; i++) {
283 err = i2c_smbus_xfer(client->adapter, client->addr,
284 client->flags,
285 I2C_SMBUS_WRITE, command,
286 I2C_SMBUS_BYTE_DATA, &data);
287 if (!err)
288 break;
289 }
290 if (err < 0)
291 v4l_err(client, "error writing %02x, %02x, %02x\n",
292 client->addr, command, value);
293 return err;
294 }
295
296 static void adv_smbus_write_byte_no_check(struct i2c_client *client,
297 u8 command, u8 value)
298 {
299 union i2c_smbus_data data;
300 data.byte = value;
301
302 i2c_smbus_xfer(client->adapter, client->addr,
303 client->flags,
304 I2C_SMBUS_WRITE, command,
305 I2C_SMBUS_BYTE_DATA, &data);
306 }
307
308 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
309 u8 command, unsigned length, const u8 *values)
310 {
311 union i2c_smbus_data data;
312
313 if (length > I2C_SMBUS_BLOCK_MAX)
314 length = I2C_SMBUS_BLOCK_MAX;
315 data.block[0] = length;
316 memcpy(data.block + 1, values, length);
317 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
318 I2C_SMBUS_WRITE, command,
319 I2C_SMBUS_I2C_BLOCK_DATA, &data);
320 }
321
322 /* ----------------------------------------------------------------------- */
323
324 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
325 {
326 struct i2c_client *client = v4l2_get_subdevdata(sd);
327
328 return adv_smbus_read_byte_data(client, reg);
329 }
330
331 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
332 {
333 struct i2c_client *client = v4l2_get_subdevdata(sd);
334
335 return adv_smbus_write_byte_data(client, reg, val);
336 }
337
338 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
339 {
340 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
341 }
342
343 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
344 {
345 struct adv7842_state *state = to_state(sd);
346
347 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
348 }
349
350 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
351 {
352 struct adv7842_state *state = to_state(sd);
353
354 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
355 }
356
357 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
358 {
359 struct adv7842_state *state = to_state(sd);
360
361 return adv_smbus_read_byte_data(state->i2c_cec, reg);
362 }
363
364 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
365 {
366 struct adv7842_state *state = to_state(sd);
367
368 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
369 }
370
371 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
372 {
373 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
374 }
375
376 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
377 {
378 struct adv7842_state *state = to_state(sd);
379
380 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
381 }
382
383 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
384 {
385 struct adv7842_state *state = to_state(sd);
386
387 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
388 }
389
390 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
391 {
392 struct adv7842_state *state = to_state(sd);
393
394 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
395 }
396
397 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
398 {
399 struct adv7842_state *state = to_state(sd);
400
401 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
402 }
403
404 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
405 {
406 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
407 }
408
409 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
410 {
411 struct adv7842_state *state = to_state(sd);
412
413 return adv_smbus_read_byte_data(state->i2c_sdp, reg);
414 }
415
416 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
417 {
418 struct adv7842_state *state = to_state(sd);
419
420 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
421 }
422
423 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
424 {
425 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
426 }
427
428 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
429 {
430 struct adv7842_state *state = to_state(sd);
431
432 return adv_smbus_read_byte_data(state->i2c_afe, reg);
433 }
434
435 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
436 {
437 struct adv7842_state *state = to_state(sd);
438
439 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
440 }
441
442 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
443 {
444 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
445 }
446
447 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
448 {
449 struct adv7842_state *state = to_state(sd);
450
451 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
452 }
453
454 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
455 {
456 struct adv7842_state *state = to_state(sd);
457
458 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
459 }
460
461 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
462 {
463 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
464 }
465
466 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
467 {
468 struct adv7842_state *state = to_state(sd);
469
470 return adv_smbus_read_byte_data(state->i2c_edid, reg);
471 }
472
473 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
474 {
475 struct adv7842_state *state = to_state(sd);
476
477 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
478 }
479
480 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
481 {
482 struct adv7842_state *state = to_state(sd);
483
484 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
485 }
486
487 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
488 {
489 struct adv7842_state *state = to_state(sd);
490
491 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
492 }
493
494 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
495 {
496 struct adv7842_state *state = to_state(sd);
497
498 return adv_smbus_read_byte_data(state->i2c_cp, reg);
499 }
500
501 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
502 {
503 struct adv7842_state *state = to_state(sd);
504
505 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
506 }
507
508 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
509 {
510 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
511 }
512
513 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
514 {
515 struct adv7842_state *state = to_state(sd);
516
517 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
518 }
519
520 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
521 {
522 struct adv7842_state *state = to_state(sd);
523
524 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
525 }
526
527 static void main_reset(struct v4l2_subdev *sd)
528 {
529 struct i2c_client *client = v4l2_get_subdevdata(sd);
530
531 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
532
533 adv_smbus_write_byte_no_check(client, 0xff, 0x80);
534
535 mdelay(2);
536 }
537
538 /* ----------------------------------------------------------------------- */
539
540 static inline bool is_digital_input(struct v4l2_subdev *sd)
541 {
542 struct adv7842_state *state = to_state(sd);
543
544 return state->mode == ADV7842_MODE_HDMI;
545 }
546
547 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
548 .type = V4L2_DV_BT_656_1120,
549 .bt = {
550 .max_width = 1920,
551 .max_height = 1200,
552 .min_pixelclock = 25000000,
553 .max_pixelclock = 170000000,
554 .standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
555 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
556 .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
557 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM,
558 },
559 };
560
561 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
562 .type = V4L2_DV_BT_656_1120,
563 .bt = {
564 .max_width = 1920,
565 .max_height = 1200,
566 .min_pixelclock = 25000000,
567 .max_pixelclock = 225000000,
568 .standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
569 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
570 .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
571 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM,
572 },
573 };
574
575 static inline const struct v4l2_dv_timings_cap *
576 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
577 {
578 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
579 &adv7842_timings_cap_analog;
580 }
581
582 /* ----------------------------------------------------------------------- */
583
584 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
585 {
586 struct delayed_work *dwork = to_delayed_work(work);
587 struct adv7842_state *state = container_of(dwork,
588 struct adv7842_state, delayed_work_enable_hotplug);
589 struct v4l2_subdev *sd = &state->sd;
590 int present = state->hdmi_edid.present;
591 u8 mask = 0;
592
593 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
594 __func__, present);
595
596 if (present & 0x1)
597 mask |= 0x20; /* port A */
598 if (present & 0x2)
599 mask |= 0x10; /* port B */
600 io_write_and_or(sd, 0x20, 0xcf, mask);
601 }
602
603 static int edid_write_vga_segment(struct v4l2_subdev *sd)
604 {
605 struct i2c_client *client = v4l2_get_subdevdata(sd);
606 struct adv7842_state *state = to_state(sd);
607 const u8 *val = state->vga_edid.edid;
608 int err = 0;
609 int i;
610
611 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
612
613 /* HPA disable on port A and B */
614 io_write_and_or(sd, 0x20, 0xcf, 0x00);
615
616 /* Disable I2C access to internal EDID ram from VGA DDC port */
617 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
618
619 /* edid segment pointer '1' for VGA port */
620 rep_write_and_or(sd, 0x77, 0xef, 0x10);
621
622 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
623 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
624 I2C_SMBUS_BLOCK_MAX, val + i);
625 if (err)
626 return err;
627
628 /* Calculates the checksums and enables I2C access
629 * to internal EDID ram from VGA DDC port.
630 */
631 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
632
633 for (i = 0; i < 1000; i++) {
634 if (rep_read(sd, 0x79) & 0x20)
635 break;
636 mdelay(1);
637 }
638 if (i == 1000) {
639 v4l_err(client, "error enabling edid on VGA port\n");
640 return -EIO;
641 }
642
643 /* enable hotplug after 200 ms */
644 queue_delayed_work(state->work_queues,
645 &state->delayed_work_enable_hotplug, HZ / 5);
646
647 return 0;
648 }
649
650 static int edid_spa_location(const u8 *edid)
651 {
652 u8 d;
653
654 /*
655 * TODO, improve and update for other CEA extensions
656 * currently only for 1 segment (256 bytes),
657 * i.e. 1 extension block and CEA revision 3.
658 */
659 if ((edid[0x7e] != 1) ||
660 (edid[0x80] != 0x02) ||
661 (edid[0x81] != 0x03)) {
662 return -EINVAL;
663 }
664 /*
665 * search Vendor Specific Data Block (tag 3)
666 */
667 d = edid[0x82] & 0x7f;
668 if (d > 4) {
669 int i = 0x84;
670 int end = 0x80 + d;
671 do {
672 u8 tag = edid[i]>>5;
673 u8 len = edid[i] & 0x1f;
674
675 if ((tag == 3) && (len >= 5))
676 return i + 4;
677 i += len + 1;
678 } while (i < end);
679 }
680 return -EINVAL;
681 }
682
683 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
684 {
685 struct i2c_client *client = v4l2_get_subdevdata(sd);
686 struct adv7842_state *state = to_state(sd);
687 const u8 *val = state->hdmi_edid.edid;
688 u8 cur_mask = rep_read(sd, 0x77) & 0x0c;
689 u8 mask = port == 0 ? 0x4 : 0x8;
690 int spa_loc = edid_spa_location(val);
691 int err = 0;
692 int i;
693
694 v4l2_dbg(2, debug, sd, "%s: write EDID on port %d (spa at 0x%x)\n",
695 __func__, port, spa_loc);
696
697 /* HPA disable on port A and B */
698 io_write_and_or(sd, 0x20, 0xcf, 0x00);
699
700 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
701 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
702
703 /* edid segment pointer '0' for HDMI ports */
704 rep_write_and_or(sd, 0x77, 0xef, 0x00);
705
706 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
707 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
708 I2C_SMBUS_BLOCK_MAX, val + i);
709 if (err)
710 return err;
711
712 if (spa_loc > 0) {
713 if (port == 0) {
714 /* port A SPA */
715 rep_write(sd, 0x72, val[spa_loc]);
716 rep_write(sd, 0x73, val[spa_loc + 1]);
717 } else {
718 /* port B SPA */
719 rep_write(sd, 0x74, val[spa_loc]);
720 rep_write(sd, 0x75, val[spa_loc + 1]);
721 }
722 rep_write(sd, 0x76, spa_loc);
723 } else {
724 /* default register values for SPA */
725 if (port == 0) {
726 /* port A SPA */
727 rep_write(sd, 0x72, 0);
728 rep_write(sd, 0x73, 0);
729 } else {
730 /* port B SPA */
731 rep_write(sd, 0x74, 0);
732 rep_write(sd, 0x75, 0);
733 }
734 rep_write(sd, 0x76, 0xc0);
735 }
736 rep_write_and_or(sd, 0x77, 0xbf, 0x00);
737
738 /* Calculates the checksums and enables I2C access to internal
739 * EDID ram from HDMI DDC ports
740 */
741 rep_write_and_or(sd, 0x77, 0xf3, mask | cur_mask);
742
743 for (i = 0; i < 1000; i++) {
744 if (rep_read(sd, 0x7d) & mask)
745 break;
746 mdelay(1);
747 }
748 if (i == 1000) {
749 v4l_err(client, "error enabling edid on port %d\n", port);
750 return -EIO;
751 }
752
753 /* enable hotplug after 200 ms */
754 queue_delayed_work(state->work_queues,
755 &state->delayed_work_enable_hotplug, HZ / 5);
756
757 return 0;
758 }
759
760 /* ----------------------------------------------------------------------- */
761
762 #ifdef CONFIG_VIDEO_ADV_DEBUG
763 static void adv7842_inv_register(struct v4l2_subdev *sd)
764 {
765 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
766 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
767 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
768 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
769 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
770 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
771 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
772 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
773 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
774 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
775 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
776 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
777 }
778
779 static int adv7842_g_register(struct v4l2_subdev *sd,
780 struct v4l2_dbg_register *reg)
781 {
782 reg->size = 1;
783 switch (reg->reg >> 8) {
784 case 0:
785 reg->val = io_read(sd, reg->reg & 0xff);
786 break;
787 case 1:
788 reg->val = avlink_read(sd, reg->reg & 0xff);
789 break;
790 case 2:
791 reg->val = cec_read(sd, reg->reg & 0xff);
792 break;
793 case 3:
794 reg->val = infoframe_read(sd, reg->reg & 0xff);
795 break;
796 case 4:
797 reg->val = sdp_io_read(sd, reg->reg & 0xff);
798 break;
799 case 5:
800 reg->val = sdp_read(sd, reg->reg & 0xff);
801 break;
802 case 6:
803 reg->val = afe_read(sd, reg->reg & 0xff);
804 break;
805 case 7:
806 reg->val = rep_read(sd, reg->reg & 0xff);
807 break;
808 case 8:
809 reg->val = edid_read(sd, reg->reg & 0xff);
810 break;
811 case 9:
812 reg->val = hdmi_read(sd, reg->reg & 0xff);
813 break;
814 case 0xa:
815 reg->val = cp_read(sd, reg->reg & 0xff);
816 break;
817 case 0xb:
818 reg->val = vdp_read(sd, reg->reg & 0xff);
819 break;
820 default:
821 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
822 adv7842_inv_register(sd);
823 break;
824 }
825 return 0;
826 }
827
828 static int adv7842_s_register(struct v4l2_subdev *sd,
829 const struct v4l2_dbg_register *reg)
830 {
831 u8 val = reg->val & 0xff;
832
833 switch (reg->reg >> 8) {
834 case 0:
835 io_write(sd, reg->reg & 0xff, val);
836 break;
837 case 1:
838 avlink_write(sd, reg->reg & 0xff, val);
839 break;
840 case 2:
841 cec_write(sd, reg->reg & 0xff, val);
842 break;
843 case 3:
844 infoframe_write(sd, reg->reg & 0xff, val);
845 break;
846 case 4:
847 sdp_io_write(sd, reg->reg & 0xff, val);
848 break;
849 case 5:
850 sdp_write(sd, reg->reg & 0xff, val);
851 break;
852 case 6:
853 afe_write(sd, reg->reg & 0xff, val);
854 break;
855 case 7:
856 rep_write(sd, reg->reg & 0xff, val);
857 break;
858 case 8:
859 edid_write(sd, reg->reg & 0xff, val);
860 break;
861 case 9:
862 hdmi_write(sd, reg->reg & 0xff, val);
863 break;
864 case 0xa:
865 cp_write(sd, reg->reg & 0xff, val);
866 break;
867 case 0xb:
868 vdp_write(sd, reg->reg & 0xff, val);
869 break;
870 default:
871 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
872 adv7842_inv_register(sd);
873 break;
874 }
875 return 0;
876 }
877 #endif
878
879 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
880 {
881 struct adv7842_state *state = to_state(sd);
882 int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl);
883 u8 reg_io_6f = io_read(sd, 0x6f);
884 int val = 0;
885
886 if (reg_io_6f & 0x02)
887 val |= 1; /* port A */
888 if (reg_io_6f & 0x01)
889 val |= 2; /* port B */
890
891 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val);
892
893 if (val != prev)
894 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val);
895 return 0;
896 }
897
898 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
899 u8 prim_mode,
900 const struct adv7842_video_standards *predef_vid_timings,
901 const struct v4l2_dv_timings *timings)
902 {
903 int i;
904
905 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
906 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
907 is_digital_input(sd) ? 250000 : 1000000))
908 continue;
909 /* video std */
910 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
911 /* v_freq and prim mode */
912 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
913 return 0;
914 }
915
916 return -1;
917 }
918
919 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
920 struct v4l2_dv_timings *timings)
921 {
922 struct adv7842_state *state = to_state(sd);
923 int err;
924
925 v4l2_dbg(1, debug, sd, "%s\n", __func__);
926
927 /* reset to default values */
928 io_write(sd, 0x16, 0x43);
929 io_write(sd, 0x17, 0x5a);
930 /* disable embedded syncs for auto graphics mode */
931 cp_write_and_or(sd, 0x81, 0xef, 0x00);
932 cp_write(sd, 0x26, 0x00);
933 cp_write(sd, 0x27, 0x00);
934 cp_write(sd, 0x28, 0x00);
935 cp_write(sd, 0x29, 0x00);
936 cp_write(sd, 0x8f, 0x00);
937 cp_write(sd, 0x90, 0x00);
938 cp_write(sd, 0xa5, 0x00);
939 cp_write(sd, 0xa6, 0x00);
940 cp_write(sd, 0xa7, 0x00);
941 cp_write(sd, 0xab, 0x00);
942 cp_write(sd, 0xac, 0x00);
943
944 switch (state->mode) {
945 case ADV7842_MODE_COMP:
946 case ADV7842_MODE_RGB:
947 err = find_and_set_predefined_video_timings(sd,
948 0x01, adv7842_prim_mode_comp, timings);
949 if (err)
950 err = find_and_set_predefined_video_timings(sd,
951 0x02, adv7842_prim_mode_gr, timings);
952 break;
953 case ADV7842_MODE_HDMI:
954 err = find_and_set_predefined_video_timings(sd,
955 0x05, adv7842_prim_mode_hdmi_comp, timings);
956 if (err)
957 err = find_and_set_predefined_video_timings(sd,
958 0x06, adv7842_prim_mode_hdmi_gr, timings);
959 break;
960 default:
961 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
962 __func__, state->mode);
963 err = -1;
964 break;
965 }
966
967
968 return err;
969 }
970
971 static void configure_custom_video_timings(struct v4l2_subdev *sd,
972 const struct v4l2_bt_timings *bt)
973 {
974 struct adv7842_state *state = to_state(sd);
975 struct i2c_client *client = v4l2_get_subdevdata(sd);
976 u32 width = htotal(bt);
977 u32 height = vtotal(bt);
978 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
979 u16 cp_start_eav = width - bt->hfrontporch;
980 u16 cp_start_vbi = height - bt->vfrontporch + 1;
981 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
982 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
983 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
984 const u8 pll[2] = {
985 0xc0 | ((width >> 8) & 0x1f),
986 width & 0xff
987 };
988
989 v4l2_dbg(2, debug, sd, "%s\n", __func__);
990
991 switch (state->mode) {
992 case ADV7842_MODE_COMP:
993 case ADV7842_MODE_RGB:
994 /* auto graphics */
995 io_write(sd, 0x00, 0x07); /* video std */
996 io_write(sd, 0x01, 0x02); /* prim mode */
997 /* enable embedded syncs for auto graphics mode */
998 cp_write_and_or(sd, 0x81, 0xef, 0x10);
999
1000 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1001 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1002 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1003 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
1004 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1005 break;
1006 }
1007
1008 /* active video - horizontal timing */
1009 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1010 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1011 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1012 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1013
1014 /* active video - vertical timing */
1015 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1016 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1017 ((cp_end_vbi >> 8) & 0xf));
1018 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1019 break;
1020 case ADV7842_MODE_HDMI:
1021 /* set default prim_mode/vid_std for HDMI
1022 accoring to [REF_03, c. 4.2] */
1023 io_write(sd, 0x00, 0x02); /* video std */
1024 io_write(sd, 0x01, 0x06); /* prim mode */
1025 break;
1026 default:
1027 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1028 __func__, state->mode);
1029 break;
1030 }
1031
1032 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1033 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1034 cp_write(sd, 0xab, (height >> 4) & 0xff);
1035 cp_write(sd, 0xac, (height & 0x0f) << 4);
1036 }
1037
1038 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1039 {
1040 struct adv7842_state *state = to_state(sd);
1041
1042 switch (state->rgb_quantization_range) {
1043 case V4L2_DV_RGB_RANGE_AUTO:
1044 /* automatic */
1045 if (is_digital_input(sd) && !(hdmi_read(sd, 0x05) & 0x80)) {
1046 /* receiving DVI-D signal */
1047
1048 /* ADV7842 selects RGB limited range regardless of
1049 input format (CE/IT) in automatic mode */
1050 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1051 /* RGB limited range (16-235) */
1052 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1053
1054 } else {
1055 /* RGB full range (0-255) */
1056 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1057 }
1058 } else {
1059 /* receiving HDMI or analog signal, set automode */
1060 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1061 }
1062 break;
1063 case V4L2_DV_RGB_RANGE_LIMITED:
1064 /* RGB limited range (16-235) */
1065 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1066 break;
1067 case V4L2_DV_RGB_RANGE_FULL:
1068 /* RGB full range (0-255) */
1069 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1070 break;
1071 }
1072 }
1073
1074 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1075 {
1076 struct v4l2_subdev *sd = to_sd(ctrl);
1077 struct adv7842_state *state = to_state(sd);
1078
1079 /* TODO SDP ctrls
1080 contrast/brightness/hue/free run is acting a bit strange,
1081 not sure if sdp csc is correct.
1082 */
1083 switch (ctrl->id) {
1084 /* standard ctrls */
1085 case V4L2_CID_BRIGHTNESS:
1086 cp_write(sd, 0x3c, ctrl->val);
1087 sdp_write(sd, 0x14, ctrl->val);
1088 /* ignore lsb sdp 0x17[3:2] */
1089 return 0;
1090 case V4L2_CID_CONTRAST:
1091 cp_write(sd, 0x3a, ctrl->val);
1092 sdp_write(sd, 0x13, ctrl->val);
1093 /* ignore lsb sdp 0x17[1:0] */
1094 return 0;
1095 case V4L2_CID_SATURATION:
1096 cp_write(sd, 0x3b, ctrl->val);
1097 sdp_write(sd, 0x15, ctrl->val);
1098 /* ignore lsb sdp 0x17[5:4] */
1099 return 0;
1100 case V4L2_CID_HUE:
1101 cp_write(sd, 0x3d, ctrl->val);
1102 sdp_write(sd, 0x16, ctrl->val);
1103 /* ignore lsb sdp 0x17[7:6] */
1104 return 0;
1105 /* custom ctrls */
1106 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1107 afe_write(sd, 0xc8, ctrl->val);
1108 return 0;
1109 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1110 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1111 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1112 return 0;
1113 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1114 u8 R = (ctrl->val & 0xff0000) >> 16;
1115 u8 G = (ctrl->val & 0x00ff00) >> 8;
1116 u8 B = (ctrl->val & 0x0000ff);
1117 /* RGB -> YUV, numerical approximation */
1118 int Y = 66 * R + 129 * G + 25 * B;
1119 int U = -38 * R - 74 * G + 112 * B;
1120 int V = 112 * R - 94 * G - 18 * B;
1121
1122 /* Scale down to 8 bits with rounding */
1123 Y = (Y + 128) >> 8;
1124 U = (U + 128) >> 8;
1125 V = (V + 128) >> 8;
1126 /* make U,V positive */
1127 Y += 16;
1128 U += 128;
1129 V += 128;
1130
1131 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1132 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1133
1134 /* CP */
1135 cp_write(sd, 0xc1, R);
1136 cp_write(sd, 0xc0, G);
1137 cp_write(sd, 0xc2, B);
1138 /* SDP */
1139 sdp_write(sd, 0xde, Y);
1140 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1141 return 0;
1142 }
1143 case V4L2_CID_DV_RX_RGB_RANGE:
1144 state->rgb_quantization_range = ctrl->val;
1145 set_rgb_quantization_range(sd);
1146 return 0;
1147 }
1148 return -EINVAL;
1149 }
1150
1151 static inline bool no_power(struct v4l2_subdev *sd)
1152 {
1153 return io_read(sd, 0x0c) & 0x24;
1154 }
1155
1156 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1157 {
1158 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1159 }
1160
1161 static inline bool is_hdmi(struct v4l2_subdev *sd)
1162 {
1163 return hdmi_read(sd, 0x05) & 0x80;
1164 }
1165
1166 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1167 {
1168 struct adv7842_state *state = to_state(sd);
1169
1170 *status = 0;
1171
1172 if (io_read(sd, 0x0c) & 0x24)
1173 *status |= V4L2_IN_ST_NO_POWER;
1174
1175 if (state->mode == ADV7842_MODE_SDP) {
1176 /* status from SDP block */
1177 if (!(sdp_read(sd, 0x5A) & 0x01))
1178 *status |= V4L2_IN_ST_NO_SIGNAL;
1179
1180 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1181 __func__, *status);
1182 return 0;
1183 }
1184 /* status from CP block */
1185 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1186 !(cp_read(sd, 0xb1) & 0x80))
1187 /* TODO channel 2 */
1188 *status |= V4L2_IN_ST_NO_SIGNAL;
1189
1190 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1191 *status |= V4L2_IN_ST_NO_SIGNAL;
1192
1193 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1194 __func__, *status);
1195
1196 return 0;
1197 }
1198
1199 struct stdi_readback {
1200 u16 bl, lcf, lcvs;
1201 u8 hs_pol, vs_pol;
1202 bool interlaced;
1203 };
1204
1205 static int stdi2dv_timings(struct v4l2_subdev *sd,
1206 struct stdi_readback *stdi,
1207 struct v4l2_dv_timings *timings)
1208 {
1209 struct adv7842_state *state = to_state(sd);
1210 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1211 u32 pix_clk;
1212 int i;
1213
1214 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1215 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1216
1217 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1218 adv7842_get_dv_timings_cap(sd),
1219 adv7842_check_dv_timings, NULL))
1220 continue;
1221 if (vtotal(bt) != stdi->lcf + 1)
1222 continue;
1223 if (bt->vsync != stdi->lcvs)
1224 continue;
1225
1226 pix_clk = hfreq * htotal(bt);
1227
1228 if ((pix_clk < bt->pixelclock + 1000000) &&
1229 (pix_clk > bt->pixelclock - 1000000)) {
1230 *timings = v4l2_dv_timings_presets[i];
1231 return 0;
1232 }
1233 }
1234
1235 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1236 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1237 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1238 timings))
1239 return 0;
1240 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1241 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1242 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1243 state->aspect_ratio, timings))
1244 return 0;
1245
1246 v4l2_dbg(2, debug, sd,
1247 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1248 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1249 stdi->hs_pol, stdi->vs_pol);
1250 return -1;
1251 }
1252
1253 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1254 {
1255 u32 status;
1256
1257 adv7842_g_input_status(sd, &status);
1258 if (status & V4L2_IN_ST_NO_SIGNAL) {
1259 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1260 return -ENOLINK;
1261 }
1262
1263 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1264 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1265 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1266
1267 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1268 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1269 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1270 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1271 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1272 } else {
1273 stdi->hs_pol = 'x';
1274 stdi->vs_pol = 'x';
1275 }
1276 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1277
1278 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1279 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1280 return -ENOLINK;
1281 }
1282
1283 v4l2_dbg(2, debug, sd,
1284 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1285 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1286 stdi->hs_pol, stdi->vs_pol,
1287 stdi->interlaced ? "interlaced" : "progressive");
1288
1289 return 0;
1290 }
1291
1292 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1293 struct v4l2_enum_dv_timings *timings)
1294 {
1295 return v4l2_enum_dv_timings_cap(timings,
1296 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1297 }
1298
1299 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1300 struct v4l2_dv_timings_cap *cap)
1301 {
1302 *cap = *adv7842_get_dv_timings_cap(sd);
1303 return 0;
1304 }
1305
1306 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1307 if the format is listed in adv7604_timings[] */
1308 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1309 struct v4l2_dv_timings *timings)
1310 {
1311 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1312 is_digital_input(sd) ? 250000 : 1000000,
1313 adv7842_check_dv_timings, NULL);
1314 }
1315
1316 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1317 struct v4l2_dv_timings *timings)
1318 {
1319 struct adv7842_state *state = to_state(sd);
1320 struct v4l2_bt_timings *bt = &timings->bt;
1321 struct stdi_readback stdi = { 0 };
1322
1323 /* SDP block */
1324 if (state->mode == ADV7842_MODE_SDP)
1325 return -ENODATA;
1326
1327 /* read STDI */
1328 if (read_stdi(sd, &stdi)) {
1329 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1330 return -ENOLINK;
1331 }
1332 bt->interlaced = stdi.interlaced ?
1333 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1334 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1335 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1336 bt->vsync = stdi.lcvs;
1337
1338 if (is_digital_input(sd)) {
1339 bool lock = hdmi_read(sd, 0x04) & 0x02;
1340 bool interlaced = hdmi_read(sd, 0x0b) & 0x20;
1341 unsigned w = (hdmi_read(sd, 0x07) & 0x1f) * 256 + hdmi_read(sd, 0x08);
1342 unsigned h = (hdmi_read(sd, 0x09) & 0x1f) * 256 + hdmi_read(sd, 0x0a);
1343 unsigned w_total = (hdmi_read(sd, 0x1e) & 0x3f) * 256 +
1344 hdmi_read(sd, 0x1f);
1345 unsigned h_total = ((hdmi_read(sd, 0x26) & 0x3f) * 256 +
1346 hdmi_read(sd, 0x27)) / 2;
1347 unsigned freq = (((hdmi_read(sd, 0x51) << 1) +
1348 (hdmi_read(sd, 0x52) >> 7)) * 1000000) +
1349 ((hdmi_read(sd, 0x52) & 0x7f) * 1000000) / 128;
1350 int i;
1351
1352 if (is_hdmi(sd)) {
1353 /* adjust for deep color mode */
1354 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0)>>6) * 2 + 8);
1355 }
1356
1357 /* No lock? */
1358 if (!lock) {
1359 v4l2_dbg(1, debug, sd, "%s: no lock on TMDS signal\n", __func__);
1360 return -ENOLCK;
1361 }
1362 /* Interlaced? */
1363 if (interlaced) {
1364 v4l2_dbg(1, debug, sd, "%s: interlaced video not supported\n", __func__);
1365 return -ERANGE;
1366 }
1367
1368 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1369 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1370
1371 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1372 adv7842_get_dv_timings_cap(sd),
1373 adv7842_check_dv_timings, NULL))
1374 continue;
1375 if (w_total != htotal(bt) || h_total != vtotal(bt))
1376 continue;
1377
1378 if (w != bt->width || h != bt->height)
1379 continue;
1380
1381 if (abs(freq - bt->pixelclock) > 1000000)
1382 continue;
1383 *timings = v4l2_dv_timings_presets[i];
1384 return 0;
1385 }
1386
1387 timings->type = V4L2_DV_BT_656_1120;
1388
1389 bt->width = w;
1390 bt->height = h;
1391 bt->interlaced = (hdmi_read(sd, 0x0b) & 0x20) ?
1392 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1393 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ?
1394 V4L2_DV_VSYNC_POS_POL : 0) | ((hdmi_read(sd, 0x05) & 0x20) ?
1395 V4L2_DV_HSYNC_POS_POL : 0);
1396 bt->pixelclock = (((hdmi_read(sd, 0x51) << 1) +
1397 (hdmi_read(sd, 0x52) >> 7)) * 1000000) +
1398 ((hdmi_read(sd, 0x52) & 0x7f) * 1000000) / 128;
1399 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x1f) * 256 +
1400 hdmi_read(sd, 0x21);
1401 bt->hsync = (hdmi_read(sd, 0x22) & 0x1f) * 256 +
1402 hdmi_read(sd, 0x23);
1403 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x1f) * 256 +
1404 hdmi_read(sd, 0x25);
1405 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x3f) * 256 +
1406 hdmi_read(sd, 0x2b)) / 2;
1407 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x3f) * 256 +
1408 hdmi_read(sd, 0x2d)) / 2;
1409 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x3f) * 256 +
1410 hdmi_read(sd, 0x2f)) / 2;
1411 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x3f) * 256 +
1412 hdmi_read(sd, 0x31)) / 2;
1413 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x3f) * 256 +
1414 hdmi_read(sd, 0x33)) / 2;
1415 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x3f) * 256 +
1416 hdmi_read(sd, 0x35)) / 2;
1417
1418 bt->standards = 0;
1419 bt->flags = 0;
1420 } else {
1421 /* Interlaced? */
1422 if (stdi.interlaced) {
1423 v4l2_dbg(1, debug, sd, "%s: interlaced video not supported\n", __func__);
1424 return -ERANGE;
1425 }
1426
1427 if (stdi2dv_timings(sd, &stdi, timings)) {
1428 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1429 return -ERANGE;
1430 }
1431 }
1432
1433 if (debug > 1)
1434 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings: ",
1435 timings, true);
1436 return 0;
1437 }
1438
1439 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1440 struct v4l2_dv_timings *timings)
1441 {
1442 struct adv7842_state *state = to_state(sd);
1443 struct v4l2_bt_timings *bt;
1444 int err;
1445
1446 if (state->mode == ADV7842_MODE_SDP)
1447 return -ENODATA;
1448
1449 bt = &timings->bt;
1450
1451 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1452 adv7842_check_dv_timings, NULL))
1453 return -ERANGE;
1454
1455 adv7842_fill_optional_dv_timings_fields(sd, timings);
1456
1457 state->timings = *timings;
1458
1459 cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1460
1461 /* Use prim_mode and vid_std when available */
1462 err = configure_predefined_video_timings(sd, timings);
1463 if (err) {
1464 /* custom settings when the video format
1465 does not have prim_mode/vid_std */
1466 configure_custom_video_timings(sd, bt);
1467 }
1468
1469 set_rgb_quantization_range(sd);
1470
1471
1472 if (debug > 1)
1473 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1474 timings, true);
1475 return 0;
1476 }
1477
1478 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1479 struct v4l2_dv_timings *timings)
1480 {
1481 struct adv7842_state *state = to_state(sd);
1482
1483 if (state->mode == ADV7842_MODE_SDP)
1484 return -ENODATA;
1485 *timings = state->timings;
1486 return 0;
1487 }
1488
1489 static void enable_input(struct v4l2_subdev *sd)
1490 {
1491 struct adv7842_state *state = to_state(sd);
1492 switch (state->mode) {
1493 case ADV7842_MODE_SDP:
1494 case ADV7842_MODE_COMP:
1495 case ADV7842_MODE_RGB:
1496 /* enable */
1497 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1498 break;
1499 case ADV7842_MODE_HDMI:
1500 /* enable */
1501 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1502 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1503 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1504 break;
1505 default:
1506 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1507 __func__, state->mode);
1508 break;
1509 }
1510 }
1511
1512 static void disable_input(struct v4l2_subdev *sd)
1513 {
1514 /* disable */
1515 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1516 hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1517 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1518 }
1519
1520 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1521 const struct adv7842_sdp_csc_coeff *c)
1522 {
1523 /* csc auto/manual */
1524 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1525
1526 if (!c->manual)
1527 return;
1528
1529 /* csc scaling */
1530 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1531
1532 /* A coeff */
1533 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1534 sdp_io_write(sd, 0xe1, c->A1);
1535 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1536 sdp_io_write(sd, 0xe3, c->A2);
1537 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1538 sdp_io_write(sd, 0xe5, c->A3);
1539
1540 /* A scale */
1541 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1542 sdp_io_write(sd, 0xe7, c->A4);
1543
1544 /* B coeff */
1545 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1546 sdp_io_write(sd, 0xe9, c->B1);
1547 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1548 sdp_io_write(sd, 0xeb, c->B2);
1549 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1550 sdp_io_write(sd, 0xed, c->B3);
1551
1552 /* B scale */
1553 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1554 sdp_io_write(sd, 0xef, c->B4);
1555
1556 /* C coeff */
1557 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1558 sdp_io_write(sd, 0xf1, c->C1);
1559 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1560 sdp_io_write(sd, 0xf3, c->C2);
1561 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1562 sdp_io_write(sd, 0xf5, c->C3);
1563
1564 /* C scale */
1565 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1566 sdp_io_write(sd, 0xf7, c->C4);
1567 }
1568
1569 static void select_input(struct v4l2_subdev *sd,
1570 enum adv7842_vid_std_select vid_std_select)
1571 {
1572 struct adv7842_state *state = to_state(sd);
1573
1574 switch (state->mode) {
1575 case ADV7842_MODE_SDP:
1576 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1577 io_write(sd, 0x01, 0); /* prim mode */
1578 /* enable embedded syncs for auto graphics mode */
1579 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1580
1581 afe_write(sd, 0x00, 0x00); /* power up ADC */
1582 afe_write(sd, 0xc8, 0x00); /* phase control */
1583
1584 io_write(sd, 0x19, 0x83); /* LLC DLL phase */
1585 io_write(sd, 0x33, 0x40); /* LLC DLL enable */
1586
1587 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1588 /* script says register 0xde, which don't exist in manual */
1589
1590 /* Manual analog input muxing mode, CVBS (6.4)*/
1591 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1592 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1593 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1594 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1595 } else {
1596 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1597 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1598 }
1599 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1600 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1601
1602 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1603 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1604
1605 /* SDP recommended settings */
1606 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1607 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1608
1609 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1610 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1611 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1612 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1613 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1614 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1615 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1616
1617 /* deinterlacer enabled and 3D comb */
1618 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1619
1620 sdp_write(sd, 0xdd, 0x08); /* free run auto */
1621
1622 break;
1623
1624 case ADV7842_MODE_COMP:
1625 case ADV7842_MODE_RGB:
1626 /* Automatic analog input muxing mode */
1627 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1628 /* set mode and select free run resolution */
1629 io_write(sd, 0x00, vid_std_select); /* video std */
1630 io_write(sd, 0x01, 0x02); /* prim mode */
1631 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1632 for auto graphics mode */
1633
1634 afe_write(sd, 0x00, 0x00); /* power up ADC */
1635 afe_write(sd, 0xc8, 0x00); /* phase control */
1636
1637 /* set ADI recommended settings for digitizer */
1638 /* "ADV7842 Register Settings Recommendations
1639 * (rev. 1.8, November 2010)" p. 9. */
1640 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1641 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1642
1643 /* set to default gain for RGB */
1644 cp_write(sd, 0x73, 0x10);
1645 cp_write(sd, 0x74, 0x04);
1646 cp_write(sd, 0x75, 0x01);
1647 cp_write(sd, 0x76, 0x00);
1648
1649 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1650 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1651 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1652 break;
1653
1654 case ADV7842_MODE_HDMI:
1655 /* Automatic analog input muxing mode */
1656 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1657 /* set mode and select free run resolution */
1658 if (state->hdmi_port_a)
1659 hdmi_write(sd, 0x00, 0x02); /* select port A */
1660 else
1661 hdmi_write(sd, 0x00, 0x03); /* select port B */
1662 io_write(sd, 0x00, vid_std_select); /* video std */
1663 io_write(sd, 0x01, 5); /* prim mode */
1664 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1665 for auto graphics mode */
1666
1667 /* set ADI recommended settings for HDMI: */
1668 /* "ADV7842 Register Settings Recommendations
1669 * (rev. 1.8, November 2010)" p. 3. */
1670 hdmi_write(sd, 0xc0, 0x00);
1671 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1672 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1673 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1674 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1675 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1676 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1677 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1678 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1679 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1680 Improve robustness */
1681 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1682 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1683 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1684 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1685 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1686 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1687 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1688 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1689 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1690 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1691
1692 afe_write(sd, 0x00, 0xff); /* power down ADC */
1693 afe_write(sd, 0xc8, 0x40); /* phase control */
1694
1695 /* set to default gain for HDMI */
1696 cp_write(sd, 0x73, 0x10);
1697 cp_write(sd, 0x74, 0x04);
1698 cp_write(sd, 0x75, 0x01);
1699 cp_write(sd, 0x76, 0x00);
1700
1701 /* reset ADI recommended settings for digitizer */
1702 /* "ADV7842 Register Settings Recommendations
1703 * (rev. 2.5, June 2010)" p. 17. */
1704 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1705 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1706 cp_write(sd, 0x3e, 0x80); /* CP core pre-gain control,
1707 enable color control */
1708 /* CP coast control */
1709 cp_write(sd, 0xc3, 0x33); /* Component mode */
1710
1711 /* color space conversion, autodetect color space */
1712 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1713 break;
1714
1715 default:
1716 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1717 __func__, state->mode);
1718 break;
1719 }
1720 }
1721
1722 static int adv7842_s_routing(struct v4l2_subdev *sd,
1723 u32 input, u32 output, u32 config)
1724 {
1725 struct adv7842_state *state = to_state(sd);
1726
1727 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1728
1729 switch (input) {
1730 case ADV7842_SELECT_HDMI_PORT_A:
1731 /* TODO select HDMI_COMP or HDMI_GR */
1732 state->mode = ADV7842_MODE_HDMI;
1733 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1734 state->hdmi_port_a = true;
1735 break;
1736 case ADV7842_SELECT_HDMI_PORT_B:
1737 /* TODO select HDMI_COMP or HDMI_GR */
1738 state->mode = ADV7842_MODE_HDMI;
1739 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1740 state->hdmi_port_a = false;
1741 break;
1742 case ADV7842_SELECT_VGA_COMP:
1743 v4l2_info(sd, "%s: VGA component: todo\n", __func__);
1744 case ADV7842_SELECT_VGA_RGB:
1745 state->mode = ADV7842_MODE_RGB;
1746 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1747 break;
1748 case ADV7842_SELECT_SDP_CVBS:
1749 state->mode = ADV7842_MODE_SDP;
1750 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1751 break;
1752 case ADV7842_SELECT_SDP_YC:
1753 state->mode = ADV7842_MODE_SDP;
1754 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1755 break;
1756 default:
1757 return -EINVAL;
1758 }
1759
1760 disable_input(sd);
1761 select_input(sd, state->vid_std_select);
1762 enable_input(sd);
1763
1764 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1765
1766 return 0;
1767 }
1768
1769 static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1770 enum v4l2_mbus_pixelcode *code)
1771 {
1772 if (index)
1773 return -EINVAL;
1774 /* Good enough for now */
1775 *code = V4L2_MBUS_FMT_FIXED;
1776 return 0;
1777 }
1778
1779 static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd,
1780 struct v4l2_mbus_framefmt *fmt)
1781 {
1782 struct adv7842_state *state = to_state(sd);
1783
1784 fmt->width = state->timings.bt.width;
1785 fmt->height = state->timings.bt.height;
1786 fmt->code = V4L2_MBUS_FMT_FIXED;
1787 fmt->field = V4L2_FIELD_NONE;
1788
1789 if (state->mode == ADV7842_MODE_SDP) {
1790 /* SPD block */
1791 if (!(sdp_read(sd, 0x5A) & 0x01))
1792 return -EINVAL;
1793 fmt->width = 720;
1794 /* valid signal */
1795 if (state->norm & V4L2_STD_525_60)
1796 fmt->height = 480;
1797 else
1798 fmt->height = 576;
1799 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1800 return 0;
1801 }
1802
1803 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1804 fmt->colorspace = (state->timings.bt.height <= 576) ?
1805 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1806 }
1807 return 0;
1808 }
1809
1810 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
1811 {
1812 if (enable) {
1813 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
1814 io_write(sd, 0x46, 0x9c);
1815 /* ESDP_50HZ_DET interrupt */
1816 io_write(sd, 0x5a, 0x10);
1817 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
1818 io_write(sd, 0x73, 0x03);
1819 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1820 io_write(sd, 0x78, 0x03);
1821 /* Enable SDP Standard Detection Change and SDP Video Detected */
1822 io_write(sd, 0xa0, 0x09);
1823 } else {
1824 io_write(sd, 0x46, 0x0);
1825 io_write(sd, 0x5a, 0x0);
1826 io_write(sd, 0x73, 0x0);
1827 io_write(sd, 0x78, 0x0);
1828 io_write(sd, 0xa0, 0x0);
1829 }
1830 }
1831
1832 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1833 {
1834 struct adv7842_state *state = to_state(sd);
1835 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
1836 u8 irq_status[5];
1837 u8 irq_cfg = io_read(sd, 0x40);
1838
1839 /* disable irq-pin output */
1840 io_write(sd, 0x40, irq_cfg | 0x3);
1841
1842 /* read status */
1843 irq_status[0] = io_read(sd, 0x43);
1844 irq_status[1] = io_read(sd, 0x57);
1845 irq_status[2] = io_read(sd, 0x70);
1846 irq_status[3] = io_read(sd, 0x75);
1847 irq_status[4] = io_read(sd, 0x9d);
1848
1849 /* and clear */
1850 if (irq_status[0])
1851 io_write(sd, 0x44, irq_status[0]);
1852 if (irq_status[1])
1853 io_write(sd, 0x58, irq_status[1]);
1854 if (irq_status[2])
1855 io_write(sd, 0x71, irq_status[2]);
1856 if (irq_status[3])
1857 io_write(sd, 0x76, irq_status[3]);
1858 if (irq_status[4])
1859 io_write(sd, 0x9e, irq_status[4]);
1860
1861 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x\n", __func__,
1862 irq_status[0], irq_status[1], irq_status[2],
1863 irq_status[3], irq_status[4]);
1864
1865 /* format change CP */
1866 fmt_change_cp = irq_status[0] & 0x9c;
1867
1868 /* format change SDP */
1869 if (state->mode == ADV7842_MODE_SDP)
1870 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
1871 else
1872 fmt_change_sdp = 0;
1873
1874 /* digital format CP */
1875 if (is_digital_input(sd))
1876 fmt_change_digital = irq_status[3] & 0x03;
1877 else
1878 fmt_change_digital = 0;
1879
1880 /* notify */
1881 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
1882 v4l2_dbg(1, debug, sd,
1883 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
1884 __func__, fmt_change_cp, fmt_change_digital,
1885 fmt_change_sdp);
1886 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1887 }
1888
1889 /* 5v cable detect */
1890 if (irq_status[2])
1891 adv7842_s_detect_tx_5v_ctrl(sd);
1892
1893 if (handled)
1894 *handled = true;
1895
1896 /* re-enable irq-pin output */
1897 io_write(sd, 0x40, irq_cfg);
1898
1899 return 0;
1900 }
1901
1902 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *e)
1903 {
1904 struct adv7842_state *state = to_state(sd);
1905 int err = 0;
1906
1907 if (e->pad > 2)
1908 return -EINVAL;
1909 if (e->start_block != 0)
1910 return -EINVAL;
1911 if (e->blocks > 2)
1912 return -E2BIG;
1913 if (!e->edid)
1914 return -EINVAL;
1915
1916 /* todo, per edid */
1917 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
1918 e->edid[0x16]);
1919
1920 if (e->pad == 2) {
1921 memset(&state->vga_edid.edid, 0, 256);
1922 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
1923 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
1924 err = edid_write_vga_segment(sd);
1925 } else {
1926 u32 mask = 0x1<<e->pad;
1927 memset(&state->hdmi_edid.edid, 0, 256);
1928 if (e->blocks)
1929 state->hdmi_edid.present |= mask;
1930 else
1931 state->hdmi_edid.present &= ~mask;
1932 memcpy(&state->hdmi_edid.edid, e->edid, 128*e->blocks);
1933 err = edid_write_hdmi_segment(sd, e->pad);
1934 }
1935 if (err < 0)
1936 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
1937 return err;
1938 }
1939
1940 /*********** avi info frame CEA-861-E **************/
1941 /* TODO move to common library */
1942
1943 struct avi_info_frame {
1944 uint8_t f17;
1945 uint8_t y10;
1946 uint8_t a0;
1947 uint8_t b10;
1948 uint8_t s10;
1949 uint8_t c10;
1950 uint8_t m10;
1951 uint8_t r3210;
1952 uint8_t itc;
1953 uint8_t ec210;
1954 uint8_t q10;
1955 uint8_t sc10;
1956 uint8_t f47;
1957 uint8_t vic;
1958 uint8_t yq10;
1959 uint8_t cn10;
1960 uint8_t pr3210;
1961 uint16_t etb;
1962 uint16_t sbb;
1963 uint16_t elb;
1964 uint16_t srb;
1965 };
1966
1967 static const char *y10_txt[4] = {
1968 "RGB",
1969 "YCbCr 4:2:2",
1970 "YCbCr 4:4:4",
1971 "Future",
1972 };
1973
1974 static const char *c10_txt[4] = {
1975 "No Data",
1976 "SMPTE 170M",
1977 "ITU-R 709",
1978 "Extended Colorimetry information valied",
1979 };
1980
1981 static const char *itc_txt[2] = {
1982 "No Data",
1983 "IT content",
1984 };
1985
1986 static const char *ec210_txt[8] = {
1987 "xvYCC601",
1988 "xvYCC709",
1989 "sYCC601",
1990 "AdobeYCC601",
1991 "AdobeRGB",
1992 "5 reserved",
1993 "6 reserved",
1994 "7 reserved",
1995 };
1996
1997 static const char *q10_txt[4] = {
1998 "Default",
1999 "Limited Range",
2000 "Full Range",
2001 "Reserved",
2002 };
2003
2004 static void parse_avi_infoframe(struct v4l2_subdev *sd, uint8_t *buf,
2005 struct avi_info_frame *avi)
2006 {
2007 avi->f17 = (buf[1] >> 7) & 0x1;
2008 avi->y10 = (buf[1] >> 5) & 0x3;
2009 avi->a0 = (buf[1] >> 4) & 0x1;
2010 avi->b10 = (buf[1] >> 2) & 0x3;
2011 avi->s10 = buf[1] & 0x3;
2012 avi->c10 = (buf[2] >> 6) & 0x3;
2013 avi->m10 = (buf[2] >> 4) & 0x3;
2014 avi->r3210 = buf[2] & 0xf;
2015 avi->itc = (buf[3] >> 7) & 0x1;
2016 avi->ec210 = (buf[3] >> 4) & 0x7;
2017 avi->q10 = (buf[3] >> 2) & 0x3;
2018 avi->sc10 = buf[3] & 0x3;
2019 avi->f47 = (buf[4] >> 7) & 0x1;
2020 avi->vic = buf[4] & 0x7f;
2021 avi->yq10 = (buf[5] >> 6) & 0x3;
2022 avi->cn10 = (buf[5] >> 4) & 0x3;
2023 avi->pr3210 = buf[5] & 0xf;
2024 avi->etb = buf[6] + 256*buf[7];
2025 avi->sbb = buf[8] + 256*buf[9];
2026 avi->elb = buf[10] + 256*buf[11];
2027 avi->srb = buf[12] + 256*buf[13];
2028 }
2029
2030 static void print_avi_infoframe(struct v4l2_subdev *sd)
2031 {
2032 int i;
2033 uint8_t buf[14];
2034 uint8_t avi_inf_len;
2035 struct avi_info_frame avi;
2036
2037 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2038 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2039 return;
2040 }
2041 if (!(io_read(sd, 0x60) & 0x01)) {
2042 v4l2_info(sd, "AVI infoframe not received\n");
2043 return;
2044 }
2045
2046 if (io_read(sd, 0x88) & 0x10) {
2047 /* Note: the ADV7842 calculated incorrect checksums for InfoFrames
2048 with a length of 14 or 15. See the ADV7842 Register Settings
2049 Recommendations document for more details. */
2050 v4l2_info(sd, "AVI infoframe checksum error\n");
2051 return;
2052 }
2053
2054 avi_inf_len = infoframe_read(sd, 0xe2);
2055 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2056 infoframe_read(sd, 0xe1), avi_inf_len);
2057
2058 if (infoframe_read(sd, 0xe1) != 0x02)
2059 return;
2060
2061 for (i = 0; i < 14; i++)
2062 buf[i] = infoframe_read(sd, i);
2063
2064 v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2065 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2066 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2067
2068 parse_avi_infoframe(sd, buf, &avi);
2069
2070 if (avi.vic)
2071 v4l2_info(sd, "\tVIC: %d\n", avi.vic);
2072 if (avi.itc)
2073 v4l2_info(sd, "\t%s\n", itc_txt[avi.itc]);
2074
2075 if (avi.y10)
2076 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], !avi.c10 ? "" :
2077 (avi.c10 == 0x3 ? ec210_txt[avi.ec210] : c10_txt[avi.c10]));
2078 else
2079 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], q10_txt[avi.q10]);
2080 }
2081
2082 static const char * const prim_mode_txt[] = {
2083 "SDP",
2084 "Component",
2085 "Graphics",
2086 "Reserved",
2087 "CVBS & HDMI AUDIO",
2088 "HDMI-Comp",
2089 "HDMI-GR",
2090 "Reserved",
2091 "Reserved",
2092 "Reserved",
2093 "Reserved",
2094 "Reserved",
2095 "Reserved",
2096 "Reserved",
2097 "Reserved",
2098 "Reserved",
2099 };
2100
2101 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2102 {
2103 /* SDP (Standard definition processor) block */
2104 uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2105
2106 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2107 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2108 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2109
2110 v4l2_info(sd, "SDP: free run: %s\n",
2111 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2112 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2113 "valid SD/PR signal detected" : "invalid/no signal");
2114 if (sdp_signal_detected) {
2115 static const char * const sdp_std_txt[] = {
2116 "NTSC-M/J",
2117 "1?",
2118 "NTSC-443",
2119 "60HzSECAM",
2120 "PAL-M",
2121 "5?",
2122 "PAL-60",
2123 "7?", "8?", "9?", "a?", "b?",
2124 "PAL-CombN",
2125 "d?",
2126 "PAL-BGHID",
2127 "SECAM"
2128 };
2129 v4l2_info(sd, "SDP: standard %s\n",
2130 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2131 v4l2_info(sd, "SDP: %s\n",
2132 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2133 v4l2_info(sd, "SDP: %s\n",
2134 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2135 v4l2_info(sd, "SDP: deinterlacer %s\n",
2136 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2137 v4l2_info(sd, "SDP: csc %s mode\n",
2138 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2139 }
2140 return 0;
2141 }
2142
2143 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2144 {
2145 /* CP block */
2146 struct adv7842_state *state = to_state(sd);
2147 struct v4l2_dv_timings timings;
2148 uint8_t reg_io_0x02 = io_read(sd, 0x02);
2149 uint8_t reg_io_0x21 = io_read(sd, 0x21);
2150 uint8_t reg_rep_0x77 = rep_read(sd, 0x77);
2151 uint8_t reg_rep_0x7d = rep_read(sd, 0x7d);
2152 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2153 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2154 bool audio_mute = io_read(sd, 0x65) & 0x40;
2155
2156 static const char * const csc_coeff_sel_rb[16] = {
2157 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2158 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2159 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2160 "reserved", "reserved", "reserved", "reserved", "manual"
2161 };
2162 static const char * const input_color_space_txt[16] = {
2163 "RGB limited range (16-235)", "RGB full range (0-255)",
2164 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2165 "XvYCC Bt.601", "XvYCC Bt.709",
2166 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2167 "invalid", "invalid", "invalid", "invalid", "invalid",
2168 "invalid", "invalid", "automatic"
2169 };
2170 static const char * const rgb_quantization_range_txt[] = {
2171 "Automatic",
2172 "RGB limited range (16-235)",
2173 "RGB full range (0-255)",
2174 };
2175 static const char * const deep_color_mode_txt[4] = {
2176 "8-bits per channel",
2177 "10-bits per channel",
2178 "12-bits per channel",
2179 "16-bits per channel (not supported)"
2180 };
2181
2182 v4l2_info(sd, "-----Chip status-----\n");
2183 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2184 v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ?
2185 "HDMI" : (is_digital_input(sd) ? "DVI-D" : "DVI-A"));
2186 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2187 state->hdmi_port_a ? "A" : "B");
2188 v4l2_info(sd, "EDID A %s, B %s\n",
2189 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2190 "enabled" : "disabled",
2191 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2192 "enabled" : "disabled");
2193 v4l2_info(sd, "HPD A %s, B %s\n",
2194 reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2195 reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2196 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2197 "enabled" : "disabled");
2198
2199 v4l2_info(sd, "-----Signal status-----\n");
2200 if (state->hdmi_port_a) {
2201 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2202 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2203 v4l2_info(sd, "TMDS signal detected: %s\n",
2204 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2205 v4l2_info(sd, "TMDS signal locked: %s\n",
2206 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2207 } else {
2208 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2209 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2210 v4l2_info(sd, "TMDS signal detected: %s\n",
2211 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2212 v4l2_info(sd, "TMDS signal locked: %s\n",
2213 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2214 }
2215 v4l2_info(sd, "CP free run: %s\n",
2216 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2217 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2218 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2219 (io_read(sd, 0x01) & 0x70) >> 4);
2220
2221 v4l2_info(sd, "-----Video Timings-----\n");
2222 if (no_cp_signal(sd)) {
2223 v4l2_info(sd, "STDI: not locked\n");
2224 } else {
2225 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2226 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2227 uint32_t lcvs = cp_read(sd, 0xb3) >> 3;
2228 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2229 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2230 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2231 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2232 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2233 v4l2_info(sd,
2234 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2235 lcf, bl, lcvs, fcl,
2236 (cp_read(sd, 0xb1) & 0x40) ?
2237 "interlaced" : "progressive",
2238 hs_pol, vs_pol);
2239 }
2240 if (adv7842_query_dv_timings(sd, &timings))
2241 v4l2_info(sd, "No video detected\n");
2242 else
2243 v4l2_print_dv_timings(sd->name, "Detected format: ",
2244 &timings, true);
2245 v4l2_print_dv_timings(sd->name, "Configured format: ",
2246 &state->timings, true);
2247
2248 if (no_cp_signal(sd))
2249 return 0;
2250
2251 v4l2_info(sd, "-----Color space-----\n");
2252 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2253 rgb_quantization_range_txt[state->rgb_quantization_range]);
2254 v4l2_info(sd, "Input color space: %s\n",
2255 input_color_space_txt[reg_io_0x02 >> 4]);
2256 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2257 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2258 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2259 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2260 "enabled" : "disabled");
2261 v4l2_info(sd, "Color space conversion: %s\n",
2262 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2263
2264 if (!is_digital_input(sd))
2265 return 0;
2266
2267 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2268 v4l2_info(sd, "HDCP encrypted content: %s\n",
2269 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2270 v4l2_info(sd, "HDCP keys read: %s%s\n",
2271 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2272 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2273 if (!is_hdmi(sd))
2274 return 0;
2275
2276 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2277 audio_pll_locked ? "locked" : "not locked",
2278 audio_sample_packet_detect ? "detected" : "not detected",
2279 audio_mute ? "muted" : "enabled");
2280 if (audio_pll_locked && audio_sample_packet_detect) {
2281 v4l2_info(sd, "Audio format: %s\n",
2282 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2283 }
2284 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2285 (hdmi_read(sd, 0x5c) << 8) +
2286 (hdmi_read(sd, 0x5d) & 0xf0));
2287 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2288 (hdmi_read(sd, 0x5e) << 8) +
2289 hdmi_read(sd, 0x5f));
2290 v4l2_info(sd, "AV Mute: %s\n",
2291 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2292 v4l2_info(sd, "Deep color mode: %s\n",
2293 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2294
2295 print_avi_infoframe(sd);
2296 return 0;
2297 }
2298
2299 static int adv7842_log_status(struct v4l2_subdev *sd)
2300 {
2301 struct adv7842_state *state = to_state(sd);
2302
2303 if (state->mode == ADV7842_MODE_SDP)
2304 return adv7842_sdp_log_status(sd);
2305 return adv7842_cp_log_status(sd);
2306 }
2307
2308 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2309 {
2310 struct adv7842_state *state = to_state(sd);
2311
2312 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2313
2314 if (state->mode != ADV7842_MODE_SDP)
2315 return -ENODATA;
2316
2317 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2318 *std = 0;
2319 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2320 return 0;
2321 }
2322
2323 switch (sdp_read(sd, 0x52) & 0x0f) {
2324 case 0:
2325 /* NTSC-M/J */
2326 *std &= V4L2_STD_NTSC;
2327 break;
2328 case 2:
2329 /* NTSC-443 */
2330 *std &= V4L2_STD_NTSC_443;
2331 break;
2332 case 3:
2333 /* 60HzSECAM */
2334 *std &= V4L2_STD_SECAM;
2335 break;
2336 case 4:
2337 /* PAL-M */
2338 *std &= V4L2_STD_PAL_M;
2339 break;
2340 case 6:
2341 /* PAL-60 */
2342 *std &= V4L2_STD_PAL_60;
2343 break;
2344 case 0xc:
2345 /* PAL-CombN */
2346 *std &= V4L2_STD_PAL_Nc;
2347 break;
2348 case 0xe:
2349 /* PAL-BGHID */
2350 *std &= V4L2_STD_PAL;
2351 break;
2352 case 0xf:
2353 /* SECAM */
2354 *std &= V4L2_STD_SECAM;
2355 break;
2356 default:
2357 *std &= V4L2_STD_ALL;
2358 break;
2359 }
2360 return 0;
2361 }
2362
2363 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2364 {
2365 struct adv7842_state *state = to_state(sd);
2366
2367 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2368
2369 if (state->mode != ADV7842_MODE_SDP)
2370 return -ENODATA;
2371
2372 if (norm & V4L2_STD_ALL) {
2373 state->norm = norm;
2374 return 0;
2375 }
2376 return -EINVAL;
2377 }
2378
2379 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2380 {
2381 struct adv7842_state *state = to_state(sd);
2382
2383 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2384
2385 if (state->mode != ADV7842_MODE_SDP)
2386 return -ENODATA;
2387
2388 *norm = state->norm;
2389 return 0;
2390 }
2391
2392 /* ----------------------------------------------------------------------- */
2393
2394 static int adv7842_core_init(struct v4l2_subdev *sd,
2395 const struct adv7842_platform_data *pdata)
2396 {
2397 hdmi_write(sd, 0x48,
2398 (pdata->disable_pwrdnb ? 0x80 : 0) |
2399 (pdata->disable_cable_det_rst ? 0x40 : 0));
2400
2401 disable_input(sd);
2402
2403 /* power */
2404 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2405 io_write(sd, 0x15, 0x80); /* Power up pads */
2406
2407 /* video format */
2408 io_write(sd, 0x02,
2409 pdata->inp_color_space << 4 |
2410 pdata->alt_gamma << 3 |
2411 pdata->op_656_range << 2 |
2412 pdata->rgb_out << 1 |
2413 pdata->alt_data_sat << 0);
2414 io_write(sd, 0x03, pdata->op_format_sel);
2415 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2416 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2417 pdata->insert_av_codes << 2 |
2418 pdata->replicate_av_codes << 1 |
2419 pdata->invert_cbcr << 0);
2420
2421 /* Drive strength */
2422 io_write_and_or(sd, 0x14, 0xc0, pdata->drive_strength.data<<4 |
2423 pdata->drive_strength.clock<<2 |
2424 pdata->drive_strength.sync);
2425
2426 /* HDMI free run */
2427 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01);
2428
2429 /* TODO from platform data */
2430 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
2431 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
2432 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2433 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2434
2435 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2436 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2437
2438 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
2439
2440 if (pdata->sdp_io_sync.adjust) {
2441 const struct adv7842_sdp_io_sync_adjustment *s = &pdata->sdp_io_sync;
2442 sdp_io_write(sd, 0x94, (s->hs_beg>>8) & 0xf);
2443 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2444 sdp_io_write(sd, 0x96, (s->hs_width>>8) & 0xf);
2445 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2446 sdp_io_write(sd, 0x98, (s->de_beg>>8) & 0xf);
2447 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2448 sdp_io_write(sd, 0x9a, (s->de_end>>8) & 0xf);
2449 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2450 }
2451
2452 /* todo, improve settings for sdram */
2453 if (pdata->sd_ram_size >= 128) {
2454 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
2455 if (pdata->sd_ram_ddr) {
2456 /* SDP setup for the AD eval board */
2457 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
2458 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
2459 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2460 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2461 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2462 } else {
2463 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
2464 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
2465 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
2466 depends on memory */
2467 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
2468 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2469 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2470 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2471 }
2472 } else {
2473 /*
2474 * Manual UG-214, rev 0 is bit confusing on this bit
2475 * but a '1' disables any signal if the Ram is active.
2476 */
2477 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
2478 }
2479
2480 select_input(sd, pdata->vid_std_select);
2481
2482 enable_input(sd);
2483
2484 /* disable I2C access to internal EDID ram from HDMI DDC ports */
2485 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
2486
2487 hdmi_write(sd, 0x69, 0xa3); /* HPA manual */
2488 /* HPA disable on port A and B */
2489 io_write_and_or(sd, 0x20, 0xcf, 0x00);
2490
2491 /* LLC */
2492 /* Set phase to 16. TODO: get this from platform_data */
2493 io_write(sd, 0x19, 0x90);
2494 io_write(sd, 0x33, 0x40);
2495
2496 /* interrupts */
2497 io_write(sd, 0x40, 0xe2); /* Configure INT1 */
2498
2499 adv7842_irq_enable(sd, true);
2500
2501 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2502 }
2503
2504 /* ----------------------------------------------------------------------- */
2505
2506 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
2507 {
2508 /*
2509 * From ADV784x external Memory test.pdf
2510 *
2511 * Reset must just been performed before running test.
2512 * Recommended to reset after test.
2513 */
2514 int i;
2515 int pass = 0;
2516 int fail = 0;
2517 int complete = 0;
2518
2519 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
2520 io_write(sd, 0x01, 0x00); /* Program SDP mode */
2521 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
2522 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
2523 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
2524 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
2525 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
2526 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
2527 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
2528 io_write(sd, 0x15, 0xBA); /* Enable outputs */
2529 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
2530 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
2531
2532 mdelay(5);
2533
2534 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
2535 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
2536 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
2537 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
2538 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
2539 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
2540 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
2541 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
2542 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
2543 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
2544 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
2545
2546 mdelay(5);
2547
2548 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
2549 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
2550
2551 mdelay(20);
2552
2553 for (i = 0; i < 10; i++) {
2554 u8 result = sdp_io_read(sd, 0xdb);
2555 if (result & 0x10) {
2556 complete++;
2557 if (result & 0x20)
2558 fail++;
2559 else
2560 pass++;
2561 }
2562 mdelay(20);
2563 }
2564
2565 v4l2_dbg(1, debug, sd,
2566 "Ram Test: completed %d of %d: pass %d, fail %d\n",
2567 complete, i, pass, fail);
2568
2569 if (!complete || fail)
2570 return -EIO;
2571 return 0;
2572 }
2573
2574 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
2575 struct adv7842_platform_data *pdata)
2576 {
2577 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
2578 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
2579 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
2580 io_write(sd, 0xf4, pdata->i2c_cec << 1);
2581 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
2582
2583 io_write(sd, 0xf8, pdata->i2c_afe << 1);
2584 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
2585 io_write(sd, 0xfa, pdata->i2c_edid << 1);
2586 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
2587
2588 io_write(sd, 0xfd, pdata->i2c_cp << 1);
2589 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
2590 }
2591
2592 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
2593 {
2594 struct i2c_client *client = v4l2_get_subdevdata(sd);
2595 struct adv7842_state *state = to_state(sd);
2596 struct adv7842_platform_data *pdata = client->dev.platform_data;
2597 int ret = 0;
2598
2599 if (!pdata)
2600 return -ENODEV;
2601
2602 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
2603 v4l2_info(sd, "no sdram or no ddr sdram\n");
2604 return -EINVAL;
2605 }
2606
2607 main_reset(sd);
2608
2609 adv7842_rewrite_i2c_addresses(sd, pdata);
2610
2611 /* run ram test */
2612 ret = adv7842_ddr_ram_test(sd);
2613
2614 main_reset(sd);
2615
2616 adv7842_rewrite_i2c_addresses(sd, pdata);
2617
2618 /* and re-init chip and state */
2619 adv7842_core_init(sd, pdata);
2620
2621 disable_input(sd);
2622
2623 select_input(sd, state->vid_std_select);
2624
2625 enable_input(sd);
2626
2627 adv7842_s_dv_timings(sd, &state->timings);
2628
2629 edid_write_vga_segment(sd);
2630 edid_write_hdmi_segment(sd, 0);
2631 edid_write_hdmi_segment(sd, 1);
2632
2633 return ret;
2634 }
2635
2636 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
2637 {
2638 switch (cmd) {
2639 case ADV7842_CMD_RAM_TEST:
2640 return adv7842_command_ram_test(sd);
2641 }
2642 return -ENOTTY;
2643 }
2644
2645 /* ----------------------------------------------------------------------- */
2646
2647 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
2648 .s_ctrl = adv7842_s_ctrl,
2649 };
2650
2651 static const struct v4l2_subdev_core_ops adv7842_core_ops = {
2652 .log_status = adv7842_log_status,
2653 .g_std = adv7842_g_std,
2654 .s_std = adv7842_s_std,
2655 .ioctl = adv7842_ioctl,
2656 .interrupt_service_routine = adv7842_isr,
2657 #ifdef CONFIG_VIDEO_ADV_DEBUG
2658 .g_register = adv7842_g_register,
2659 .s_register = adv7842_s_register,
2660 #endif
2661 };
2662
2663 static const struct v4l2_subdev_video_ops adv7842_video_ops = {
2664 .s_routing = adv7842_s_routing,
2665 .querystd = adv7842_querystd,
2666 .g_input_status = adv7842_g_input_status,
2667 .s_dv_timings = adv7842_s_dv_timings,
2668 .g_dv_timings = adv7842_g_dv_timings,
2669 .query_dv_timings = adv7842_query_dv_timings,
2670 .enum_dv_timings = adv7842_enum_dv_timings,
2671 .dv_timings_cap = adv7842_dv_timings_cap,
2672 .enum_mbus_fmt = adv7842_enum_mbus_fmt,
2673 .g_mbus_fmt = adv7842_g_mbus_fmt,
2674 .try_mbus_fmt = adv7842_g_mbus_fmt,
2675 .s_mbus_fmt = adv7842_g_mbus_fmt,
2676 };
2677
2678 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
2679 .set_edid = adv7842_set_edid,
2680 };
2681
2682 static const struct v4l2_subdev_ops adv7842_ops = {
2683 .core = &adv7842_core_ops,
2684 .video = &adv7842_video_ops,
2685 .pad = &adv7842_pad_ops,
2686 };
2687
2688 /* -------------------------- custom ctrls ---------------------------------- */
2689
2690 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
2691 .ops = &adv7842_ctrl_ops,
2692 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2693 .name = "Analog Sampling Phase",
2694 .type = V4L2_CTRL_TYPE_INTEGER,
2695 .min = 0,
2696 .max = 0x1f,
2697 .step = 1,
2698 .def = 0,
2699 };
2700
2701 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
2702 .ops = &adv7842_ctrl_ops,
2703 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2704 .name = "Free Running Color, Manual",
2705 .type = V4L2_CTRL_TYPE_BOOLEAN,
2706 .max = 1,
2707 .step = 1,
2708 .def = 1,
2709 };
2710
2711 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
2712 .ops = &adv7842_ctrl_ops,
2713 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2714 .name = "Free Running Color",
2715 .type = V4L2_CTRL_TYPE_INTEGER,
2716 .max = 0xffffff,
2717 .step = 0x1,
2718 };
2719
2720
2721 static void adv7842_unregister_clients(struct adv7842_state *state)
2722 {
2723 if (state->i2c_avlink)
2724 i2c_unregister_device(state->i2c_avlink);
2725 if (state->i2c_cec)
2726 i2c_unregister_device(state->i2c_cec);
2727 if (state->i2c_infoframe)
2728 i2c_unregister_device(state->i2c_infoframe);
2729 if (state->i2c_sdp_io)
2730 i2c_unregister_device(state->i2c_sdp_io);
2731 if (state->i2c_sdp)
2732 i2c_unregister_device(state->i2c_sdp);
2733 if (state->i2c_afe)
2734 i2c_unregister_device(state->i2c_afe);
2735 if (state->i2c_repeater)
2736 i2c_unregister_device(state->i2c_repeater);
2737 if (state->i2c_edid)
2738 i2c_unregister_device(state->i2c_edid);
2739 if (state->i2c_hdmi)
2740 i2c_unregister_device(state->i2c_hdmi);
2741 if (state->i2c_cp)
2742 i2c_unregister_device(state->i2c_cp);
2743 if (state->i2c_vdp)
2744 i2c_unregister_device(state->i2c_vdp);
2745 }
2746
2747 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd,
2748 u8 addr, u8 io_reg)
2749 {
2750 struct i2c_client *client = v4l2_get_subdevdata(sd);
2751
2752 io_write(sd, io_reg, addr << 1);
2753 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2754 }
2755
2756 static int adv7842_probe(struct i2c_client *client,
2757 const struct i2c_device_id *id)
2758 {
2759 struct adv7842_state *state;
2760 struct adv7842_platform_data *pdata = client->dev.platform_data;
2761 struct v4l2_ctrl_handler *hdl;
2762 struct v4l2_subdev *sd;
2763 u16 rev;
2764 int err;
2765
2766 /* Check if the adapter supports the needed features */
2767 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2768 return -EIO;
2769
2770 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
2771 client->addr << 1);
2772
2773 if (!pdata) {
2774 v4l_err(client, "No platform data!\n");
2775 return -ENODEV;
2776 }
2777
2778 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
2779 if (!state) {
2780 v4l_err(client, "Could not allocate adv7842_state memory!\n");
2781 return -ENOMEM;
2782 }
2783
2784 sd = &state->sd;
2785 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
2786 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2787 state->connector_hdmi = pdata->connector_hdmi;
2788 state->mode = pdata->mode;
2789
2790 state->hdmi_port_a = true;
2791
2792 /* i2c access to adv7842? */
2793 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2794 adv_smbus_read_byte_data_check(client, 0xeb, false);
2795 if (rev != 0x2012) {
2796 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
2797 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2798 adv_smbus_read_byte_data_check(client, 0xeb, false);
2799 }
2800 if (rev != 0x2012) {
2801 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
2802 client->addr << 1, rev);
2803 return -ENODEV;
2804 }
2805
2806 if (pdata->chip_reset)
2807 main_reset(sd);
2808
2809 /* control handlers */
2810 hdl = &state->hdl;
2811 v4l2_ctrl_handler_init(hdl, 6);
2812
2813 /* add in ascending ID order */
2814 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2815 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2816 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2817 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2818 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2819 V4L2_CID_SATURATION, 0, 255, 1, 128);
2820 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2821 V4L2_CID_HUE, 0, 128, 1, 0);
2822
2823 /* custom controls */
2824 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2825 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
2826 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
2827 &adv7842_ctrl_analog_sampling_phase, NULL);
2828 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
2829 &adv7842_ctrl_free_run_color_manual, NULL);
2830 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
2831 &adv7842_ctrl_free_run_color, NULL);
2832 state->rgb_quantization_range_ctrl =
2833 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
2834 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2835 0, V4L2_DV_RGB_RANGE_AUTO);
2836 sd->ctrl_handler = hdl;
2837 if (hdl->error) {
2838 err = hdl->error;
2839 goto err_hdl;
2840 }
2841 state->detect_tx_5v_ctrl->is_private = true;
2842 state->rgb_quantization_range_ctrl->is_private = true;
2843 state->analog_sampling_phase_ctrl->is_private = true;
2844 state->free_run_color_ctrl_manual->is_private = true;
2845 state->free_run_color_ctrl->is_private = true;
2846
2847 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
2848 err = -ENODEV;
2849 goto err_hdl;
2850 }
2851
2852 state->i2c_avlink = adv7842_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2853 state->i2c_cec = adv7842_dummy_client(sd, pdata->i2c_cec, 0xf4);
2854 state->i2c_infoframe = adv7842_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2855 state->i2c_sdp_io = adv7842_dummy_client(sd, pdata->i2c_sdp_io, 0xf2);
2856 state->i2c_sdp = adv7842_dummy_client(sd, pdata->i2c_sdp, 0xf1);
2857 state->i2c_afe = adv7842_dummy_client(sd, pdata->i2c_afe, 0xf8);
2858 state->i2c_repeater = adv7842_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2859 state->i2c_edid = adv7842_dummy_client(sd, pdata->i2c_edid, 0xfa);
2860 state->i2c_hdmi = adv7842_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2861 state->i2c_cp = adv7842_dummy_client(sd, pdata->i2c_cp, 0xfd);
2862 state->i2c_vdp = adv7842_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2863 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2864 !state->i2c_sdp_io || !state->i2c_sdp || !state->i2c_afe ||
2865 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2866 !state->i2c_cp || !state->i2c_vdp) {
2867 err = -ENOMEM;
2868 v4l2_err(sd, "failed to create all i2c clients\n");
2869 goto err_i2c;
2870 }
2871
2872 /* work queues */
2873 state->work_queues = create_singlethread_workqueue(client->name);
2874 if (!state->work_queues) {
2875 v4l2_err(sd, "Could not create work queue\n");
2876 err = -ENOMEM;
2877 goto err_i2c;
2878 }
2879
2880 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2881 adv7842_delayed_work_enable_hotplug);
2882
2883 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2884 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2885 if (err)
2886 goto err_work_queues;
2887
2888 err = adv7842_core_init(sd, pdata);
2889 if (err)
2890 goto err_entity;
2891
2892 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2893 client->addr << 1, client->adapter->name);
2894 return 0;
2895
2896 err_entity:
2897 media_entity_cleanup(&sd->entity);
2898 err_work_queues:
2899 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2900 destroy_workqueue(state->work_queues);
2901 err_i2c:
2902 adv7842_unregister_clients(state);
2903 err_hdl:
2904 v4l2_ctrl_handler_free(hdl);
2905 return err;
2906 }
2907
2908 /* ----------------------------------------------------------------------- */
2909
2910 static int adv7842_remove(struct i2c_client *client)
2911 {
2912 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2913 struct adv7842_state *state = to_state(sd);
2914
2915 adv7842_irq_enable(sd, false);
2916
2917 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2918 destroy_workqueue(state->work_queues);
2919 v4l2_device_unregister_subdev(sd);
2920 media_entity_cleanup(&sd->entity);
2921 adv7842_unregister_clients(to_state(sd));
2922 v4l2_ctrl_handler_free(sd->ctrl_handler);
2923 return 0;
2924 }
2925
2926 /* ----------------------------------------------------------------------- */
2927
2928 static struct i2c_device_id adv7842_id[] = {
2929 { "adv7842", 0 },
2930 { }
2931 };
2932 MODULE_DEVICE_TABLE(i2c, adv7842_id);
2933
2934 /* ----------------------------------------------------------------------- */
2935
2936 static struct i2c_driver adv7842_driver = {
2937 .driver = {
2938 .owner = THIS_MODULE,
2939 .name = "adv7842",
2940 },
2941 .probe = adv7842_probe,
2942 .remove = adv7842_remove,
2943 .id_table = adv7842_id,
2944 };
2945
2946 module_i2c_driver(adv7842_driver);
Linux kernel - Deliverables
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