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Merge remote-tracking branch 'regmap/fix/rbtree' into regmap-linus
[deliverable/linux.git] / drivers / media / platform / s5p-mfc / s5p_mfc.c
1 /*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
24 #include <linux/of.h>
25 #include <linux/of_reserved_mem.h>
26 #include <media/videobuf2-v4l2.h>
27 #include "s5p_mfc_common.h"
28 #include "s5p_mfc_ctrl.h"
29 #include "s5p_mfc_debug.h"
30 #include "s5p_mfc_dec.h"
31 #include "s5p_mfc_enc.h"
32 #include "s5p_mfc_intr.h"
33 #include "s5p_mfc_iommu.h"
34 #include "s5p_mfc_opr.h"
35 #include "s5p_mfc_cmd.h"
36 #include "s5p_mfc_pm.h"
37
38 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
39 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
40
41 int mfc_debug_level;
42 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
43 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
44
45 /* Helper functions for interrupt processing */
46
47 /* Remove from hw execution round robin */
48 void clear_work_bit(struct s5p_mfc_ctx *ctx)
49 {
50 struct s5p_mfc_dev *dev = ctx->dev;
51
52 spin_lock(&dev->condlock);
53 __clear_bit(ctx->num, &dev->ctx_work_bits);
54 spin_unlock(&dev->condlock);
55 }
56
57 /* Add to hw execution round robin */
58 void set_work_bit(struct s5p_mfc_ctx *ctx)
59 {
60 struct s5p_mfc_dev *dev = ctx->dev;
61
62 spin_lock(&dev->condlock);
63 __set_bit(ctx->num, &dev->ctx_work_bits);
64 spin_unlock(&dev->condlock);
65 }
66
67 /* Remove from hw execution round robin */
68 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
69 {
70 struct s5p_mfc_dev *dev = ctx->dev;
71 unsigned long flags;
72
73 spin_lock_irqsave(&dev->condlock, flags);
74 __clear_bit(ctx->num, &dev->ctx_work_bits);
75 spin_unlock_irqrestore(&dev->condlock, flags);
76 }
77
78 /* Add to hw execution round robin */
79 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
80 {
81 struct s5p_mfc_dev *dev = ctx->dev;
82 unsigned long flags;
83
84 spin_lock_irqsave(&dev->condlock, flags);
85 __set_bit(ctx->num, &dev->ctx_work_bits);
86 spin_unlock_irqrestore(&dev->condlock, flags);
87 }
88
89 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
90 {
91 unsigned long flags;
92 int ctx;
93
94 spin_lock_irqsave(&dev->condlock, flags);
95 ctx = dev->curr_ctx;
96 do {
97 ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
98 if (ctx == dev->curr_ctx) {
99 if (!test_bit(ctx, &dev->ctx_work_bits))
100 ctx = -EAGAIN;
101 break;
102 }
103 } while (!test_bit(ctx, &dev->ctx_work_bits));
104 spin_unlock_irqrestore(&dev->condlock, flags);
105
106 return ctx;
107 }
108
109 /* Wake up context wait_queue */
110 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
111 unsigned int err)
112 {
113 ctx->int_cond = 1;
114 ctx->int_type = reason;
115 ctx->int_err = err;
116 wake_up(&ctx->queue);
117 }
118
119 /* Wake up device wait_queue */
120 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
121 unsigned int err)
122 {
123 dev->int_cond = 1;
124 dev->int_type = reason;
125 dev->int_err = err;
126 wake_up(&dev->queue);
127 }
128
129 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
130 {
131 struct s5p_mfc_buf *b;
132 int i;
133
134 while (!list_empty(lh)) {
135 b = list_entry(lh->next, struct s5p_mfc_buf, list);
136 for (i = 0; i < b->b->vb2_buf.num_planes; i++)
137 vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
138 vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
139 list_del(&b->list);
140 }
141 }
142
143 static void s5p_mfc_watchdog(unsigned long arg)
144 {
145 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
146
147 if (test_bit(0, &dev->hw_lock))
148 atomic_inc(&dev->watchdog_cnt);
149 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
150 /* This means that hw is busy and no interrupts were
151 * generated by hw for the Nth time of running this
152 * watchdog timer. This usually means a serious hw
153 * error. Now it is time to kill all instances and
154 * reset the MFC. */
155 mfc_err("Time out during waiting for HW\n");
156 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
157 }
158 dev->watchdog_timer.expires = jiffies +
159 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
160 add_timer(&dev->watchdog_timer);
161 }
162
163 static void s5p_mfc_watchdog_worker(struct work_struct *work)
164 {
165 struct s5p_mfc_dev *dev;
166 struct s5p_mfc_ctx *ctx;
167 unsigned long flags;
168 int mutex_locked;
169 int i, ret;
170
171 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
172
173 mfc_err("Driver timeout error handling\n");
174 /* Lock the mutex that protects open and release.
175 * This is necessary as they may load and unload firmware. */
176 mutex_locked = mutex_trylock(&dev->mfc_mutex);
177 if (!mutex_locked)
178 mfc_err("Error: some instance may be closing/opening\n");
179 spin_lock_irqsave(&dev->irqlock, flags);
180
181 s5p_mfc_clock_off();
182
183 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
184 ctx = dev->ctx[i];
185 if (!ctx)
186 continue;
187 ctx->state = MFCINST_ERROR;
188 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
189 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
190 clear_work_bit(ctx);
191 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
192 }
193 clear_bit(0, &dev->hw_lock);
194 spin_unlock_irqrestore(&dev->irqlock, flags);
195
196 /* De-init MFC */
197 s5p_mfc_deinit_hw(dev);
198
199 /* Double check if there is at least one instance running.
200 * If no instance is in memory than no firmware should be present */
201 if (dev->num_inst > 0) {
202 ret = s5p_mfc_load_firmware(dev);
203 if (ret) {
204 mfc_err("Failed to reload FW\n");
205 goto unlock;
206 }
207 s5p_mfc_clock_on();
208 ret = s5p_mfc_init_hw(dev);
209 if (ret)
210 mfc_err("Failed to reinit FW\n");
211 }
212 unlock:
213 if (mutex_locked)
214 mutex_unlock(&dev->mfc_mutex);
215 }
216
217 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
218 {
219 struct s5p_mfc_buf *dst_buf;
220 struct s5p_mfc_dev *dev = ctx->dev;
221
222 ctx->state = MFCINST_FINISHED;
223 ctx->sequence++;
224 while (!list_empty(&ctx->dst_queue)) {
225 dst_buf = list_entry(ctx->dst_queue.next,
226 struct s5p_mfc_buf, list);
227 mfc_debug(2, "Cleaning up buffer: %d\n",
228 dst_buf->b->vb2_buf.index);
229 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
230 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
231 list_del(&dst_buf->list);
232 dst_buf->flags |= MFC_BUF_FLAG_EOS;
233 ctx->dst_queue_cnt--;
234 dst_buf->b->sequence = (ctx->sequence++);
235
236 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
237 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
238 dst_buf->b->field = V4L2_FIELD_NONE;
239 else
240 dst_buf->b->field = V4L2_FIELD_INTERLACED;
241 dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
242
243 ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
244 vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
245 }
246 }
247
248 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
249 {
250 struct s5p_mfc_dev *dev = ctx->dev;
251 struct s5p_mfc_buf *dst_buf, *src_buf;
252 size_t dec_y_addr;
253 unsigned int frame_type;
254
255 /* Make sure we actually have a new frame before continuing. */
256 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
257 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
258 return;
259 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
260
261 /* Copy timestamp / timecode from decoded src to dst and set
262 appropriate flags. */
263 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
264 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
265 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
266 == dec_y_addr) {
267 dst_buf->b->timecode =
268 src_buf->b->timecode;
269 dst_buf->b->vb2_buf.timestamp =
270 src_buf->b->vb2_buf.timestamp;
271 dst_buf->b->flags &=
272 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
273 dst_buf->b->flags |=
274 src_buf->b->flags
275 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
276 switch (frame_type) {
277 case S5P_FIMV_DECODE_FRAME_I_FRAME:
278 dst_buf->b->flags |=
279 V4L2_BUF_FLAG_KEYFRAME;
280 break;
281 case S5P_FIMV_DECODE_FRAME_P_FRAME:
282 dst_buf->b->flags |=
283 V4L2_BUF_FLAG_PFRAME;
284 break;
285 case S5P_FIMV_DECODE_FRAME_B_FRAME:
286 dst_buf->b->flags |=
287 V4L2_BUF_FLAG_BFRAME;
288 break;
289 default:
290 /* Don't know how to handle
291 S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
292 mfc_debug(2, "Unexpected frame type: %d\n",
293 frame_type);
294 }
295 break;
296 }
297 }
298 }
299
300 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
301 {
302 struct s5p_mfc_dev *dev = ctx->dev;
303 struct s5p_mfc_buf *dst_buf;
304 size_t dspl_y_addr;
305 unsigned int frame_type;
306
307 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
308 if (IS_MFCV6_PLUS(dev))
309 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
310 get_disp_frame_type, ctx);
311 else
312 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
313 get_dec_frame_type, dev);
314
315 /* If frame is same as previous then skip and do not dequeue */
316 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
317 if (!ctx->after_packed_pb)
318 ctx->sequence++;
319 ctx->after_packed_pb = 0;
320 return;
321 }
322 ctx->sequence++;
323 /* The MFC returns address of the buffer, now we have to
324 * check which videobuf does it correspond to */
325 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
326 /* Check if this is the buffer we're looking for */
327 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
328 == dspl_y_addr) {
329 list_del(&dst_buf->list);
330 ctx->dst_queue_cnt--;
331 dst_buf->b->sequence = ctx->sequence;
332 if (s5p_mfc_hw_call(dev->mfc_ops,
333 get_pic_type_top, ctx) ==
334 s5p_mfc_hw_call(dev->mfc_ops,
335 get_pic_type_bot, ctx))
336 dst_buf->b->field = V4L2_FIELD_NONE;
337 else
338 dst_buf->b->field =
339 V4L2_FIELD_INTERLACED;
340 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
341 ctx->luma_size);
342 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
343 ctx->chroma_size);
344 clear_bit(dst_buf->b->vb2_buf.index,
345 &ctx->dec_dst_flag);
346
347 vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
348 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
349
350 break;
351 }
352 }
353 }
354
355 /* Handle frame decoding interrupt */
356 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
357 unsigned int reason, unsigned int err)
358 {
359 struct s5p_mfc_dev *dev = ctx->dev;
360 unsigned int dst_frame_status;
361 unsigned int dec_frame_status;
362 struct s5p_mfc_buf *src_buf;
363 unsigned int res_change;
364
365 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
366 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
367 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
368 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
369 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
370 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
371 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
372 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
373 if (ctx->state == MFCINST_RES_CHANGE_INIT)
374 ctx->state = MFCINST_RES_CHANGE_FLUSH;
375 if (res_change == S5P_FIMV_RES_INCREASE ||
376 res_change == S5P_FIMV_RES_DECREASE) {
377 ctx->state = MFCINST_RES_CHANGE_INIT;
378 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
379 wake_up_ctx(ctx, reason, err);
380 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
381 s5p_mfc_clock_off();
382 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
383 return;
384 }
385 if (ctx->dpb_flush_flag)
386 ctx->dpb_flush_flag = 0;
387
388 /* All frames remaining in the buffer have been extracted */
389 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
390 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
391 static const struct v4l2_event ev_src_ch = {
392 .type = V4L2_EVENT_SOURCE_CHANGE,
393 .u.src_change.changes =
394 V4L2_EVENT_SRC_CH_RESOLUTION,
395 };
396
397 s5p_mfc_handle_frame_all_extracted(ctx);
398 ctx->state = MFCINST_RES_CHANGE_END;
399 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
400
401 goto leave_handle_frame;
402 } else {
403 s5p_mfc_handle_frame_all_extracted(ctx);
404 }
405 }
406
407 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
408 s5p_mfc_handle_frame_copy_time(ctx);
409
410 /* A frame has been decoded and is in the buffer */
411 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
412 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
413 s5p_mfc_handle_frame_new(ctx, err);
414 } else {
415 mfc_debug(2, "No frame decode\n");
416 }
417 /* Mark source buffer as complete */
418 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
419 && !list_empty(&ctx->src_queue)) {
420 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
421 list);
422 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
423 get_consumed_stream, dev);
424 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
425 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
426 ctx->consumed_stream + STUFF_BYTE <
427 src_buf->b->vb2_buf.planes[0].bytesused) {
428 /* Run MFC again on the same buffer */
429 mfc_debug(2, "Running again the same buffer\n");
430 ctx->after_packed_pb = 1;
431 } else {
432 mfc_debug(2, "MFC needs next buffer\n");
433 ctx->consumed_stream = 0;
434 if (src_buf->flags & MFC_BUF_FLAG_EOS)
435 ctx->state = MFCINST_FINISHING;
436 list_del(&src_buf->list);
437 ctx->src_queue_cnt--;
438 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
439 vb2_buffer_done(&src_buf->b->vb2_buf,
440 VB2_BUF_STATE_ERROR);
441 else
442 vb2_buffer_done(&src_buf->b->vb2_buf,
443 VB2_BUF_STATE_DONE);
444 }
445 }
446 leave_handle_frame:
447 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
448 || ctx->dst_queue_cnt < ctx->pb_count)
449 clear_work_bit(ctx);
450 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
451 wake_up_ctx(ctx, reason, err);
452 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
453 s5p_mfc_clock_off();
454 /* if suspending, wake up device and do not try_run again*/
455 if (test_bit(0, &dev->enter_suspend))
456 wake_up_dev(dev, reason, err);
457 else
458 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
459 }
460
461 /* Error handling for interrupt */
462 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
463 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
464 {
465 mfc_err("Interrupt Error: %08x\n", err);
466
467 if (ctx != NULL) {
468 /* Error recovery is dependent on the state of context */
469 switch (ctx->state) {
470 case MFCINST_RES_CHANGE_INIT:
471 case MFCINST_RES_CHANGE_FLUSH:
472 case MFCINST_RES_CHANGE_END:
473 case MFCINST_FINISHING:
474 case MFCINST_FINISHED:
475 case MFCINST_RUNNING:
476 /* It is highly probable that an error occurred
477 * while decoding a frame */
478 clear_work_bit(ctx);
479 ctx->state = MFCINST_ERROR;
480 /* Mark all dst buffers as having an error */
481 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
482 /* Mark all src buffers as having an error */
483 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
484 wake_up_ctx(ctx, reason, err);
485 break;
486 default:
487 clear_work_bit(ctx);
488 ctx->state = MFCINST_ERROR;
489 wake_up_ctx(ctx, reason, err);
490 break;
491 }
492 }
493 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
494 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
495 s5p_mfc_clock_off();
496 wake_up_dev(dev, reason, err);
497 return;
498 }
499
500 /* Header parsing interrupt handling */
501 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
502 unsigned int reason, unsigned int err)
503 {
504 struct s5p_mfc_dev *dev;
505
506 if (ctx == NULL)
507 return;
508 dev = ctx->dev;
509 if (ctx->c_ops->post_seq_start) {
510 if (ctx->c_ops->post_seq_start(ctx))
511 mfc_err("post_seq_start() failed\n");
512 } else {
513 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
514 dev);
515 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
516 dev);
517
518 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
519
520 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
521 dev);
522 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
523 dev);
524 if (ctx->img_width == 0 || ctx->img_height == 0)
525 ctx->state = MFCINST_ERROR;
526 else
527 ctx->state = MFCINST_HEAD_PARSED;
528
529 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
530 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
531 !list_empty(&ctx->src_queue)) {
532 struct s5p_mfc_buf *src_buf;
533 src_buf = list_entry(ctx->src_queue.next,
534 struct s5p_mfc_buf, list);
535 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
536 dev) <
537 src_buf->b->vb2_buf.planes[0].bytesused)
538 ctx->head_processed = 0;
539 else
540 ctx->head_processed = 1;
541 } else {
542 ctx->head_processed = 1;
543 }
544 }
545 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
546 clear_work_bit(ctx);
547 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
548 s5p_mfc_clock_off();
549 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
550 wake_up_ctx(ctx, reason, err);
551 }
552
553 /* Header parsing interrupt handling */
554 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
555 unsigned int reason, unsigned int err)
556 {
557 struct s5p_mfc_buf *src_buf;
558 struct s5p_mfc_dev *dev;
559
560 if (ctx == NULL)
561 return;
562 dev = ctx->dev;
563 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
564 ctx->int_type = reason;
565 ctx->int_err = err;
566 ctx->int_cond = 1;
567 clear_work_bit(ctx);
568 if (err == 0) {
569 ctx->state = MFCINST_RUNNING;
570 if (!ctx->dpb_flush_flag && ctx->head_processed) {
571 if (!list_empty(&ctx->src_queue)) {
572 src_buf = list_entry(ctx->src_queue.next,
573 struct s5p_mfc_buf, list);
574 list_del(&src_buf->list);
575 ctx->src_queue_cnt--;
576 vb2_buffer_done(&src_buf->b->vb2_buf,
577 VB2_BUF_STATE_DONE);
578 }
579 } else {
580 ctx->dpb_flush_flag = 0;
581 }
582 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
583
584 s5p_mfc_clock_off();
585
586 wake_up(&ctx->queue);
587 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
588 } else {
589 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
590
591 s5p_mfc_clock_off();
592
593 wake_up(&ctx->queue);
594 }
595 }
596
597 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
598 {
599 struct s5p_mfc_dev *dev = ctx->dev;
600 struct s5p_mfc_buf *mb_entry;
601
602 mfc_debug(2, "Stream completed\n");
603
604 ctx->state = MFCINST_FINISHED;
605
606 if (!list_empty(&ctx->dst_queue)) {
607 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
608 list);
609 list_del(&mb_entry->list);
610 ctx->dst_queue_cnt--;
611 vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
612 vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
613 }
614
615 clear_work_bit(ctx);
616
617 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
618
619 s5p_mfc_clock_off();
620 wake_up(&ctx->queue);
621 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
622 }
623
624 /* Interrupt processing */
625 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
626 {
627 struct s5p_mfc_dev *dev = priv;
628 struct s5p_mfc_ctx *ctx;
629 unsigned int reason;
630 unsigned int err;
631
632 mfc_debug_enter();
633 /* Reset the timeout watchdog */
634 atomic_set(&dev->watchdog_cnt, 0);
635 spin_lock(&dev->irqlock);
636 ctx = dev->ctx[dev->curr_ctx];
637 /* Get the reason of interrupt and the error code */
638 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
639 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
640 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
641 switch (reason) {
642 case S5P_MFC_R2H_CMD_ERR_RET:
643 /* An error has occurred */
644 if (ctx->state == MFCINST_RUNNING &&
645 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
646 dev->warn_start)
647 s5p_mfc_handle_frame(ctx, reason, err);
648 else
649 s5p_mfc_handle_error(dev, ctx, reason, err);
650 clear_bit(0, &dev->enter_suspend);
651 break;
652
653 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
654 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
655 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
656 if (ctx->c_ops->post_frame_start) {
657 if (ctx->c_ops->post_frame_start(ctx))
658 mfc_err("post_frame_start() failed\n");
659
660 if (ctx->state == MFCINST_FINISHING &&
661 list_empty(&ctx->ref_queue)) {
662 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
663 s5p_mfc_handle_stream_complete(ctx);
664 break;
665 }
666 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
667 wake_up_ctx(ctx, reason, err);
668 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
669 s5p_mfc_clock_off();
670 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
671 } else {
672 s5p_mfc_handle_frame(ctx, reason, err);
673 }
674 break;
675
676 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
677 s5p_mfc_handle_seq_done(ctx, reason, err);
678 break;
679
680 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
681 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
682 ctx->state = MFCINST_GOT_INST;
683 clear_work_bit(ctx);
684 wake_up(&ctx->queue);
685 goto irq_cleanup_hw;
686
687 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
688 clear_work_bit(ctx);
689 ctx->inst_no = MFC_NO_INSTANCE_SET;
690 ctx->state = MFCINST_FREE;
691 wake_up(&ctx->queue);
692 goto irq_cleanup_hw;
693
694 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
695 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
696 case S5P_MFC_R2H_CMD_SLEEP_RET:
697 case S5P_MFC_R2H_CMD_WAKEUP_RET:
698 if (ctx)
699 clear_work_bit(ctx);
700 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
701 wake_up_dev(dev, reason, err);
702 clear_bit(0, &dev->hw_lock);
703 clear_bit(0, &dev->enter_suspend);
704 break;
705
706 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
707 s5p_mfc_handle_init_buffers(ctx, reason, err);
708 break;
709
710 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
711 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
712 ctx->int_type = reason;
713 ctx->int_err = err;
714 s5p_mfc_handle_stream_complete(ctx);
715 break;
716
717 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
718 clear_work_bit(ctx);
719 ctx->state = MFCINST_RUNNING;
720 wake_up(&ctx->queue);
721 goto irq_cleanup_hw;
722
723 default:
724 mfc_debug(2, "Unknown int reason\n");
725 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
726 }
727 spin_unlock(&dev->irqlock);
728 mfc_debug_leave();
729 return IRQ_HANDLED;
730 irq_cleanup_hw:
731 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
732 ctx->int_type = reason;
733 ctx->int_err = err;
734 ctx->int_cond = 1;
735 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
736 mfc_err("Failed to unlock hw\n");
737
738 s5p_mfc_clock_off();
739
740 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
741 spin_unlock(&dev->irqlock);
742 mfc_debug(2, "Exit via irq_cleanup_hw\n");
743 return IRQ_HANDLED;
744 }
745
746 /* Open an MFC node */
747 static int s5p_mfc_open(struct file *file)
748 {
749 struct video_device *vdev = video_devdata(file);
750 struct s5p_mfc_dev *dev = video_drvdata(file);
751 struct s5p_mfc_ctx *ctx = NULL;
752 struct vb2_queue *q;
753 int ret = 0;
754
755 mfc_debug_enter();
756 if (mutex_lock_interruptible(&dev->mfc_mutex))
757 return -ERESTARTSYS;
758 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
759 /* Allocate memory for context */
760 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
761 if (!ctx) {
762 mfc_err("Not enough memory\n");
763 ret = -ENOMEM;
764 goto err_alloc;
765 }
766 v4l2_fh_init(&ctx->fh, vdev);
767 file->private_data = &ctx->fh;
768 v4l2_fh_add(&ctx->fh);
769 ctx->dev = dev;
770 INIT_LIST_HEAD(&ctx->src_queue);
771 INIT_LIST_HEAD(&ctx->dst_queue);
772 ctx->src_queue_cnt = 0;
773 ctx->dst_queue_cnt = 0;
774 /* Get context number */
775 ctx->num = 0;
776 while (dev->ctx[ctx->num]) {
777 ctx->num++;
778 if (ctx->num >= MFC_NUM_CONTEXTS) {
779 mfc_err("Too many open contexts\n");
780 ret = -EBUSY;
781 goto err_no_ctx;
782 }
783 }
784 /* Mark context as idle */
785 clear_work_bit_irqsave(ctx);
786 dev->ctx[ctx->num] = ctx;
787 if (vdev == dev->vfd_dec) {
788 ctx->type = MFCINST_DECODER;
789 ctx->c_ops = get_dec_codec_ops();
790 s5p_mfc_dec_init(ctx);
791 /* Setup ctrl handler */
792 ret = s5p_mfc_dec_ctrls_setup(ctx);
793 if (ret) {
794 mfc_err("Failed to setup mfc controls\n");
795 goto err_ctrls_setup;
796 }
797 } else if (vdev == dev->vfd_enc) {
798 ctx->type = MFCINST_ENCODER;
799 ctx->c_ops = get_enc_codec_ops();
800 /* only for encoder */
801 INIT_LIST_HEAD(&ctx->ref_queue);
802 ctx->ref_queue_cnt = 0;
803 s5p_mfc_enc_init(ctx);
804 /* Setup ctrl handler */
805 ret = s5p_mfc_enc_ctrls_setup(ctx);
806 if (ret) {
807 mfc_err("Failed to setup mfc controls\n");
808 goto err_ctrls_setup;
809 }
810 } else {
811 ret = -ENOENT;
812 goto err_bad_node;
813 }
814 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
815 ctx->inst_no = MFC_NO_INSTANCE_SET;
816 /* Load firmware if this is the first instance */
817 if (dev->num_inst == 1) {
818 dev->watchdog_timer.expires = jiffies +
819 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
820 add_timer(&dev->watchdog_timer);
821 ret = s5p_mfc_power_on();
822 if (ret < 0) {
823 mfc_err("power on failed\n");
824 goto err_pwr_enable;
825 }
826 s5p_mfc_clock_on();
827 ret = s5p_mfc_load_firmware(dev);
828 if (ret) {
829 s5p_mfc_clock_off();
830 goto err_load_fw;
831 }
832 /* Init the FW */
833 ret = s5p_mfc_init_hw(dev);
834 s5p_mfc_clock_off();
835 if (ret)
836 goto err_init_hw;
837 }
838 /* Init videobuf2 queue for CAPTURE */
839 q = &ctx->vq_dst;
840 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
841 q->drv_priv = &ctx->fh;
842 q->lock = &dev->mfc_mutex;
843 if (vdev == dev->vfd_dec) {
844 q->io_modes = VB2_MMAP;
845 q->ops = get_dec_queue_ops();
846 } else if (vdev == dev->vfd_enc) {
847 q->io_modes = VB2_MMAP | VB2_USERPTR;
848 q->ops = get_enc_queue_ops();
849 } else {
850 ret = -ENOENT;
851 goto err_queue_init;
852 }
853 q->mem_ops = &vb2_dma_contig_memops;
854 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
855 ret = vb2_queue_init(q);
856 if (ret) {
857 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
858 goto err_queue_init;
859 }
860 /* Init videobuf2 queue for OUTPUT */
861 q = &ctx->vq_src;
862 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
863 q->io_modes = VB2_MMAP;
864 q->drv_priv = &ctx->fh;
865 q->lock = &dev->mfc_mutex;
866 if (vdev == dev->vfd_dec) {
867 q->io_modes = VB2_MMAP;
868 q->ops = get_dec_queue_ops();
869 } else if (vdev == dev->vfd_enc) {
870 q->io_modes = VB2_MMAP | VB2_USERPTR;
871 q->ops = get_enc_queue_ops();
872 } else {
873 ret = -ENOENT;
874 goto err_queue_init;
875 }
876 /* One way to indicate end-of-stream for MFC is to set the
877 * bytesused == 0. However by default videobuf2 handles bytesused
878 * equal to 0 as a special case and changes its value to the size
879 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
880 * will keep the value of bytesused intact.
881 */
882 q->allow_zero_bytesused = 1;
883 q->mem_ops = &vb2_dma_contig_memops;
884 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
885 ret = vb2_queue_init(q);
886 if (ret) {
887 mfc_err("Failed to initialize videobuf2 queue(output)\n");
888 goto err_queue_init;
889 }
890 init_waitqueue_head(&ctx->queue);
891 mutex_unlock(&dev->mfc_mutex);
892 mfc_debug_leave();
893 return ret;
894 /* Deinit when failure occurred */
895 err_queue_init:
896 if (dev->num_inst == 1)
897 s5p_mfc_deinit_hw(dev);
898 err_init_hw:
899 err_load_fw:
900 err_pwr_enable:
901 if (dev->num_inst == 1) {
902 if (s5p_mfc_power_off() < 0)
903 mfc_err("power off failed\n");
904 del_timer_sync(&dev->watchdog_timer);
905 }
906 err_ctrls_setup:
907 s5p_mfc_dec_ctrls_delete(ctx);
908 err_bad_node:
909 dev->ctx[ctx->num] = NULL;
910 err_no_ctx:
911 v4l2_fh_del(&ctx->fh);
912 v4l2_fh_exit(&ctx->fh);
913 kfree(ctx);
914 err_alloc:
915 dev->num_inst--;
916 mutex_unlock(&dev->mfc_mutex);
917 mfc_debug_leave();
918 return ret;
919 }
920
921 /* Release MFC context */
922 static int s5p_mfc_release(struct file *file)
923 {
924 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
925 struct s5p_mfc_dev *dev = ctx->dev;
926
927 mfc_debug_enter();
928 mutex_lock(&dev->mfc_mutex);
929 s5p_mfc_clock_on();
930 vb2_queue_release(&ctx->vq_src);
931 vb2_queue_release(&ctx->vq_dst);
932 /* Mark context as idle */
933 clear_work_bit_irqsave(ctx);
934 /* If instance was initialised and not yet freed,
935 * return instance and free resources */
936 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
937 mfc_debug(2, "Has to free instance\n");
938 s5p_mfc_close_mfc_inst(dev, ctx);
939 }
940 /* hardware locking scheme */
941 if (dev->curr_ctx == ctx->num)
942 clear_bit(0, &dev->hw_lock);
943 dev->num_inst--;
944 if (dev->num_inst == 0) {
945 mfc_debug(2, "Last instance\n");
946 s5p_mfc_deinit_hw(dev);
947 del_timer_sync(&dev->watchdog_timer);
948 if (s5p_mfc_power_off() < 0)
949 mfc_err("Power off failed\n");
950 }
951 mfc_debug(2, "Shutting down clock\n");
952 s5p_mfc_clock_off();
953 dev->ctx[ctx->num] = NULL;
954 s5p_mfc_dec_ctrls_delete(ctx);
955 v4l2_fh_del(&ctx->fh);
956 v4l2_fh_exit(&ctx->fh);
957 kfree(ctx);
958 mfc_debug_leave();
959 mutex_unlock(&dev->mfc_mutex);
960 return 0;
961 }
962
963 /* Poll */
964 static unsigned int s5p_mfc_poll(struct file *file,
965 struct poll_table_struct *wait)
966 {
967 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
968 struct s5p_mfc_dev *dev = ctx->dev;
969 struct vb2_queue *src_q, *dst_q;
970 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
971 unsigned int rc = 0;
972 unsigned long flags;
973
974 mutex_lock(&dev->mfc_mutex);
975 src_q = &ctx->vq_src;
976 dst_q = &ctx->vq_dst;
977 /*
978 * There has to be at least one buffer queued on each queued_list, which
979 * means either in driver already or waiting for driver to claim it
980 * and start processing.
981 */
982 if ((!src_q->streaming || list_empty(&src_q->queued_list))
983 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
984 rc = POLLERR;
985 goto end;
986 }
987 mutex_unlock(&dev->mfc_mutex);
988 poll_wait(file, &ctx->fh.wait, wait);
989 poll_wait(file, &src_q->done_wq, wait);
990 poll_wait(file, &dst_q->done_wq, wait);
991 mutex_lock(&dev->mfc_mutex);
992 if (v4l2_event_pending(&ctx->fh))
993 rc |= POLLPRI;
994 spin_lock_irqsave(&src_q->done_lock, flags);
995 if (!list_empty(&src_q->done_list))
996 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
997 done_entry);
998 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
999 || src_vb->state == VB2_BUF_STATE_ERROR))
1000 rc |= POLLOUT | POLLWRNORM;
1001 spin_unlock_irqrestore(&src_q->done_lock, flags);
1002 spin_lock_irqsave(&dst_q->done_lock, flags);
1003 if (!list_empty(&dst_q->done_list))
1004 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1005 done_entry);
1006 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1007 || dst_vb->state == VB2_BUF_STATE_ERROR))
1008 rc |= POLLIN | POLLRDNORM;
1009 spin_unlock_irqrestore(&dst_q->done_lock, flags);
1010 end:
1011 mutex_unlock(&dev->mfc_mutex);
1012 return rc;
1013 }
1014
1015 /* Mmap */
1016 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1017 {
1018 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1019 struct s5p_mfc_dev *dev = ctx->dev;
1020 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1021 int ret;
1022
1023 if (mutex_lock_interruptible(&dev->mfc_mutex))
1024 return -ERESTARTSYS;
1025 if (offset < DST_QUEUE_OFF_BASE) {
1026 mfc_debug(2, "mmaping source\n");
1027 ret = vb2_mmap(&ctx->vq_src, vma);
1028 } else { /* capture */
1029 mfc_debug(2, "mmaping destination\n");
1030 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1031 ret = vb2_mmap(&ctx->vq_dst, vma);
1032 }
1033 mutex_unlock(&dev->mfc_mutex);
1034 return ret;
1035 }
1036
1037 /* v4l2 ops */
1038 static const struct v4l2_file_operations s5p_mfc_fops = {
1039 .owner = THIS_MODULE,
1040 .open = s5p_mfc_open,
1041 .release = s5p_mfc_release,
1042 .poll = s5p_mfc_poll,
1043 .unlocked_ioctl = video_ioctl2,
1044 .mmap = s5p_mfc_mmap,
1045 };
1046
1047 /* DMA memory related helper functions */
1048 static void s5p_mfc_memdev_release(struct device *dev)
1049 {
1050 of_reserved_mem_device_release(dev);
1051 }
1052
1053 static struct device *s5p_mfc_alloc_memdev(struct device *dev,
1054 const char *name, unsigned int idx)
1055 {
1056 struct device *child;
1057 int ret;
1058
1059 child = devm_kzalloc(dev, sizeof(struct device), GFP_KERNEL);
1060 if (!child)
1061 return NULL;
1062
1063 device_initialize(child);
1064 dev_set_name(child, "%s:%s", dev_name(dev), name);
1065 child->parent = dev;
1066 child->bus = dev->bus;
1067 child->coherent_dma_mask = dev->coherent_dma_mask;
1068 child->dma_mask = dev->dma_mask;
1069 child->release = s5p_mfc_memdev_release;
1070
1071 if (device_add(child) == 0) {
1072 ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
1073 idx);
1074 if (ret == 0)
1075 return child;
1076 }
1077
1078 put_device(child);
1079 return NULL;
1080 }
1081
1082 static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1083 {
1084 struct device *dev = &mfc_dev->plat_dev->dev;
1085
1086 /*
1087 * When IOMMU is available, we cannot use the default configuration,
1088 * because of MFC firmware requirements: address space limited to
1089 * 256M and non-zero default start address.
1090 * This is still simplified, not optimal configuration, but for now
1091 * IOMMU core doesn't allow to configure device's IOMMUs channel
1092 * separately.
1093 */
1094 if (exynos_is_iommu_available(dev)) {
1095 int ret = exynos_configure_iommu(dev, S5P_MFC_IOMMU_DMA_BASE,
1096 S5P_MFC_IOMMU_DMA_SIZE);
1097 if (ret == 0)
1098 mfc_dev->mem_dev_l = mfc_dev->mem_dev_r = dev;
1099 return ret;
1100 }
1101
1102 /*
1103 * Create and initialize virtual devices for accessing
1104 * reserved memory regions.
1105 */
1106 mfc_dev->mem_dev_l = s5p_mfc_alloc_memdev(dev, "left",
1107 MFC_BANK1_ALLOC_CTX);
1108 if (!mfc_dev->mem_dev_l)
1109 return -ENODEV;
1110 mfc_dev->mem_dev_r = s5p_mfc_alloc_memdev(dev, "right",
1111 MFC_BANK2_ALLOC_CTX);
1112 if (!mfc_dev->mem_dev_r) {
1113 device_unregister(mfc_dev->mem_dev_l);
1114 return -ENODEV;
1115 }
1116
1117 return 0;
1118 }
1119
1120 static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1121 {
1122 struct device *dev = &mfc_dev->plat_dev->dev;
1123
1124 if (exynos_is_iommu_available(dev)) {
1125 exynos_unconfigure_iommu(dev);
1126 return;
1127 }
1128
1129 device_unregister(mfc_dev->mem_dev_l);
1130 device_unregister(mfc_dev->mem_dev_r);
1131 }
1132
1133 static void *mfc_get_drv_data(struct platform_device *pdev);
1134
1135 /* MFC probe function */
1136 static int s5p_mfc_probe(struct platform_device *pdev)
1137 {
1138 struct s5p_mfc_dev *dev;
1139 struct video_device *vfd;
1140 struct resource *res;
1141 int ret;
1142
1143 pr_debug("%s++\n", __func__);
1144 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1145 if (!dev) {
1146 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1147 return -ENOMEM;
1148 }
1149
1150 spin_lock_init(&dev->irqlock);
1151 spin_lock_init(&dev->condlock);
1152 dev->plat_dev = pdev;
1153 if (!dev->plat_dev) {
1154 dev_err(&pdev->dev, "No platform data specified\n");
1155 return -ENODEV;
1156 }
1157
1158 dev->variant = mfc_get_drv_data(pdev);
1159
1160 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1161 if (res == NULL) {
1162 dev_err(&pdev->dev, "failed to get io resource\n");
1163 return -ENOENT;
1164 }
1165 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1166 if (IS_ERR(dev->regs_base))
1167 return PTR_ERR(dev->regs_base);
1168
1169 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1170 if (res == NULL) {
1171 dev_err(&pdev->dev, "failed to get irq resource\n");
1172 return -ENOENT;
1173 }
1174 dev->irq = res->start;
1175 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1176 0, pdev->name, dev);
1177 if (ret) {
1178 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1179 return ret;
1180 }
1181
1182 ret = s5p_mfc_configure_dma_memory(dev);
1183 if (ret < 0) {
1184 dev_err(&pdev->dev, "failed to configure DMA memory\n");
1185 return ret;
1186 }
1187
1188 ret = s5p_mfc_init_pm(dev);
1189 if (ret < 0) {
1190 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1191 goto err_dma;
1192 }
1193
1194 vb2_dma_contig_set_max_seg_size(dev->mem_dev_l, DMA_BIT_MASK(32));
1195 vb2_dma_contig_set_max_seg_size(dev->mem_dev_r, DMA_BIT_MASK(32));
1196
1197 mutex_init(&dev->mfc_mutex);
1198
1199 ret = s5p_mfc_alloc_firmware(dev);
1200 if (ret)
1201 goto err_res;
1202
1203 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1204 if (ret)
1205 goto err_v4l2_dev_reg;
1206 init_waitqueue_head(&dev->queue);
1207
1208 /* decoder */
1209 vfd = video_device_alloc();
1210 if (!vfd) {
1211 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1212 ret = -ENOMEM;
1213 goto err_dec_alloc;
1214 }
1215 vfd->fops = &s5p_mfc_fops;
1216 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1217 vfd->release = video_device_release;
1218 vfd->lock = &dev->mfc_mutex;
1219 vfd->v4l2_dev = &dev->v4l2_dev;
1220 vfd->vfl_dir = VFL_DIR_M2M;
1221 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1222 dev->vfd_dec = vfd;
1223 video_set_drvdata(vfd, dev);
1224
1225 /* encoder */
1226 vfd = video_device_alloc();
1227 if (!vfd) {
1228 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1229 ret = -ENOMEM;
1230 goto err_enc_alloc;
1231 }
1232 vfd->fops = &s5p_mfc_fops;
1233 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1234 vfd->release = video_device_release;
1235 vfd->lock = &dev->mfc_mutex;
1236 vfd->v4l2_dev = &dev->v4l2_dev;
1237 vfd->vfl_dir = VFL_DIR_M2M;
1238 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1239 dev->vfd_enc = vfd;
1240 video_set_drvdata(vfd, dev);
1241 platform_set_drvdata(pdev, dev);
1242
1243 dev->hw_lock = 0;
1244 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1245 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1246 atomic_set(&dev->watchdog_cnt, 0);
1247 init_timer(&dev->watchdog_timer);
1248 dev->watchdog_timer.data = (unsigned long)dev;
1249 dev->watchdog_timer.function = s5p_mfc_watchdog;
1250
1251 /* Initialize HW ops and commands based on MFC version */
1252 s5p_mfc_init_hw_ops(dev);
1253 s5p_mfc_init_hw_cmds(dev);
1254 s5p_mfc_init_regs(dev);
1255
1256 /* Register decoder and encoder */
1257 ret = video_register_device(dev->vfd_dec, VFL_TYPE_GRABBER, 0);
1258 if (ret) {
1259 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1260 goto err_dec_reg;
1261 }
1262 v4l2_info(&dev->v4l2_dev,
1263 "decoder registered as /dev/video%d\n", dev->vfd_dec->num);
1264
1265 ret = video_register_device(dev->vfd_enc, VFL_TYPE_GRABBER, 0);
1266 if (ret) {
1267 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1268 goto err_enc_reg;
1269 }
1270 v4l2_info(&dev->v4l2_dev,
1271 "encoder registered as /dev/video%d\n", dev->vfd_enc->num);
1272
1273 pr_debug("%s--\n", __func__);
1274 return 0;
1275
1276 /* Deinit MFC if probe had failed */
1277 err_enc_reg:
1278 video_unregister_device(dev->vfd_dec);
1279 err_dec_reg:
1280 video_device_release(dev->vfd_enc);
1281 err_enc_alloc:
1282 video_device_release(dev->vfd_dec);
1283 err_dec_alloc:
1284 v4l2_device_unregister(&dev->v4l2_dev);
1285 err_v4l2_dev_reg:
1286 s5p_mfc_release_firmware(dev);
1287 err_res:
1288 s5p_mfc_final_pm(dev);
1289 err_dma:
1290 s5p_mfc_unconfigure_dma_memory(dev);
1291
1292 pr_debug("%s-- with error\n", __func__);
1293 return ret;
1294
1295 }
1296
1297 /* Remove the driver */
1298 static int s5p_mfc_remove(struct platform_device *pdev)
1299 {
1300 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1301
1302 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1303
1304 del_timer_sync(&dev->watchdog_timer);
1305 flush_workqueue(dev->watchdog_workqueue);
1306 destroy_workqueue(dev->watchdog_workqueue);
1307
1308 video_unregister_device(dev->vfd_enc);
1309 video_unregister_device(dev->vfd_dec);
1310 video_device_release(dev->vfd_enc);
1311 video_device_release(dev->vfd_dec);
1312 v4l2_device_unregister(&dev->v4l2_dev);
1313 s5p_mfc_release_firmware(dev);
1314 s5p_mfc_unconfigure_dma_memory(dev);
1315 vb2_dma_contig_clear_max_seg_size(dev->mem_dev_l);
1316 vb2_dma_contig_clear_max_seg_size(dev->mem_dev_r);
1317
1318 s5p_mfc_final_pm(dev);
1319 return 0;
1320 }
1321
1322 #ifdef CONFIG_PM_SLEEP
1323
1324 static int s5p_mfc_suspend(struct device *dev)
1325 {
1326 struct platform_device *pdev = to_platform_device(dev);
1327 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1328 int ret;
1329
1330 if (m_dev->num_inst == 0)
1331 return 0;
1332
1333 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1334 mfc_err("Error: going to suspend for a second time\n");
1335 return -EIO;
1336 }
1337
1338 /* Check if we're processing then wait if it necessary. */
1339 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1340 /* Try and lock the HW */
1341 /* Wait on the interrupt waitqueue */
1342 ret = wait_event_interruptible_timeout(m_dev->queue,
1343 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1344 if (ret == 0) {
1345 mfc_err("Waiting for hardware to finish timed out\n");
1346 clear_bit(0, &m_dev->enter_suspend);
1347 return -EIO;
1348 }
1349 }
1350
1351 ret = s5p_mfc_sleep(m_dev);
1352 if (ret) {
1353 clear_bit(0, &m_dev->enter_suspend);
1354 clear_bit(0, &m_dev->hw_lock);
1355 }
1356 return ret;
1357 }
1358
1359 static int s5p_mfc_resume(struct device *dev)
1360 {
1361 struct platform_device *pdev = to_platform_device(dev);
1362 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1363
1364 if (m_dev->num_inst == 0)
1365 return 0;
1366 return s5p_mfc_wakeup(m_dev);
1367 }
1368 #endif
1369
1370 #ifdef CONFIG_PM
1371 static int s5p_mfc_runtime_suspend(struct device *dev)
1372 {
1373 struct platform_device *pdev = to_platform_device(dev);
1374 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1375
1376 atomic_set(&m_dev->pm.power, 0);
1377 return 0;
1378 }
1379
1380 static int s5p_mfc_runtime_resume(struct device *dev)
1381 {
1382 struct platform_device *pdev = to_platform_device(dev);
1383 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1384
1385 atomic_set(&m_dev->pm.power, 1);
1386 return 0;
1387 }
1388 #endif
1389
1390 /* Power management */
1391 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1392 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1393 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1394 NULL)
1395 };
1396
1397 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1398 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1399 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1400 .dsc = DESC_BUF_SIZE,
1401 .shm = SHARED_BUF_SIZE,
1402 };
1403
1404 static struct s5p_mfc_buf_size buf_size_v5 = {
1405 .fw = MAX_FW_SIZE,
1406 .cpb = MAX_CPB_SIZE,
1407 .priv = &mfc_buf_size_v5,
1408 };
1409
1410 static struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1411 .base = MFC_BASE_ALIGN_ORDER,
1412 };
1413
1414 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1415 .version = MFC_VERSION,
1416 .version_bit = MFC_V5_BIT,
1417 .port_num = MFC_NUM_PORTS,
1418 .buf_size = &buf_size_v5,
1419 .buf_align = &mfc_buf_align_v5,
1420 .fw_name[0] = "s5p-mfc.fw",
1421 };
1422
1423 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1424 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1425 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1426 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1427 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1428 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1429 };
1430
1431 static struct s5p_mfc_buf_size buf_size_v6 = {
1432 .fw = MAX_FW_SIZE_V6,
1433 .cpb = MAX_CPB_SIZE_V6,
1434 .priv = &mfc_buf_size_v6,
1435 };
1436
1437 static struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1438 .base = 0,
1439 };
1440
1441 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1442 .version = MFC_VERSION_V6,
1443 .version_bit = MFC_V6_BIT,
1444 .port_num = MFC_NUM_PORTS_V6,
1445 .buf_size = &buf_size_v6,
1446 .buf_align = &mfc_buf_align_v6,
1447 .fw_name[0] = "s5p-mfc-v6.fw",
1448 /*
1449 * v6-v2 firmware contains bug fixes and interface change
1450 * for init buffer command
1451 */
1452 .fw_name[1] = "s5p-mfc-v6-v2.fw",
1453 };
1454
1455 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1456 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1457 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1458 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1459 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1460 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1461 };
1462
1463 static struct s5p_mfc_buf_size buf_size_v7 = {
1464 .fw = MAX_FW_SIZE_V7,
1465 .cpb = MAX_CPB_SIZE_V7,
1466 .priv = &mfc_buf_size_v7,
1467 };
1468
1469 static struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1470 .base = 0,
1471 };
1472
1473 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1474 .version = MFC_VERSION_V7,
1475 .version_bit = MFC_V7_BIT,
1476 .port_num = MFC_NUM_PORTS_V7,
1477 .buf_size = &buf_size_v7,
1478 .buf_align = &mfc_buf_align_v7,
1479 .fw_name[0] = "s5p-mfc-v7.fw",
1480 };
1481
1482 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1483 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1484 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1485 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1486 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1487 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1488 };
1489
1490 static struct s5p_mfc_buf_size buf_size_v8 = {
1491 .fw = MAX_FW_SIZE_V8,
1492 .cpb = MAX_CPB_SIZE_V8,
1493 .priv = &mfc_buf_size_v8,
1494 };
1495
1496 static struct s5p_mfc_buf_align mfc_buf_align_v8 = {
1497 .base = 0,
1498 };
1499
1500 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1501 .version = MFC_VERSION_V8,
1502 .version_bit = MFC_V8_BIT,
1503 .port_num = MFC_NUM_PORTS_V8,
1504 .buf_size = &buf_size_v8,
1505 .buf_align = &mfc_buf_align_v8,
1506 .fw_name[0] = "s5p-mfc-v8.fw",
1507 };
1508
1509 static const struct of_device_id exynos_mfc_match[] = {
1510 {
1511 .compatible = "samsung,mfc-v5",
1512 .data = &mfc_drvdata_v5,
1513 }, {
1514 .compatible = "samsung,mfc-v6",
1515 .data = &mfc_drvdata_v6,
1516 }, {
1517 .compatible = "samsung,mfc-v7",
1518 .data = &mfc_drvdata_v7,
1519 }, {
1520 .compatible = "samsung,mfc-v8",
1521 .data = &mfc_drvdata_v8,
1522 },
1523 {},
1524 };
1525 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1526
1527 static void *mfc_get_drv_data(struct platform_device *pdev)
1528 {
1529 struct s5p_mfc_variant *driver_data = NULL;
1530 const struct of_device_id *match;
1531
1532 match = of_match_node(exynos_mfc_match, pdev->dev.of_node);
1533 if (match)
1534 driver_data = (struct s5p_mfc_variant *)match->data;
1535
1536 return driver_data;
1537 }
1538
1539 static struct platform_driver s5p_mfc_driver = {
1540 .probe = s5p_mfc_probe,
1541 .remove = s5p_mfc_remove,
1542 .driver = {
1543 .name = S5P_MFC_NAME,
1544 .pm = &s5p_mfc_pm_ops,
1545 .of_match_table = exynos_mfc_match,
1546 },
1547 };
1548
1549 module_platform_driver(s5p_mfc_driver);
1550
1551 MODULE_LICENSE("GPL");
1552 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1553 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1554
Linux kernel - Deliverables
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