2 * Samsung S5P Multi Format Codec v 5.0
4 * This file contains definitions of enums and structs used by the codec
7 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
8 * Kamil Debski, <k.debski@samsung.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version
16 #ifndef S5P_MFC_COMMON_H_
17 #define S5P_MFC_COMMON_H_
19 #include <linux/platform_device.h>
20 #include <linux/videodev2.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-ioctl.h>
24 #include <media/videobuf2-v4l2.h>
26 #include "regs-mfc-v8.h"
28 #define S5P_MFC_NAME "s5p-mfc"
30 /* Definitions related to MFC memory */
32 /* Offset base used to differentiate between CAPTURE and OUTPUT
34 #define DST_QUEUE_OFF_BASE (1 << 30)
36 #define MFC_BANK1_ALLOC_CTX 0
37 #define MFC_BANK2_ALLOC_CTX 1
39 #define MFC_BANK1_ALIGN_ORDER 13
40 #define MFC_BANK2_ALIGN_ORDER 13
41 #define MFC_BASE_ALIGN_ORDER 17
43 #define MFC_FW_MAX_VERSIONS 2
45 #include <media/videobuf2-dma-contig.h>
47 static inline dma_addr_t
s5p_mfc_mem_cookie(void *a
, void *b
)
49 /* Same functionality as the vb2_dma_contig_plane_paddr */
50 dma_addr_t
*paddr
= vb2_dma_contig_memops
.cookie(b
);
56 #define MFC_MAX_EXTRA_DPB 5
57 #define MFC_MAX_BUFFERS 32
58 #define MFC_NUM_CONTEXTS 4
59 /* Interrupt timeout */
60 #define MFC_INT_TIMEOUT 2000
61 /* Busy wait timeout */
62 #define MFC_BW_TIMEOUT 500
63 /* Watchdog interval */
64 #define MFC_WATCHDOG_INTERVAL 1000
65 /* After how many executions watchdog should assume lock up */
66 #define MFC_WATCHDOG_CNT 10
67 #define MFC_NO_INSTANCE_SET -1
68 #define MFC_ENC_CAP_PLANE_COUNT 1
69 #define MFC_ENC_OUT_PLANE_COUNT 2
71 #define MFC_MAX_CTRLS 77
73 #define S5P_MFC_CODEC_NONE -1
74 #define S5P_MFC_CODEC_H264_DEC 0
75 #define S5P_MFC_CODEC_H264_MVC_DEC 1
76 #define S5P_MFC_CODEC_VC1_DEC 2
77 #define S5P_MFC_CODEC_MPEG4_DEC 3
78 #define S5P_MFC_CODEC_MPEG2_DEC 4
79 #define S5P_MFC_CODEC_H263_DEC 5
80 #define S5P_MFC_CODEC_VC1RCV_DEC 6
81 #define S5P_MFC_CODEC_VP8_DEC 7
83 #define S5P_MFC_CODEC_H264_ENC 20
84 #define S5P_MFC_CODEC_H264_MVC_ENC 21
85 #define S5P_MFC_CODEC_MPEG4_ENC 22
86 #define S5P_MFC_CODEC_H263_ENC 23
87 #define S5P_MFC_CODEC_VP8_ENC 24
89 #define S5P_MFC_R2H_CMD_EMPTY 0
90 #define S5P_MFC_R2H_CMD_SYS_INIT_RET 1
91 #define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2
92 #define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3
93 #define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4
94 #define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6
95 #define S5P_MFC_R2H_CMD_SLEEP_RET 7
96 #define S5P_MFC_R2H_CMD_WAKEUP_RET 8
97 #define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9
98 #define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10
99 #define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11
100 #define S5P_MFC_R2H_CMD_FW_STATUS_RET 12
101 #define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13
102 #define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14
103 #define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15
104 #define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16
105 #define S5P_MFC_R2H_CMD_ERR_RET 32
107 #define mfc_read(dev, offset) readl(dev->regs_base + (offset))
108 #define mfc_write(dev, data, offset) writel((data), dev->regs_base + \
112 * enum s5p_mfc_fmt_type - type of the pixelformat
114 enum s5p_mfc_fmt_type
{
121 * enum s5p_mfc_inst_type - The type of an MFC instance.
123 enum s5p_mfc_inst_type
{
130 * enum s5p_mfc_inst_state - The state of an MFC instance.
132 enum s5p_mfc_inst_state
{
137 MFCINST_HEAD_PRODUCED
,
146 MFCINST_RES_CHANGE_INIT
,
147 MFCINST_RES_CHANGE_FLUSH
,
148 MFCINST_RES_CHANGE_END
,
152 * enum s5p_mfc_queue_state - The state of buffer queue.
154 enum s5p_mfc_queue_state
{
156 QUEUE_BUFS_REQUESTED
,
162 * enum s5p_mfc_decode_arg - type of frame decoding
164 enum s5p_mfc_decode_arg
{
170 enum s5p_mfc_fw_ver
{
175 #define MFC_BUF_FLAG_USED (1 << 0)
176 #define MFC_BUF_FLAG_EOS (1 << 1)
181 * struct s5p_mfc_buf - MFC buffer
184 struct vb2_v4l2_buffer
*b
;
185 struct list_head list
;
197 * struct s5p_mfc_pm - power management data structure
201 struct clk
*clock_gate
;
203 struct device
*device
;
206 struct s5p_mfc_buf_size_v5
{
207 unsigned int h264_ctx
;
208 unsigned int non_h264_ctx
;
213 struct s5p_mfc_buf_size_v6
{
214 unsigned int dev_ctx
;
215 unsigned int h264_dec_ctx
;
216 unsigned int other_dec_ctx
;
217 unsigned int h264_enc_ctx
;
218 unsigned int other_enc_ctx
;
221 struct s5p_mfc_buf_size
{
227 struct s5p_mfc_buf_align
{
231 struct s5p_mfc_variant
{
232 unsigned int version
;
233 unsigned int port_num
;
235 struct s5p_mfc_buf_size
*buf_size
;
236 struct s5p_mfc_buf_align
*buf_align
;
237 char *fw_name
[MFC_FW_MAX_VERSIONS
];
241 * struct s5p_mfc_priv_buf - represents internal used buffer
242 * @ofs: offset of each buffer, will be used for MFC
243 * @virt: kernel virtual address, only valid when the
244 * buffer accessed by driver
245 * @dma: DMA address, only valid when kernel DMA API used
246 * @size: size of the buffer
248 struct s5p_mfc_priv_buf
{
256 * struct s5p_mfc_dev - The struct containing driver internal parameters.
258 * @v4l2_dev: v4l2_device
259 * @vfd_dec: video device for decoding
260 * @vfd_enc: video device for encoding
261 * @plat_dev: platform device
262 * @mem_dev_l: child device of the left memory bank (0)
263 * @mem_dev_r: child device of the right memory bank (1)
264 * @regs_base: base address of the MFC hw registers
266 * @dec_ctrl_handler: control framework handler for decoding
267 * @enc_ctrl_handler: control framework handler for encoding
268 * @pm: power management control
269 * @variant: MFC hardware variant information
270 * @num_inst: couter of active MFC instances
271 * @irqlock: lock for operations on videobuf2 queues
272 * @condlock: lock for changing/checking if a context is ready to be
274 * @mfc_mutex: lock for video_device
275 * @int_cond: variable used by the waitqueue
276 * @int_type: type of last interrupt
277 * @int_err: error number for last interrupt
278 * @queue: waitqueue for waiting for completion of device commands
279 * @fw_size: size of firmware
280 * @fw_virt_addr: virtual firmware address
281 * @bank1: address of the beginning of bank 1 memory
282 * @bank2: address of the beginning of bank 2 memory
283 * @hw_lock: used for hardware locking
284 * @ctx: array of driver contexts
285 * @curr_ctx: number of the currently running context
286 * @ctx_work_bits: used to mark which contexts are waiting for hardware
287 * @watchdog_cnt: counter for the watchdog
288 * @watchdog_workqueue: workqueue for the watchdog
289 * @watchdog_work: worker for the watchdog
290 * @enter_suspend: flag set when entering suspend
291 * @ctx_buf: common context memory (MFCv6)
292 * @warn_start: hardware error code from which warnings start
293 * @mfc_ops: ops structure holding HW operation function pointers
294 * @mfc_cmds: cmd structure holding HW commands function pointers
295 * @fw_ver: loaded firmware sub-version
299 struct v4l2_device v4l2_dev
;
300 struct video_device
*vfd_dec
;
301 struct video_device
*vfd_enc
;
302 struct platform_device
*plat_dev
;
303 struct device
*mem_dev_l
;
304 struct device
*mem_dev_r
;
305 void __iomem
*regs_base
;
307 struct v4l2_ctrl_handler dec_ctrl_handler
;
308 struct v4l2_ctrl_handler enc_ctrl_handler
;
309 struct s5p_mfc_pm pm
;
310 struct s5p_mfc_variant
*variant
;
312 spinlock_t irqlock
; /* lock when operating on context */
313 spinlock_t condlock
; /* lock when changing/checking if a context is
314 ready to be processed */
315 struct mutex mfc_mutex
; /* video_device lock */
318 unsigned int int_err
;
319 wait_queue_head_t queue
;
324 unsigned long hw_lock
;
325 struct s5p_mfc_ctx
*ctx
[MFC_NUM_CONTEXTS
];
327 unsigned long ctx_work_bits
;
328 atomic_t watchdog_cnt
;
329 struct timer_list watchdog_timer
;
330 struct workqueue_struct
*watchdog_workqueue
;
331 struct work_struct watchdog_work
;
332 unsigned long enter_suspend
;
334 struct s5p_mfc_priv_buf ctx_buf
;
336 struct s5p_mfc_hw_ops
*mfc_ops
;
337 struct s5p_mfc_hw_cmds
*mfc_cmds
;
338 const struct s5p_mfc_regs
*mfc_regs
;
339 enum s5p_mfc_fw_ver fw_ver
;
340 bool risc_on
; /* indicates if RISC is on or off */
344 * struct s5p_mfc_h264_enc_params - encoding parameters for h264
346 struct s5p_mfc_h264_enc_params
{
347 enum v4l2_mpeg_video_h264_profile profile
;
348 enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode
;
349 s8 loop_filter_alpha
;
351 enum v4l2_mpeg_video_h264_entropy_mode entropy_mode
;
361 u16 vui_ext_sar_width
;
362 u16 vui_ext_sar_height
;
370 enum v4l2_mpeg_video_h264_level level_v4l2
;
377 u8 hier_qp_layer_qp
[7];
378 u8 sei_frame_packing
;
379 u8 sei_fp_curr_frame_0
;
380 u8 sei_fp_arrangement_type
;
389 u32 aso_slice_order
[8];
393 * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
395 struct s5p_mfc_mpeg4_enc_params
{
397 enum v4l2_mpeg_video_mpeg4_profile profile
;
399 /* Common for MPEG4, H263 */
407 enum v4l2_mpeg_video_mpeg4_level level_v4l2
;
412 * struct s5p_mfc_vp8_enc_params - encoding parameters for vp8
414 struct s5p_mfc_vp8_enc_params
{
416 enum v4l2_vp8_num_partitions num_partitions
;
417 enum v4l2_vp8_num_ref_frames num_ref
;
420 u32 golden_frame_ref_period
;
421 enum v4l2_vp8_golden_frame_sel golden_frame_sel
;
432 * struct s5p_mfc_enc_params - general encoding parameters
434 struct s5p_mfc_enc_params
{
441 enum v4l2_mpeg_video_multi_slice_mode slice_mode
;
444 u16 intra_refresh_mb
;
452 u16 rc_reaction_coeff
;
456 enum v4l2_mpeg_video_header_mode seq_hdr_mode
;
457 enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode
;
458 int fixed_target_bit
;
461 u32 rc_framerate_num
;
462 u32 rc_framerate_denom
;
465 struct s5p_mfc_h264_enc_params h264
;
466 struct s5p_mfc_mpeg4_enc_params mpeg4
;
467 struct s5p_mfc_vp8_enc_params vp8
;
473 * struct s5p_mfc_codec_ops - codec ops, used by encoding
475 struct s5p_mfc_codec_ops
{
476 /* initialization routines */
477 int (*pre_seq_start
) (struct s5p_mfc_ctx
*ctx
);
478 int (*post_seq_start
) (struct s5p_mfc_ctx
*ctx
);
479 /* execution routines */
480 int (*pre_frame_start
) (struct s5p_mfc_ctx
*ctx
);
481 int (*post_frame_start
) (struct s5p_mfc_ctx
*ctx
);
484 #define call_cop(c, op, args...) \
485 (((c)->c_ops->op) ? \
486 ((c)->c_ops->op(args)) : 0)
489 * struct s5p_mfc_ctx - This struct contains the instance context
491 * @dev: pointer to the s5p_mfc_dev of the device
492 * @fh: struct v4l2_fh
493 * @num: number of the context that this structure describes
494 * @int_cond: variable used by the waitqueue
495 * @int_type: type of the last interrupt
496 * @int_err: error number received from MFC hw in the interrupt
497 * @queue: waitqueue that can be used to wait for this context to
499 * @src_fmt: source pixelformat information
500 * @dst_fmt: destination pixelformat information
501 * @vq_src: vb2 queue for source buffers
502 * @vq_dst: vb2 queue for destination buffers
503 * @src_queue: driver internal queue for source buffers
504 * @dst_queue: driver internal queue for destination buffers
505 * @src_queue_cnt: number of buffers queued on the source internal queue
506 * @dst_queue_cnt: number of buffers queued on the dest internal queue
507 * @type: type of the instance - decoder or encoder
508 * @state: state of the context
509 * @inst_no: number of hw instance associated with the context
510 * @img_width: width of the image that is decoded or encoded
511 * @img_height: height of the image that is decoded or encoded
512 * @buf_width: width of the buffer for processed image
513 * @buf_height: height of the buffer for processed image
514 * @luma_size: size of a luma plane
515 * @chroma_size: size of a chroma plane
516 * @mv_size: size of a motion vectors buffer
517 * @consumed_stream: number of bytes that have been used so far from the
519 * @dpb_flush_flag: flag used to indicate that a DPB buffers are being
521 * @head_processed: flag mentioning whether the header data is processed
523 * @bank1: handle to memory allocated for temporary buffers from
525 * @bank2: handle to memory allocated for temporary buffers from
527 * @capture_state: state of the capture buffers queue
528 * @output_state: state of the output buffers queue
529 * @src_bufs: information on allocated source buffers
530 * @dst_bufs: information on allocated destination buffers
531 * @sequence: counter for the sequence number for v4l2
532 * @dec_dst_flag: flags for buffers queued in the hardware
533 * @dec_src_buf_size: size of the buffer for source buffers in decoding
534 * @codec_mode: number of codec mode used by MFC hw
535 * @slice_interface: slice interface flag
536 * @loop_filter_mpeg4: loop filter for MPEG4 flag
537 * @display_delay: value of the display delay for H264
538 * @display_delay_enable: display delay for H264 enable flag
539 * @after_packed_pb: flag used to track buffer when stream is in
541 * @sei_fp_parse: enable/disable parsing of frame packing SEI information
542 * @dpb_count: count of the DPB buffers required by MFC hw
543 * @total_dpb_count: count of DPB buffers with additional buffers
544 * requested by the application
545 * @ctx: context buffer information
546 * @dsc: descriptor buffer information
547 * @shm: shared memory buffer information
548 * @mv_count: number of MV buffers allocated for decoding
549 * @enc_params: encoding parameters for MFC
550 * @enc_dst_buf_size: size of the buffers for encoder output
551 * @luma_dpb_size: dpb buffer size for luma
552 * @chroma_dpb_size: dpb buffer size for chroma
553 * @me_buffer_size: size of the motion estimation buffer
554 * @tmv_buffer_size: size of temporal predictor motion vector buffer
555 * @frame_type: used to force the type of the next encoded frame
556 * @ref_queue: list of the reference buffers for encoding
557 * @ref_queue_cnt: number of the buffers in the reference list
558 * @c_ops: ops for encoding
559 * @ctrls: array of controls, used when adding controls to the
560 * v4l2 control framework
561 * @ctrl_handler: handler for v4l2 framework
564 struct s5p_mfc_dev
*dev
;
571 unsigned int int_err
;
572 wait_queue_head_t queue
;
574 struct s5p_mfc_fmt
*src_fmt
;
575 struct s5p_mfc_fmt
*dst_fmt
;
577 struct vb2_queue vq_src
;
578 struct vb2_queue vq_dst
;
580 struct list_head src_queue
;
581 struct list_head dst_queue
;
583 unsigned int src_queue_cnt
;
584 unsigned int dst_queue_cnt
;
586 enum s5p_mfc_inst_type type
;
587 enum s5p_mfc_inst_state state
;
590 /* Image parameters */
600 unsigned long consumed_stream
;
602 unsigned int dpb_flush_flag
;
603 unsigned int head_processed
;
605 struct s5p_mfc_priv_buf bank1
;
606 struct s5p_mfc_priv_buf bank2
;
608 enum s5p_mfc_queue_state capture_state
;
609 enum s5p_mfc_queue_state output_state
;
611 struct s5p_mfc_buf src_bufs
[MFC_MAX_BUFFERS
];
613 struct s5p_mfc_buf dst_bufs
[MFC_MAX_BUFFERS
];
616 unsigned int sequence
;
617 unsigned long dec_dst_flag
;
618 size_t dec_src_buf_size
;
623 int loop_filter_mpeg4
;
625 int display_delay_enable
;
633 struct s5p_mfc_priv_buf ctx
;
634 struct s5p_mfc_priv_buf dsc
;
635 struct s5p_mfc_priv_buf shm
;
637 struct s5p_mfc_enc_params enc_params
;
639 size_t enc_dst_buf_size
;
640 size_t luma_dpb_size
;
641 size_t chroma_dpb_size
;
642 size_t me_buffer_size
;
643 size_t tmv_buffer_size
;
645 enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type
;
647 struct list_head ref_queue
;
648 unsigned int ref_queue_cnt
;
650 enum v4l2_mpeg_video_multi_slice_mode slice_mode
;
656 const struct s5p_mfc_codec_ops
*c_ops
;
658 struct v4l2_ctrl
*ctrls
[MFC_MAX_CTRLS
];
659 struct v4l2_ctrl_handler ctrl_handler
;
660 unsigned int frame_tag
;
661 size_t scratch_buf_size
;
665 * struct s5p_mfc_fmt - structure used to store information about pixelformats
672 enum s5p_mfc_fmt_type type
;
678 * struct mfc_control - structure used to store information about MFC controls
679 * it is used to initialize the control framework.
683 enum v4l2_ctrl_type type
;
684 __u8 name
[32]; /* Whatever */
685 __s32 minimum
; /* Note signedness */
688 __u32 menu_skip_mask
;
695 /* Macro for making hardware specific calls */
696 #define s5p_mfc_hw_call(f, op, args...) \
697 ((f && f->op) ? f->op(args) : (typeof(f->op(args)))(-ENODEV))
699 #define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
700 #define ctrl_to_ctx(__ctrl) \
701 container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
703 void clear_work_bit(struct s5p_mfc_ctx
*ctx
);
704 void set_work_bit(struct s5p_mfc_ctx
*ctx
);
705 void clear_work_bit_irqsave(struct s5p_mfc_ctx
*ctx
);
706 void set_work_bit_irqsave(struct s5p_mfc_ctx
*ctx
);
707 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev
*dev
);
708 void s5p_mfc_cleanup_queue(struct list_head
*lh
, struct vb2_queue
*vq
);
710 #define HAS_PORTNUM(dev) (dev ? (dev->variant ? \
711 (dev->variant->port_num ? 1 : 0) : 0) : 0)
712 #define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0)
713 #define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60 ? 1 : 0)
714 #define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70 ? 1 : 0)
715 #define IS_MFCV8(dev) (dev->variant->version >= 0x80 ? 1 : 0)
717 #define MFC_V5_BIT BIT(0)
718 #define MFC_V6_BIT BIT(1)
719 #define MFC_V7_BIT BIT(2)
720 #define MFC_V8_BIT BIT(3)
723 #endif /* S5P_MFC_COMMON_H_ */