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[deliverable/linux.git] / drivers / media / platform / soc_camera / mx2_camera.c
1 /*
2 * V4L2 Driver for i.MX27 camera host
3 *
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/errno.h>
21 #include <linux/fs.h>
22 #include <linux/gcd.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/math64.h>
26 #include <linux/mm.h>
27 #include <linux/moduleparam.h>
28 #include <linux/time.h>
29 #include <linux/device.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32
33 #include <media/v4l2-common.h>
34 #include <media/v4l2-dev.h>
35 #include <media/videobuf2-core.h>
36 #include <media/videobuf2-dma-contig.h>
37 #include <media/soc_camera.h>
38 #include <media/soc_mediabus.h>
39
40 #include <linux/videodev2.h>
41
42 #include <linux/platform_data/camera-mx2.h>
43
44 #include <asm/dma.h>
45
46 #define MX2_CAM_DRV_NAME "mx2-camera"
47 #define MX2_CAM_VERSION "0.0.6"
48 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
49
50 /* reset values */
51 #define CSICR1_RESET_VAL 0x40000800
52 #define CSICR2_RESET_VAL 0x0
53 #define CSICR3_RESET_VAL 0x0
54
55 /* csi control reg 1 */
56 #define CSICR1_SWAP16_EN (1 << 31)
57 #define CSICR1_EXT_VSYNC (1 << 30)
58 #define CSICR1_EOF_INTEN (1 << 29)
59 #define CSICR1_PRP_IF_EN (1 << 28)
60 #define CSICR1_CCIR_MODE (1 << 27)
61 #define CSICR1_COF_INTEN (1 << 26)
62 #define CSICR1_SF_OR_INTEN (1 << 25)
63 #define CSICR1_RF_OR_INTEN (1 << 24)
64 #define CSICR1_STATFF_LEVEL (3 << 22)
65 #define CSICR1_STATFF_INTEN (1 << 21)
66 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19)
67 #define CSICR1_RXFF_INTEN (1 << 18)
68 #define CSICR1_SOF_POL (1 << 17)
69 #define CSICR1_SOF_INTEN (1 << 16)
70 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
71 #define CSICR1_HSYNC_POL (1 << 11)
72 #define CSICR1_CCIR_EN (1 << 10)
73 #define CSICR1_MCLKEN (1 << 9)
74 #define CSICR1_FCC (1 << 8)
75 #define CSICR1_PACK_DIR (1 << 7)
76 #define CSICR1_CLR_STATFIFO (1 << 6)
77 #define CSICR1_CLR_RXFIFO (1 << 5)
78 #define CSICR1_GCLK_MODE (1 << 4)
79 #define CSICR1_INV_DATA (1 << 3)
80 #define CSICR1_INV_PCLK (1 << 2)
81 #define CSICR1_REDGE (1 << 1)
82 #define CSICR1_FMT_MASK (CSICR1_PACK_DIR | CSICR1_SWAP16_EN)
83
84 #define SHIFT_STATFF_LEVEL 22
85 #define SHIFT_RXFF_LEVEL 19
86 #define SHIFT_MCLKDIV 12
87
88 #define SHIFT_FRMCNT 16
89
90 #define CSICR1 0x00
91 #define CSICR2 0x04
92 #define CSISR 0x08
93 #define CSISTATFIFO 0x0c
94 #define CSIRFIFO 0x10
95 #define CSIRXCNT 0x14
96 #define CSICR3 0x1c
97 #define CSIDMASA_STATFIFO 0x20
98 #define CSIDMATA_STATFIFO 0x24
99 #define CSIDMASA_FB1 0x28
100 #define CSIDMASA_FB2 0x2c
101 #define CSIFBUF_PARA 0x30
102 #define CSIIMAG_PARA 0x34
103
104 /* EMMA PrP */
105 #define PRP_CNTL 0x00
106 #define PRP_INTR_CNTL 0x04
107 #define PRP_INTRSTATUS 0x08
108 #define PRP_SOURCE_Y_PTR 0x0c
109 #define PRP_SOURCE_CB_PTR 0x10
110 #define PRP_SOURCE_CR_PTR 0x14
111 #define PRP_DEST_RGB1_PTR 0x18
112 #define PRP_DEST_RGB2_PTR 0x1c
113 #define PRP_DEST_Y_PTR 0x20
114 #define PRP_DEST_CB_PTR 0x24
115 #define PRP_DEST_CR_PTR 0x28
116 #define PRP_SRC_FRAME_SIZE 0x2c
117 #define PRP_DEST_CH1_LINE_STRIDE 0x30
118 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
119 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
120 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
121 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
122 #define PRP_SRC_LINE_STRIDE 0x44
123 #define PRP_CSC_COEF_012 0x48
124 #define PRP_CSC_COEF_345 0x4c
125 #define PRP_CSC_COEF_678 0x50
126 #define PRP_CH1_RZ_HORI_COEF1 0x54
127 #define PRP_CH1_RZ_HORI_COEF2 0x58
128 #define PRP_CH1_RZ_HORI_VALID 0x5c
129 #define PRP_CH1_RZ_VERT_COEF1 0x60
130 #define PRP_CH1_RZ_VERT_COEF2 0x64
131 #define PRP_CH1_RZ_VERT_VALID 0x68
132 #define PRP_CH2_RZ_HORI_COEF1 0x6c
133 #define PRP_CH2_RZ_HORI_COEF2 0x70
134 #define PRP_CH2_RZ_HORI_VALID 0x74
135 #define PRP_CH2_RZ_VERT_COEF1 0x78
136 #define PRP_CH2_RZ_VERT_COEF2 0x7c
137 #define PRP_CH2_RZ_VERT_VALID 0x80
138
139 #define PRP_CNTL_CH1EN (1 << 0)
140 #define PRP_CNTL_CH2EN (1 << 1)
141 #define PRP_CNTL_CSIEN (1 << 2)
142 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
143 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
144 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
145 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
146 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
147 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
148 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
149 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
150 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
151 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
152 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
153 #define PRP_CNTL_CH1_LEN (1 << 9)
154 #define PRP_CNTL_CH2_LEN (1 << 10)
155 #define PRP_CNTL_SKIP_FRAME (1 << 11)
156 #define PRP_CNTL_SWRST (1 << 12)
157 #define PRP_CNTL_CLKEN (1 << 13)
158 #define PRP_CNTL_WEN (1 << 14)
159 #define PRP_CNTL_CH1BYP (1 << 15)
160 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
161 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
162 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
163 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
164 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
165 #define PRP_CNTL_CH2B1EN (1 << 29)
166 #define PRP_CNTL_CH2B2EN (1 << 30)
167 #define PRP_CNTL_CH2FEN (1 << 31)
168
169 /* IRQ Enable and status register */
170 #define PRP_INTR_RDERR (1 << 0)
171 #define PRP_INTR_CH1WERR (1 << 1)
172 #define PRP_INTR_CH2WERR (1 << 2)
173 #define PRP_INTR_CH1FC (1 << 3)
174 #define PRP_INTR_CH2FC (1 << 5)
175 #define PRP_INTR_LBOVF (1 << 7)
176 #define PRP_INTR_CH2OVF (1 << 8)
177
178 /* Resizing registers */
179 #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
180 #define PRP_RZ_VALID_BILINEAR (1 << 31)
181
182 #define MAX_VIDEO_MEM 16
183
184 #define RESIZE_NUM_MIN 1
185 #define RESIZE_NUM_MAX 20
186 #define BC_COEF 3
187 #define SZ_COEF (1 << BC_COEF)
188
189 #define RESIZE_DIR_H 0
190 #define RESIZE_DIR_V 1
191
192 #define RESIZE_ALGO_BILINEAR 0
193 #define RESIZE_ALGO_AVERAGING 1
194
195 struct mx2_prp_cfg {
196 int channel;
197 u32 in_fmt;
198 u32 out_fmt;
199 u32 src_pixel;
200 u32 ch1_pixel;
201 u32 irq_flags;
202 u32 csicr1;
203 };
204
205 /* prp resizing parameters */
206 struct emma_prp_resize {
207 int algo; /* type of algorithm used */
208 int len; /* number of coefficients */
209 unsigned char s[RESIZE_NUM_MAX]; /* table of coefficients */
210 };
211
212 /* prp configuration for a client-host fmt pair */
213 struct mx2_fmt_cfg {
214 u32 in_fmt;
215 u32 out_fmt;
216 struct mx2_prp_cfg cfg;
217 };
218
219 struct mx2_buf_internal {
220 struct list_head queue;
221 int bufnum;
222 bool discard;
223 };
224
225 /* buffer for one video frame */
226 struct mx2_buffer {
227 /* common v4l buffer stuff -- must be first */
228 struct vb2_buffer vb;
229 struct mx2_buf_internal internal;
230 };
231
232 enum mx2_camera_type {
233 IMX27_CAMERA,
234 };
235
236 struct mx2_camera_dev {
237 struct device *dev;
238 struct soc_camera_host soc_host;
239 struct clk *clk_emma_ahb, *clk_emma_ipg;
240 struct clk *clk_csi_ahb, *clk_csi_per;
241
242 void __iomem *base_csi, *base_emma;
243
244 struct mx2_camera_platform_data *pdata;
245 unsigned long platform_flags;
246
247 struct list_head capture;
248 struct list_head active_bufs;
249 struct list_head discard;
250
251 spinlock_t lock;
252
253 int dma;
254 struct mx2_buffer *active;
255 struct mx2_buffer *fb1_active;
256 struct mx2_buffer *fb2_active;
257
258 u32 csicr1;
259 enum mx2_camera_type devtype;
260
261 struct mx2_buf_internal buf_discard[2];
262 void *discard_buffer;
263 dma_addr_t discard_buffer_dma;
264 size_t discard_size;
265 struct mx2_fmt_cfg *emma_prp;
266 struct emma_prp_resize resizing[2];
267 unsigned int s_width, s_height;
268 u32 frame_count;
269 struct vb2_alloc_ctx *alloc_ctx;
270 };
271
272 static struct platform_device_id mx2_camera_devtype[] = {
273 {
274 .name = "imx27-camera",
275 .driver_data = IMX27_CAMERA,
276 }, {
277 /* sentinel */
278 }
279 };
280 MODULE_DEVICE_TABLE(platform, mx2_camera_devtype);
281
282 static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf)
283 {
284 return container_of(int_buf, struct mx2_buffer, internal);
285 }
286
287 static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
288 /*
289 * This is a generic configuration which is valid for most
290 * prp input-output format combinations.
291 * We set the incoming and outgoing pixelformat to a
292 * 16 Bit wide format and adjust the bytesperline
293 * accordingly. With this configuration the inputdata
294 * will not be changed by the emma and could be any type
295 * of 16 Bit Pixelformat.
296 */
297 {
298 .in_fmt = 0,
299 .out_fmt = 0,
300 .cfg = {
301 .channel = 1,
302 .in_fmt = PRP_CNTL_DATA_IN_RGB16,
303 .out_fmt = PRP_CNTL_CH1_OUT_RGB16,
304 .src_pixel = 0x2ca00565, /* RGB565 */
305 .ch1_pixel = 0x2ca00565, /* RGB565 */
306 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
307 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
308 .csicr1 = 0,
309 }
310 },
311 {
312 .in_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
313 .out_fmt = V4L2_PIX_FMT_YUYV,
314 .cfg = {
315 .channel = 1,
316 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
317 .out_fmt = PRP_CNTL_CH1_OUT_YUV422,
318 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
319 .ch1_pixel = 0x62000888, /* YUV422 (YUYV) */
320 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
321 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
322 .csicr1 = CSICR1_SWAP16_EN,
323 }
324 },
325 {
326 .in_fmt = MEDIA_BUS_FMT_YUYV8_2X8,
327 .out_fmt = V4L2_PIX_FMT_YUYV,
328 .cfg = {
329 .channel = 1,
330 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
331 .out_fmt = PRP_CNTL_CH1_OUT_YUV422,
332 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
333 .ch1_pixel = 0x62000888, /* YUV422 (YUYV) */
334 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
335 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
336 .csicr1 = CSICR1_PACK_DIR,
337 }
338 },
339 {
340 .in_fmt = MEDIA_BUS_FMT_YUYV8_2X8,
341 .out_fmt = V4L2_PIX_FMT_YUV420,
342 .cfg = {
343 .channel = 2,
344 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
345 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
346 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
347 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
348 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
349 PRP_INTR_CH2OVF,
350 .csicr1 = CSICR1_PACK_DIR,
351 }
352 },
353 {
354 .in_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
355 .out_fmt = V4L2_PIX_FMT_YUV420,
356 .cfg = {
357 .channel = 2,
358 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
359 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
360 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
361 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
362 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
363 PRP_INTR_CH2OVF,
364 .csicr1 = CSICR1_SWAP16_EN,
365 }
366 },
367 };
368
369 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(u32 in_fmt, u32 out_fmt)
370 {
371 int i;
372
373 for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
374 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
375 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
376 return &mx27_emma_prp_table[i];
377 }
378 /* If no match return the most generic configuration */
379 return &mx27_emma_prp_table[0];
380 };
381
382 static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
383 unsigned long phys, int bufnum)
384 {
385 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
386
387 if (prp->cfg.channel == 1) {
388 writel(phys, pcdev->base_emma +
389 PRP_DEST_RGB1_PTR + 4 * bufnum);
390 } else {
391 writel(phys, pcdev->base_emma +
392 PRP_DEST_Y_PTR - 0x14 * bufnum);
393 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
394 u32 imgsize = pcdev->soc_host.icd->user_height *
395 pcdev->soc_host.icd->user_width;
396
397 writel(phys + imgsize, pcdev->base_emma +
398 PRP_DEST_CB_PTR - 0x14 * bufnum);
399 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
400 PRP_DEST_CR_PTR - 0x14 * bufnum);
401 }
402 }
403 }
404
405 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
406 {
407 clk_disable_unprepare(pcdev->clk_csi_ahb);
408 clk_disable_unprepare(pcdev->clk_csi_per);
409 writel(0, pcdev->base_csi + CSICR1);
410 writel(0, pcdev->base_emma + PRP_CNTL);
411 }
412
413 static int mx2_camera_add_device(struct soc_camera_device *icd)
414 {
415 dev_info(icd->parent, "Camera driver attached to camera %d\n",
416 icd->devnum);
417
418 return 0;
419 }
420
421 static void mx2_camera_remove_device(struct soc_camera_device *icd)
422 {
423 dev_info(icd->parent, "Camera driver detached from camera %d\n",
424 icd->devnum);
425 }
426
427 /*
428 * The following two functions absolutely depend on the fact, that
429 * there can be only one camera on mx2 camera sensor interface
430 */
431 static int mx2_camera_clock_start(struct soc_camera_host *ici)
432 {
433 struct mx2_camera_dev *pcdev = ici->priv;
434 int ret;
435 u32 csicr1;
436
437 ret = clk_prepare_enable(pcdev->clk_csi_ahb);
438 if (ret < 0)
439 return ret;
440
441 ret = clk_prepare_enable(pcdev->clk_csi_per);
442 if (ret < 0)
443 goto exit_csi_ahb;
444
445 csicr1 = CSICR1_MCLKEN | CSICR1_PRP_IF_EN | CSICR1_FCC |
446 CSICR1_RXFF_LEVEL(0);
447
448 pcdev->csicr1 = csicr1;
449 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
450
451 pcdev->frame_count = 0;
452
453 return 0;
454
455 exit_csi_ahb:
456 clk_disable_unprepare(pcdev->clk_csi_ahb);
457
458 return ret;
459 }
460
461 static void mx2_camera_clock_stop(struct soc_camera_host *ici)
462 {
463 struct mx2_camera_dev *pcdev = ici->priv;
464
465 mx2_camera_deactivate(pcdev);
466 }
467
468 /*
469 * Videobuf operations
470 */
471 static int mx2_videobuf_setup(struct vb2_queue *vq,
472 const struct v4l2_format *fmt,
473 unsigned int *count, unsigned int *num_planes,
474 unsigned int sizes[], void *alloc_ctxs[])
475 {
476 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
477 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
478 struct mx2_camera_dev *pcdev = ici->priv;
479
480 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
481
482 /* TODO: support for VIDIOC_CREATE_BUFS not ready */
483 if (fmt != NULL)
484 return -ENOTTY;
485
486 alloc_ctxs[0] = pcdev->alloc_ctx;
487
488 sizes[0] = icd->sizeimage;
489
490 if (0 == *count)
491 *count = 32;
492 if (!*num_planes &&
493 sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
494 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
495
496 *num_planes = 1;
497
498 return 0;
499 }
500
501 static int mx2_videobuf_prepare(struct vb2_buffer *vb)
502 {
503 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
504 int ret = 0;
505
506 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
507 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
508
509 #ifdef DEBUG
510 /*
511 * This can be useful if you want to see if we actually fill
512 * the buffer with something
513 */
514 memset((void *)vb2_plane_vaddr(vb, 0),
515 0xaa, vb2_get_plane_payload(vb, 0));
516 #endif
517
518 vb2_set_plane_payload(vb, 0, icd->sizeimage);
519 if (vb2_plane_vaddr(vb, 0) &&
520 vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
521 ret = -EINVAL;
522 goto out;
523 }
524
525 return 0;
526
527 out:
528 return ret;
529 }
530
531 static void mx2_videobuf_queue(struct vb2_buffer *vb)
532 {
533 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
534 struct soc_camera_host *ici =
535 to_soc_camera_host(icd->parent);
536 struct mx2_camera_dev *pcdev = ici->priv;
537 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
538 unsigned long flags;
539
540 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
541 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
542
543 spin_lock_irqsave(&pcdev->lock, flags);
544
545 list_add_tail(&buf->internal.queue, &pcdev->capture);
546
547 spin_unlock_irqrestore(&pcdev->lock, flags);
548 }
549
550 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
551 int bytesperline)
552 {
553 struct soc_camera_host *ici =
554 to_soc_camera_host(icd->parent);
555 struct mx2_camera_dev *pcdev = ici->priv;
556 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
557
558 writel((pcdev->s_width << 16) | pcdev->s_height,
559 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
560 writel(prp->cfg.src_pixel,
561 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
562 if (prp->cfg.channel == 1) {
563 writel((icd->user_width << 16) | icd->user_height,
564 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
565 writel(bytesperline,
566 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
567 writel(prp->cfg.ch1_pixel,
568 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
569 } else { /* channel 2 */
570 writel((icd->user_width << 16) | icd->user_height,
571 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
572 }
573
574 /* Enable interrupts */
575 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
576 }
577
578 static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev)
579 {
580 int dir;
581
582 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
583 unsigned char *s = pcdev->resizing[dir].s;
584 int len = pcdev->resizing[dir].len;
585 unsigned int coeff[2] = {0, 0};
586 unsigned int valid = 0;
587 int i;
588
589 if (len == 0)
590 continue;
591
592 for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) {
593 int j;
594
595 j = i > 9 ? 1 : 0;
596 coeff[j] = (coeff[j] << BC_COEF) |
597 (s[i] & (SZ_COEF - 1));
598
599 if (i == 5 || i == 15)
600 coeff[j] <<= 1;
601
602 valid = (valid << 1) | (s[i] >> BC_COEF);
603 }
604
605 valid |= PRP_RZ_VALID_TBL_LEN(len);
606
607 if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR)
608 valid |= PRP_RZ_VALID_BILINEAR;
609
610 if (pcdev->emma_prp->cfg.channel == 1) {
611 if (dir == RESIZE_DIR_H) {
612 writel(coeff[0], pcdev->base_emma +
613 PRP_CH1_RZ_HORI_COEF1);
614 writel(coeff[1], pcdev->base_emma +
615 PRP_CH1_RZ_HORI_COEF2);
616 writel(valid, pcdev->base_emma +
617 PRP_CH1_RZ_HORI_VALID);
618 } else {
619 writel(coeff[0], pcdev->base_emma +
620 PRP_CH1_RZ_VERT_COEF1);
621 writel(coeff[1], pcdev->base_emma +
622 PRP_CH1_RZ_VERT_COEF2);
623 writel(valid, pcdev->base_emma +
624 PRP_CH1_RZ_VERT_VALID);
625 }
626 } else {
627 if (dir == RESIZE_DIR_H) {
628 writel(coeff[0], pcdev->base_emma +
629 PRP_CH2_RZ_HORI_COEF1);
630 writel(coeff[1], pcdev->base_emma +
631 PRP_CH2_RZ_HORI_COEF2);
632 writel(valid, pcdev->base_emma +
633 PRP_CH2_RZ_HORI_VALID);
634 } else {
635 writel(coeff[0], pcdev->base_emma +
636 PRP_CH2_RZ_VERT_COEF1);
637 writel(coeff[1], pcdev->base_emma +
638 PRP_CH2_RZ_VERT_COEF2);
639 writel(valid, pcdev->base_emma +
640 PRP_CH2_RZ_VERT_VALID);
641 }
642 }
643 }
644 }
645
646 static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
647 {
648 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
649 struct soc_camera_host *ici =
650 to_soc_camera_host(icd->parent);
651 struct mx2_camera_dev *pcdev = ici->priv;
652 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
653 struct vb2_buffer *vb;
654 struct mx2_buffer *buf;
655 unsigned long phys;
656 int bytesperline;
657 unsigned long flags;
658
659 if (count < 2)
660 return -ENOBUFS;
661
662 spin_lock_irqsave(&pcdev->lock, flags);
663
664 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
665 internal.queue);
666 buf->internal.bufnum = 0;
667 vb = &buf->vb;
668
669 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
670 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
671 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
672
673 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
674 internal.queue);
675 buf->internal.bufnum = 1;
676 vb = &buf->vb;
677
678 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
679 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
680 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
681
682 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
683 icd->current_fmt->host_fmt);
684 if (bytesperline < 0) {
685 spin_unlock_irqrestore(&pcdev->lock, flags);
686 return bytesperline;
687 }
688
689 /*
690 * I didn't manage to properly enable/disable the prp
691 * on a per frame basis during running transfers,
692 * thus we allocate a buffer here and use it to
693 * discard frames when no buffer is available.
694 * Feel free to work on this ;)
695 */
696 pcdev->discard_size = icd->user_height * bytesperline;
697 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
698 pcdev->discard_size,
699 &pcdev->discard_buffer_dma, GFP_ATOMIC);
700 if (!pcdev->discard_buffer) {
701 spin_unlock_irqrestore(&pcdev->lock, flags);
702 return -ENOMEM;
703 }
704
705 pcdev->buf_discard[0].discard = true;
706 list_add_tail(&pcdev->buf_discard[0].queue,
707 &pcdev->discard);
708
709 pcdev->buf_discard[1].discard = true;
710 list_add_tail(&pcdev->buf_discard[1].queue,
711 &pcdev->discard);
712
713 mx2_prp_resize_commit(pcdev);
714
715 mx27_camera_emma_buf_init(icd, bytesperline);
716
717 if (prp->cfg.channel == 1) {
718 writel(PRP_CNTL_CH1EN |
719 PRP_CNTL_CSIEN |
720 prp->cfg.in_fmt |
721 prp->cfg.out_fmt |
722 PRP_CNTL_CH1_LEN |
723 PRP_CNTL_CH1BYP |
724 PRP_CNTL_CH1_TSKIP(0) |
725 PRP_CNTL_IN_TSKIP(0),
726 pcdev->base_emma + PRP_CNTL);
727 } else {
728 writel(PRP_CNTL_CH2EN |
729 PRP_CNTL_CSIEN |
730 prp->cfg.in_fmt |
731 prp->cfg.out_fmt |
732 PRP_CNTL_CH2_LEN |
733 PRP_CNTL_CH2_TSKIP(0) |
734 PRP_CNTL_IN_TSKIP(0),
735 pcdev->base_emma + PRP_CNTL);
736 }
737 spin_unlock_irqrestore(&pcdev->lock, flags);
738
739 return 0;
740 }
741
742 static void mx2_stop_streaming(struct vb2_queue *q)
743 {
744 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
745 struct soc_camera_host *ici =
746 to_soc_camera_host(icd->parent);
747 struct mx2_camera_dev *pcdev = ici->priv;
748 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
749 unsigned long flags;
750 void *b;
751 u32 cntl;
752
753 spin_lock_irqsave(&pcdev->lock, flags);
754
755 cntl = readl(pcdev->base_emma + PRP_CNTL);
756 if (prp->cfg.channel == 1) {
757 writel(cntl & ~PRP_CNTL_CH1EN,
758 pcdev->base_emma + PRP_CNTL);
759 } else {
760 writel(cntl & ~PRP_CNTL_CH2EN,
761 pcdev->base_emma + PRP_CNTL);
762 }
763 INIT_LIST_HEAD(&pcdev->capture);
764 INIT_LIST_HEAD(&pcdev->active_bufs);
765 INIT_LIST_HEAD(&pcdev->discard);
766
767 b = pcdev->discard_buffer;
768 pcdev->discard_buffer = NULL;
769
770 spin_unlock_irqrestore(&pcdev->lock, flags);
771
772 dma_free_coherent(ici->v4l2_dev.dev,
773 pcdev->discard_size, b, pcdev->discard_buffer_dma);
774 }
775
776 static struct vb2_ops mx2_videobuf_ops = {
777 .queue_setup = mx2_videobuf_setup,
778 .buf_prepare = mx2_videobuf_prepare,
779 .buf_queue = mx2_videobuf_queue,
780 .start_streaming = mx2_start_streaming,
781 .stop_streaming = mx2_stop_streaming,
782 };
783
784 static int mx2_camera_init_videobuf(struct vb2_queue *q,
785 struct soc_camera_device *icd)
786 {
787 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
788 q->io_modes = VB2_MMAP | VB2_USERPTR;
789 q->drv_priv = icd;
790 q->ops = &mx2_videobuf_ops;
791 q->mem_ops = &vb2_dma_contig_memops;
792 q->buf_struct_size = sizeof(struct mx2_buffer);
793 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
794
795 return vb2_queue_init(q);
796 }
797
798 #define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
799 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
800 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
801 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
802 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
803 V4L2_MBUS_PCLK_SAMPLE_RISING | \
804 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
805 V4L2_MBUS_DATA_ACTIVE_HIGH | \
806 V4L2_MBUS_DATA_ACTIVE_LOW)
807
808 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
809 {
810 int count = 0;
811
812 readl(pcdev->base_emma + PRP_CNTL);
813 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
814 while (count++ < 100) {
815 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
816 return 0;
817 barrier();
818 udelay(1);
819 }
820
821 return -ETIMEDOUT;
822 }
823
824 static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
825 {
826 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
827 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
828 struct mx2_camera_dev *pcdev = ici->priv;
829 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
830 unsigned long common_flags;
831 int ret;
832 int bytesperline;
833 u32 csicr1 = pcdev->csicr1;
834
835 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
836 if (!ret) {
837 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
838 if (!common_flags) {
839 dev_warn(icd->parent,
840 "Flags incompatible: camera 0x%x, host 0x%x\n",
841 cfg.flags, MX2_BUS_FLAGS);
842 return -EINVAL;
843 }
844 } else if (ret != -ENOIOCTLCMD) {
845 return ret;
846 } else {
847 common_flags = MX2_BUS_FLAGS;
848 }
849
850 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
851 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
852 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
853 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
854 else
855 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
856 }
857
858 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
859 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
860 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
861 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
862 else
863 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
864 }
865
866 cfg.flags = common_flags;
867 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
868 if (ret < 0 && ret != -ENOIOCTLCMD) {
869 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
870 common_flags, ret);
871 return ret;
872 }
873
874 csicr1 = (csicr1 & ~CSICR1_FMT_MASK) | pcdev->emma_prp->cfg.csicr1;
875
876 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
877 csicr1 |= CSICR1_REDGE;
878 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
879 csicr1 |= CSICR1_SOF_POL;
880 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
881 csicr1 |= CSICR1_HSYNC_POL;
882 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
883 csicr1 |= CSICR1_EXT_VSYNC;
884 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
885 csicr1 |= CSICR1_CCIR_EN;
886 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
887 csicr1 |= CSICR1_CCIR_MODE;
888 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
889 csicr1 |= CSICR1_GCLK_MODE;
890 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
891 csicr1 |= CSICR1_INV_DATA;
892
893 pcdev->csicr1 = csicr1;
894
895 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
896 icd->current_fmt->host_fmt);
897 if (bytesperline < 0)
898 return bytesperline;
899
900 ret = mx27_camera_emma_prp_reset(pcdev);
901 if (ret)
902 return ret;
903
904 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
905
906 return 0;
907 }
908
909 static int mx2_camera_set_crop(struct soc_camera_device *icd,
910 const struct v4l2_crop *a)
911 {
912 struct v4l2_crop a_writable = *a;
913 struct v4l2_rect *rect = &a_writable.c;
914 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
915 struct v4l2_mbus_framefmt mf;
916 int ret;
917
918 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
919 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
920
921 ret = v4l2_subdev_call(sd, video, s_crop, a);
922 if (ret < 0)
923 return ret;
924
925 /* The capture device might have changed its output */
926 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
927 if (ret < 0)
928 return ret;
929
930 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
931 mf.width, mf.height);
932
933 icd->user_width = mf.width;
934 icd->user_height = mf.height;
935
936 return ret;
937 }
938
939 static int mx2_camera_get_formats(struct soc_camera_device *icd,
940 unsigned int idx,
941 struct soc_camera_format_xlate *xlate)
942 {
943 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
944 const struct soc_mbus_pixelfmt *fmt;
945 struct device *dev = icd->parent;
946 u32 code;
947 int ret, formats = 0;
948
949 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
950 if (ret < 0)
951 /* no more formats */
952 return 0;
953
954 fmt = soc_mbus_get_fmtdesc(code);
955 if (!fmt) {
956 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
957 return 0;
958 }
959
960 if (code == MEDIA_BUS_FMT_YUYV8_2X8 ||
961 code == MEDIA_BUS_FMT_UYVY8_2X8) {
962 formats++;
963 if (xlate) {
964 /*
965 * CH2 can output YUV420 which is a standard format in
966 * soc_mediabus.c
967 */
968 xlate->host_fmt =
969 soc_mbus_get_fmtdesc(MEDIA_BUS_FMT_YUYV8_1_5X8);
970 xlate->code = code;
971 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
972 xlate->host_fmt->name, code);
973 xlate++;
974 }
975 }
976
977 if (code == MEDIA_BUS_FMT_UYVY8_2X8) {
978 formats++;
979 if (xlate) {
980 xlate->host_fmt =
981 soc_mbus_get_fmtdesc(MEDIA_BUS_FMT_YUYV8_2X8);
982 xlate->code = code;
983 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
984 xlate->host_fmt->name, code);
985 xlate++;
986 }
987 }
988
989 /* Generic pass-trough */
990 formats++;
991 if (xlate) {
992 xlate->host_fmt = fmt;
993 xlate->code = code;
994 xlate++;
995 }
996 return formats;
997 }
998
999 static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev,
1000 struct v4l2_mbus_framefmt *mf_in,
1001 struct v4l2_pix_format *pix_out, bool apply)
1002 {
1003 unsigned int num, den;
1004 unsigned long m;
1005 int i, dir;
1006
1007 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
1008 struct emma_prp_resize tmprsz;
1009 unsigned char *s = tmprsz.s;
1010 int len = 0;
1011 int in, out;
1012
1013 if (dir == RESIZE_DIR_H) {
1014 in = mf_in->width;
1015 out = pix_out->width;
1016 } else {
1017 in = mf_in->height;
1018 out = pix_out->height;
1019 }
1020
1021 if (in < out)
1022 return -EINVAL;
1023 else if (in == out)
1024 continue;
1025
1026 /* Calculate ratio */
1027 m = gcd(in, out);
1028 num = in / m;
1029 den = out / m;
1030 if (num > RESIZE_NUM_MAX)
1031 return -EINVAL;
1032
1033 if ((num >= 2 * den) && (den == 1) &&
1034 (num < 9) && (!(num & 0x01))) {
1035 int sum = 0;
1036 int j;
1037
1038 /* Average scaling for >= 2:1 ratios */
1039 /* Support can be added for num >=9 and odd values */
1040
1041 tmprsz.algo = RESIZE_ALGO_AVERAGING;
1042 len = num;
1043
1044 for (i = 0; i < (len / 2); i++)
1045 s[i] = 8;
1046
1047 do {
1048 for (i = 0; i < (len / 2); i++) {
1049 s[i] = s[i] >> 1;
1050 sum = 0;
1051 for (j = 0; j < (len / 2); j++)
1052 sum += s[j];
1053 if (sum == 4)
1054 break;
1055 }
1056 } while (sum != 4);
1057
1058 for (i = (len / 2); i < len; i++)
1059 s[i] = s[len - i - 1];
1060
1061 s[len - 1] |= SZ_COEF;
1062 } else {
1063 /* bilinear scaling for < 2:1 ratios */
1064 int v; /* overflow counter */
1065 int coeff, nxt; /* table output */
1066 int in_pos_inc = 2 * den;
1067 int out_pos = num;
1068 int out_pos_inc = 2 * num;
1069 int init_carry = num - den;
1070 int carry = init_carry;
1071
1072 tmprsz.algo = RESIZE_ALGO_BILINEAR;
1073 v = den + in_pos_inc;
1074 do {
1075 coeff = v - out_pos;
1076 out_pos += out_pos_inc;
1077 carry += out_pos_inc;
1078 for (nxt = 0; v < out_pos; nxt++) {
1079 v += in_pos_inc;
1080 carry -= in_pos_inc;
1081 }
1082
1083 if (len > RESIZE_NUM_MAX)
1084 return -EINVAL;
1085
1086 coeff = ((coeff << BC_COEF) +
1087 (in_pos_inc >> 1)) / in_pos_inc;
1088
1089 if (coeff >= (SZ_COEF - 1))
1090 coeff--;
1091
1092 coeff |= SZ_COEF;
1093 s[len] = (unsigned char)coeff;
1094 len++;
1095
1096 for (i = 1; i < nxt; i++) {
1097 if (len >= RESIZE_NUM_MAX)
1098 return -EINVAL;
1099 s[len] = 0;
1100 len++;
1101 }
1102 } while (carry != init_carry);
1103 }
1104 tmprsz.len = len;
1105 if (dir == RESIZE_DIR_H)
1106 mf_in->width = pix_out->width;
1107 else
1108 mf_in->height = pix_out->height;
1109
1110 if (apply)
1111 memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz));
1112 }
1113 return 0;
1114 }
1115
1116 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1117 struct v4l2_format *f)
1118 {
1119 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1120 struct mx2_camera_dev *pcdev = ici->priv;
1121 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1122 const struct soc_camera_format_xlate *xlate;
1123 struct v4l2_pix_format *pix = &f->fmt.pix;
1124 struct v4l2_mbus_framefmt mf;
1125 int ret;
1126
1127 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1128 __func__, pix->width, pix->height);
1129
1130 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1131 if (!xlate) {
1132 dev_warn(icd->parent, "Format %x not found\n",
1133 pix->pixelformat);
1134 return -EINVAL;
1135 }
1136
1137 mf.width = pix->width;
1138 mf.height = pix->height;
1139 mf.field = pix->field;
1140 mf.colorspace = pix->colorspace;
1141 mf.code = xlate->code;
1142
1143 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1144 if (ret < 0 && ret != -ENOIOCTLCMD)
1145 return ret;
1146
1147 /* Store width and height returned by the sensor for resizing */
1148 pcdev->s_width = mf.width;
1149 pcdev->s_height = mf.height;
1150 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1151 __func__, pcdev->s_width, pcdev->s_height);
1152
1153 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1154 xlate->host_fmt->fourcc);
1155
1156 memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1157 if ((mf.width != pix->width || mf.height != pix->height) &&
1158 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1159 if (mx2_emmaprp_resize(pcdev, &mf, pix, true) < 0)
1160 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1161 }
1162
1163 if (mf.code != xlate->code)
1164 return -EINVAL;
1165
1166 pix->width = mf.width;
1167 pix->height = mf.height;
1168 pix->field = mf.field;
1169 pix->colorspace = mf.colorspace;
1170 icd->current_fmt = xlate;
1171
1172 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1173 __func__, pix->width, pix->height);
1174
1175 return 0;
1176 }
1177
1178 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1179 struct v4l2_format *f)
1180 {
1181 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1182 const struct soc_camera_format_xlate *xlate;
1183 struct v4l2_pix_format *pix = &f->fmt.pix;
1184 struct v4l2_mbus_framefmt mf;
1185 __u32 pixfmt = pix->pixelformat;
1186 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1187 struct mx2_camera_dev *pcdev = ici->priv;
1188 struct mx2_fmt_cfg *emma_prp;
1189 int ret;
1190
1191 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1192 __func__, pix->width, pix->height);
1193
1194 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1195 if (pixfmt && !xlate) {
1196 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1197 return -EINVAL;
1198 }
1199
1200 /*
1201 * limit to MX27 hardware capabilities: width must be a multiple of 8 as
1202 * requested by the CSI. (Table 39-2 in the i.MX27 Reference Manual).
1203 */
1204 pix->width &= ~0x7;
1205
1206 /* limit to sensor capabilities */
1207 mf.width = pix->width;
1208 mf.height = pix->height;
1209 mf.field = pix->field;
1210 mf.colorspace = pix->colorspace;
1211 mf.code = xlate->code;
1212
1213 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1214 if (ret < 0)
1215 return ret;
1216
1217 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1218 __func__, pcdev->s_width, pcdev->s_height);
1219
1220 /* If the sensor does not support image size try PrP resizing */
1221 emma_prp = mx27_emma_prp_get_format(xlate->code,
1222 xlate->host_fmt->fourcc);
1223
1224 if ((mf.width != pix->width || mf.height != pix->height) &&
1225 emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1226 if (mx2_emmaprp_resize(pcdev, &mf, pix, false) < 0)
1227 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1228 }
1229
1230 if (mf.field == V4L2_FIELD_ANY)
1231 mf.field = V4L2_FIELD_NONE;
1232 /*
1233 * Driver supports interlaced images provided they have
1234 * both fields so that they can be processed as if they
1235 * were progressive.
1236 */
1237 if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) {
1238 dev_err(icd->parent, "Field type %d unsupported.\n",
1239 mf.field);
1240 return -EINVAL;
1241 }
1242
1243 pix->width = mf.width;
1244 pix->height = mf.height;
1245 pix->field = mf.field;
1246 pix->colorspace = mf.colorspace;
1247
1248 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1249 __func__, pix->width, pix->height);
1250
1251 return 0;
1252 }
1253
1254 static int mx2_camera_querycap(struct soc_camera_host *ici,
1255 struct v4l2_capability *cap)
1256 {
1257 /* cap->name is set by the friendly caller:-> */
1258 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1259 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1260 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1261
1262 return 0;
1263 }
1264
1265 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1266 {
1267 struct soc_camera_device *icd = file->private_data;
1268
1269 return vb2_poll(&icd->vb2_vidq, file, pt);
1270 }
1271
1272 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1273 .owner = THIS_MODULE,
1274 .add = mx2_camera_add_device,
1275 .remove = mx2_camera_remove_device,
1276 .clock_start = mx2_camera_clock_start,
1277 .clock_stop = mx2_camera_clock_stop,
1278 .set_fmt = mx2_camera_set_fmt,
1279 .set_crop = mx2_camera_set_crop,
1280 .get_formats = mx2_camera_get_formats,
1281 .try_fmt = mx2_camera_try_fmt,
1282 .init_videobuf2 = mx2_camera_init_videobuf,
1283 .poll = mx2_camera_poll,
1284 .querycap = mx2_camera_querycap,
1285 .set_bus_param = mx2_camera_set_bus_param,
1286 };
1287
1288 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1289 int bufnum, bool err)
1290 {
1291 #ifdef DEBUG
1292 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1293 #endif
1294 struct mx2_buf_internal *ibuf;
1295 struct mx2_buffer *buf;
1296 struct vb2_buffer *vb;
1297 unsigned long phys;
1298
1299 ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal,
1300 queue);
1301
1302 BUG_ON(ibuf->bufnum != bufnum);
1303
1304 if (ibuf->discard) {
1305 /*
1306 * Discard buffer must not be returned to user space.
1307 * Just return it to the discard queue.
1308 */
1309 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1310 } else {
1311 buf = mx2_ibuf_to_buf(ibuf);
1312
1313 vb = &buf->vb;
1314 #ifdef DEBUG
1315 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1316 if (prp->cfg.channel == 1) {
1317 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1318 4 * bufnum) != phys) {
1319 dev_err(pcdev->dev, "%lx != %x\n", phys,
1320 readl(pcdev->base_emma +
1321 PRP_DEST_RGB1_PTR + 4 * bufnum));
1322 }
1323 } else {
1324 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1325 0x14 * bufnum) != phys) {
1326 dev_err(pcdev->dev, "%lx != %x\n", phys,
1327 readl(pcdev->base_emma +
1328 PRP_DEST_Y_PTR - 0x14 * bufnum));
1329 }
1330 }
1331 #endif
1332 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1333 vb2_plane_vaddr(vb, 0),
1334 vb2_get_plane_payload(vb, 0));
1335
1336 list_del_init(&buf->internal.queue);
1337 v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
1338 vb->v4l2_buf.sequence = pcdev->frame_count;
1339 if (err)
1340 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1341 else
1342 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1343 }
1344
1345 pcdev->frame_count++;
1346
1347 if (list_empty(&pcdev->capture)) {
1348 if (list_empty(&pcdev->discard)) {
1349 dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1350 __func__);
1351 return;
1352 }
1353
1354 ibuf = list_first_entry(&pcdev->discard,
1355 struct mx2_buf_internal, queue);
1356 ibuf->bufnum = bufnum;
1357
1358 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1359 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1360 return;
1361 }
1362
1363 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
1364 internal.queue);
1365
1366 buf->internal.bufnum = bufnum;
1367
1368 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1369
1370 vb = &buf->vb;
1371
1372 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1373 mx27_update_emma_buf(pcdev, phys, bufnum);
1374 }
1375
1376 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1377 {
1378 struct mx2_camera_dev *pcdev = data;
1379 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1380 struct mx2_buf_internal *ibuf;
1381
1382 spin_lock(&pcdev->lock);
1383
1384 if (list_empty(&pcdev->active_bufs)) {
1385 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1386 __func__);
1387
1388 if (!status) {
1389 spin_unlock(&pcdev->lock);
1390 return IRQ_NONE;
1391 }
1392 }
1393
1394 if (status & (1 << 7)) { /* overflow */
1395 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1396 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1397 pcdev->base_emma + PRP_CNTL);
1398 writel(cntl, pcdev->base_emma + PRP_CNTL);
1399
1400 ibuf = list_first_entry(&pcdev->active_bufs,
1401 struct mx2_buf_internal, queue);
1402 mx27_camera_frame_done_emma(pcdev,
1403 ibuf->bufnum, true);
1404
1405 status &= ~(1 << 7);
1406 } else if (((status & (3 << 5)) == (3 << 5)) ||
1407 ((status & (3 << 3)) == (3 << 3))) {
1408 /*
1409 * Both buffers have triggered, process the one we're expecting
1410 * to first
1411 */
1412 ibuf = list_first_entry(&pcdev->active_bufs,
1413 struct mx2_buf_internal, queue);
1414 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false);
1415 status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */
1416 } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1417 mx27_camera_frame_done_emma(pcdev, 0, false);
1418 } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1419 mx27_camera_frame_done_emma(pcdev, 1, false);
1420 }
1421
1422 spin_unlock(&pcdev->lock);
1423 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1424
1425 return IRQ_HANDLED;
1426 }
1427
1428 static int mx27_camera_emma_init(struct platform_device *pdev)
1429 {
1430 struct mx2_camera_dev *pcdev = platform_get_drvdata(pdev);
1431 struct resource *res_emma;
1432 int irq_emma;
1433 int err = 0;
1434
1435 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1436 irq_emma = platform_get_irq(pdev, 1);
1437 if (!res_emma || !irq_emma) {
1438 dev_err(pcdev->dev, "no EMMA resources\n");
1439 err = -ENODEV;
1440 goto out;
1441 }
1442
1443 pcdev->base_emma = devm_ioremap_resource(pcdev->dev, res_emma);
1444 if (IS_ERR(pcdev->base_emma)) {
1445 err = PTR_ERR(pcdev->base_emma);
1446 goto out;
1447 }
1448
1449 err = devm_request_irq(pcdev->dev, irq_emma, mx27_camera_emma_irq, 0,
1450 MX2_CAM_DRV_NAME, pcdev);
1451 if (err) {
1452 dev_err(pcdev->dev, "Camera EMMA interrupt register failed\n");
1453 goto out;
1454 }
1455
1456 pcdev->clk_emma_ipg = devm_clk_get(pcdev->dev, "emma-ipg");
1457 if (IS_ERR(pcdev->clk_emma_ipg)) {
1458 err = PTR_ERR(pcdev->clk_emma_ipg);
1459 goto out;
1460 }
1461
1462 clk_prepare_enable(pcdev->clk_emma_ipg);
1463
1464 pcdev->clk_emma_ahb = devm_clk_get(pcdev->dev, "emma-ahb");
1465 if (IS_ERR(pcdev->clk_emma_ahb)) {
1466 err = PTR_ERR(pcdev->clk_emma_ahb);
1467 goto exit_clk_emma_ipg;
1468 }
1469
1470 clk_prepare_enable(pcdev->clk_emma_ahb);
1471
1472 err = mx27_camera_emma_prp_reset(pcdev);
1473 if (err)
1474 goto exit_clk_emma_ahb;
1475
1476 return err;
1477
1478 exit_clk_emma_ahb:
1479 clk_disable_unprepare(pcdev->clk_emma_ahb);
1480 exit_clk_emma_ipg:
1481 clk_disable_unprepare(pcdev->clk_emma_ipg);
1482 out:
1483 return err;
1484 }
1485
1486 static int mx2_camera_probe(struct platform_device *pdev)
1487 {
1488 struct mx2_camera_dev *pcdev;
1489 struct resource *res_csi;
1490 int irq_csi;
1491 int err = 0;
1492
1493 dev_dbg(&pdev->dev, "initialising\n");
1494
1495 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1496 irq_csi = platform_get_irq(pdev, 0);
1497 if (res_csi == NULL || irq_csi < 0) {
1498 dev_err(&pdev->dev, "Missing platform resources data\n");
1499 err = -ENODEV;
1500 goto exit;
1501 }
1502
1503 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
1504 if (!pcdev) {
1505 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1506 err = -ENOMEM;
1507 goto exit;
1508 }
1509
1510 pcdev->clk_csi_ahb = devm_clk_get(&pdev->dev, "ahb");
1511 if (IS_ERR(pcdev->clk_csi_ahb)) {
1512 dev_err(&pdev->dev, "Could not get csi ahb clock\n");
1513 err = PTR_ERR(pcdev->clk_csi_ahb);
1514 goto exit;
1515 }
1516
1517 pcdev->clk_csi_per = devm_clk_get(&pdev->dev, "per");
1518 if (IS_ERR(pcdev->clk_csi_per)) {
1519 dev_err(&pdev->dev, "Could not get csi per clock\n");
1520 err = PTR_ERR(pcdev->clk_csi_per);
1521 goto exit;
1522 }
1523
1524 pcdev->pdata = pdev->dev.platform_data;
1525 if (pcdev->pdata) {
1526 long rate;
1527
1528 pcdev->platform_flags = pcdev->pdata->flags;
1529
1530 rate = clk_round_rate(pcdev->clk_csi_per,
1531 pcdev->pdata->clk * 2);
1532 if (rate <= 0) {
1533 err = -ENODEV;
1534 goto exit;
1535 }
1536 err = clk_set_rate(pcdev->clk_csi_per, rate);
1537 if (err < 0)
1538 goto exit;
1539 }
1540
1541 INIT_LIST_HEAD(&pcdev->capture);
1542 INIT_LIST_HEAD(&pcdev->active_bufs);
1543 INIT_LIST_HEAD(&pcdev->discard);
1544 spin_lock_init(&pcdev->lock);
1545
1546 pcdev->base_csi = devm_ioremap_resource(&pdev->dev, res_csi);
1547 if (IS_ERR(pcdev->base_csi)) {
1548 err = PTR_ERR(pcdev->base_csi);
1549 goto exit;
1550 }
1551
1552 pcdev->dev = &pdev->dev;
1553 platform_set_drvdata(pdev, pcdev);
1554
1555 err = mx27_camera_emma_init(pdev);
1556 if (err)
1557 goto exit;
1558
1559 /*
1560 * We're done with drvdata here. Clear the pointer so that
1561 * v4l2 core can start using drvdata on its purpose.
1562 */
1563 platform_set_drvdata(pdev, NULL);
1564
1565 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1566 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1567 pcdev->soc_host.priv = pcdev;
1568 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1569 pcdev->soc_host.nr = pdev->id;
1570
1571 pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1572 if (IS_ERR(pcdev->alloc_ctx)) {
1573 err = PTR_ERR(pcdev->alloc_ctx);
1574 goto eallocctx;
1575 }
1576 err = soc_camera_host_register(&pcdev->soc_host);
1577 if (err)
1578 goto exit_free_emma;
1579
1580 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1581 clk_get_rate(pcdev->clk_csi_per));
1582
1583 return 0;
1584
1585 exit_free_emma:
1586 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1587 eallocctx:
1588 clk_disable_unprepare(pcdev->clk_emma_ipg);
1589 clk_disable_unprepare(pcdev->clk_emma_ahb);
1590 exit:
1591 return err;
1592 }
1593
1594 static int mx2_camera_remove(struct platform_device *pdev)
1595 {
1596 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1597 struct mx2_camera_dev *pcdev = container_of(soc_host,
1598 struct mx2_camera_dev, soc_host);
1599
1600 soc_camera_host_unregister(&pcdev->soc_host);
1601
1602 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1603
1604 clk_disable_unprepare(pcdev->clk_emma_ipg);
1605 clk_disable_unprepare(pcdev->clk_emma_ahb);
1606
1607 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1608
1609 return 0;
1610 }
1611
1612 static struct platform_driver mx2_camera_driver = {
1613 .driver = {
1614 .name = MX2_CAM_DRV_NAME,
1615 },
1616 .id_table = mx2_camera_devtype,
1617 .remove = mx2_camera_remove,
1618 };
1619
1620 module_platform_driver_probe(mx2_camera_driver, mx2_camera_probe);
1621
1622 MODULE_DESCRIPTION("i.MX27 SoC Camera Host driver");
1623 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1624 MODULE_LICENSE("GPL");
1625 MODULE_VERSION(MX2_CAM_VERSION);
Linux kernel - Deliverables
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