2 * Rafael Micro R820T driver
4 * Copyright (C) 2013 Mauro Carvalho Chehab <mchehab@redhat.com>
6 * This driver was written from scratch, based on an existing driver
7 * that it is part of rtl-sdr git tree, released under GPLv2:
8 * https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug
9 * https://github.com/n1gp/gr-baz
11 * From what I understood from the threads, the original driver was converted
12 * to userspace from a Realtek tree. I couldn't find the original tree.
13 * However, the original driver look awkward on my eyes. So, I decided to
14 * write a new version from it from the scratch, while trying to reproduce
15 * everything found there.
18 * After locking, the original driver seems to have some routines to
19 * improve reception. This was not implemented here yet.
21 * RF Gain set/get is not implemented.
23 * This program is free software; you can redistribute it and/or modify
24 * it under the terms of the GNU General Public License as published by
25 * the Free Software Foundation; either version 2 of the License, or
26 * (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
35 #include <linux/videodev2.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/bitrev.h>
40 #include "tuner-i2c.h"
44 * FIXME: I think that there are only 32 registers, but better safe than
45 * sorry. After finishing the driver, we may review it.
47 #define REG_SHADOW_START 5
55 module_param(debug
, int, 0644);
56 MODULE_PARM_DESC(debug
, "enable verbose debug messages");
58 static int no_imr_cal
;
59 module_param(no_imr_cal
, int, 0444);
60 MODULE_PARM_DESC(no_imr_cal
, "Disable IMR calibration at module init");
64 * enums and structures
75 struct r820t_sect_type
{
82 struct list_head hybrid_tuner_instance_list
;
83 const struct r820t_config
*cfg
;
84 struct tuner_i2c_props i2c_props
;
89 enum xtal_cap_value xtal_cap_sel
;
96 struct r820t_sect_type imr_data
[NUM_IMR
];
98 /* Store current mode */
100 enum v4l2_tuner_type type
;
105 struct r820t_freq_range
{
113 u8 imr_mem
; /* Not used, currently */
116 #define VCO_POWER_REF 0x02
117 #define DIP_FREQ 32000000
123 static LIST_HEAD(hybrid_tuner_instance_list
);
124 static DEFINE_MUTEX(r820t_list_mutex
);
126 /* Those initial values start from REG_SHADOW_START */
127 static const u8 r820t_init_array
[NUM_REGS
] = {
128 0x83, 0x32, 0x75, /* 05 to 07 */
129 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */
130 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */
131 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */
132 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */
133 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */
134 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */
137 /* Tuner frequency ranges */
138 static const struct r820t_freq_range freq_ranges
[] = {
141 .open_d
= 0x08, /* low */
142 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
143 .tf_c
= 0xdf, /* R27[7:0] band2,band0 */
144 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
149 .freq
= 50, /* Start freq, in MHz */
150 .open_d
= 0x08, /* low */
151 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
152 .tf_c
= 0xbe, /* R27[7:0] band4,band1 */
153 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
158 .freq
= 55, /* Start freq, in MHz */
159 .open_d
= 0x08, /* low */
160 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
161 .tf_c
= 0x8b, /* R27[7:0] band7,band4 */
162 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
167 .freq
= 60, /* Start freq, in MHz */
168 .open_d
= 0x08, /* low */
169 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
170 .tf_c
= 0x7b, /* R27[7:0] band8,band4 */
171 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
176 .freq
= 65, /* Start freq, in MHz */
177 .open_d
= 0x08, /* low */
178 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
179 .tf_c
= 0x69, /* R27[7:0] band9,band6 */
180 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
185 .freq
= 70, /* Start freq, in MHz */
186 .open_d
= 0x08, /* low */
187 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
188 .tf_c
= 0x58, /* R27[7:0] band10,band7 */
189 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
194 .freq
= 75, /* Start freq, in MHz */
195 .open_d
= 0x00, /* high */
196 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
197 .tf_c
= 0x44, /* R27[7:0] band11,band11 */
198 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
203 .freq
= 80, /* Start freq, in MHz */
204 .open_d
= 0x00, /* high */
205 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
206 .tf_c
= 0x44, /* R27[7:0] band11,band11 */
207 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
212 .freq
= 90, /* Start freq, in MHz */
213 .open_d
= 0x00, /* high */
214 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
215 .tf_c
= 0x34, /* R27[7:0] band12,band11 */
216 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
221 .freq
= 100, /* Start freq, in MHz */
222 .open_d
= 0x00, /* high */
223 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
224 .tf_c
= 0x34, /* R27[7:0] band12,band11 */
225 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
230 .freq
= 110, /* Start freq, in MHz */
231 .open_d
= 0x00, /* high */
232 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
233 .tf_c
= 0x24, /* R27[7:0] band13,band11 */
234 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
239 .freq
= 120, /* Start freq, in MHz */
240 .open_d
= 0x00, /* high */
241 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
242 .tf_c
= 0x24, /* R27[7:0] band13,band11 */
243 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
248 .freq
= 140, /* Start freq, in MHz */
249 .open_d
= 0x00, /* high */
250 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
251 .tf_c
= 0x14, /* R27[7:0] band14,band11 */
252 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
257 .freq
= 180, /* Start freq, in MHz */
258 .open_d
= 0x00, /* high */
259 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
260 .tf_c
= 0x13, /* R27[7:0] band14,band12 */
261 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
266 .freq
= 220, /* Start freq, in MHz */
267 .open_d
= 0x00, /* high */
268 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
269 .tf_c
= 0x13, /* R27[7:0] band14,band12 */
270 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
275 .freq
= 250, /* Start freq, in MHz */
276 .open_d
= 0x00, /* high */
277 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
278 .tf_c
= 0x11, /* R27[7:0] highest,highest */
279 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
284 .freq
= 280, /* Start freq, in MHz */
285 .open_d
= 0x00, /* high */
286 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
287 .tf_c
= 0x00, /* R27[7:0] highest,highest */
288 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
293 .freq
= 310, /* Start freq, in MHz */
294 .open_d
= 0x00, /* high */
295 .rf_mux_ploy
= 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
296 .tf_c
= 0x00, /* R27[7:0] highest,highest */
297 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
302 .freq
= 450, /* Start freq, in MHz */
303 .open_d
= 0x00, /* high */
304 .rf_mux_ploy
= 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
305 .tf_c
= 0x00, /* R27[7:0] highest,highest */
306 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
311 .freq
= 588, /* Start freq, in MHz */
312 .open_d
= 0x00, /* high */
313 .rf_mux_ploy
= 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
314 .tf_c
= 0x00, /* R27[7:0] highest,highest */
315 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
320 .freq
= 650, /* Start freq, in MHz */
321 .open_d
= 0x00, /* high */
322 .rf_mux_ploy
= 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
323 .tf_c
= 0x00, /* R27[7:0] highest,highest */
324 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
331 static int r820t_xtal_capacitor
[][2] = {
332 { 0x0b, XTAL_LOW_CAP_30P
},
333 { 0x02, XTAL_LOW_CAP_20P
},
334 { 0x01, XTAL_LOW_CAP_10P
},
335 { 0x00, XTAL_LOW_CAP_0P
},
336 { 0x10, XTAL_HIGH_CAP_0P
},
340 * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
341 * input power, for raw results see:
342 * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
345 static const int r820t_lna_gain_steps
[] = {
346 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
349 static const int r820t_mixer_gain_steps
[] = {
350 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
354 * I2C read/write code and shadow registers logic
356 static void shadow_store(struct r820t_priv
*priv
, u8 reg
, const u8
*val
,
359 int r
= reg
- REG_SHADOW_START
;
370 tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n",
371 __func__
, r
+ REG_SHADOW_START
, len
, len
, val
);
373 memcpy(&priv
->regs
[r
], val
, len
);
376 static int r820t_write(struct r820t_priv
*priv
, u8 reg
, const u8
*val
,
379 int rc
, size
, pos
= 0;
381 /* Store the shadow registers */
382 shadow_store(priv
, reg
, val
, len
);
385 if (len
> priv
->cfg
->max_i2c_msg_len
- 1)
386 size
= priv
->cfg
->max_i2c_msg_len
- 1;
390 /* Fill I2C buffer */
392 memcpy(&priv
->buf
[1], &val
[pos
], size
);
394 rc
= tuner_i2c_xfer_send(&priv
->i2c_props
, priv
->buf
, size
+ 1);
395 if (rc
!= size
+ 1) {
396 tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
397 __func__
, rc
, reg
, size
, size
, &priv
->buf
[1]);
402 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
403 __func__
, reg
, size
, size
, &priv
->buf
[1]);
413 static int r820t_write_reg(struct r820t_priv
*priv
, u8 reg
, u8 val
)
415 return r820t_write(priv
, reg
, &val
, 1);
418 static int r820t_read_cache_reg(struct r820t_priv
*priv
, int reg
)
420 reg
-= REG_SHADOW_START
;
422 if (reg
>= 0 && reg
< NUM_REGS
)
423 return priv
->regs
[reg
];
428 static int r820t_write_reg_mask(struct r820t_priv
*priv
, u8 reg
, u8 val
,
431 int rc
= r820t_read_cache_reg(priv
, reg
);
436 val
= (rc
& ~bit_mask
) | (val
& bit_mask
);
438 return r820t_write(priv
, reg
, &val
, 1);
441 static int r820t_read(struct r820t_priv
*priv
, u8 reg
, u8
*val
, int len
)
444 u8
*p
= &priv
->buf
[1];
448 rc
= tuner_i2c_xfer_send_recv(&priv
->i2c_props
, priv
->buf
, 1, p
, len
);
450 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
451 __func__
, rc
, reg
, len
, len
, p
);
457 /* Copy data to the output buffer */
458 for (i
= 0; i
< len
; i
++)
459 val
[i
] = bitrev8(p
[i
]);
461 tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
462 __func__
, reg
, len
, len
, val
);
471 static int r820t_set_mux(struct r820t_priv
*priv
, u32 freq
)
473 const struct r820t_freq_range
*range
;
475 u8 val
, reg08
, reg09
;
477 /* Get the proper frequency range */
478 freq
= freq
/ 1000000;
479 for (i
= 0; i
< ARRAY_SIZE(freq_ranges
) - 1; i
++) {
480 if (freq
< freq_ranges
[i
+ 1].freq
)
483 range
= &freq_ranges
[i
];
485 tuner_dbg("set r820t range#%d for frequency %d MHz\n", i
, freq
);
488 rc
= r820t_write_reg_mask(priv
, 0x17, range
->open_d
, 0x08);
493 rc
= r820t_write_reg_mask(priv
, 0x1a, range
->rf_mux_ploy
, 0xc3);
498 rc
= r820t_write_reg(priv
, 0x1b, range
->tf_c
);
502 /* XTAL CAP & Drive */
503 switch (priv
->xtal_cap_sel
) {
504 case XTAL_LOW_CAP_30P
:
505 case XTAL_LOW_CAP_20P
:
506 val
= range
->xtal_cap20p
| 0x08;
508 case XTAL_LOW_CAP_10P
:
509 val
= range
->xtal_cap10p
| 0x08;
511 case XTAL_HIGH_CAP_0P
:
512 val
= range
->xtal_cap0p
| 0x00;
515 case XTAL_LOW_CAP_0P
:
516 val
= range
->xtal_cap0p
| 0x08;
519 rc
= r820t_write_reg_mask(priv
, 0x10, val
, 0x0b);
523 if (priv
->imr_done
) {
524 reg08
= priv
->imr_data
[range
->imr_mem
].gain_x
;
525 reg09
= priv
->imr_data
[range
->imr_mem
].phase_y
;
530 rc
= r820t_write_reg_mask(priv
, 0x08, reg08
, 0x3f);
534 rc
= r820t_write_reg_mask(priv
, 0x09, reg09
, 0x3f);
539 static int r820t_set_pll(struct r820t_priv
*priv
, enum v4l2_tuner_type type
,
544 unsigned sleep_time
= 10000;
545 u32 vco_fra
; /* VCO contribution by SDM (kHz) */
546 u32 vco_min
= 1770000;
547 u32 vco_max
= vco_min
* 2;
555 u8 ni
, si
, nint
, vco_fine_tune
, val
;
558 /* Frequency in kHz */
560 pll_ref
= priv
->cfg
->xtal
/ 1000;
562 if ((priv
->cfg
->rafael_chip
== CHIP_R620D
) ||
563 (priv
->cfg
->rafael_chip
== CHIP_R828D
) ||
564 (priv
->cfg
->rafael_chip
== CHIP_R828
)) {
565 /* ref set refdiv2, reffreq = Xtal/2 on ATV application */
566 if (type
!= V4L2_TUNER_DIGITAL_TV
) {
572 if (priv
->cfg
->xtal
> 24000000) {
578 rc
= r820t_write_reg_mask(priv
, 0x10, refdiv2
, 0x10);
582 /* set pll autotune = 128kHz */
583 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x00, 0x0c);
587 /* set VCO current = 100 */
588 rc
= r820t_write_reg_mask(priv
, 0x12, 0x80, 0xe0);
592 /* Calculate divider */
593 while (mix_div
<= 64) {
594 if (((freq
* mix_div
) >= vco_min
) &&
595 ((freq
* mix_div
) < vco_max
)) {
597 while (div_buf
> 2) {
598 div_buf
= div_buf
>> 1;
603 mix_div
= mix_div
<< 1;
606 rc
= r820t_read(priv
, 0x00, data
, sizeof(data
));
610 vco_fine_tune
= (data
[4] & 0x30) >> 4;
612 if (vco_fine_tune
> VCO_POWER_REF
)
613 div_num
= div_num
- 1;
614 else if (vco_fine_tune
< VCO_POWER_REF
)
615 div_num
= div_num
+ 1;
617 rc
= r820t_write_reg_mask(priv
, 0x10, div_num
<< 5, 0xe0);
621 vco_freq
= freq
* mix_div
;
622 nint
= vco_freq
/ (2 * pll_ref
);
623 vco_fra
= vco_freq
- 2 * pll_ref
* nint
;
625 /* boundary spur prevention */
626 if (vco_fra
< pll_ref
/ 64) {
628 } else if (vco_fra
> pll_ref
* 127 / 64) {
631 } else if ((vco_fra
> pll_ref
* 127 / 128) && (vco_fra
< pll_ref
)) {
632 vco_fra
= pll_ref
* 127 / 128;
633 } else if ((vco_fra
> pll_ref
) && (vco_fra
< pll_ref
* 129 / 128)) {
634 vco_fra
= pll_ref
* 129 / 128;
638 tuner_info("No valid PLL values for %u kHz!\n", freq
);
642 ni
= (nint
- 13) / 4;
643 si
= nint
- 4 * ni
- 13;
645 rc
= r820t_write_reg(priv
, 0x14, ni
+ (si
<< 6));
655 rc
= r820t_write_reg_mask(priv
, 0x12, val
, 0x08);
660 while (vco_fra
> 1) {
661 if (vco_fra
> (2 * pll_ref
/ n_sdm
)) {
662 sdm
= sdm
+ 32768 / (n_sdm
/ 2);
663 vco_fra
= vco_fra
- 2 * pll_ref
/ n_sdm
;
670 tuner_dbg("freq %d kHz, pll ref %d%s, sdm=0x%04x\n",
671 freq
, pll_ref
, refdiv2
? " / 2" : "", sdm
);
673 rc
= r820t_write_reg(priv
, 0x16, sdm
>> 8);
676 rc
= r820t_write_reg(priv
, 0x15, sdm
& 0xff);
680 for (i
= 0; i
< 2; i
++) {
681 usleep_range(sleep_time
, sleep_time
+ 1000);
683 /* Check if PLL has locked */
684 rc
= r820t_read(priv
, 0x00, data
, 3);
691 /* Didn't lock. Increase VCO current */
692 rc
= r820t_write_reg_mask(priv
, 0x12, 0x60, 0xe0);
698 if (!(data
[2] & 0x40)) {
699 priv
->has_lock
= false;
703 priv
->has_lock
= true;
704 tuner_dbg("tuner has lock at frequency %d kHz\n", freq
);
706 /* set pll autotune = 8kHz */
707 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x08, 0x08);
712 static int r820t_sysfreq_sel(struct r820t_priv
*priv
, u32 freq
,
713 enum v4l2_tuner_type type
,
718 u8 mixer_top
, lna_top
, cp_cur
, div_buf_cur
, lna_vth_l
, mixer_vth_l
;
719 u8 air_cable1_in
, cable2_in
, pre_dect
, lna_discharge
, filter_cur
;
721 tuner_dbg("adjusting tuner parameters for the standard\n");
725 if ((freq
== 506000000) || (freq
== 666000000) ||
726 (freq
== 818000000)) {
727 mixer_top
= 0x14; /* mixer top:14 , top-1, low-discharge */
728 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
729 cp_cur
= 0x28; /* 101, 0.2 */
730 div_buf_cur
= 0x20; /* 10, 200u */
732 mixer_top
= 0x24; /* mixer top:13 , top-1, low-discharge */
733 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
734 cp_cur
= 0x38; /* 111, auto */
735 div_buf_cur
= 0x30; /* 11, 150u */
737 lna_vth_l
= 0x53; /* lna vth 0.84 , vtl 0.64 */
738 mixer_vth_l
= 0x75; /* mixer vth 1.04, vtl 0.84 */
739 air_cable1_in
= 0x00;
743 filter_cur
= 0x40; /* 10, low */
746 mixer_top
= 0x24; /* mixer top:13 , top-1, low-discharge */
747 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
748 lna_vth_l
= 0x53; /* lna vth 0.84 , vtl 0.64 */
749 mixer_vth_l
= 0x75; /* mixer vth 1.04, vtl 0.84 */
750 air_cable1_in
= 0x00;
754 cp_cur
= 0x38; /* 111, auto */
755 div_buf_cur
= 0x30; /* 11, 150u */
756 filter_cur
= 0x40; /* 10, low */
759 mixer_top
= 0x24; /* mixer top:13 , top-1, low-discharge */
760 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
761 lna_vth_l
= 0x75; /* lna vth 1.04 , vtl 0.84 */
762 mixer_vth_l
= 0x75; /* mixer vth 1.04, vtl 0.84 */
763 air_cable1_in
= 0x00;
767 cp_cur
= 0x38; /* 111, auto */
768 div_buf_cur
= 0x30; /* 11, 150u */
769 filter_cur
= 0x40; /* 10, low */
771 default: /* DVB-T 8M */
772 mixer_top
= 0x24; /* mixer top:13 , top-1, low-discharge */
773 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
774 lna_vth_l
= 0x53; /* lna vth 0.84 , vtl 0.64 */
775 mixer_vth_l
= 0x75; /* mixer vth 1.04, vtl 0.84 */
776 air_cable1_in
= 0x00;
780 cp_cur
= 0x38; /* 111, auto */
781 div_buf_cur
= 0x30; /* 11, 150u */
782 filter_cur
= 0x40; /* 10, low */
786 if (priv
->cfg
->use_diplexer
&&
787 ((priv
->cfg
->rafael_chip
== CHIP_R820T
) ||
788 (priv
->cfg
->rafael_chip
== CHIP_R828S
) ||
789 (priv
->cfg
->rafael_chip
== CHIP_R820C
))) {
791 air_cable1_in
= 0x00;
793 air_cable1_in
= 0x60;
797 rc
= r820t_write_reg_mask(priv
, 0x1d, lna_top
, 0xc7);
800 rc
= r820t_write_reg_mask(priv
, 0x1c, mixer_top
, 0xf8);
803 rc
= r820t_write_reg(priv
, 0x0d, lna_vth_l
);
806 rc
= r820t_write_reg(priv
, 0x0e, mixer_vth_l
);
810 /* Air-IN only for Astrometa */
811 rc
= r820t_write_reg_mask(priv
, 0x05, air_cable1_in
, 0x60);
814 rc
= r820t_write_reg_mask(priv
, 0x06, cable2_in
, 0x08);
818 rc
= r820t_write_reg_mask(priv
, 0x11, cp_cur
, 0x38);
821 rc
= r820t_write_reg_mask(priv
, 0x17, div_buf_cur
, 0x30);
824 rc
= r820t_write_reg_mask(priv
, 0x0a, filter_cur
, 0x60);
828 * Original driver initializes regs 0x05 and 0x06 with the
829 * same value again on this point. Probably, it is just an
837 tuner_dbg("adjusting LNA parameters\n");
838 if (type
!= V4L2_TUNER_ANALOG_TV
) {
839 /* LNA TOP: lowest */
840 rc
= r820t_write_reg_mask(priv
, 0x1d, 0, 0x38);
845 rc
= r820t_write_reg_mask(priv
, 0x1c, 0, 0x04);
849 /* 0: PRE_DECT off */
850 rc
= r820t_write_reg_mask(priv
, 0x06, 0, 0x40);
855 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x30, 0x30);
861 /* write LNA TOP = 3 */
862 rc
= r820t_write_reg_mask(priv
, 0x1d, 0x18, 0x38);
867 * write discharge mode
868 * FIXME: IMHO, the mask here is wrong, but it matches
869 * what's there at the original driver
871 rc
= r820t_write_reg_mask(priv
, 0x1c, mixer_top
, 0x04);
875 /* LNA discharge current */
876 rc
= r820t_write_reg_mask(priv
, 0x1e, lna_discharge
, 0x1f);
881 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x20, 0x30);
886 rc
= r820t_write_reg_mask(priv
, 0x06, 0, 0x40);
891 rc
= r820t_write_reg_mask(priv
, 0x1d, lna_top
, 0x38);
896 * write discharge mode
897 * FIXME: IMHO, the mask here is wrong, but it matches
898 * what's there at the original driver
900 rc
= r820t_write_reg_mask(priv
, 0x1c, mixer_top
, 0x04);
904 /* LNA discharge current */
905 rc
= r820t_write_reg_mask(priv
, 0x1e, lna_discharge
, 0x1f);
909 /* agc clk 1Khz, external det1 cap 1u */
910 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x00, 0x30);
914 rc
= r820t_write_reg_mask(priv
, 0x10, 0x00, 0x04);
921 static int r820t_set_tv_standard(struct r820t_priv
*priv
,
923 enum v4l2_tuner_type type
,
924 v4l2_std_id std
, u32 delsys
)
928 u32 if_khz
, filt_cal_lo
;
930 u8 filt_gain
, img_r
, filt_q
, hp_cor
, ext_enable
, loop_through
;
931 u8 lt_att
, flt_ext_widest
, polyfil_cur
;
932 bool need_calibration
;
934 tuner_dbg("selecting the delivery system\n");
936 if (delsys
== SYS_ISDBT
) {
939 filt_gain
= 0x10; /* +3db, 6mhz on */
940 img_r
= 0x00; /* image negative */
941 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
942 hp_cor
= 0x6a; /* 1.7m disable, +2cap, 1.25mhz */
943 ext_enable
= 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */
944 loop_through
= 0x00; /* r5[7], lt on */
945 lt_att
= 0x00; /* r31[7], lt att enable */
946 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
947 polyfil_cur
= 0x60; /* r25[6:5]:min */
951 filt_cal_lo
= 56000; /* 52000->56000 */
952 filt_gain
= 0x10; /* +3db, 6mhz on */
953 img_r
= 0x00; /* image negative */
954 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
955 hp_cor
= 0x6b; /* 1.7m disable, +2cap, 1.0mhz */
956 ext_enable
= 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
957 loop_through
= 0x00; /* r5[7], lt on */
958 lt_att
= 0x00; /* r31[7], lt att enable */
959 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
960 polyfil_cur
= 0x60; /* r25[6:5]:min */
961 } else if (bw
== 7) {
964 * There are two 7 MHz tables defined on the original
965 * driver, but just the second one seems to be visible
966 * by rtl2832. Keep this one here commented, as it
967 * might be needed in the future
972 filt_gain
= 0x10; /* +3db, 6mhz on */
973 img_r
= 0x00; /* image negative */
974 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
975 hp_cor
= 0x2b; /* 1.7m disable, +1cap, 1.0mhz */
976 ext_enable
= 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
977 loop_through
= 0x00; /* r5[7], lt on */
978 lt_att
= 0x00; /* r31[7], lt att enable */
979 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
980 polyfil_cur
= 0x60; /* r25[6:5]:min */
982 /* 7 MHz, second table */
985 filt_gain
= 0x10; /* +3db, 6mhz on */
986 img_r
= 0x00; /* image negative */
987 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
988 hp_cor
= 0x2a; /* 1.7m disable, +1cap, 1.25mhz */
989 ext_enable
= 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
990 loop_through
= 0x00; /* r5[7], lt on */
991 lt_att
= 0x00; /* r31[7], lt att enable */
992 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
993 polyfil_cur
= 0x60; /* r25[6:5]:min */
997 filt_gain
= 0x10; /* +3db, 6mhz on */
998 img_r
= 0x00; /* image negative */
999 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
1000 hp_cor
= 0x0b; /* 1.7m disable, +0cap, 1.0mhz */
1001 ext_enable
= 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1002 loop_through
= 0x00; /* r5[7], lt on */
1003 lt_att
= 0x00; /* r31[7], lt att enable */
1004 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
1005 polyfil_cur
= 0x60; /* r25[6:5]:min */
1009 /* Initialize the shadow registers */
1010 memcpy(priv
->regs
, r820t_init_array
, sizeof(r820t_init_array
));
1012 /* Init Flag & Xtal_check Result */
1014 val
= 1 | priv
->xtal_cap_sel
<< 1;
1017 rc
= r820t_write_reg_mask(priv
, 0x0c, val
, 0x0f);
1022 rc
= r820t_write_reg_mask(priv
, 0x13, VER_NUM
, 0x3f);
1026 /* for LT Gain test */
1027 if (type
!= V4L2_TUNER_ANALOG_TV
) {
1028 rc
= r820t_write_reg_mask(priv
, 0x1d, 0x00, 0x38);
1031 usleep_range(1000, 2000);
1033 priv
->int_freq
= if_khz
* 1000;
1035 /* Check if standard changed. If so, filter calibration is needed */
1036 if (type
!= priv
->type
)
1037 need_calibration
= true;
1038 else if ((type
== V4L2_TUNER_ANALOG_TV
) && (std
!= priv
->std
))
1039 need_calibration
= true;
1040 else if ((type
== V4L2_TUNER_DIGITAL_TV
) &&
1041 ((delsys
!= priv
->delsys
) || bw
!= priv
->bw
))
1042 need_calibration
= true;
1044 need_calibration
= false;
1046 if (need_calibration
) {
1047 tuner_dbg("calibrating the tuner\n");
1048 for (i
= 0; i
< 2; i
++) {
1050 rc
= r820t_write_reg_mask(priv
, 0x0b, hp_cor
, 0x60);
1054 /* set cali clk =on */
1055 rc
= r820t_write_reg_mask(priv
, 0x0f, 0x04, 0x04);
1059 /* X'tal cap 0pF for PLL */
1060 rc
= r820t_write_reg_mask(priv
, 0x10, 0x00, 0x03);
1064 rc
= r820t_set_pll(priv
, type
, filt_cal_lo
* 1000);
1065 if (rc
< 0 || !priv
->has_lock
)
1069 rc
= r820t_write_reg_mask(priv
, 0x0b, 0x10, 0x10);
1073 usleep_range(1000, 2000);
1076 rc
= r820t_write_reg_mask(priv
, 0x0b, 0x00, 0x10);
1080 /* set cali clk =off */
1081 rc
= r820t_write_reg_mask(priv
, 0x0f, 0x00, 0x04);
1085 /* Check if calibration worked */
1086 rc
= r820t_read(priv
, 0x00, data
, sizeof(data
));
1090 priv
->fil_cal_code
= data
[4] & 0x0f;
1091 if (priv
->fil_cal_code
&& priv
->fil_cal_code
!= 0x0f)
1095 if (priv
->fil_cal_code
== 0x0f)
1096 priv
->fil_cal_code
= 0;
1099 rc
= r820t_write_reg_mask(priv
, 0x0a,
1100 filt_q
| priv
->fil_cal_code
, 0x1f);
1104 /* Set BW, Filter_gain, & HP corner */
1105 rc
= r820t_write_reg_mask(priv
, 0x0b, hp_cor
, 0xef);
1111 rc
= r820t_write_reg_mask(priv
, 0x07, img_r
, 0x80);
1115 /* Set filt_3dB, V6MHz */
1116 rc
= r820t_write_reg_mask(priv
, 0x06, filt_gain
, 0x30);
1120 /* channel filter extension */
1121 rc
= r820t_write_reg_mask(priv
, 0x1e, ext_enable
, 0x60);
1126 rc
= r820t_write_reg_mask(priv
, 0x05, loop_through
, 0x80);
1130 /* Loop through attenuation */
1131 rc
= r820t_write_reg_mask(priv
, 0x1f, lt_att
, 0x80);
1135 /* filter extension widest */
1136 rc
= r820t_write_reg_mask(priv
, 0x0f, flt_ext_widest
, 0x80);
1140 /* RF poly filter current */
1141 rc
= r820t_write_reg_mask(priv
, 0x19, polyfil_cur
, 0x60);
1145 /* Store current standard. If it changes, re-calibrate the tuner */
1146 priv
->delsys
= delsys
;
1154 static int r820t_read_gain(struct r820t_priv
*priv
)
1159 rc
= r820t_read(priv
, 0x00, data
, sizeof(data
));
1163 return ((data
[3] & 0x0f) << 1) + ((data
[3] & 0xf0) >> 4);
1166 static int r820t_set_gain_mode(struct r820t_priv
*priv
,
1167 bool set_manual_gain
,
1172 if (set_manual_gain
) {
1173 int i
, total_gain
= 0;
1174 uint8_t mix_index
= 0, lna_index
= 0;
1178 rc
= r820t_write_reg_mask(priv
, 0x05, 0x10, 0x10);
1182 /* Mixer auto off */
1183 rc
= r820t_write_reg_mask(priv
, 0x07, 0, 0x10);
1187 rc
= r820t_read(priv
, 0x00, data
, sizeof(data
));
1191 /* set fixed VGA gain for now (16.3 dB) */
1192 rc
= r820t_write_reg_mask(priv
, 0x0c, 0x08, 0x9f);
1196 for (i
= 0; i
< 15; i
++) {
1197 if (total_gain
>= gain
)
1200 total_gain
+= r820t_lna_gain_steps
[++lna_index
];
1202 if (total_gain
>= gain
)
1205 total_gain
+= r820t_mixer_gain_steps
[++mix_index
];
1209 rc
= r820t_write_reg_mask(priv
, 0x05, lna_index
, 0x0f);
1213 /* set Mixer gain */
1214 rc
= r820t_write_reg_mask(priv
, 0x07, mix_index
, 0x0f);
1219 rc
= r820t_write_reg_mask(priv
, 0x05, 0, 0xef);
1224 rc
= r820t_write_reg_mask(priv
, 0x07, 0x10, 0xef);
1228 /* set fixed VGA gain for now (26.5 dB) */
1229 rc
= r820t_write_reg_mask(priv
, 0x0c, 0x0b, 0x9f);
1238 static int generic_set_freq(struct dvb_frontend
*fe
,
1239 u32 freq
/* in HZ */,
1241 enum v4l2_tuner_type type
,
1242 v4l2_std_id std
, u32 delsys
)
1244 struct r820t_priv
*priv
= fe
->tuner_priv
;
1248 tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
1251 rc
= r820t_set_tv_standard(priv
, bw
, type
, std
, delsys
);
1255 if ((type
== V4L2_TUNER_ANALOG_TV
) && (std
== V4L2_STD_SECAM_LC
))
1256 lo_freq
= freq
- priv
->int_freq
;
1258 lo_freq
= freq
+ priv
->int_freq
;
1260 rc
= r820t_set_mux(priv
, lo_freq
);
1264 rc
= r820t_set_gain_mode(priv
, true, 0);
1268 rc
= r820t_set_pll(priv
, type
, lo_freq
);
1269 if (rc
< 0 || !priv
->has_lock
)
1272 rc
= r820t_sysfreq_sel(priv
, freq
, type
, std
, delsys
);
1276 tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
1277 __func__
, freq
, r820t_read_gain(priv
));
1282 tuner_dbg("%s: failed=%d\n", __func__
, rc
);
1287 * r820t standby logic
1290 static int r820t_standby(struct r820t_priv
*priv
)
1294 /* If device was not initialized yet, don't need to standby */
1295 if (!priv
->init_done
)
1298 rc
= r820t_write_reg(priv
, 0x06, 0xb1);
1301 rc
= r820t_write_reg(priv
, 0x05, 0x03);
1304 rc
= r820t_write_reg(priv
, 0x07, 0x3a);
1307 rc
= r820t_write_reg(priv
, 0x08, 0x40);
1310 rc
= r820t_write_reg(priv
, 0x09, 0xc0);
1313 rc
= r820t_write_reg(priv
, 0x0a, 0x36);
1316 rc
= r820t_write_reg(priv
, 0x0c, 0x35);
1319 rc
= r820t_write_reg(priv
, 0x0f, 0x68);
1322 rc
= r820t_write_reg(priv
, 0x11, 0x03);
1325 rc
= r820t_write_reg(priv
, 0x17, 0xf4);
1328 rc
= r820t_write_reg(priv
, 0x19, 0x0c);
1330 /* Force initial calibration */
1337 * r820t device init logic
1340 static int r820t_xtal_check(struct r820t_priv
*priv
)
1345 /* Initialize the shadow registers */
1346 memcpy(priv
->regs
, r820t_init_array
, sizeof(r820t_init_array
));
1348 /* cap 30pF & Drive Low */
1349 rc
= r820t_write_reg_mask(priv
, 0x10, 0x0b, 0x0b);
1353 /* set pll autotune = 128kHz */
1354 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x00, 0x0c);
1358 /* set manual initial reg = 111111; */
1359 rc
= r820t_write_reg_mask(priv
, 0x13, 0x7f, 0x7f);
1364 rc
= r820t_write_reg_mask(priv
, 0x13, 0x00, 0x40);
1368 /* Try several xtal capacitor alternatives */
1369 for (i
= 0; i
< ARRAY_SIZE(r820t_xtal_capacitor
); i
++) {
1370 rc
= r820t_write_reg_mask(priv
, 0x10,
1371 r820t_xtal_capacitor
[i
][0], 0x1b);
1375 usleep_range(5000, 6000);
1377 rc
= r820t_read(priv
, 0x00, data
, sizeof(data
));
1380 if ((!data
[2]) & 0x40)
1383 val
= data
[2] & 0x3f;
1385 if (priv
->cfg
->xtal
== 16000000 && (val
> 29 || val
< 23))
1392 if (i
== ARRAY_SIZE(r820t_xtal_capacitor
))
1395 return r820t_xtal_capacitor
[i
][1];
1398 static int r820t_imr_prepare(struct r820t_priv
*priv
)
1402 /* Initialize the shadow registers */
1403 memcpy(priv
->regs
, r820t_init_array
, sizeof(r820t_init_array
));
1405 /* lna off (air-in off) */
1406 rc
= r820t_write_reg_mask(priv
, 0x05, 0x20, 0x20);
1410 /* mixer gain mode = manual */
1411 rc
= r820t_write_reg_mask(priv
, 0x07, 0, 0x10);
1415 /* filter corner = lowest */
1416 rc
= r820t_write_reg_mask(priv
, 0x0a, 0x0f, 0x0f);
1420 /* filter bw=+2cap, hp=5M */
1421 rc
= r820t_write_reg_mask(priv
, 0x0b, 0x60, 0x6f);
1425 /* adc=on, vga code mode, gain = 26.5dB */
1426 rc
= r820t_write_reg_mask(priv
, 0x0c, 0x0b, 0x9f);
1431 rc
= r820t_write_reg_mask(priv
, 0x0f, 0, 0x08);
1435 /* ring power = on */
1436 rc
= r820t_write_reg_mask(priv
, 0x18, 0x10, 0x10);
1440 /* from ring = ring pll in */
1441 rc
= r820t_write_reg_mask(priv
, 0x1c, 0x02, 0x02);
1445 /* sw_pdect = det3 */
1446 rc
= r820t_write_reg_mask(priv
, 0x1e, 0x80, 0x80);
1451 rc
= r820t_write_reg_mask(priv
, 0x06, 0x20, 0x20);
1456 static int r820t_multi_read(struct r820t_priv
*priv
)
1459 u8 data
[2], min
= 0, max
= 255, sum
= 0;
1461 usleep_range(5000, 6000);
1463 for (i
= 0; i
< 6; i
++) {
1464 rc
= r820t_read(priv
, 0x00, data
, sizeof(data
));
1476 rc
= sum
- max
- min
;
1481 static int r820t_imr_cross(struct r820t_priv
*priv
,
1482 struct r820t_sect_type iq_point
[3],
1485 struct r820t_sect_type cross
[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */
1486 struct r820t_sect_type tmp
;
1490 reg08
= r820t_read_cache_reg(priv
, 8) & 0xc0;
1491 reg09
= r820t_read_cache_reg(priv
, 9) & 0xc0;
1497 for (i
= 0; i
< 5; i
++) {
1500 cross
[i
].gain_x
= reg08
;
1501 cross
[i
].phase_y
= reg09
;
1504 cross
[i
].gain_x
= reg08
; /* 0 */
1505 cross
[i
].phase_y
= reg09
+ 1; /* Q-1 */
1508 cross
[i
].gain_x
= reg08
; /* 0 */
1509 cross
[i
].phase_y
= (reg09
| 0x20) + 1; /* I-1 */
1512 cross
[i
].gain_x
= reg08
+ 1; /* Q-1 */
1513 cross
[i
].phase_y
= reg09
;
1516 cross
[i
].gain_x
= (reg08
| 0x20) + 1; /* I-1 */
1517 cross
[i
].phase_y
= reg09
;
1520 rc
= r820t_write_reg(priv
, 0x08, cross
[i
].gain_x
);
1524 rc
= r820t_write_reg(priv
, 0x09, cross
[i
].phase_y
);
1528 rc
= r820t_multi_read(priv
);
1532 cross
[i
].value
= rc
;
1534 if (cross
[i
].value
< tmp
.value
)
1535 memcpy(&tmp
, &cross
[i
], sizeof(tmp
));
1538 if ((tmp
.phase_y
& 0x1f) == 1) { /* y-direction */
1541 iq_point
[0] = cross
[0];
1542 iq_point
[1] = cross
[1];
1543 iq_point
[2] = cross
[2];
1544 } else { /* (0,0) or x-direction */
1547 iq_point
[0] = cross
[0];
1548 iq_point
[1] = cross
[3];
1549 iq_point
[2] = cross
[4];
1554 static void r820t_compre_cor(struct r820t_sect_type iq
[3])
1558 for (i
= 3; i
> 0; i
--) {
1559 if (iq
[0].value
> iq
[i
- 1].value
)
1560 swap(iq
[0], iq
[i
- 1]);
1564 static int r820t_compre_step(struct r820t_priv
*priv
,
1565 struct r820t_sect_type iq
[3], u8 reg
)
1568 struct r820t_sect_type tmp
;
1571 * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare
1573 * new < min => update to min and continue
1577 /* min value already saved in iq[0] */
1578 tmp
.phase_y
= iq
[0].phase_y
;
1579 tmp
.gain_x
= iq
[0].gain_x
;
1581 while (((tmp
.gain_x
& 0x1f) < IMR_TRIAL
) &&
1582 ((tmp
.phase_y
& 0x1f) < IMR_TRIAL
)) {
1588 rc
= r820t_write_reg(priv
, 0x08, tmp
.gain_x
);
1592 rc
= r820t_write_reg(priv
, 0x09, tmp
.phase_y
);
1596 rc
= r820t_multi_read(priv
);
1601 if (tmp
.value
<= iq
[0].value
) {
1602 iq
[0].gain_x
= tmp
.gain_x
;
1603 iq
[0].phase_y
= tmp
.phase_y
;
1604 iq
[0].value
= tmp
.value
;
1614 static int r820t_iq_tree(struct r820t_priv
*priv
,
1615 struct r820t_sect_type iq
[3],
1616 u8 fix_val
, u8 var_val
, u8 fix_reg
)
1622 * record IMC results by input gain/phase location then adjust
1623 * gain or phase positive 1 step and negtive 1 step,
1624 * both record results
1627 if (fix_reg
== 0x08)
1632 for (i
= 0; i
< 3; i
++) {
1633 rc
= r820t_write_reg(priv
, fix_reg
, fix_val
);
1637 rc
= r820t_write_reg(priv
, var_reg
, var_val
);
1641 rc
= r820t_multi_read(priv
);
1646 if (fix_reg
== 0x08) {
1647 iq
[i
].gain_x
= fix_val
;
1648 iq
[i
].phase_y
= var_val
;
1650 iq
[i
].phase_y
= fix_val
;
1651 iq
[i
].gain_x
= var_val
;
1654 if (i
== 0) { /* try right-side point */
1656 } else if (i
== 1) { /* try left-side point */
1657 /* if absolute location is 1, change I/Q direction */
1658 if ((var_val
& 0x1f) < 0x02) {
1659 tmp
= 2 - (var_val
& 0x1f);
1661 /* b[5]:I/Q selection. 0:Q-path, 1:I-path */
1662 if (var_val
& 0x20) {
1666 var_val
|= 0x20 | tmp
;
1677 static int r820t_section(struct r820t_priv
*priv
,
1678 struct r820t_sect_type
*iq_point
)
1681 struct r820t_sect_type compare_iq
[3], compare_bet
[3];
1683 /* Try X-1 column and save min result to compare_bet[0] */
1684 if (!(iq_point
->gain_x
& 0x1f))
1685 compare_iq
[0].gain_x
= ((iq_point
->gain_x
) & 0xdf) + 1; /* Q-path, Gain=1 */
1687 compare_iq
[0].gain_x
= iq_point
->gain_x
- 1; /* left point */
1688 compare_iq
[0].phase_y
= iq_point
->phase_y
;
1691 rc
= r820t_iq_tree(priv
, compare_iq
, compare_iq
[0].gain_x
,
1692 compare_iq
[0].phase_y
, 0x08);
1696 r820t_compre_cor(compare_iq
);
1698 compare_bet
[0] = compare_iq
[0];
1700 /* Try X column and save min result to compare_bet[1] */
1701 compare_iq
[0].gain_x
= iq_point
->gain_x
;
1702 compare_iq
[0].phase_y
= iq_point
->phase_y
;
1704 rc
= r820t_iq_tree(priv
, compare_iq
, compare_iq
[0].gain_x
,
1705 compare_iq
[0].phase_y
, 0x08);
1709 r820t_compre_cor(compare_iq
);
1711 compare_bet
[1] = compare_iq
[0];
1713 /* Try X+1 column and save min result to compare_bet[2] */
1714 if ((iq_point
->gain_x
& 0x1f) == 0x00)
1715 compare_iq
[0].gain_x
= ((iq_point
->gain_x
) | 0x20) + 1; /* I-path, Gain=1 */
1717 compare_iq
[0].gain_x
= iq_point
->gain_x
+ 1;
1718 compare_iq
[0].phase_y
= iq_point
->phase_y
;
1720 rc
= r820t_iq_tree(priv
, compare_iq
, compare_iq
[0].gain_x
,
1721 compare_iq
[0].phase_y
, 0x08);
1725 r820t_compre_cor(compare_iq
);
1727 compare_bet
[2] = compare_iq
[0];
1729 r820t_compre_cor(compare_bet
);
1731 *iq_point
= compare_bet
[0];
1736 static int r820t_vga_adjust(struct r820t_priv
*priv
)
1741 /* increase vga power to let image significant */
1742 for (vga_count
= 12; vga_count
< 16; vga_count
++) {
1743 rc
= r820t_write_reg_mask(priv
, 0x0c, vga_count
, 0x0f);
1747 usleep_range(10000, 11000);
1749 rc
= r820t_multi_read(priv
);
1760 static int r820t_iq(struct r820t_priv
*priv
, struct r820t_sect_type
*iq_pont
)
1762 struct r820t_sect_type compare_iq
[3];
1764 u8 x_direction
= 0; /* 1:x, 0:y */
1765 u8 dir_reg
, other_reg
;
1767 r820t_vga_adjust(priv
);
1769 rc
= r820t_imr_cross(priv
, compare_iq
, &x_direction
);
1773 if (x_direction
== 1) {
1781 /* compare and find min of 3 points. determine i/q direction */
1782 r820t_compre_cor(compare_iq
);
1784 /* increase step to find min value of this direction */
1785 rc
= r820t_compre_step(priv
, compare_iq
, dir_reg
);
1789 /* the other direction */
1790 rc
= r820t_iq_tree(priv
, compare_iq
, compare_iq
[0].gain_x
,
1791 compare_iq
[0].phase_y
, dir_reg
);
1795 /* compare and find min of 3 points. determine i/q direction */
1796 r820t_compre_cor(compare_iq
);
1798 /* increase step to find min value on this direction */
1799 rc
= r820t_compre_step(priv
, compare_iq
, other_reg
);
1803 /* check 3 points again */
1804 rc
= r820t_iq_tree(priv
, compare_iq
, compare_iq
[0].gain_x
,
1805 compare_iq
[0].phase_y
, other_reg
);
1809 r820t_compre_cor(compare_iq
);
1811 /* section-9 check */
1812 rc
= r820t_section(priv
, compare_iq
);
1814 *iq_pont
= compare_iq
[0];
1816 /* reset gain/phase control setting */
1817 rc
= r820t_write_reg_mask(priv
, 0x08, 0, 0x3f);
1821 rc
= r820t_write_reg_mask(priv
, 0x09, 0, 0x3f);
1826 static int r820t_f_imr(struct r820t_priv
*priv
, struct r820t_sect_type
*iq_pont
)
1830 r820t_vga_adjust(priv
);
1833 * search surrounding points from previous point
1834 * try (x-1), (x), (x+1) columns, and find min IMR result point
1836 rc
= r820t_section(priv
, iq_pont
);
1843 static int r820t_imr(struct r820t_priv
*priv
, unsigned imr_mem
, bool im_flag
)
1845 struct r820t_sect_type imr_point
;
1847 u32 ring_vco
, ring_freq
, ring_ref
;
1849 int reg18
, reg19
, reg1f
;
1851 if (priv
->cfg
->xtal
> 24000000)
1852 ring_ref
= priv
->cfg
->xtal
/ 2;
1854 ring_ref
= priv
->cfg
->xtal
;
1856 for (n
= 0; n
< 16; n
++) {
1857 if ((16 + n
) * 8 * ring_ref
>= 3100000) {
1862 /* n_ring not found */
1867 reg18
= r820t_read_cache_reg(priv
, 0x18);
1868 reg19
= r820t_read_cache_reg(priv
, 0x19);
1869 reg1f
= r820t_read_cache_reg(priv
, 0x1f);
1871 reg18
&= 0xf0; /* set ring[3:0] */
1874 ring_vco
= (16 + n_ring
) * 8 * ring_ref
;
1876 reg18
&= 0xdf; /* clear ring_se23 */
1877 reg19
&= 0xfc; /* clear ring_seldiv */
1878 reg1f
&= 0xfc; /* clear ring_att */
1882 ring_freq
= ring_vco
/ 48;
1883 reg18
|= 0x20; /* ring_se23 = 1 */
1884 reg19
|= 0x03; /* ring_seldiv = 3 */
1885 reg1f
|= 0x02; /* ring_att 10 */
1888 ring_freq
= ring_vco
/ 16;
1889 reg18
|= 0x00; /* ring_se23 = 0 */
1890 reg19
|= 0x02; /* ring_seldiv = 2 */
1891 reg1f
|= 0x00; /* pw_ring 00 */
1894 ring_freq
= ring_vco
/ 8;
1895 reg18
|= 0x00; /* ring_se23 = 0 */
1896 reg19
|= 0x01; /* ring_seldiv = 1 */
1897 reg1f
|= 0x03; /* pw_ring 11 */
1900 ring_freq
= ring_vco
/ 6;
1901 reg18
|= 0x20; /* ring_se23 = 1 */
1902 reg19
|= 0x00; /* ring_seldiv = 0 */
1903 reg1f
|= 0x03; /* pw_ring 11 */
1906 ring_freq
= ring_vco
/ 4;
1907 reg18
|= 0x00; /* ring_se23 = 0 */
1908 reg19
|= 0x00; /* ring_seldiv = 0 */
1909 reg1f
|= 0x01; /* pw_ring 01 */
1912 ring_freq
= ring_vco
/ 4;
1913 reg18
|= 0x00; /* ring_se23 = 0 */
1914 reg19
|= 0x00; /* ring_seldiv = 0 */
1915 reg1f
|= 0x01; /* pw_ring 01 */
1920 /* write pw_ring, n_ring, ringdiv2 registers */
1922 /* n_ring, ring_se23 */
1923 rc
= r820t_write_reg(priv
, 0x18, reg18
);
1928 rc
= r820t_write_reg(priv
, 0x19, reg19
);
1933 rc
= r820t_write_reg(priv
, 0x1f, reg1f
);
1937 /* mux input freq ~ rf_in freq */
1938 rc
= r820t_set_mux(priv
, (ring_freq
- 5300) * 1000);
1942 rc
= r820t_set_pll(priv
, V4L2_TUNER_DIGITAL_TV
,
1943 (ring_freq
- 5300) * 1000);
1944 if (!priv
->has_lock
)
1950 rc
= r820t_iq(priv
, &imr_point
);
1952 imr_point
.gain_x
= priv
->imr_data
[3].gain_x
;
1953 imr_point
.phase_y
= priv
->imr_data
[3].phase_y
;
1954 imr_point
.value
= priv
->imr_data
[3].value
;
1956 rc
= r820t_f_imr(priv
, &imr_point
);
1961 /* save IMR value */
1964 priv
->imr_data
[0].gain_x
= imr_point
.gain_x
;
1965 priv
->imr_data
[0].phase_y
= imr_point
.phase_y
;
1966 priv
->imr_data
[0].value
= imr_point
.value
;
1969 priv
->imr_data
[1].gain_x
= imr_point
.gain_x
;
1970 priv
->imr_data
[1].phase_y
= imr_point
.phase_y
;
1971 priv
->imr_data
[1].value
= imr_point
.value
;
1974 priv
->imr_data
[2].gain_x
= imr_point
.gain_x
;
1975 priv
->imr_data
[2].phase_y
= imr_point
.phase_y
;
1976 priv
->imr_data
[2].value
= imr_point
.value
;
1979 priv
->imr_data
[3].gain_x
= imr_point
.gain_x
;
1980 priv
->imr_data
[3].phase_y
= imr_point
.phase_y
;
1981 priv
->imr_data
[3].value
= imr_point
.value
;
1984 priv
->imr_data
[4].gain_x
= imr_point
.gain_x
;
1985 priv
->imr_data
[4].phase_y
= imr_point
.phase_y
;
1986 priv
->imr_data
[4].value
= imr_point
.value
;
1989 priv
->imr_data
[4].gain_x
= imr_point
.gain_x
;
1990 priv
->imr_data
[4].phase_y
= imr_point
.phase_y
;
1991 priv
->imr_data
[4].value
= imr_point
.value
;
1998 static int r820t_imr_callibrate(struct r820t_priv
*priv
)
2003 if (priv
->init_done
)
2006 /* Detect Xtal capacitance */
2007 if ((priv
->cfg
->rafael_chip
== CHIP_R820T
) ||
2008 (priv
->cfg
->rafael_chip
== CHIP_R828S
) ||
2009 (priv
->cfg
->rafael_chip
== CHIP_R820C
)) {
2010 priv
->xtal_cap_sel
= XTAL_HIGH_CAP_0P
;
2012 /* Initialize registers */
2013 rc
= r820t_write(priv
, 0x05,
2014 r820t_init_array
, sizeof(r820t_init_array
));
2017 for (i
= 0; i
< 3; i
++) {
2018 rc
= r820t_xtal_check(priv
);
2021 if (!i
|| rc
> xtal_cap
)
2024 priv
->xtal_cap_sel
= xtal_cap
;
2028 * Disables IMR callibration. That emulates the same behaviour
2029 * as what is done by rtl-sdr userspace library. Useful for testing
2032 priv
->init_done
= true;
2037 /* Initialize registers */
2038 rc
= r820t_write(priv
, 0x05,
2039 r820t_init_array
, sizeof(r820t_init_array
));
2043 rc
= r820t_imr_prepare(priv
);
2047 rc
= r820t_imr(priv
, 3, true);
2050 rc
= r820t_imr(priv
, 1, false);
2053 rc
= r820t_imr(priv
, 0, false);
2056 rc
= r820t_imr(priv
, 2, false);
2059 rc
= r820t_imr(priv
, 4, false);
2063 priv
->init_done
= true;
2064 priv
->imr_done
= true;
2070 /* Not used, for now */
2071 static int r820t_gpio(struct r820t_priv
*priv
, bool enable
)
2073 return r820t_write_reg_mask(priv
, 0x0f, enable
? 1 : 0, 0x01);
2078 * r820t frontend operations and tuner attach code
2080 * All driver locks and i2c control are only in this part of the code
2083 static int r820t_init(struct dvb_frontend
*fe
)
2085 struct r820t_priv
*priv
= fe
->tuner_priv
;
2088 tuner_dbg("%s:\n", __func__
);
2090 mutex_lock(&priv
->lock
);
2091 if (fe
->ops
.i2c_gate_ctrl
)
2092 fe
->ops
.i2c_gate_ctrl(fe
, 1);
2094 rc
= r820t_imr_callibrate(priv
);
2098 /* Initialize registers */
2099 rc
= r820t_write(priv
, 0x05,
2100 r820t_init_array
, sizeof(r820t_init_array
));
2103 if (fe
->ops
.i2c_gate_ctrl
)
2104 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2105 mutex_unlock(&priv
->lock
);
2108 tuner_dbg("%s: failed=%d\n", __func__
, rc
);
2112 static int r820t_sleep(struct dvb_frontend
*fe
)
2114 struct r820t_priv
*priv
= fe
->tuner_priv
;
2117 tuner_dbg("%s:\n", __func__
);
2119 mutex_lock(&priv
->lock
);
2120 if (fe
->ops
.i2c_gate_ctrl
)
2121 fe
->ops
.i2c_gate_ctrl(fe
, 1);
2123 rc
= r820t_standby(priv
);
2125 if (fe
->ops
.i2c_gate_ctrl
)
2126 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2127 mutex_unlock(&priv
->lock
);
2129 tuner_dbg("%s: failed=%d\n", __func__
, rc
);
2133 static int r820t_set_analog_freq(struct dvb_frontend
*fe
,
2134 struct analog_parameters
*p
)
2136 struct r820t_priv
*priv
= fe
->tuner_priv
;
2140 tuner_dbg("%s called\n", __func__
);
2142 /* if std is not defined, choose one */
2144 p
->std
= V4L2_STD_MN
;
2146 if ((p
->std
== V4L2_STD_PAL_M
) || (p
->std
== V4L2_STD_NTSC
))
2151 mutex_lock(&priv
->lock
);
2152 if (fe
->ops
.i2c_gate_ctrl
)
2153 fe
->ops
.i2c_gate_ctrl(fe
, 1);
2155 rc
= generic_set_freq(fe
, 62500l * p
->frequency
, bw
,
2156 V4L2_TUNER_ANALOG_TV
, p
->std
, SYS_UNDEFINED
);
2158 if (fe
->ops
.i2c_gate_ctrl
)
2159 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2160 mutex_unlock(&priv
->lock
);
2165 static int r820t_set_params(struct dvb_frontend
*fe
)
2167 struct r820t_priv
*priv
= fe
->tuner_priv
;
2168 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
2172 tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
2173 __func__
, c
->delivery_system
, c
->frequency
, c
->bandwidth_hz
);
2175 mutex_lock(&priv
->lock
);
2176 if (fe
->ops
.i2c_gate_ctrl
)
2177 fe
->ops
.i2c_gate_ctrl(fe
, 1);
2179 bw
= (c
->bandwidth_hz
+ 500000) / 1000000;
2183 rc
= generic_set_freq(fe
, c
->frequency
, bw
,
2184 V4L2_TUNER_DIGITAL_TV
, 0, c
->delivery_system
);
2186 if (fe
->ops
.i2c_gate_ctrl
)
2187 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2188 mutex_unlock(&priv
->lock
);
2191 tuner_dbg("%s: failed=%d\n", __func__
, rc
);
2195 static int r820t_signal(struct dvb_frontend
*fe
, u16
*strength
)
2197 struct r820t_priv
*priv
= fe
->tuner_priv
;
2200 mutex_lock(&priv
->lock
);
2201 if (fe
->ops
.i2c_gate_ctrl
)
2202 fe
->ops
.i2c_gate_ctrl(fe
, 1);
2204 if (priv
->has_lock
) {
2205 rc
= r820t_read_gain(priv
);
2209 /* A higher gain at LNA means a lower signal strength */
2210 *strength
= (45 - rc
) << 4 | 0xff;
2211 if (*strength
== 0xff)
2218 if (fe
->ops
.i2c_gate_ctrl
)
2219 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2220 mutex_unlock(&priv
->lock
);
2222 tuner_dbg("%s: %s, gain=%d strength=%d\n",
2224 priv
->has_lock
? "PLL locked" : "no signal",
2230 static int r820t_get_if_frequency(struct dvb_frontend
*fe
, u32
*frequency
)
2232 struct r820t_priv
*priv
= fe
->tuner_priv
;
2234 tuner_dbg("%s:\n", __func__
);
2236 *frequency
= priv
->int_freq
;
2241 static int r820t_release(struct dvb_frontend
*fe
)
2243 struct r820t_priv
*priv
= fe
->tuner_priv
;
2245 tuner_dbg("%s:\n", __func__
);
2247 mutex_lock(&r820t_list_mutex
);
2250 hybrid_tuner_release_state(priv
);
2252 mutex_unlock(&r820t_list_mutex
);
2254 fe
->tuner_priv
= NULL
;
2256 kfree(fe
->tuner_priv
);
2261 static const struct dvb_tuner_ops r820t_tuner_ops
= {
2263 .name
= "Rafael Micro R820T",
2264 .frequency_min
= 42000000,
2265 .frequency_max
= 1002000000,
2268 .release
= r820t_release
,
2269 .sleep
= r820t_sleep
,
2270 .set_params
= r820t_set_params
,
2271 .set_analog_params
= r820t_set_analog_freq
,
2272 .get_if_frequency
= r820t_get_if_frequency
,
2273 .get_rf_strength
= r820t_signal
,
2276 struct dvb_frontend
*r820t_attach(struct dvb_frontend
*fe
,
2277 struct i2c_adapter
*i2c
,
2278 const struct r820t_config
*cfg
)
2280 struct r820t_priv
*priv
;
2285 mutex_lock(&r820t_list_mutex
);
2287 instance
= hybrid_tuner_request_state(struct r820t_priv
, priv
,
2288 hybrid_tuner_instance_list
,
2293 /* memory allocation failure */
2297 /* new tuner instance */
2300 mutex_init(&priv
->lock
);
2302 fe
->tuner_priv
= priv
;
2305 /* existing tuner instance */
2306 fe
->tuner_priv
= priv
;
2310 memcpy(&fe
->ops
.tuner_ops
, &r820t_tuner_ops
, sizeof(r820t_tuner_ops
));
2312 if (fe
->ops
.i2c_gate_ctrl
)
2313 fe
->ops
.i2c_gate_ctrl(fe
, 1);
2315 /* check if the tuner is there */
2316 rc
= r820t_read(priv
, 0x00, data
, sizeof(data
));
2320 rc
= r820t_sleep(fe
);
2324 tuner_info("Rafael Micro r820t successfully identified\n");
2326 fe
->tuner_priv
= priv
;
2327 memcpy(&fe
->ops
.tuner_ops
, &r820t_tuner_ops
,
2328 sizeof(struct dvb_tuner_ops
));
2330 if (fe
->ops
.i2c_gate_ctrl
)
2331 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2333 mutex_unlock(&r820t_list_mutex
);
2337 if (fe
->ops
.i2c_gate_ctrl
)
2338 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2341 mutex_unlock(&r820t_list_mutex
);
2343 tuner_info("%s: failed=%d\n", __func__
, rc
);
2347 EXPORT_SYMBOL_GPL(r820t_attach
);
2349 MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
2350 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2351 MODULE_LICENSE("GPL");