projects / deliverable / linux.git / blob
? search:


eaaf1dc9dfa8b96e52dcede772cda7f2455ef051
[deliverable/linux.git] / drivers / media / tuners / r820t.c
1 /*
2 * Rafael Micro R820T driver
3 *
4 * Copyright (C) 2013 Mauro Carvalho Chehab
5 *
6 * This driver was written from scratch, based on an existing driver
7 * that it is part of rtl-sdr git tree, released under GPLv2:
8 * https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug
9 * https://github.com/n1gp/gr-baz
10 *
11 * From what I understood from the threads, the original driver was converted
12 * to userspace from a Realtek tree. I couldn't find the original tree.
13 * However, the original driver look awkward on my eyes. So, I decided to
14 * write a new version from it from the scratch, while trying to reproduce
15 * everything found there.
16 *
17 * TODO:
18 * After locking, the original driver seems to have some routines to
19 * improve reception. This was not implemented here yet.
20 *
21 * RF Gain set/get is not implemented.
22 *
23 * This program is free software; you can redistribute it and/or modify
24 * it under the terms of the GNU General Public License as published by
25 * the Free Software Foundation; either version 2 of the License, or
26 * (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 */
34
35 #include <linux/videodev2.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/bitrev.h>
39
40 #include "tuner-i2c.h"
41 #include "r820t.h"
42
43 /*
44 * FIXME: I think that there are only 32 registers, but better safe than
45 * sorry. After finishing the driver, we may review it.
46 */
47 #define REG_SHADOW_START 5
48 #define NUM_REGS 27
49 #define NUM_IMR 5
50 #define IMR_TRIAL 9
51
52 #define VER_NUM 49
53
54 static int debug;
55 module_param(debug, int, 0644);
56 MODULE_PARM_DESC(debug, "enable verbose debug messages");
57
58 static int no_imr_cal;
59 module_param(no_imr_cal, int, 0444);
60 MODULE_PARM_DESC(no_imr_cal, "Disable IMR calibration at module init");
61
62
63 /*
64 * enums and structures
65 */
66
67 enum xtal_cap_value {
68 XTAL_LOW_CAP_30P = 0,
69 XTAL_LOW_CAP_20P,
70 XTAL_LOW_CAP_10P,
71 XTAL_LOW_CAP_0P,
72 XTAL_HIGH_CAP_0P
73 };
74
75 struct r820t_sect_type {
76 u8 phase_y;
77 u8 gain_x;
78 u16 value;
79 };
80
81 struct r820t_priv {
82 struct list_head hybrid_tuner_instance_list;
83 const struct r820t_config *cfg;
84 struct tuner_i2c_props i2c_props;
85 struct mutex lock;
86
87 u8 regs[NUM_REGS];
88 u8 buf[NUM_REGS + 1];
89 enum xtal_cap_value xtal_cap_sel;
90 u16 pll; /* kHz */
91 u32 int_freq;
92 u8 fil_cal_code;
93 bool imr_done;
94 bool has_lock;
95 bool init_done;
96 struct r820t_sect_type imr_data[NUM_IMR];
97
98 /* Store current mode */
99 u32 delsys;
100 enum v4l2_tuner_type type;
101 v4l2_std_id std;
102 u32 bw; /* in MHz */
103 };
104
105 struct r820t_freq_range {
106 u32 freq;
107 u8 open_d;
108 u8 rf_mux_ploy;
109 u8 tf_c;
110 u8 xtal_cap20p;
111 u8 xtal_cap10p;
112 u8 xtal_cap0p;
113 u8 imr_mem; /* Not used, currently */
114 };
115
116 #define VCO_POWER_REF 0x02
117 #define DIP_FREQ 32000000
118
119 /*
120 * Static constants
121 */
122
123 static LIST_HEAD(hybrid_tuner_instance_list);
124 static DEFINE_MUTEX(r820t_list_mutex);
125
126 /* Those initial values start from REG_SHADOW_START */
127 static const u8 r820t_init_array[NUM_REGS] = {
128 0x83, 0x32, 0x75, /* 05 to 07 */
129 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */
130 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */
131 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */
132 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */
133 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */
134 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */
135 };
136
137 /* Tuner frequency ranges */
138 static const struct r820t_freq_range freq_ranges[] = {
139 {
140 .freq = 0,
141 .open_d = 0x08, /* low */
142 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
143 .tf_c = 0xdf, /* R27[7:0] band2,band0 */
144 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
145 .xtal_cap10p = 0x01,
146 .xtal_cap0p = 0x00,
147 .imr_mem = 0,
148 }, {
149 .freq = 50, /* Start freq, in MHz */
150 .open_d = 0x08, /* low */
151 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
152 .tf_c = 0xbe, /* R27[7:0] band4,band1 */
153 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
154 .xtal_cap10p = 0x01,
155 .xtal_cap0p = 0x00,
156 .imr_mem = 0,
157 }, {
158 .freq = 55, /* Start freq, in MHz */
159 .open_d = 0x08, /* low */
160 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
161 .tf_c = 0x8b, /* R27[7:0] band7,band4 */
162 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
163 .xtal_cap10p = 0x01,
164 .xtal_cap0p = 0x00,
165 .imr_mem = 0,
166 }, {
167 .freq = 60, /* Start freq, in MHz */
168 .open_d = 0x08, /* low */
169 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
170 .tf_c = 0x7b, /* R27[7:0] band8,band4 */
171 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
172 .xtal_cap10p = 0x01,
173 .xtal_cap0p = 0x00,
174 .imr_mem = 0,
175 }, {
176 .freq = 65, /* Start freq, in MHz */
177 .open_d = 0x08, /* low */
178 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
179 .tf_c = 0x69, /* R27[7:0] band9,band6 */
180 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
181 .xtal_cap10p = 0x01,
182 .xtal_cap0p = 0x00,
183 .imr_mem = 0,
184 }, {
185 .freq = 70, /* Start freq, in MHz */
186 .open_d = 0x08, /* low */
187 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
188 .tf_c = 0x58, /* R27[7:0] band10,band7 */
189 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
190 .xtal_cap10p = 0x01,
191 .xtal_cap0p = 0x00,
192 .imr_mem = 0,
193 }, {
194 .freq = 75, /* Start freq, in MHz */
195 .open_d = 0x00, /* high */
196 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
197 .tf_c = 0x44, /* R27[7:0] band11,band11 */
198 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
199 .xtal_cap10p = 0x01,
200 .xtal_cap0p = 0x00,
201 .imr_mem = 0,
202 }, {
203 .freq = 80, /* Start freq, in MHz */
204 .open_d = 0x00, /* high */
205 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
206 .tf_c = 0x44, /* R27[7:0] band11,band11 */
207 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
208 .xtal_cap10p = 0x01,
209 .xtal_cap0p = 0x00,
210 .imr_mem = 0,
211 }, {
212 .freq = 90, /* Start freq, in MHz */
213 .open_d = 0x00, /* high */
214 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
215 .tf_c = 0x34, /* R27[7:0] band12,band11 */
216 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
217 .xtal_cap10p = 0x01,
218 .xtal_cap0p = 0x00,
219 .imr_mem = 0,
220 }, {
221 .freq = 100, /* Start freq, in MHz */
222 .open_d = 0x00, /* high */
223 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
224 .tf_c = 0x34, /* R27[7:0] band12,band11 */
225 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
226 .xtal_cap10p = 0x01,
227 .xtal_cap0p = 0x00,
228 .imr_mem = 0,
229 }, {
230 .freq = 110, /* Start freq, in MHz */
231 .open_d = 0x00, /* high */
232 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
233 .tf_c = 0x24, /* R27[7:0] band13,band11 */
234 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
235 .xtal_cap10p = 0x01,
236 .xtal_cap0p = 0x00,
237 .imr_mem = 1,
238 }, {
239 .freq = 120, /* Start freq, in MHz */
240 .open_d = 0x00, /* high */
241 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
242 .tf_c = 0x24, /* R27[7:0] band13,band11 */
243 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
244 .xtal_cap10p = 0x01,
245 .xtal_cap0p = 0x00,
246 .imr_mem = 1,
247 }, {
248 .freq = 140, /* Start freq, in MHz */
249 .open_d = 0x00, /* high */
250 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
251 .tf_c = 0x14, /* R27[7:0] band14,band11 */
252 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
253 .xtal_cap10p = 0x01,
254 .xtal_cap0p = 0x00,
255 .imr_mem = 1,
256 }, {
257 .freq = 180, /* Start freq, in MHz */
258 .open_d = 0x00, /* high */
259 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
260 .tf_c = 0x13, /* R27[7:0] band14,band12 */
261 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
262 .xtal_cap10p = 0x00,
263 .xtal_cap0p = 0x00,
264 .imr_mem = 1,
265 }, {
266 .freq = 220, /* Start freq, in MHz */
267 .open_d = 0x00, /* high */
268 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
269 .tf_c = 0x13, /* R27[7:0] band14,band12 */
270 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
271 .xtal_cap10p = 0x00,
272 .xtal_cap0p = 0x00,
273 .imr_mem = 2,
274 }, {
275 .freq = 250, /* Start freq, in MHz */
276 .open_d = 0x00, /* high */
277 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
278 .tf_c = 0x11, /* R27[7:0] highest,highest */
279 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
280 .xtal_cap10p = 0x00,
281 .xtal_cap0p = 0x00,
282 .imr_mem = 2,
283 }, {
284 .freq = 280, /* Start freq, in MHz */
285 .open_d = 0x00, /* high */
286 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
287 .tf_c = 0x00, /* R27[7:0] highest,highest */
288 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
289 .xtal_cap10p = 0x00,
290 .xtal_cap0p = 0x00,
291 .imr_mem = 2,
292 }, {
293 .freq = 310, /* Start freq, in MHz */
294 .open_d = 0x00, /* high */
295 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
296 .tf_c = 0x00, /* R27[7:0] highest,highest */
297 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
298 .xtal_cap10p = 0x00,
299 .xtal_cap0p = 0x00,
300 .imr_mem = 2,
301 }, {
302 .freq = 450, /* Start freq, in MHz */
303 .open_d = 0x00, /* high */
304 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
305 .tf_c = 0x00, /* R27[7:0] highest,highest */
306 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
307 .xtal_cap10p = 0x00,
308 .xtal_cap0p = 0x00,
309 .imr_mem = 3,
310 }, {
311 .freq = 588, /* Start freq, in MHz */
312 .open_d = 0x00, /* high */
313 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
314 .tf_c = 0x00, /* R27[7:0] highest,highest */
315 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
316 .xtal_cap10p = 0x00,
317 .xtal_cap0p = 0x00,
318 .imr_mem = 3,
319 }, {
320 .freq = 650, /* Start freq, in MHz */
321 .open_d = 0x00, /* high */
322 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
323 .tf_c = 0x00, /* R27[7:0] highest,highest */
324 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
325 .xtal_cap10p = 0x00,
326 .xtal_cap0p = 0x00,
327 .imr_mem = 4,
328 }
329 };
330
331 static int r820t_xtal_capacitor[][2] = {
332 { 0x0b, XTAL_LOW_CAP_30P },
333 { 0x02, XTAL_LOW_CAP_20P },
334 { 0x01, XTAL_LOW_CAP_10P },
335 { 0x00, XTAL_LOW_CAP_0P },
336 { 0x10, XTAL_HIGH_CAP_0P },
337 };
338
339 /*
340 * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
341 * input power, for raw results see:
342 * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
343 */
344
345 static const int r820t_lna_gain_steps[] = {
346 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
347 };
348
349 static const int r820t_mixer_gain_steps[] = {
350 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
351 };
352
353 /*
354 * I2C read/write code and shadow registers logic
355 */
356 static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val,
357 int len)
358 {
359 int r = reg - REG_SHADOW_START;
360
361 if (r < 0) {
362 len += r;
363 r = 0;
364 }
365 if (len <= 0)
366 return;
367 if (len > NUM_REGS - r)
368 len = NUM_REGS - r;
369
370 tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n",
371 __func__, r + REG_SHADOW_START, len, len, val);
372
373 memcpy(&priv->regs[r], val, len);
374 }
375
376 static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val,
377 int len)
378 {
379 int rc, size, pos = 0;
380
381 /* Store the shadow registers */
382 shadow_store(priv, reg, val, len);
383
384 do {
385 if (len > priv->cfg->max_i2c_msg_len - 1)
386 size = priv->cfg->max_i2c_msg_len - 1;
387 else
388 size = len;
389
390 /* Fill I2C buffer */
391 priv->buf[0] = reg;
392 memcpy(&priv->buf[1], &val[pos], size);
393
394 rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1);
395 if (rc != size + 1) {
396 tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
397 __func__, rc, reg, size, size, &priv->buf[1]);
398 if (rc < 0)
399 return rc;
400 return -EREMOTEIO;
401 }
402 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
403 __func__, reg, size, size, &priv->buf[1]);
404
405 reg += size;
406 len -= size;
407 pos += size;
408 } while (len > 0);
409
410 return 0;
411 }
412
413 static int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val)
414 {
415 return r820t_write(priv, reg, &val, 1);
416 }
417
418 static int r820t_read_cache_reg(struct r820t_priv *priv, int reg)
419 {
420 reg -= REG_SHADOW_START;
421
422 if (reg >= 0 && reg < NUM_REGS)
423 return priv->regs[reg];
424 else
425 return -EINVAL;
426 }
427
428 static int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val,
429 u8 bit_mask)
430 {
431 int rc = r820t_read_cache_reg(priv, reg);
432
433 if (rc < 0)
434 return rc;
435
436 val = (rc & ~bit_mask) | (val & bit_mask);
437
438 return r820t_write(priv, reg, &val, 1);
439 }
440
441 static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len)
442 {
443 int rc, i;
444 u8 *p = &priv->buf[1];
445
446 priv->buf[0] = reg;
447
448 rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len);
449 if (rc != len) {
450 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
451 __func__, rc, reg, len, len, p);
452 if (rc < 0)
453 return rc;
454 return -EREMOTEIO;
455 }
456
457 /* Copy data to the output buffer */
458 for (i = 0; i < len; i++)
459 val[i] = bitrev8(p[i]);
460
461 tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
462 __func__, reg, len, len, val);
463
464 return 0;
465 }
466
467 /*
468 * r820t tuning logic
469 */
470
471 static int r820t_set_mux(struct r820t_priv *priv, u32 freq)
472 {
473 const struct r820t_freq_range *range;
474 int i, rc;
475 u8 val, reg08, reg09;
476
477 /* Get the proper frequency range */
478 freq = freq / 1000000;
479 for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) {
480 if (freq < freq_ranges[i + 1].freq)
481 break;
482 }
483 range = &freq_ranges[i];
484
485 tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq);
486
487 /* Open Drain */
488 rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08);
489 if (rc < 0)
490 return rc;
491
492 /* RF_MUX,Polymux */
493 rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3);
494 if (rc < 0)
495 return rc;
496
497 /* TF BAND */
498 rc = r820t_write_reg(priv, 0x1b, range->tf_c);
499 if (rc < 0)
500 return rc;
501
502 /* XTAL CAP & Drive */
503 switch (priv->xtal_cap_sel) {
504 case XTAL_LOW_CAP_30P:
505 case XTAL_LOW_CAP_20P:
506 val = range->xtal_cap20p | 0x08;
507 break;
508 case XTAL_LOW_CAP_10P:
509 val = range->xtal_cap10p | 0x08;
510 break;
511 case XTAL_HIGH_CAP_0P:
512 val = range->xtal_cap0p | 0x00;
513 break;
514 default:
515 case XTAL_LOW_CAP_0P:
516 val = range->xtal_cap0p | 0x08;
517 break;
518 }
519 rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b);
520 if (rc < 0)
521 return rc;
522
523 if (priv->imr_done) {
524 reg08 = priv->imr_data[range->imr_mem].gain_x;
525 reg09 = priv->imr_data[range->imr_mem].phase_y;
526 } else {
527 reg08 = 0;
528 reg09 = 0;
529 }
530 rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f);
531 if (rc < 0)
532 return rc;
533
534 rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f);
535
536 return rc;
537 }
538
539 static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type,
540 u32 freq)
541 {
542 u32 vco_freq;
543 int rc, i;
544 unsigned sleep_time = 10000;
545 u32 vco_fra; /* VCO contribution by SDM (kHz) */
546 u32 vco_min = 1770000;
547 u32 vco_max = vco_min * 2;
548 u32 pll_ref;
549 u16 n_sdm = 2;
550 u16 sdm = 0;
551 u8 mix_div = 2;
552 u8 div_buf = 0;
553 u8 div_num = 0;
554 u8 refdiv2 = 0;
555 u8 ni, si, nint, vco_fine_tune, val;
556 u8 data[5];
557
558 /* Frequency in kHz */
559 freq = freq / 1000;
560 pll_ref = priv->cfg->xtal / 1000;
561
562 #if 0
563 /* Doesn't exist on rtl-sdk, and on field tests, caused troubles */
564 if ((priv->cfg->rafael_chip == CHIP_R620D) ||
565 (priv->cfg->rafael_chip == CHIP_R828D) ||
566 (priv->cfg->rafael_chip == CHIP_R828)) {
567 /* ref set refdiv2, reffreq = Xtal/2 on ATV application */
568 if (type != V4L2_TUNER_DIGITAL_TV) {
569 pll_ref /= 2;
570 refdiv2 = 0x10;
571 sleep_time = 20000;
572 }
573 } else {
574 if (priv->cfg->xtal > 24000000) {
575 pll_ref /= 2;
576 refdiv2 = 0x10;
577 }
578 }
579 #endif
580
581 rc = r820t_write_reg_mask(priv, 0x10, refdiv2, 0x10);
582 if (rc < 0)
583 return rc;
584
585 /* set pll autotune = 128kHz */
586 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
587 if (rc < 0)
588 return rc;
589
590 /* set VCO current = 100 */
591 rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0);
592 if (rc < 0)
593 return rc;
594
595 /* Calculate divider */
596 while (mix_div <= 64) {
597 if (((freq * mix_div) >= vco_min) &&
598 ((freq * mix_div) < vco_max)) {
599 div_buf = mix_div;
600 while (div_buf > 2) {
601 div_buf = div_buf >> 1;
602 div_num++;
603 }
604 break;
605 }
606 mix_div = mix_div << 1;
607 }
608
609 rc = r820t_read(priv, 0x00, data, sizeof(data));
610 if (rc < 0)
611 return rc;
612
613 vco_fine_tune = (data[4] & 0x30) >> 4;
614
615 tuner_dbg("mix_div=%d div_num=%d vco_fine_tune=%d\n",
616 mix_div, div_num, vco_fine_tune);
617
618 /*
619 * XXX: R828D/16MHz seems to have always vco_fine_tune=1.
620 * Due to that, this calculation goes wrong.
621 */
622 if (priv->cfg->rafael_chip != CHIP_R828D) {
623 if (vco_fine_tune > VCO_POWER_REF)
624 div_num = div_num - 1;
625 else if (vco_fine_tune < VCO_POWER_REF)
626 div_num = div_num + 1;
627 }
628
629 rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0);
630 if (rc < 0)
631 return rc;
632
633 vco_freq = freq * mix_div;
634 nint = vco_freq / (2 * pll_ref);
635 vco_fra = vco_freq - 2 * pll_ref * nint;
636
637 /* boundary spur prevention */
638 if (vco_fra < pll_ref / 64) {
639 vco_fra = 0;
640 } else if (vco_fra > pll_ref * 127 / 64) {
641 vco_fra = 0;
642 nint++;
643 } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) {
644 vco_fra = pll_ref * 127 / 128;
645 } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) {
646 vco_fra = pll_ref * 129 / 128;
647 }
648
649 ni = (nint - 13) / 4;
650 si = nint - 4 * ni - 13;
651
652 rc = r820t_write_reg(priv, 0x14, ni + (si << 6));
653 if (rc < 0)
654 return rc;
655
656 /* pw_sdm */
657 if (!vco_fra)
658 val = 0x08;
659 else
660 val = 0x00;
661
662 rc = r820t_write_reg_mask(priv, 0x12, val, 0x08);
663 if (rc < 0)
664 return rc;
665
666 /* sdm calculator */
667 while (vco_fra > 1) {
668 if (vco_fra > (2 * pll_ref / n_sdm)) {
669 sdm = sdm + 32768 / (n_sdm / 2);
670 vco_fra = vco_fra - 2 * pll_ref / n_sdm;
671 if (n_sdm >= 0x8000)
672 break;
673 }
674 n_sdm = n_sdm << 1;
675 }
676
677 tuner_dbg("freq %d kHz, pll ref %d%s, sdm=0x%04x\n",
678 freq, pll_ref, refdiv2 ? " / 2" : "", sdm);
679
680 rc = r820t_write_reg(priv, 0x16, sdm >> 8);
681 if (rc < 0)
682 return rc;
683 rc = r820t_write_reg(priv, 0x15, sdm & 0xff);
684 if (rc < 0)
685 return rc;
686
687 for (i = 0; i < 2; i++) {
688 usleep_range(sleep_time, sleep_time + 1000);
689
690 /* Check if PLL has locked */
691 rc = r820t_read(priv, 0x00, data, 3);
692 if (rc < 0)
693 return rc;
694 if (data[2] & 0x40)
695 break;
696
697 if (!i) {
698 /* Didn't lock. Increase VCO current */
699 rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0);
700 if (rc < 0)
701 return rc;
702 }
703 }
704
705 if (!(data[2] & 0x40)) {
706 priv->has_lock = false;
707 return 0;
708 }
709
710 priv->has_lock = true;
711 tuner_dbg("tuner has lock at frequency %d kHz\n", freq);
712
713 /* set pll autotune = 8kHz */
714 rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08);
715
716 return rc;
717 }
718
719 static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq,
720 enum v4l2_tuner_type type,
721 v4l2_std_id std,
722 u32 delsys)
723 {
724 int rc;
725 u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l;
726 u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur;
727
728 tuner_dbg("adjusting tuner parameters for the standard\n");
729
730 switch (delsys) {
731 case SYS_DVBT:
732 if ((freq == 506000000) || (freq == 666000000) ||
733 (freq == 818000000)) {
734 mixer_top = 0x14; /* mixer top:14 , top-1, low-discharge */
735 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
736 cp_cur = 0x28; /* 101, 0.2 */
737 div_buf_cur = 0x20; /* 10, 200u */
738 } else {
739 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
740 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
741 cp_cur = 0x38; /* 111, auto */
742 div_buf_cur = 0x30; /* 11, 150u */
743 }
744 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
745 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
746 air_cable1_in = 0x00;
747 cable2_in = 0x00;
748 pre_dect = 0x40;
749 lna_discharge = 14;
750 filter_cur = 0x40; /* 10, low */
751 break;
752 case SYS_DVBT2:
753 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
754 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
755 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
756 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
757 air_cable1_in = 0x00;
758 cable2_in = 0x00;
759 pre_dect = 0x40;
760 lna_discharge = 14;
761 cp_cur = 0x38; /* 111, auto */
762 div_buf_cur = 0x30; /* 11, 150u */
763 filter_cur = 0x40; /* 10, low */
764 break;
765 case SYS_ISDBT:
766 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
767 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
768 lna_vth_l = 0x75; /* lna vth 1.04 , vtl 0.84 */
769 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
770 air_cable1_in = 0x00;
771 cable2_in = 0x00;
772 pre_dect = 0x40;
773 lna_discharge = 14;
774 cp_cur = 0x38; /* 111, auto */
775 div_buf_cur = 0x30; /* 11, 150u */
776 filter_cur = 0x40; /* 10, low */
777 break;
778 case SYS_DVBC_ANNEX_A:
779 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
780 lna_top = 0xe5;
781 lna_vth_l = 0x62;
782 mixer_vth_l = 0x75;
783 air_cable1_in = 0x60;
784 cable2_in = 0x00;
785 pre_dect = 0x40;
786 lna_discharge = 14;
787 cp_cur = 0x38; /* 111, auto */
788 div_buf_cur = 0x30; /* 11, 150u */
789 filter_cur = 0x40; /* 10, low */
790 break;
791 default: /* DVB-T 8M */
792 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
793 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
794 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
795 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
796 air_cable1_in = 0x00;
797 cable2_in = 0x00;
798 pre_dect = 0x40;
799 lna_discharge = 14;
800 cp_cur = 0x38; /* 111, auto */
801 div_buf_cur = 0x30; /* 11, 150u */
802 filter_cur = 0x40; /* 10, low */
803 break;
804 }
805
806 if (priv->cfg->use_diplexer &&
807 ((priv->cfg->rafael_chip == CHIP_R820T) ||
808 (priv->cfg->rafael_chip == CHIP_R828S) ||
809 (priv->cfg->rafael_chip == CHIP_R820C))) {
810 if (freq > DIP_FREQ)
811 air_cable1_in = 0x00;
812 else
813 air_cable1_in = 0x60;
814 cable2_in = 0x00;
815 }
816
817
818 if (priv->cfg->use_predetect) {
819 rc = r820t_write_reg_mask(priv, 0x06, pre_dect, 0x40);
820 if (rc < 0)
821 return rc;
822 }
823
824 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7);
825 if (rc < 0)
826 return rc;
827 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8);
828 if (rc < 0)
829 return rc;
830 rc = r820t_write_reg(priv, 0x0d, lna_vth_l);
831 if (rc < 0)
832 return rc;
833 rc = r820t_write_reg(priv, 0x0e, mixer_vth_l);
834 if (rc < 0)
835 return rc;
836
837 /* Air-IN only for Astrometa */
838 rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60);
839 if (rc < 0)
840 return rc;
841 rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08);
842 if (rc < 0)
843 return rc;
844
845 rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38);
846 if (rc < 0)
847 return rc;
848 rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30);
849 if (rc < 0)
850 return rc;
851 rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60);
852 if (rc < 0)
853 return rc;
854 /*
855 * Original driver initializes regs 0x05 and 0x06 with the
856 * same value again on this point. Probably, it is just an
857 * error there
858 */
859
860 /*
861 * Set LNA
862 */
863
864 tuner_dbg("adjusting LNA parameters\n");
865 if (type != V4L2_TUNER_ANALOG_TV) {
866 /* LNA TOP: lowest */
867 rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38);
868 if (rc < 0)
869 return rc;
870
871 /* 0: normal mode */
872 rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04);
873 if (rc < 0)
874 return rc;
875
876 /* 0: PRE_DECT off */
877 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
878 if (rc < 0)
879 return rc;
880
881 /* agc clk 250hz */
882 rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30);
883 if (rc < 0)
884 return rc;
885
886 msleep(250);
887
888 /* write LNA TOP = 3 */
889 rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38);
890 if (rc < 0)
891 return rc;
892
893 /*
894 * write discharge mode
895 * FIXME: IMHO, the mask here is wrong, but it matches
896 * what's there at the original driver
897 */
898 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
899 if (rc < 0)
900 return rc;
901
902 /* LNA discharge current */
903 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
904 if (rc < 0)
905 return rc;
906
907 /* agc clk 60hz */
908 rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30);
909 if (rc < 0)
910 return rc;
911 } else {
912 /* PRE_DECT off */
913 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
914 if (rc < 0)
915 return rc;
916
917 /* write LNA TOP */
918 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38);
919 if (rc < 0)
920 return rc;
921
922 /*
923 * write discharge mode
924 * FIXME: IMHO, the mask here is wrong, but it matches
925 * what's there at the original driver
926 */
927 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
928 if (rc < 0)
929 return rc;
930
931 /* LNA discharge current */
932 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
933 if (rc < 0)
934 return rc;
935
936 /* agc clk 1Khz, external det1 cap 1u */
937 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30);
938 if (rc < 0)
939 return rc;
940
941 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04);
942 if (rc < 0)
943 return rc;
944 }
945 return 0;
946 }
947
948 static int r820t_set_tv_standard(struct r820t_priv *priv,
949 unsigned bw,
950 enum v4l2_tuner_type type,
951 v4l2_std_id std, u32 delsys)
952
953 {
954 int rc, i;
955 u32 if_khz, filt_cal_lo;
956 u8 data[5], val;
957 u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through;
958 u8 lt_att, flt_ext_widest, polyfil_cur;
959 bool need_calibration;
960
961 tuner_dbg("selecting the delivery system\n");
962
963 if (delsys == SYS_ISDBT) {
964 if_khz = 4063;
965 filt_cal_lo = 59000;
966 filt_gain = 0x10; /* +3db, 6mhz on */
967 img_r = 0x00; /* image negative */
968 filt_q = 0x10; /* r10[4]:low q(1'b1) */
969 hp_cor = 0x6a; /* 1.7m disable, +2cap, 1.25mhz */
970 ext_enable = 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */
971 loop_through = 0x00; /* r5[7], lt on */
972 lt_att = 0x00; /* r31[7], lt att enable */
973 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
974 polyfil_cur = 0x60; /* r25[6:5]:min */
975 } else if (delsys == SYS_DVBC_ANNEX_A) {
976 if_khz = 5070;
977 filt_cal_lo = 73500;
978 filt_gain = 0x10; /* +3db, 6mhz on */
979 img_r = 0x00; /* image negative */
980 filt_q = 0x10; /* r10[4]:low q(1'b1) */
981 hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */
982 ext_enable = 0x40; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
983 loop_through = 0x00; /* r5[7], lt on */
984 lt_att = 0x00; /* r31[7], lt att enable */
985 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
986 polyfil_cur = 0x60; /* r25[6:5]:min */
987 } else {
988 if (bw <= 6) {
989 if_khz = 3570;
990 filt_cal_lo = 56000; /* 52000->56000 */
991 filt_gain = 0x10; /* +3db, 6mhz on */
992 img_r = 0x00; /* image negative */
993 filt_q = 0x10; /* r10[4]:low q(1'b1) */
994 hp_cor = 0x6b; /* 1.7m disable, +2cap, 1.0mhz */
995 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
996 loop_through = 0x00; /* r5[7], lt on */
997 lt_att = 0x00; /* r31[7], lt att enable */
998 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
999 polyfil_cur = 0x60; /* r25[6:5]:min */
1000 } else if (bw == 7) {
1001 #if 0
1002 /*
1003 * There are two 7 MHz tables defined on the original
1004 * driver, but just the second one seems to be visible
1005 * by rtl2832. Keep this one here commented, as it
1006 * might be needed in the future
1007 */
1008
1009 if_khz = 4070;
1010 filt_cal_lo = 60000;
1011 filt_gain = 0x10; /* +3db, 6mhz on */
1012 img_r = 0x00; /* image negative */
1013 filt_q = 0x10; /* r10[4]:low q(1'b1) */
1014 hp_cor = 0x2b; /* 1.7m disable, +1cap, 1.0mhz */
1015 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1016 loop_through = 0x00; /* r5[7], lt on */
1017 lt_att = 0x00; /* r31[7], lt att enable */
1018 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
1019 polyfil_cur = 0x60; /* r25[6:5]:min */
1020 #endif
1021 /* 7 MHz, second table */
1022 if_khz = 4570;
1023 filt_cal_lo = 63000;
1024 filt_gain = 0x10; /* +3db, 6mhz on */
1025 img_r = 0x00; /* image negative */
1026 filt_q = 0x10; /* r10[4]:low q(1'b1) */
1027 hp_cor = 0x2a; /* 1.7m disable, +1cap, 1.25mhz */
1028 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1029 loop_through = 0x00; /* r5[7], lt on */
1030 lt_att = 0x00; /* r31[7], lt att enable */
1031 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
1032 polyfil_cur = 0x60; /* r25[6:5]:min */
1033 } else {
1034 if_khz = 4570;
1035 filt_cal_lo = 68500;
1036 filt_gain = 0x10; /* +3db, 6mhz on */
1037 img_r = 0x00; /* image negative */
1038 filt_q = 0x10; /* r10[4]:low q(1'b1) */
1039 hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */
1040 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1041 loop_through = 0x00; /* r5[7], lt on */
1042 lt_att = 0x00; /* r31[7], lt att enable */
1043 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
1044 polyfil_cur = 0x60; /* r25[6:5]:min */
1045 }
1046 }
1047
1048 /* Initialize the shadow registers */
1049 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1050
1051 /* Init Flag & Xtal_check Result */
1052 if (priv->imr_done)
1053 val = 1 | priv->xtal_cap_sel << 1;
1054 else
1055 val = 0;
1056 rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f);
1057 if (rc < 0)
1058 return rc;
1059
1060 /* version */
1061 rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f);
1062 if (rc < 0)
1063 return rc;
1064
1065 /* for LT Gain test */
1066 if (type != V4L2_TUNER_ANALOG_TV) {
1067 rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38);
1068 if (rc < 0)
1069 return rc;
1070 usleep_range(1000, 2000);
1071 }
1072 priv->int_freq = if_khz * 1000;
1073
1074 /* Check if standard changed. If so, filter calibration is needed */
1075 if (type != priv->type)
1076 need_calibration = true;
1077 else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std))
1078 need_calibration = true;
1079 else if ((type == V4L2_TUNER_DIGITAL_TV) &&
1080 ((delsys != priv->delsys) || bw != priv->bw))
1081 need_calibration = true;
1082 else
1083 need_calibration = false;
1084
1085 if (need_calibration) {
1086 tuner_dbg("calibrating the tuner\n");
1087 for (i = 0; i < 2; i++) {
1088 /* Set filt_cap */
1089 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60);
1090 if (rc < 0)
1091 return rc;
1092
1093 /* set cali clk =on */
1094 rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04);
1095 if (rc < 0)
1096 return rc;
1097
1098 /* X'tal cap 0pF for PLL */
1099 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03);
1100 if (rc < 0)
1101 return rc;
1102
1103 rc = r820t_set_pll(priv, type, filt_cal_lo * 1000);
1104 if (rc < 0 || !priv->has_lock)
1105 return rc;
1106
1107 /* Start Trigger */
1108 rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10);
1109 if (rc < 0)
1110 return rc;
1111
1112 usleep_range(1000, 2000);
1113
1114 /* Stop Trigger */
1115 rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10);
1116 if (rc < 0)
1117 return rc;
1118
1119 /* set cali clk =off */
1120 rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04);
1121 if (rc < 0)
1122 return rc;
1123
1124 /* Check if calibration worked */
1125 rc = r820t_read(priv, 0x00, data, sizeof(data));
1126 if (rc < 0)
1127 return rc;
1128
1129 priv->fil_cal_code = data[4] & 0x0f;
1130 if (priv->fil_cal_code && priv->fil_cal_code != 0x0f)
1131 break;
1132 }
1133 /* narrowest */
1134 if (priv->fil_cal_code == 0x0f)
1135 priv->fil_cal_code = 0;
1136 }
1137
1138 rc = r820t_write_reg_mask(priv, 0x0a,
1139 filt_q | priv->fil_cal_code, 0x1f);
1140 if (rc < 0)
1141 return rc;
1142
1143 /* Set BW, Filter_gain, & HP corner */
1144 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0xef);
1145 if (rc < 0)
1146 return rc;
1147
1148
1149 /* Set Img_R */
1150 rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80);
1151 if (rc < 0)
1152 return rc;
1153
1154 /* Set filt_3dB, V6MHz */
1155 rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30);
1156 if (rc < 0)
1157 return rc;
1158
1159 /* channel filter extension */
1160 rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60);
1161 if (rc < 0)
1162 return rc;
1163
1164 /* Loop through */
1165 rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80);
1166 if (rc < 0)
1167 return rc;
1168
1169 /* Loop through attenuation */
1170 rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80);
1171 if (rc < 0)
1172 return rc;
1173
1174 /* filter extension widest */
1175 rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80);
1176 if (rc < 0)
1177 return rc;
1178
1179 /* RF poly filter current */
1180 rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60);
1181 if (rc < 0)
1182 return rc;
1183
1184 /* Store current standard. If it changes, re-calibrate the tuner */
1185 priv->delsys = delsys;
1186 priv->type = type;
1187 priv->std = std;
1188 priv->bw = bw;
1189
1190 return 0;
1191 }
1192
1193 static int r820t_read_gain(struct r820t_priv *priv)
1194 {
1195 u8 data[4];
1196 int rc;
1197
1198 rc = r820t_read(priv, 0x00, data, sizeof(data));
1199 if (rc < 0)
1200 return rc;
1201
1202 return ((data[3] & 0x08) << 1) + ((data[3] & 0xf0) >> 4);
1203 }
1204
1205 #if 0
1206 /* FIXME: This routine requires more testing */
1207 static int r820t_set_gain_mode(struct r820t_priv *priv,
1208 bool set_manual_gain,
1209 int gain)
1210 {
1211 int rc;
1212
1213 if (set_manual_gain) {
1214 int i, total_gain = 0;
1215 uint8_t mix_index = 0, lna_index = 0;
1216 u8 data[4];
1217
1218 /* LNA auto off */
1219 rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10);
1220 if (rc < 0)
1221 return rc;
1222
1223 /* Mixer auto off */
1224 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1225 if (rc < 0)
1226 return rc;
1227
1228 rc = r820t_read(priv, 0x00, data, sizeof(data));
1229 if (rc < 0)
1230 return rc;
1231
1232 /* set fixed VGA gain for now (16.3 dB) */
1233 rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f);
1234 if (rc < 0)
1235 return rc;
1236
1237 for (i = 0; i < 15; i++) {
1238 if (total_gain >= gain)
1239 break;
1240
1241 total_gain += r820t_lna_gain_steps[++lna_index];
1242
1243 if (total_gain >= gain)
1244 break;
1245
1246 total_gain += r820t_mixer_gain_steps[++mix_index];
1247 }
1248
1249 /* set LNA gain */
1250 rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f);
1251 if (rc < 0)
1252 return rc;
1253
1254 /* set Mixer gain */
1255 rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f);
1256 if (rc < 0)
1257 return rc;
1258 } else {
1259 /* LNA */
1260 rc = r820t_write_reg_mask(priv, 0x05, 0, 0x10);
1261 if (rc < 0)
1262 return rc;
1263
1264 /* Mixer */
1265 rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0x10);
1266 if (rc < 0)
1267 return rc;
1268
1269 /* set fixed VGA gain for now (26.5 dB) */
1270 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1271 if (rc < 0)
1272 return rc;
1273 }
1274
1275 return 0;
1276 }
1277 #endif
1278
1279 static int generic_set_freq(struct dvb_frontend *fe,
1280 u32 freq /* in HZ */,
1281 unsigned bw,
1282 enum v4l2_tuner_type type,
1283 v4l2_std_id std, u32 delsys)
1284 {
1285 struct r820t_priv *priv = fe->tuner_priv;
1286 int rc = -EINVAL;
1287 u32 lo_freq;
1288
1289 tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
1290 freq / 1000, bw);
1291
1292 rc = r820t_set_tv_standard(priv, bw, type, std, delsys);
1293 if (rc < 0)
1294 goto err;
1295
1296 if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC))
1297 lo_freq = freq - priv->int_freq;
1298 else
1299 lo_freq = freq + priv->int_freq;
1300
1301 rc = r820t_set_mux(priv, lo_freq);
1302 if (rc < 0)
1303 goto err;
1304
1305 rc = r820t_set_pll(priv, type, lo_freq);
1306 if (rc < 0 || !priv->has_lock)
1307 goto err;
1308
1309 rc = r820t_sysfreq_sel(priv, freq, type, std, delsys);
1310 if (rc < 0)
1311 goto err;
1312
1313 tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
1314 __func__, freq, r820t_read_gain(priv));
1315
1316 err:
1317
1318 if (rc < 0)
1319 tuner_dbg("%s: failed=%d\n", __func__, rc);
1320 return rc;
1321 }
1322
1323 /*
1324 * r820t standby logic
1325 */
1326
1327 static int r820t_standby(struct r820t_priv *priv)
1328 {
1329 int rc;
1330
1331 /* If device was not initialized yet, don't need to standby */
1332 if (!priv->init_done)
1333 return 0;
1334
1335 rc = r820t_write_reg(priv, 0x06, 0xb1);
1336 if (rc < 0)
1337 return rc;
1338 rc = r820t_write_reg(priv, 0x05, 0x03);
1339 if (rc < 0)
1340 return rc;
1341 rc = r820t_write_reg(priv, 0x07, 0x3a);
1342 if (rc < 0)
1343 return rc;
1344 rc = r820t_write_reg(priv, 0x08, 0x40);
1345 if (rc < 0)
1346 return rc;
1347 rc = r820t_write_reg(priv, 0x09, 0xc0);
1348 if (rc < 0)
1349 return rc;
1350 rc = r820t_write_reg(priv, 0x0a, 0x36);
1351 if (rc < 0)
1352 return rc;
1353 rc = r820t_write_reg(priv, 0x0c, 0x35);
1354 if (rc < 0)
1355 return rc;
1356 rc = r820t_write_reg(priv, 0x0f, 0x68);
1357 if (rc < 0)
1358 return rc;
1359 rc = r820t_write_reg(priv, 0x11, 0x03);
1360 if (rc < 0)
1361 return rc;
1362 rc = r820t_write_reg(priv, 0x17, 0xf4);
1363 if (rc < 0)
1364 return rc;
1365 rc = r820t_write_reg(priv, 0x19, 0x0c);
1366
1367 /* Force initial calibration */
1368 priv->type = -1;
1369
1370 return rc;
1371 }
1372
1373 /*
1374 * r820t device init logic
1375 */
1376
1377 static int r820t_xtal_check(struct r820t_priv *priv)
1378 {
1379 int rc, i;
1380 u8 data[3], val;
1381
1382 /* Initialize the shadow registers */
1383 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1384
1385 /* cap 30pF & Drive Low */
1386 rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b);
1387 if (rc < 0)
1388 return rc;
1389
1390 /* set pll autotune = 128kHz */
1391 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
1392 if (rc < 0)
1393 return rc;
1394
1395 /* set manual initial reg = 111111; */
1396 rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f);
1397 if (rc < 0)
1398 return rc;
1399
1400 /* set auto */
1401 rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40);
1402 if (rc < 0)
1403 return rc;
1404
1405 /* Try several xtal capacitor alternatives */
1406 for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) {
1407 rc = r820t_write_reg_mask(priv, 0x10,
1408 r820t_xtal_capacitor[i][0], 0x1b);
1409 if (rc < 0)
1410 return rc;
1411
1412 usleep_range(5000, 6000);
1413
1414 rc = r820t_read(priv, 0x00, data, sizeof(data));
1415 if (rc < 0)
1416 return rc;
1417 if (!(data[2] & 0x40))
1418 continue;
1419
1420 val = data[2] & 0x3f;
1421
1422 if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23))
1423 break;
1424
1425 if (val != 0x3f)
1426 break;
1427 }
1428
1429 if (i == ARRAY_SIZE(r820t_xtal_capacitor))
1430 return -EINVAL;
1431
1432 return r820t_xtal_capacitor[i][1];
1433 }
1434
1435 static int r820t_imr_prepare(struct r820t_priv *priv)
1436 {
1437 int rc;
1438
1439 /* Initialize the shadow registers */
1440 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1441
1442 /* lna off (air-in off) */
1443 rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20);
1444 if (rc < 0)
1445 return rc;
1446
1447 /* mixer gain mode = manual */
1448 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1449 if (rc < 0)
1450 return rc;
1451
1452 /* filter corner = lowest */
1453 rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f);
1454 if (rc < 0)
1455 return rc;
1456
1457 /* filter bw=+2cap, hp=5M */
1458 rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f);
1459 if (rc < 0)
1460 return rc;
1461
1462 /* adc=on, vga code mode, gain = 26.5dB */
1463 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1464 if (rc < 0)
1465 return rc;
1466
1467 /* ring clk = on */
1468 rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08);
1469 if (rc < 0)
1470 return rc;
1471
1472 /* ring power = on */
1473 rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10);
1474 if (rc < 0)
1475 return rc;
1476
1477 /* from ring = ring pll in */
1478 rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02);
1479 if (rc < 0)
1480 return rc;
1481
1482 /* sw_pdect = det3 */
1483 rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80);
1484 if (rc < 0)
1485 return rc;
1486
1487 /* Set filt_3dB */
1488 rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20);
1489
1490 return rc;
1491 }
1492
1493 static int r820t_multi_read(struct r820t_priv *priv)
1494 {
1495 int rc, i;
1496 u16 sum = 0;
1497 u8 data[2], min = 255, max = 0;
1498
1499 usleep_range(5000, 6000);
1500
1501 for (i = 0; i < 6; i++) {
1502 rc = r820t_read(priv, 0x00, data, sizeof(data));
1503 if (rc < 0)
1504 return rc;
1505
1506 sum += data[1];
1507
1508 if (data[1] < min)
1509 min = data[1];
1510
1511 if (data[1] > max)
1512 max = data[1];
1513 }
1514 rc = sum - max - min;
1515
1516 return rc;
1517 }
1518
1519 static int r820t_imr_cross(struct r820t_priv *priv,
1520 struct r820t_sect_type iq_point[3],
1521 u8 *x_direct)
1522 {
1523 struct r820t_sect_type cross[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */
1524 struct r820t_sect_type tmp;
1525 int i, rc;
1526 u8 reg08, reg09;
1527
1528 reg08 = r820t_read_cache_reg(priv, 8) & 0xc0;
1529 reg09 = r820t_read_cache_reg(priv, 9) & 0xc0;
1530
1531 tmp.gain_x = 0;
1532 tmp.phase_y = 0;
1533 tmp.value = 255;
1534
1535 for (i = 0; i < 5; i++) {
1536 switch (i) {
1537 case 0:
1538 cross[i].gain_x = reg08;
1539 cross[i].phase_y = reg09;
1540 break;
1541 case 1:
1542 cross[i].gain_x = reg08; /* 0 */
1543 cross[i].phase_y = reg09 + 1; /* Q-1 */
1544 break;
1545 case 2:
1546 cross[i].gain_x = reg08; /* 0 */
1547 cross[i].phase_y = (reg09 | 0x20) + 1; /* I-1 */
1548 break;
1549 case 3:
1550 cross[i].gain_x = reg08 + 1; /* Q-1 */
1551 cross[i].phase_y = reg09;
1552 break;
1553 default:
1554 cross[i].gain_x = (reg08 | 0x20) + 1; /* I-1 */
1555 cross[i].phase_y = reg09;
1556 }
1557
1558 rc = r820t_write_reg(priv, 0x08, cross[i].gain_x);
1559 if (rc < 0)
1560 return rc;
1561
1562 rc = r820t_write_reg(priv, 0x09, cross[i].phase_y);
1563 if (rc < 0)
1564 return rc;
1565
1566 rc = r820t_multi_read(priv);
1567 if (rc < 0)
1568 return rc;
1569
1570 cross[i].value = rc;
1571
1572 if (cross[i].value < tmp.value)
1573 tmp = cross[i];
1574 }
1575
1576 if ((tmp.phase_y & 0x1f) == 1) { /* y-direction */
1577 *x_direct = 0;
1578
1579 iq_point[0] = cross[0];
1580 iq_point[1] = cross[1];
1581 iq_point[2] = cross[2];
1582 } else { /* (0,0) or x-direction */
1583 *x_direct = 1;
1584
1585 iq_point[0] = cross[0];
1586 iq_point[1] = cross[3];
1587 iq_point[2] = cross[4];
1588 }
1589 return 0;
1590 }
1591
1592 static void r820t_compre_cor(struct r820t_sect_type iq[3])
1593 {
1594 int i;
1595
1596 for (i = 3; i > 0; i--) {
1597 if (iq[0].value > iq[i - 1].value)
1598 swap(iq[0], iq[i - 1]);
1599 }
1600 }
1601
1602 static int r820t_compre_step(struct r820t_priv *priv,
1603 struct r820t_sect_type iq[3], u8 reg)
1604 {
1605 int rc;
1606 struct r820t_sect_type tmp;
1607
1608 /*
1609 * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare
1610 * with min value:
1611 * new < min => update to min and continue
1612 * new > min => Exit
1613 */
1614
1615 /* min value already saved in iq[0] */
1616 tmp.phase_y = iq[0].phase_y;
1617 tmp.gain_x = iq[0].gain_x;
1618
1619 while (((tmp.gain_x & 0x1f) < IMR_TRIAL) &&
1620 ((tmp.phase_y & 0x1f) < IMR_TRIAL)) {
1621 if (reg == 0x08)
1622 tmp.gain_x++;
1623 else
1624 tmp.phase_y++;
1625
1626 rc = r820t_write_reg(priv, 0x08, tmp.gain_x);
1627 if (rc < 0)
1628 return rc;
1629
1630 rc = r820t_write_reg(priv, 0x09, tmp.phase_y);
1631 if (rc < 0)
1632 return rc;
1633
1634 rc = r820t_multi_read(priv);
1635 if (rc < 0)
1636 return rc;
1637 tmp.value = rc;
1638
1639 if (tmp.value <= iq[0].value) {
1640 iq[0].gain_x = tmp.gain_x;
1641 iq[0].phase_y = tmp.phase_y;
1642 iq[0].value = tmp.value;
1643 } else {
1644 return 0;
1645 }
1646
1647 }
1648
1649 return 0;
1650 }
1651
1652 static int r820t_iq_tree(struct r820t_priv *priv,
1653 struct r820t_sect_type iq[3],
1654 u8 fix_val, u8 var_val, u8 fix_reg)
1655 {
1656 int rc, i;
1657 u8 tmp, var_reg;
1658
1659 /*
1660 * record IMC results by input gain/phase location then adjust
1661 * gain or phase positive 1 step and negtive 1 step,
1662 * both record results
1663 */
1664
1665 if (fix_reg == 0x08)
1666 var_reg = 0x09;
1667 else
1668 var_reg = 0x08;
1669
1670 for (i = 0; i < 3; i++) {
1671 rc = r820t_write_reg(priv, fix_reg, fix_val);
1672 if (rc < 0)
1673 return rc;
1674
1675 rc = r820t_write_reg(priv, var_reg, var_val);
1676 if (rc < 0)
1677 return rc;
1678
1679 rc = r820t_multi_read(priv);
1680 if (rc < 0)
1681 return rc;
1682 iq[i].value = rc;
1683
1684 if (fix_reg == 0x08) {
1685 iq[i].gain_x = fix_val;
1686 iq[i].phase_y = var_val;
1687 } else {
1688 iq[i].phase_y = fix_val;
1689 iq[i].gain_x = var_val;
1690 }
1691
1692 if (i == 0) { /* try right-side point */
1693 var_val++;
1694 } else if (i == 1) { /* try left-side point */
1695 /* if absolute location is 1, change I/Q direction */
1696 if ((var_val & 0x1f) < 0x02) {
1697 tmp = 2 - (var_val & 0x1f);
1698
1699 /* b[5]:I/Q selection. 0:Q-path, 1:I-path */
1700 if (var_val & 0x20) {
1701 var_val &= 0xc0;
1702 var_val |= tmp;
1703 } else {
1704 var_val |= 0x20 | tmp;
1705 }
1706 } else {
1707 var_val -= 2;
1708 }
1709 }
1710 }
1711
1712 return 0;
1713 }
1714
1715 static int r820t_section(struct r820t_priv *priv,
1716 struct r820t_sect_type *iq_point)
1717 {
1718 int rc;
1719 struct r820t_sect_type compare_iq[3], compare_bet[3];
1720
1721 /* Try X-1 column and save min result to compare_bet[0] */
1722 if (!(iq_point->gain_x & 0x1f))
1723 compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1; /* Q-path, Gain=1 */
1724 else
1725 compare_iq[0].gain_x = iq_point->gain_x - 1; /* left point */
1726 compare_iq[0].phase_y = iq_point->phase_y;
1727
1728 /* y-direction */
1729 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1730 compare_iq[0].phase_y, 0x08);
1731 if (rc < 0)
1732 return rc;
1733
1734 r820t_compre_cor(compare_iq);
1735
1736 compare_bet[0] = compare_iq[0];
1737
1738 /* Try X column and save min result to compare_bet[1] */
1739 compare_iq[0].gain_x = iq_point->gain_x;
1740 compare_iq[0].phase_y = iq_point->phase_y;
1741
1742 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1743 compare_iq[0].phase_y, 0x08);
1744 if (rc < 0)
1745 return rc;
1746
1747 r820t_compre_cor(compare_iq);
1748
1749 compare_bet[1] = compare_iq[0];
1750
1751 /* Try X+1 column and save min result to compare_bet[2] */
1752 if ((iq_point->gain_x & 0x1f) == 0x00)
1753 compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1; /* I-path, Gain=1 */
1754 else
1755 compare_iq[0].gain_x = iq_point->gain_x + 1;
1756 compare_iq[0].phase_y = iq_point->phase_y;
1757
1758 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1759 compare_iq[0].phase_y, 0x08);
1760 if (rc < 0)
1761 return rc;
1762
1763 r820t_compre_cor(compare_iq);
1764
1765 compare_bet[2] = compare_iq[0];
1766
1767 r820t_compre_cor(compare_bet);
1768
1769 *iq_point = compare_bet[0];
1770
1771 return 0;
1772 }
1773
1774 static int r820t_vga_adjust(struct r820t_priv *priv)
1775 {
1776 int rc;
1777 u8 vga_count;
1778
1779 /* increase vga power to let image significant */
1780 for (vga_count = 12; vga_count < 16; vga_count++) {
1781 rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f);
1782 if (rc < 0)
1783 return rc;
1784
1785 usleep_range(10000, 11000);
1786
1787 rc = r820t_multi_read(priv);
1788 if (rc < 0)
1789 return rc;
1790
1791 if (rc > 40 * 4)
1792 break;
1793 }
1794
1795 return 0;
1796 }
1797
1798 static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1799 {
1800 struct r820t_sect_type compare_iq[3];
1801 int rc;
1802 u8 x_direction = 0; /* 1:x, 0:y */
1803 u8 dir_reg, other_reg;
1804
1805 r820t_vga_adjust(priv);
1806
1807 rc = r820t_imr_cross(priv, compare_iq, &x_direction);
1808 if (rc < 0)
1809 return rc;
1810
1811 if (x_direction == 1) {
1812 dir_reg = 0x08;
1813 other_reg = 0x09;
1814 } else {
1815 dir_reg = 0x09;
1816 other_reg = 0x08;
1817 }
1818
1819 /* compare and find min of 3 points. determine i/q direction */
1820 r820t_compre_cor(compare_iq);
1821
1822 /* increase step to find min value of this direction */
1823 rc = r820t_compre_step(priv, compare_iq, dir_reg);
1824 if (rc < 0)
1825 return rc;
1826
1827 /* the other direction */
1828 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1829 compare_iq[0].phase_y, dir_reg);
1830 if (rc < 0)
1831 return rc;
1832
1833 /* compare and find min of 3 points. determine i/q direction */
1834 r820t_compre_cor(compare_iq);
1835
1836 /* increase step to find min value on this direction */
1837 rc = r820t_compre_step(priv, compare_iq, other_reg);
1838 if (rc < 0)
1839 return rc;
1840
1841 /* check 3 points again */
1842 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1843 compare_iq[0].phase_y, other_reg);
1844 if (rc < 0)
1845 return rc;
1846
1847 r820t_compre_cor(compare_iq);
1848
1849 /* section-9 check */
1850 rc = r820t_section(priv, compare_iq);
1851
1852 *iq_pont = compare_iq[0];
1853
1854 /* reset gain/phase control setting */
1855 rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);
1856 if (rc < 0)
1857 return rc;
1858
1859 rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);
1860
1861 return rc;
1862 }
1863
1864 static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1865 {
1866 int rc;
1867
1868 r820t_vga_adjust(priv);
1869
1870 /*
1871 * search surrounding points from previous point
1872 * try (x-1), (x), (x+1) columns, and find min IMR result point
1873 */
1874 rc = r820t_section(priv, iq_pont);
1875 if (rc < 0)
1876 return rc;
1877
1878 return 0;
1879 }
1880
1881 static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag)
1882 {
1883 struct r820t_sect_type imr_point;
1884 int rc;
1885 u32 ring_vco, ring_freq, ring_ref;
1886 u8 n_ring, n;
1887 int reg18, reg19, reg1f;
1888
1889 if (priv->cfg->xtal > 24000000)
1890 ring_ref = priv->cfg->xtal / 2000;
1891 else
1892 ring_ref = priv->cfg->xtal / 1000;
1893
1894 n_ring = 15;
1895 for (n = 0; n < 16; n++) {
1896 if ((16 + n) * 8 * ring_ref >= 3100000) {
1897 n_ring = n;
1898 break;
1899 }
1900 }
1901
1902 reg18 = r820t_read_cache_reg(priv, 0x18);
1903 reg19 = r820t_read_cache_reg(priv, 0x19);
1904 reg1f = r820t_read_cache_reg(priv, 0x1f);
1905
1906 reg18 &= 0xf0; /* set ring[3:0] */
1907 reg18 |= n_ring;
1908
1909 ring_vco = (16 + n_ring) * 8 * ring_ref;
1910
1911 reg18 &= 0xdf; /* clear ring_se23 */
1912 reg19 &= 0xfc; /* clear ring_seldiv */
1913 reg1f &= 0xfc; /* clear ring_att */
1914
1915 switch (imr_mem) {
1916 case 0:
1917 ring_freq = ring_vco / 48;
1918 reg18 |= 0x20; /* ring_se23 = 1 */
1919 reg19 |= 0x03; /* ring_seldiv = 3 */
1920 reg1f |= 0x02; /* ring_att 10 */
1921 break;
1922 case 1:
1923 ring_freq = ring_vco / 16;
1924 reg18 |= 0x00; /* ring_se23 = 0 */
1925 reg19 |= 0x02; /* ring_seldiv = 2 */
1926 reg1f |= 0x00; /* pw_ring 00 */
1927 break;
1928 case 2:
1929 ring_freq = ring_vco / 8;
1930 reg18 |= 0x00; /* ring_se23 = 0 */
1931 reg19 |= 0x01; /* ring_seldiv = 1 */
1932 reg1f |= 0x03; /* pw_ring 11 */
1933 break;
1934 case 3:
1935 ring_freq = ring_vco / 6;
1936 reg18 |= 0x20; /* ring_se23 = 1 */
1937 reg19 |= 0x00; /* ring_seldiv = 0 */
1938 reg1f |= 0x03; /* pw_ring 11 */
1939 break;
1940 case 4:
1941 ring_freq = ring_vco / 4;
1942 reg18 |= 0x00; /* ring_se23 = 0 */
1943 reg19 |= 0x00; /* ring_seldiv = 0 */
1944 reg1f |= 0x01; /* pw_ring 01 */
1945 break;
1946 default:
1947 ring_freq = ring_vco / 4;
1948 reg18 |= 0x00; /* ring_se23 = 0 */
1949 reg19 |= 0x00; /* ring_seldiv = 0 */
1950 reg1f |= 0x01; /* pw_ring 01 */
1951 break;
1952 }
1953
1954
1955 /* write pw_ring, n_ring, ringdiv2 registers */
1956
1957 /* n_ring, ring_se23 */
1958 rc = r820t_write_reg(priv, 0x18, reg18);
1959 if (rc < 0)
1960 return rc;
1961
1962 /* ring_sediv */
1963 rc = r820t_write_reg(priv, 0x19, reg19);
1964 if (rc < 0)
1965 return rc;
1966
1967 /* pw_ring */
1968 rc = r820t_write_reg(priv, 0x1f, reg1f);
1969 if (rc < 0)
1970 return rc;
1971
1972 /* mux input freq ~ rf_in freq */
1973 rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000);
1974 if (rc < 0)
1975 return rc;
1976
1977 rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV,
1978 (ring_freq - 5300) * 1000);
1979 if (!priv->has_lock)
1980 rc = -EINVAL;
1981 if (rc < 0)
1982 return rc;
1983
1984 if (im_flag) {
1985 rc = r820t_iq(priv, &imr_point);
1986 } else {
1987 imr_point.gain_x = priv->imr_data[3].gain_x;
1988 imr_point.phase_y = priv->imr_data[3].phase_y;
1989 imr_point.value = priv->imr_data[3].value;
1990
1991 rc = r820t_f_imr(priv, &imr_point);
1992 }
1993 if (rc < 0)
1994 return rc;
1995
1996 /* save IMR value */
1997 switch (imr_mem) {
1998 case 0:
1999 priv->imr_data[0].gain_x = imr_point.gain_x;
2000 priv->imr_data[0].phase_y = imr_point.phase_y;
2001 priv->imr_data[0].value = imr_point.value;
2002 break;
2003 case 1:
2004 priv->imr_data[1].gain_x = imr_point.gain_x;
2005 priv->imr_data[1].phase_y = imr_point.phase_y;
2006 priv->imr_data[1].value = imr_point.value;
2007 break;
2008 case 2:
2009 priv->imr_data[2].gain_x = imr_point.gain_x;
2010 priv->imr_data[2].phase_y = imr_point.phase_y;
2011 priv->imr_data[2].value = imr_point.value;
2012 break;
2013 case 3:
2014 priv->imr_data[3].gain_x = imr_point.gain_x;
2015 priv->imr_data[3].phase_y = imr_point.phase_y;
2016 priv->imr_data[3].value = imr_point.value;
2017 break;
2018 case 4:
2019 priv->imr_data[4].gain_x = imr_point.gain_x;
2020 priv->imr_data[4].phase_y = imr_point.phase_y;
2021 priv->imr_data[4].value = imr_point.value;
2022 break;
2023 default:
2024 priv->imr_data[4].gain_x = imr_point.gain_x;
2025 priv->imr_data[4].phase_y = imr_point.phase_y;
2026 priv->imr_data[4].value = imr_point.value;
2027 break;
2028 }
2029
2030 return 0;
2031 }
2032
2033 static int r820t_imr_callibrate(struct r820t_priv *priv)
2034 {
2035 int rc, i;
2036 int xtal_cap = 0;
2037
2038 if (priv->init_done)
2039 return 0;
2040
2041 /* Detect Xtal capacitance */
2042 if ((priv->cfg->rafael_chip == CHIP_R820T) ||
2043 (priv->cfg->rafael_chip == CHIP_R828S) ||
2044 (priv->cfg->rafael_chip == CHIP_R820C)) {
2045 priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
2046 } else {
2047 /* Initialize registers */
2048 rc = r820t_write(priv, 0x05,
2049 r820t_init_array, sizeof(r820t_init_array));
2050 if (rc < 0)
2051 return rc;
2052 for (i = 0; i < 3; i++) {
2053 rc = r820t_xtal_check(priv);
2054 if (rc < 0)
2055 return rc;
2056 if (!i || rc > xtal_cap)
2057 xtal_cap = rc;
2058 }
2059 priv->xtal_cap_sel = xtal_cap;
2060 }
2061
2062 /*
2063 * Disables IMR callibration. That emulates the same behaviour
2064 * as what is done by rtl-sdr userspace library. Useful for testing
2065 */
2066 if (no_imr_cal) {
2067 priv->init_done = true;
2068
2069 return 0;
2070 }
2071
2072 /* Initialize registers */
2073 rc = r820t_write(priv, 0x05,
2074 r820t_init_array, sizeof(r820t_init_array));
2075 if (rc < 0)
2076 return rc;
2077
2078 rc = r820t_imr_prepare(priv);
2079 if (rc < 0)
2080 return rc;
2081
2082 rc = r820t_imr(priv, 3, true);
2083 if (rc < 0)
2084 return rc;
2085 rc = r820t_imr(priv, 1, false);
2086 if (rc < 0)
2087 return rc;
2088 rc = r820t_imr(priv, 0, false);
2089 if (rc < 0)
2090 return rc;
2091 rc = r820t_imr(priv, 2, false);
2092 if (rc < 0)
2093 return rc;
2094 rc = r820t_imr(priv, 4, false);
2095 if (rc < 0)
2096 return rc;
2097
2098 priv->init_done = true;
2099 priv->imr_done = true;
2100
2101 return 0;
2102 }
2103
2104 #if 0
2105 /* Not used, for now */
2106 static int r820t_gpio(struct r820t_priv *priv, bool enable)
2107 {
2108 return r820t_write_reg_mask(priv, 0x0f, enable ? 1 : 0, 0x01);
2109 }
2110 #endif
2111
2112 /*
2113 * r820t frontend operations and tuner attach code
2114 *
2115 * All driver locks and i2c control are only in this part of the code
2116 */
2117
2118 static int r820t_init(struct dvb_frontend *fe)
2119 {
2120 struct r820t_priv *priv = fe->tuner_priv;
2121 int rc;
2122
2123 tuner_dbg("%s:\n", __func__);
2124
2125 mutex_lock(&priv->lock);
2126 if (fe->ops.i2c_gate_ctrl)
2127 fe->ops.i2c_gate_ctrl(fe, 1);
2128
2129 rc = r820t_imr_callibrate(priv);
2130 if (rc < 0)
2131 goto err;
2132
2133 /* Initialize registers */
2134 rc = r820t_write(priv, 0x05,
2135 r820t_init_array, sizeof(r820t_init_array));
2136
2137 err:
2138 if (fe->ops.i2c_gate_ctrl)
2139 fe->ops.i2c_gate_ctrl(fe, 0);
2140 mutex_unlock(&priv->lock);
2141
2142 if (rc < 0)
2143 tuner_dbg("%s: failed=%d\n", __func__, rc);
2144 return rc;
2145 }
2146
2147 static int r820t_sleep(struct dvb_frontend *fe)
2148 {
2149 struct r820t_priv *priv = fe->tuner_priv;
2150 int rc;
2151
2152 tuner_dbg("%s:\n", __func__);
2153
2154 mutex_lock(&priv->lock);
2155 if (fe->ops.i2c_gate_ctrl)
2156 fe->ops.i2c_gate_ctrl(fe, 1);
2157
2158 rc = r820t_standby(priv);
2159
2160 if (fe->ops.i2c_gate_ctrl)
2161 fe->ops.i2c_gate_ctrl(fe, 0);
2162 mutex_unlock(&priv->lock);
2163
2164 tuner_dbg("%s: failed=%d\n", __func__, rc);
2165 return rc;
2166 }
2167
2168 static int r820t_set_analog_freq(struct dvb_frontend *fe,
2169 struct analog_parameters *p)
2170 {
2171 struct r820t_priv *priv = fe->tuner_priv;
2172 unsigned bw;
2173 int rc;
2174
2175 tuner_dbg("%s called\n", __func__);
2176
2177 /* if std is not defined, choose one */
2178 if (!p->std)
2179 p->std = V4L2_STD_MN;
2180
2181 if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC))
2182 bw = 6;
2183 else
2184 bw = 8;
2185
2186 mutex_lock(&priv->lock);
2187 if (fe->ops.i2c_gate_ctrl)
2188 fe->ops.i2c_gate_ctrl(fe, 1);
2189
2190 rc = generic_set_freq(fe, 62500l * p->frequency, bw,
2191 V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED);
2192
2193 if (fe->ops.i2c_gate_ctrl)
2194 fe->ops.i2c_gate_ctrl(fe, 0);
2195 mutex_unlock(&priv->lock);
2196
2197 return rc;
2198 }
2199
2200 static int r820t_set_params(struct dvb_frontend *fe)
2201 {
2202 struct r820t_priv *priv = fe->tuner_priv;
2203 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2204 int rc;
2205 unsigned bw;
2206
2207 tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
2208 __func__, c->delivery_system, c->frequency, c->bandwidth_hz);
2209
2210 mutex_lock(&priv->lock);
2211 if (fe->ops.i2c_gate_ctrl)
2212 fe->ops.i2c_gate_ctrl(fe, 1);
2213
2214 bw = (c->bandwidth_hz + 500000) / 1000000;
2215 if (!bw)
2216 bw = 8;
2217
2218 rc = generic_set_freq(fe, c->frequency, bw,
2219 V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system);
2220
2221 if (fe->ops.i2c_gate_ctrl)
2222 fe->ops.i2c_gate_ctrl(fe, 0);
2223 mutex_unlock(&priv->lock);
2224
2225 if (rc)
2226 tuner_dbg("%s: failed=%d\n", __func__, rc);
2227 return rc;
2228 }
2229
2230 static int r820t_signal(struct dvb_frontend *fe, u16 *strength)
2231 {
2232 struct r820t_priv *priv = fe->tuner_priv;
2233 int rc = 0;
2234
2235 mutex_lock(&priv->lock);
2236 if (fe->ops.i2c_gate_ctrl)
2237 fe->ops.i2c_gate_ctrl(fe, 1);
2238
2239 if (priv->has_lock) {
2240 rc = r820t_read_gain(priv);
2241 if (rc < 0)
2242 goto err;
2243
2244 /* A higher gain at LNA means a lower signal strength */
2245 *strength = (45 - rc) << 4 | 0xff;
2246 if (*strength == 0xff)
2247 *strength = 0;
2248 } else {
2249 *strength = 0;
2250 }
2251
2252 err:
2253 if (fe->ops.i2c_gate_ctrl)
2254 fe->ops.i2c_gate_ctrl(fe, 0);
2255 mutex_unlock(&priv->lock);
2256
2257 tuner_dbg("%s: %s, gain=%d strength=%d\n",
2258 __func__,
2259 priv->has_lock ? "PLL locked" : "no signal",
2260 rc, *strength);
2261
2262 return 0;
2263 }
2264
2265 static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
2266 {
2267 struct r820t_priv *priv = fe->tuner_priv;
2268
2269 tuner_dbg("%s:\n", __func__);
2270
2271 *frequency = priv->int_freq;
2272
2273 return 0;
2274 }
2275
2276 static int r820t_release(struct dvb_frontend *fe)
2277 {
2278 struct r820t_priv *priv = fe->tuner_priv;
2279
2280 tuner_dbg("%s:\n", __func__);
2281
2282 mutex_lock(&r820t_list_mutex);
2283
2284 if (priv)
2285 hybrid_tuner_release_state(priv);
2286
2287 mutex_unlock(&r820t_list_mutex);
2288
2289 fe->tuner_priv = NULL;
2290
2291 return 0;
2292 }
2293
2294 static const struct dvb_tuner_ops r820t_tuner_ops = {
2295 .info = {
2296 .name = "Rafael Micro R820T",
2297 .frequency_min = 42000000,
2298 .frequency_max = 1002000000,
2299 },
2300 .init = r820t_init,
2301 .release = r820t_release,
2302 .sleep = r820t_sleep,
2303 .set_params = r820t_set_params,
2304 .set_analog_params = r820t_set_analog_freq,
2305 .get_if_frequency = r820t_get_if_frequency,
2306 .get_rf_strength = r820t_signal,
2307 };
2308
2309 struct dvb_frontend *r820t_attach(struct dvb_frontend *fe,
2310 struct i2c_adapter *i2c,
2311 const struct r820t_config *cfg)
2312 {
2313 struct r820t_priv *priv;
2314 int rc = -ENODEV;
2315 u8 data[5];
2316 int instance;
2317
2318 mutex_lock(&r820t_list_mutex);
2319
2320 instance = hybrid_tuner_request_state(struct r820t_priv, priv,
2321 hybrid_tuner_instance_list,
2322 i2c, cfg->i2c_addr,
2323 "r820t");
2324 switch (instance) {
2325 case 0:
2326 /* memory allocation failure */
2327 goto err_no_gate;
2328 case 1:
2329 /* new tuner instance */
2330 priv->cfg = cfg;
2331
2332 mutex_init(&priv->lock);
2333
2334 fe->tuner_priv = priv;
2335 break;
2336 case 2:
2337 /* existing tuner instance */
2338 fe->tuner_priv = priv;
2339 break;
2340 }
2341
2342 if (fe->ops.i2c_gate_ctrl)
2343 fe->ops.i2c_gate_ctrl(fe, 1);
2344
2345 /* check if the tuner is there */
2346 rc = r820t_read(priv, 0x00, data, sizeof(data));
2347 if (rc < 0)
2348 goto err;
2349
2350 rc = r820t_sleep(fe);
2351 if (rc < 0)
2352 goto err;
2353
2354 tuner_info("Rafael Micro r820t successfully identified\n");
2355
2356 if (fe->ops.i2c_gate_ctrl)
2357 fe->ops.i2c_gate_ctrl(fe, 0);
2358
2359 mutex_unlock(&r820t_list_mutex);
2360
2361 memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops,
2362 sizeof(struct dvb_tuner_ops));
2363
2364 return fe;
2365 err:
2366 if (fe->ops.i2c_gate_ctrl)
2367 fe->ops.i2c_gate_ctrl(fe, 0);
2368
2369 err_no_gate:
2370 mutex_unlock(&r820t_list_mutex);
2371
2372 tuner_info("%s: failed=%d\n", __func__, rc);
2373 r820t_release(fe);
2374 return NULL;
2375 }
2376 EXPORT_SYMBOL_GPL(r820t_attach);
2377
2378 MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
2379 MODULE_AUTHOR("Mauro Carvalho Chehab");
2380 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.159421 seconds and 4 git commands to generate.