2 * Rafael Micro R820T driver
4 * Copyright (C) 2013 Mauro Carvalho Chehab <mchehab@redhat.com>
6 * This driver was written from scratch, based on an existing driver
7 * that it is part of rtl-sdr git tree, released under GPLv2:
8 * https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug
9 * https://github.com/n1gp/gr-baz
11 * From what I understood from the threads, the original driver was converted
12 * to userspace from a Realtek tree. I couldn't find the original tree.
13 * However, the original driver look awkward on my eyes. So, I decided to
14 * write a new version from it from the scratch, while trying to reproduce
15 * everything found there.
18 * After locking, the original driver seems to have some routines to
19 * improve reception. This was not implemented here yet.
21 * RF Gain set/get is not implemented.
23 * This program is free software; you can redistribute it and/or modify
24 * it under the terms of the GNU General Public License as published by
25 * the Free Software Foundation; either version 2 of the License, or
26 * (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
35 #include <linux/videodev2.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/bitrev.h>
39 #include <asm/div64.h>
41 #include "tuner-i2c.h"
45 * FIXME: I think that there are only 32 registers, but better safe than
46 * sorry. After finishing the driver, we may review it.
48 #define REG_SHADOW_START 5
56 module_param(debug
, int, 0644);
57 MODULE_PARM_DESC(debug
, "enable verbose debug messages");
59 static int no_imr_cal
;
60 module_param(no_imr_cal
, int, 0444);
61 MODULE_PARM_DESC(no_imr_cal
, "Disable IMR calibration at module init");
65 * enums and structures
76 struct r820t_sect_type
{
83 struct list_head hybrid_tuner_instance_list
;
84 const struct r820t_config
*cfg
;
85 struct tuner_i2c_props i2c_props
;
90 enum xtal_cap_value xtal_cap_sel
;
97 struct r820t_sect_type imr_data
[NUM_IMR
];
99 /* Store current mode */
101 enum v4l2_tuner_type type
;
106 struct r820t_freq_range
{
114 u8 imr_mem
; /* Not used, currently */
117 #define VCO_POWER_REF 0x02
118 #define DIP_FREQ 32000000
124 static LIST_HEAD(hybrid_tuner_instance_list
);
125 static DEFINE_MUTEX(r820t_list_mutex
);
127 /* Those initial values start from REG_SHADOW_START */
128 static const u8 r820t_init_array
[NUM_REGS
] = {
129 0x83, 0x32, 0x75, /* 05 to 07 */
130 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */
131 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */
132 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */
133 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */
134 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */
135 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */
138 /* Tuner frequency ranges */
139 static const struct r820t_freq_range freq_ranges
[] = {
142 .open_d
= 0x08, /* low */
143 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
144 .tf_c
= 0xdf, /* R27[7:0] band2,band0 */
145 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
150 .freq
= 50, /* Start freq, in MHz */
151 .open_d
= 0x08, /* low */
152 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
153 .tf_c
= 0xbe, /* R27[7:0] band4,band1 */
154 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
159 .freq
= 55, /* Start freq, in MHz */
160 .open_d
= 0x08, /* low */
161 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
162 .tf_c
= 0x8b, /* R27[7:0] band7,band4 */
163 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
168 .freq
= 60, /* Start freq, in MHz */
169 .open_d
= 0x08, /* low */
170 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
171 .tf_c
= 0x7b, /* R27[7:0] band8,band4 */
172 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
177 .freq
= 65, /* Start freq, in MHz */
178 .open_d
= 0x08, /* low */
179 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
180 .tf_c
= 0x69, /* R27[7:0] band9,band6 */
181 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
186 .freq
= 70, /* Start freq, in MHz */
187 .open_d
= 0x08, /* low */
188 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
189 .tf_c
= 0x58, /* R27[7:0] band10,band7 */
190 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
195 .freq
= 75, /* Start freq, in MHz */
196 .open_d
= 0x00, /* high */
197 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
198 .tf_c
= 0x44, /* R27[7:0] band11,band11 */
199 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
204 .freq
= 80, /* Start freq, in MHz */
205 .open_d
= 0x00, /* high */
206 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
207 .tf_c
= 0x44, /* R27[7:0] band11,band11 */
208 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
213 .freq
= 90, /* Start freq, in MHz */
214 .open_d
= 0x00, /* high */
215 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
216 .tf_c
= 0x34, /* R27[7:0] band12,band11 */
217 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
222 .freq
= 100, /* Start freq, in MHz */
223 .open_d
= 0x00, /* high */
224 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
225 .tf_c
= 0x34, /* R27[7:0] band12,band11 */
226 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
231 .freq
= 110, /* Start freq, in MHz */
232 .open_d
= 0x00, /* high */
233 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
234 .tf_c
= 0x24, /* R27[7:0] band13,band11 */
235 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
240 .freq
= 120, /* Start freq, in MHz */
241 .open_d
= 0x00, /* high */
242 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
243 .tf_c
= 0x24, /* R27[7:0] band13,band11 */
244 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
249 .freq
= 140, /* Start freq, in MHz */
250 .open_d
= 0x00, /* high */
251 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
252 .tf_c
= 0x14, /* R27[7:0] band14,band11 */
253 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
258 .freq
= 180, /* Start freq, in MHz */
259 .open_d
= 0x00, /* high */
260 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
261 .tf_c
= 0x13, /* R27[7:0] band14,band12 */
262 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
267 .freq
= 220, /* Start freq, in MHz */
268 .open_d
= 0x00, /* high */
269 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
270 .tf_c
= 0x13, /* R27[7:0] band14,band12 */
271 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
276 .freq
= 250, /* Start freq, in MHz */
277 .open_d
= 0x00, /* high */
278 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
279 .tf_c
= 0x11, /* R27[7:0] highest,highest */
280 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
285 .freq
= 280, /* Start freq, in MHz */
286 .open_d
= 0x00, /* high */
287 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
288 .tf_c
= 0x00, /* R27[7:0] highest,highest */
289 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
294 .freq
= 310, /* Start freq, in MHz */
295 .open_d
= 0x00, /* high */
296 .rf_mux_ploy
= 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
297 .tf_c
= 0x00, /* R27[7:0] highest,highest */
298 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
303 .freq
= 450, /* Start freq, in MHz */
304 .open_d
= 0x00, /* high */
305 .rf_mux_ploy
= 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
306 .tf_c
= 0x00, /* R27[7:0] highest,highest */
307 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
312 .freq
= 588, /* Start freq, in MHz */
313 .open_d
= 0x00, /* high */
314 .rf_mux_ploy
= 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
315 .tf_c
= 0x00, /* R27[7:0] highest,highest */
316 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
321 .freq
= 650, /* Start freq, in MHz */
322 .open_d
= 0x00, /* high */
323 .rf_mux_ploy
= 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
324 .tf_c
= 0x00, /* R27[7:0] highest,highest */
325 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
332 static int r820t_xtal_capacitor
[][2] = {
333 { 0x0b, XTAL_LOW_CAP_30P
},
334 { 0x02, XTAL_LOW_CAP_20P
},
335 { 0x01, XTAL_LOW_CAP_10P
},
336 { 0x00, XTAL_LOW_CAP_0P
},
337 { 0x10, XTAL_HIGH_CAP_0P
},
341 * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
342 * input power, for raw results see:
343 * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
346 static const int r820t_lna_gain_steps
[] = {
347 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
350 static const int r820t_mixer_gain_steps
[] = {
351 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
355 * I2C read/write code and shadow registers logic
357 static void shadow_store(struct r820t_priv
*priv
, u8 reg
, const u8
*val
,
360 int r
= reg
- REG_SHADOW_START
;
371 tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n",
372 __func__
, r
+ REG_SHADOW_START
, len
, len
, val
);
374 memcpy(&priv
->regs
[r
], val
, len
);
377 static int r820t_write(struct r820t_priv
*priv
, u8 reg
, const u8
*val
,
380 int rc
, size
, pos
= 0;
382 /* Store the shadow registers */
383 shadow_store(priv
, reg
, val
, len
);
386 if (len
> priv
->cfg
->max_i2c_msg_len
- 1)
387 size
= priv
->cfg
->max_i2c_msg_len
- 1;
391 /* Fill I2C buffer */
393 memcpy(&priv
->buf
[1], &val
[pos
], size
);
395 rc
= tuner_i2c_xfer_send(&priv
->i2c_props
, priv
->buf
, size
+ 1);
396 if (rc
!= size
+ 1) {
397 tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
398 __func__
, rc
, reg
, size
, size
, &priv
->buf
[1]);
403 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
404 __func__
, reg
, size
, size
, &priv
->buf
[1]);
414 static int r820t_write_reg(struct r820t_priv
*priv
, u8 reg
, u8 val
)
416 return r820t_write(priv
, reg
, &val
, 1);
419 static int r820t_read_cache_reg(struct r820t_priv
*priv
, int reg
)
421 reg
-= REG_SHADOW_START
;
423 if (reg
>= 0 && reg
< NUM_REGS
)
424 return priv
->regs
[reg
];
429 static int r820t_write_reg_mask(struct r820t_priv
*priv
, u8 reg
, u8 val
,
432 int rc
= r820t_read_cache_reg(priv
, reg
);
437 val
= (rc
& ~bit_mask
) | (val
& bit_mask
);
439 return r820t_write(priv
, reg
, &val
, 1);
442 static int r820t_read(struct r820t_priv
*priv
, u8 reg
, u8
*val
, int len
)
445 u8
*p
= &priv
->buf
[1];
449 rc
= tuner_i2c_xfer_send_recv(&priv
->i2c_props
, priv
->buf
, 1, p
, len
);
451 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
452 __func__
, rc
, reg
, len
, len
, p
);
458 /* Copy data to the output buffer */
459 for (i
= 0; i
< len
; i
++)
460 val
[i
] = bitrev8(p
[i
]);
462 tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
463 __func__
, reg
, len
, len
, val
);
472 static int r820t_set_mux(struct r820t_priv
*priv
, u32 freq
)
474 const struct r820t_freq_range
*range
;
476 u8 val
, reg08
, reg09
;
478 /* Get the proper frequency range */
479 freq
= freq
/ 1000000;
480 for (i
= 0; i
< ARRAY_SIZE(freq_ranges
) - 1; i
++) {
481 if (freq
< freq_ranges
[i
+ 1].freq
)
484 range
= &freq_ranges
[i
];
486 tuner_dbg("set r820t range#%d for frequency %d MHz\n", i
, freq
);
489 rc
= r820t_write_reg_mask(priv
, 0x17, range
->open_d
, 0x08);
494 rc
= r820t_write_reg_mask(priv
, 0x1a, range
->rf_mux_ploy
, 0xc3);
499 rc
= r820t_write_reg(priv
, 0x1b, range
->tf_c
);
503 /* XTAL CAP & Drive */
504 switch (priv
->xtal_cap_sel
) {
505 case XTAL_LOW_CAP_30P
:
506 case XTAL_LOW_CAP_20P
:
507 val
= range
->xtal_cap20p
| 0x08;
509 case XTAL_LOW_CAP_10P
:
510 val
= range
->xtal_cap10p
| 0x08;
512 case XTAL_HIGH_CAP_0P
:
513 val
= range
->xtal_cap0p
| 0x00;
516 case XTAL_LOW_CAP_0P
:
517 val
= range
->xtal_cap0p
| 0x08;
520 rc
= r820t_write_reg_mask(priv
, 0x10, val
, 0x0b);
524 if (priv
->imr_done
) {
525 reg08
= priv
->imr_data
[range
->imr_mem
].gain_x
;
526 reg09
= priv
->imr_data
[range
->imr_mem
].phase_y
;
531 rc
= r820t_write_reg_mask(priv
, 0x08, reg08
, 0x3f);
535 rc
= r820t_write_reg_mask(priv
, 0x09, reg09
, 0x3f);
540 static int r820t_set_pll(struct r820t_priv
*priv
, enum v4l2_tuner_type type
,
545 unsigned sleep_time
= 10000;
546 u32 vco_fra
; /* VCO contribution by SDM (kHz) */
547 u32 vco_min
= 1770000;
548 u32 vco_max
= vco_min
* 2;
556 u8 ni
, si
, nint
, vco_fine_tune
, val
;
559 /* Frequency in kHz */
561 pll_ref
= priv
->cfg
->xtal
/ 1000;
563 if ((priv
->cfg
->rafael_chip
== CHIP_R620D
) ||
564 (priv
->cfg
->rafael_chip
== CHIP_R828D
) ||
565 (priv
->cfg
->rafael_chip
== CHIP_R828
)) {
566 /* ref set refdiv2, reffreq = Xtal/2 on ATV application */
567 if (type
!= V4L2_TUNER_DIGITAL_TV
) {
573 if (priv
->cfg
->xtal
> 24000000) {
579 tuner_dbg("set r820t pll for frequency %d kHz = %d%s\n",
580 freq
, pll_ref
, refdiv2
? " / 2" : "");
582 rc
= r820t_write_reg_mask(priv
, 0x10, refdiv2
, 0x10);
586 /* set pll autotune = 128kHz */
587 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x00, 0x0c);
591 /* set VCO current = 100 */
592 rc
= r820t_write_reg_mask(priv
, 0x12, 0x80, 0xe0);
596 /* Calculate divider */
597 while (mix_div
<= 64) {
598 if (((freq
* mix_div
) >= vco_min
) &&
599 ((freq
* mix_div
) < vco_max
)) {
601 while (div_buf
> 2) {
602 div_buf
= div_buf
>> 1;
607 mix_div
= mix_div
<< 1;
610 rc
= r820t_read(priv
, 0x00, data
, sizeof(data
));
614 vco_fine_tune
= (data
[4] & 0x30) >> 4;
616 if (vco_fine_tune
> VCO_POWER_REF
)
617 div_num
= div_num
- 1;
618 else if (vco_fine_tune
< VCO_POWER_REF
)
619 div_num
= div_num
+ 1;
621 rc
= r820t_write_reg_mask(priv
, 0x10, div_num
<< 5, 0xe0);
625 vco_freq
= (u64
)(freq
* (u64
)mix_div
);
628 do_div(tmp64
, 2 * pll_ref
);
631 tmp64
= vco_freq
- ((u64
)2) * pll_ref
* nint
;
633 vco_fra
= (u16
)(tmp64
);
635 /* boundary spur prevention */
636 if (vco_fra
< pll_ref
/ 64) {
638 } else if (vco_fra
> pll_ref
* 127 / 64) {
641 } else if ((vco_fra
> pll_ref
* 127 / 128) && (vco_fra
< pll_ref
)) {
642 vco_fra
= pll_ref
* 127 / 128;
643 } else if ((vco_fra
> pll_ref
) && (vco_fra
< pll_ref
* 129 / 128)) {
644 vco_fra
= pll_ref
* 129 / 128;
648 tuner_info("No valid PLL values for %u kHz!\n", freq
);
652 ni
= (nint
- 13) / 4;
653 si
= nint
- 4 * ni
- 13;
655 rc
= r820t_write_reg(priv
, 0x14, ni
+ (si
<< 6));
665 rc
= r820t_write_reg_mask(priv
, 0x12, val
, 0x08);
670 while (vco_fra
> 1) {
671 if (vco_fra
> (2 * pll_ref
/ n_sdm
)) {
672 sdm
= sdm
+ 32768 / (n_sdm
/ 2);
673 vco_fra
= vco_fra
- 2 * pll_ref
/ n_sdm
;
680 rc
= r820t_write_reg_mask(priv
, 0x16, sdm
>> 8, 0x08);
683 rc
= r820t_write_reg_mask(priv
, 0x15, sdm
& 0xff, 0x08);
687 for (i
= 0; i
< 2; i
++) {
688 usleep_range(sleep_time
, sleep_time
+ 1000);
690 /* Check if PLL has locked */
691 rc
= r820t_read(priv
, 0x00, data
, 3);
698 /* Didn't lock. Increase VCO current */
699 rc
= r820t_write_reg_mask(priv
, 0x12, 0x60, 0xe0);
705 if (!(data
[2] & 0x40)) {
706 priv
->has_lock
= false;
710 priv
->has_lock
= true;
711 tuner_dbg("tuner has lock at frequency %d kHz\n", freq
);
713 /* set pll autotune = 8kHz */
714 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x08, 0x08);
719 static int r820t_sysfreq_sel(struct r820t_priv
*priv
, u32 freq
,
720 enum v4l2_tuner_type type
,
725 u8 mixer_top
, lna_top
, cp_cur
, div_buf_cur
, lna_vth_l
, mixer_vth_l
;
726 u8 air_cable1_in
, cable2_in
, pre_dect
, lna_discharge
, filter_cur
;
728 tuner_dbg("adjusting tuner parameters for the standard\n");
732 if ((freq
== 506000000) || (freq
== 666000000) ||
733 (freq
== 818000000)) {
734 mixer_top
= 0x14; /* mixer top:14 , top-1, low-discharge */
735 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
736 cp_cur
= 0x28; /* 101, 0.2 */
737 div_buf_cur
= 0x20; /* 10, 200u */
739 mixer_top
= 0x24; /* mixer top:13 , top-1, low-discharge */
740 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
741 cp_cur
= 0x38; /* 111, auto */
742 div_buf_cur
= 0x30; /* 11, 150u */
744 lna_vth_l
= 0x53; /* lna vth 0.84 , vtl 0.64 */
745 mixer_vth_l
= 0x75; /* mixer vth 1.04, vtl 0.84 */
746 air_cable1_in
= 0x00;
750 filter_cur
= 0x40; /* 10, low */
753 mixer_top
= 0x24; /* mixer top:13 , top-1, low-discharge */
754 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
755 lna_vth_l
= 0x53; /* lna vth 0.84 , vtl 0.64 */
756 mixer_vth_l
= 0x75; /* mixer vth 1.04, vtl 0.84 */
757 air_cable1_in
= 0x00;
761 cp_cur
= 0x38; /* 111, auto */
762 div_buf_cur
= 0x30; /* 11, 150u */
763 filter_cur
= 0x40; /* 10, low */
766 mixer_top
= 0x24; /* mixer top:13 , top-1, low-discharge */
767 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
768 lna_vth_l
= 0x75; /* lna vth 1.04 , vtl 0.84 */
769 mixer_vth_l
= 0x75; /* mixer vth 1.04, vtl 0.84 */
770 air_cable1_in
= 0x00;
774 cp_cur
= 0x38; /* 111, auto */
775 div_buf_cur
= 0x30; /* 11, 150u */
776 filter_cur
= 0x40; /* 10, low */
778 default: /* DVB-T 8M */
779 mixer_top
= 0x24; /* mixer top:13 , top-1, low-discharge */
780 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
781 lna_vth_l
= 0x53; /* lna vth 0.84 , vtl 0.64 */
782 mixer_vth_l
= 0x75; /* mixer vth 1.04, vtl 0.84 */
783 air_cable1_in
= 0x00;
787 cp_cur
= 0x38; /* 111, auto */
788 div_buf_cur
= 0x30; /* 11, 150u */
789 filter_cur
= 0x40; /* 10, low */
793 if (priv
->cfg
->use_diplexer
&&
794 ((priv
->cfg
->rafael_chip
== CHIP_R820T
) ||
795 (priv
->cfg
->rafael_chip
== CHIP_R828S
) ||
796 (priv
->cfg
->rafael_chip
== CHIP_R820C
))) {
798 air_cable1_in
= 0x00;
800 air_cable1_in
= 0x60;
804 rc
= r820t_write_reg_mask(priv
, 0x1d, lna_top
, 0xc7);
807 rc
= r820t_write_reg_mask(priv
, 0x1c, mixer_top
, 0xf8);
810 rc
= r820t_write_reg(priv
, 0x0d, lna_vth_l
);
813 rc
= r820t_write_reg(priv
, 0x0e, mixer_vth_l
);
817 /* Air-IN only for Astrometa */
818 rc
= r820t_write_reg_mask(priv
, 0x05, air_cable1_in
, 0x60);
821 rc
= r820t_write_reg_mask(priv
, 0x06, cable2_in
, 0x08);
825 rc
= r820t_write_reg_mask(priv
, 0x11, cp_cur
, 0x38);
828 rc
= r820t_write_reg_mask(priv
, 0x17, div_buf_cur
, 0x30);
831 rc
= r820t_write_reg_mask(priv
, 0x0a, filter_cur
, 0x60);
835 * Original driver initializes regs 0x05 and 0x06 with the
836 * same value again on this point. Probably, it is just an
844 tuner_dbg("adjusting LNA parameters\n");
845 if (type
!= V4L2_TUNER_ANALOG_TV
) {
846 /* LNA TOP: lowest */
847 rc
= r820t_write_reg_mask(priv
, 0x1d, 0, 0x38);
852 rc
= r820t_write_reg_mask(priv
, 0x1c, 0, 0x04);
856 /* 0: PRE_DECT off */
857 rc
= r820t_write_reg_mask(priv
, 0x06, 0, 0x40);
862 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x30, 0x30);
868 /* write LNA TOP = 3 */
869 rc
= r820t_write_reg_mask(priv
, 0x1d, 0x18, 0x38);
874 * write discharge mode
875 * FIXME: IMHO, the mask here is wrong, but it matches
876 * what's there at the original driver
878 rc
= r820t_write_reg_mask(priv
, 0x1c, mixer_top
, 0x04);
882 /* LNA discharge current */
883 rc
= r820t_write_reg_mask(priv
, 0x1e, lna_discharge
, 0x1f);
888 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x20, 0x30);
893 rc
= r820t_write_reg_mask(priv
, 0x06, 0, 0x40);
898 rc
= r820t_write_reg_mask(priv
, 0x1d, lna_top
, 0x38);
903 * write discharge mode
904 * FIXME: IMHO, the mask here is wrong, but it matches
905 * what's there at the original driver
907 rc
= r820t_write_reg_mask(priv
, 0x1c, mixer_top
, 0x04);
911 /* LNA discharge current */
912 rc
= r820t_write_reg_mask(priv
, 0x1e, lna_discharge
, 0x1f);
916 /* agc clk 1Khz, external det1 cap 1u */
917 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x00, 0x30);
921 rc
= r820t_write_reg_mask(priv
, 0x10, 0x00, 0x04);
928 static int r820t_set_tv_standard(struct r820t_priv
*priv
,
930 enum v4l2_tuner_type type
,
931 v4l2_std_id std
, u32 delsys
)
935 u32 if_khz
, filt_cal_lo
;
937 u8 filt_gain
, img_r
, filt_q
, hp_cor
, ext_enable
, loop_through
;
938 u8 lt_att
, flt_ext_widest
, polyfil_cur
;
939 bool need_calibration
;
941 tuner_dbg("selecting the delivery system\n");
943 if (delsys
== SYS_ISDBT
) {
946 filt_gain
= 0x10; /* +3db, 6mhz on */
947 img_r
= 0x00; /* image negative */
948 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
949 hp_cor
= 0x6a; /* 1.7m disable, +2cap, 1.25mhz */
950 ext_enable
= 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */
951 loop_through
= 0x00; /* r5[7], lt on */
952 lt_att
= 0x00; /* r31[7], lt att enable */
953 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
954 polyfil_cur
= 0x60; /* r25[6:5]:min */
958 filt_cal_lo
= 56000; /* 52000->56000 */
959 filt_gain
= 0x10; /* +3db, 6mhz on */
960 img_r
= 0x00; /* image negative */
961 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
962 hp_cor
= 0x6b; /* 1.7m disable, +2cap, 1.0mhz */
963 ext_enable
= 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
964 loop_through
= 0x00; /* r5[7], lt on */
965 lt_att
= 0x00; /* r31[7], lt att enable */
966 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
967 polyfil_cur
= 0x60; /* r25[6:5]:min */
968 } else if (bw
== 7) {
971 * There are two 7 MHz tables defined on the original
972 * driver, but just the second one seems to be visible
973 * by rtl2832. Keep this one here commented, as it
974 * might be needed in the future
979 filt_gain
= 0x10; /* +3db, 6mhz on */
980 img_r
= 0x00; /* image negative */
981 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
982 hp_cor
= 0x2b; /* 1.7m disable, +1cap, 1.0mhz */
983 ext_enable
= 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
984 loop_through
= 0x00; /* r5[7], lt on */
985 lt_att
= 0x00; /* r31[7], lt att enable */
986 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
987 polyfil_cur
= 0x60; /* r25[6:5]:min */
989 /* 7 MHz, second table */
992 filt_gain
= 0x10; /* +3db, 6mhz on */
993 img_r
= 0x00; /* image negative */
994 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
995 hp_cor
= 0x2a; /* 1.7m disable, +1cap, 1.25mhz */
996 ext_enable
= 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
997 loop_through
= 0x00; /* r5[7], lt on */
998 lt_att
= 0x00; /* r31[7], lt att enable */
999 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
1000 polyfil_cur
= 0x60; /* r25[6:5]:min */
1003 filt_cal_lo
= 68500;
1004 filt_gain
= 0x10; /* +3db, 6mhz on */
1005 img_r
= 0x00; /* image negative */
1006 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
1007 hp_cor
= 0x0b; /* 1.7m disable, +0cap, 1.0mhz */
1008 ext_enable
= 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1009 loop_through
= 0x00; /* r5[7], lt on */
1010 lt_att
= 0x00; /* r31[7], lt att enable */
1011 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
1012 polyfil_cur
= 0x60; /* r25[6:5]:min */
1016 /* Initialize the shadow registers */
1017 memcpy(priv
->regs
, r820t_init_array
, sizeof(r820t_init_array
));
1019 /* Init Flag & Xtal_check Result */
1021 val
= 1 | priv
->xtal_cap_sel
<< 1;
1024 rc
= r820t_write_reg_mask(priv
, 0x0c, val
, 0x0f);
1029 rc
= r820t_write_reg_mask(priv
, 0x13, VER_NUM
, 0x3f);
1033 /* for LT Gain test */
1034 if (type
!= V4L2_TUNER_ANALOG_TV
) {
1035 rc
= r820t_write_reg_mask(priv
, 0x1d, 0x00, 0x38);
1038 usleep_range(1000, 2000);
1040 priv
->int_freq
= if_khz
* 1000;
1042 /* Check if standard changed. If so, filter calibration is needed */
1043 if (type
!= priv
->type
)
1044 need_calibration
= true;
1045 else if ((type
== V4L2_TUNER_ANALOG_TV
) && (std
!= priv
->std
))
1046 need_calibration
= true;
1047 else if ((type
== V4L2_TUNER_DIGITAL_TV
) &&
1048 ((delsys
!= priv
->delsys
) || bw
!= priv
->bw
))
1049 need_calibration
= true;
1051 need_calibration
= false;
1053 if (need_calibration
) {
1054 tuner_dbg("calibrating the tuner\n");
1055 for (i
= 0; i
< 2; i
++) {
1057 rc
= r820t_write_reg_mask(priv
, 0x0b, hp_cor
, 0x60);
1061 /* set cali clk =on */
1062 rc
= r820t_write_reg_mask(priv
, 0x0f, 0x04, 0x04);
1066 /* X'tal cap 0pF for PLL */
1067 rc
= r820t_write_reg_mask(priv
, 0x10, 0x00, 0x03);
1071 rc
= r820t_set_pll(priv
, type
, filt_cal_lo
);
1072 if (rc
< 0 || !priv
->has_lock
)
1076 rc
= r820t_write_reg_mask(priv
, 0x0b, 0x10, 0x10);
1080 usleep_range(1000, 2000);
1083 rc
= r820t_write_reg_mask(priv
, 0x0b, 0x00, 0x10);
1087 /* set cali clk =off */
1088 rc
= r820t_write_reg_mask(priv
, 0x0f, 0x00, 0x04);
1092 /* Check if calibration worked */
1093 rc
= r820t_read(priv
, 0x00, data
, sizeof(data
));
1097 priv
->fil_cal_code
= data
[4] & 0x0f;
1098 if (priv
->fil_cal_code
&& priv
->fil_cal_code
!= 0x0f)
1102 if (priv
->fil_cal_code
== 0x0f)
1103 priv
->fil_cal_code
= 0;
1106 rc
= r820t_write_reg_mask(priv
, 0x0a,
1107 filt_q
| priv
->fil_cal_code
, 0x1f);
1111 /* Set BW, Filter_gain, & HP corner */
1112 rc
= r820t_write_reg_mask(priv
, 0x0b, hp_cor
, 0x10);
1118 rc
= r820t_write_reg_mask(priv
, 0x07, img_r
, 0x80);
1122 /* Set filt_3dB, V6MHz */
1123 rc
= r820t_write_reg_mask(priv
, 0x06, filt_gain
, 0x30);
1127 /* channel filter extension */
1128 rc
= r820t_write_reg_mask(priv
, 0x1e, ext_enable
, 0x60);
1133 rc
= r820t_write_reg_mask(priv
, 0x05, loop_through
, 0x80);
1137 /* Loop through attenuation */
1138 rc
= r820t_write_reg_mask(priv
, 0x1f, lt_att
, 0x80);
1142 /* filter extension widest */
1143 rc
= r820t_write_reg_mask(priv
, 0x0f, flt_ext_widest
, 0x80);
1147 /* RF poly filter current */
1148 rc
= r820t_write_reg_mask(priv
, 0x19, polyfil_cur
, 0x60);
1152 /* Store current standard. If it changes, re-calibrate the tuner */
1153 priv
->delsys
= delsys
;
1161 static int r820t_read_gain(struct r820t_priv
*priv
)
1166 rc
= r820t_read(priv
, 0x00, data
, sizeof(data
));
1170 return ((data
[3] & 0x0f) << 1) + ((data
[3] & 0xf0) >> 4);
1173 static int r820t_set_gain_mode(struct r820t_priv
*priv
,
1174 bool set_manual_gain
,
1179 if (set_manual_gain
) {
1180 int i
, total_gain
= 0;
1181 uint8_t mix_index
= 0, lna_index
= 0;
1185 rc
= r820t_write_reg_mask(priv
, 0x05, 0x10, 0x10);
1189 /* Mixer auto off */
1190 rc
= r820t_write_reg_mask(priv
, 0x07, 0, 0x10);
1194 rc
= r820t_read(priv
, 0x00, data
, sizeof(data
));
1198 /* set fixed VGA gain for now (16.3 dB) */
1199 rc
= r820t_write_reg_mask(priv
, 0x0c, 0x08, 0x9f);
1203 for (i
= 0; i
< 15; i
++) {
1204 if (total_gain
>= gain
)
1207 total_gain
+= r820t_lna_gain_steps
[++lna_index
];
1209 if (total_gain
>= gain
)
1212 total_gain
+= r820t_mixer_gain_steps
[++mix_index
];
1216 rc
= r820t_write_reg_mask(priv
, 0x05, lna_index
, 0x0f);
1220 /* set Mixer gain */
1221 rc
= r820t_write_reg_mask(priv
, 0x07, mix_index
, 0x0f);
1226 rc
= r820t_write_reg_mask(priv
, 0x05, 0, 0xef);
1231 rc
= r820t_write_reg_mask(priv
, 0x07, 0x10, 0xef);
1235 /* set fixed VGA gain for now (26.5 dB) */
1236 rc
= r820t_write_reg_mask(priv
, 0x0c, 0x0b, 0x9f);
1245 static int generic_set_freq(struct dvb_frontend
*fe
,
1246 u32 freq
/* in HZ */,
1248 enum v4l2_tuner_type type
,
1249 v4l2_std_id std
, u32 delsys
)
1251 struct r820t_priv
*priv
= fe
->tuner_priv
;
1255 tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
1258 rc
= r820t_set_tv_standard(priv
, bw
, type
, std
, delsys
);
1262 if ((type
== V4L2_TUNER_ANALOG_TV
) && (std
== V4L2_STD_SECAM_LC
))
1263 lo_freq
= freq
- priv
->int_freq
;
1265 lo_freq
= freq
+ priv
->int_freq
;
1267 rc
= r820t_set_mux(priv
, lo_freq
);
1271 rc
= r820t_set_gain_mode(priv
, true, 0);
1275 rc
= r820t_set_pll(priv
, type
, lo_freq
);
1276 if (rc
< 0 || !priv
->has_lock
)
1279 rc
= r820t_sysfreq_sel(priv
, freq
, type
, std
, delsys
);
1283 tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
1284 __func__
, freq
, r820t_read_gain(priv
));
1289 tuner_dbg("%s: failed=%d\n", __func__
, rc
);
1294 * r820t standby logic
1297 static int r820t_standby(struct r820t_priv
*priv
)
1301 /* If device was not initialized yet, don't need to standby */
1302 if (!priv
->init_done
)
1305 rc
= r820t_write_reg(priv
, 0x06, 0xb1);
1308 rc
= r820t_write_reg(priv
, 0x05, 0x03);
1311 rc
= r820t_write_reg(priv
, 0x07, 0x3a);
1314 rc
= r820t_write_reg(priv
, 0x08, 0x40);
1317 rc
= r820t_write_reg(priv
, 0x09, 0xc0);
1320 rc
= r820t_write_reg(priv
, 0x0a, 0x36);
1323 rc
= r820t_write_reg(priv
, 0x0c, 0x35);
1326 rc
= r820t_write_reg(priv
, 0x0f, 0x68);
1329 rc
= r820t_write_reg(priv
, 0x11, 0x03);
1332 rc
= r820t_write_reg(priv
, 0x17, 0xf4);
1335 rc
= r820t_write_reg(priv
, 0x19, 0x0c);
1337 /* Force initial calibration */
1344 * r820t device init logic
1347 static int r820t_xtal_check(struct r820t_priv
*priv
)
1352 /* Initialize the shadow registers */
1353 memcpy(priv
->regs
, r820t_init_array
, sizeof(r820t_init_array
));
1355 /* cap 30pF & Drive Low */
1356 rc
= r820t_write_reg_mask(priv
, 0x10, 0x0b, 0x0b);
1360 /* set pll autotune = 128kHz */
1361 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x00, 0x0c);
1365 /* set manual initial reg = 111111; */
1366 rc
= r820t_write_reg_mask(priv
, 0x13, 0x7f, 0x7f);
1371 rc
= r820t_write_reg_mask(priv
, 0x13, 0x00, 0x40);
1375 /* Try several xtal capacitor alternatives */
1376 for (i
= 0; i
< ARRAY_SIZE(r820t_xtal_capacitor
); i
++) {
1377 rc
= r820t_write_reg_mask(priv
, 0x10,
1378 r820t_xtal_capacitor
[i
][0], 0x1b);
1382 usleep_range(5000, 6000);
1384 rc
= r820t_read(priv
, 0x00, data
, sizeof(data
));
1387 if ((!data
[2]) & 0x40)
1390 val
= data
[2] & 0x3f;
1392 if (priv
->cfg
->xtal
== 16000000 && (val
> 29 || val
< 23))
1399 if (i
== ARRAY_SIZE(r820t_xtal_capacitor
))
1402 return r820t_xtal_capacitor
[i
][1];
1405 static int r820t_imr_prepare(struct r820t_priv
*priv
)
1409 /* Initialize the shadow registers */
1410 memcpy(priv
->regs
, r820t_init_array
, sizeof(r820t_init_array
));
1412 /* lna off (air-in off) */
1413 rc
= r820t_write_reg_mask(priv
, 0x05, 0x20, 0x20);
1417 /* mixer gain mode = manual */
1418 rc
= r820t_write_reg_mask(priv
, 0x07, 0, 0x10);
1422 /* filter corner = lowest */
1423 rc
= r820t_write_reg_mask(priv
, 0x0a, 0x0f, 0x0f);
1427 /* filter bw=+2cap, hp=5M */
1428 rc
= r820t_write_reg_mask(priv
, 0x0b, 0x60, 0x6f);
1432 /* adc=on, vga code mode, gain = 26.5dB */
1433 rc
= r820t_write_reg_mask(priv
, 0x0c, 0x0b, 0x9f);
1438 rc
= r820t_write_reg_mask(priv
, 0x0f, 0, 0x08);
1442 /* ring power = on */
1443 rc
= r820t_write_reg_mask(priv
, 0x18, 0x10, 0x10);
1447 /* from ring = ring pll in */
1448 rc
= r820t_write_reg_mask(priv
, 0x1c, 0x02, 0x02);
1452 /* sw_pdect = det3 */
1453 rc
= r820t_write_reg_mask(priv
, 0x1e, 0x80, 0x80);
1458 rc
= r820t_write_reg_mask(priv
, 0x06, 0x20, 0x20);
1463 static int r820t_multi_read(struct r820t_priv
*priv
)
1466 u8 data
[2], min
= 0, max
= 255, sum
= 0;
1468 usleep_range(5000, 6000);
1470 for (i
= 0; i
< 6; i
++) {
1471 rc
= r820t_read(priv
, 0x00, data
, sizeof(data
));
1483 rc
= sum
- max
- min
;
1488 static int r820t_imr_cross(struct r820t_priv
*priv
,
1489 struct r820t_sect_type iq_point
[3],
1492 struct r820t_sect_type cross
[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */
1493 struct r820t_sect_type tmp
;
1497 reg08
= r820t_read_cache_reg(priv
, 8) & 0xc0;
1498 reg09
= r820t_read_cache_reg(priv
, 9) & 0xc0;
1504 for (i
= 0; i
< 5; i
++) {
1507 cross
[i
].gain_x
= reg08
;
1508 cross
[i
].phase_y
= reg09
;
1511 cross
[i
].gain_x
= reg08
; /* 0 */
1512 cross
[i
].phase_y
= reg09
+ 1; /* Q-1 */
1515 cross
[i
].gain_x
= reg08
; /* 0 */
1516 cross
[i
].phase_y
= (reg09
| 0x20) + 1; /* I-1 */
1519 cross
[i
].gain_x
= reg08
+ 1; /* Q-1 */
1520 cross
[i
].phase_y
= reg09
;
1523 cross
[i
].gain_x
= (reg08
| 0x20) + 1; /* I-1 */
1524 cross
[i
].phase_y
= reg09
;
1527 rc
= r820t_write_reg(priv
, 0x08, cross
[i
].gain_x
);
1531 rc
= r820t_write_reg(priv
, 0x09, cross
[i
].phase_y
);
1535 rc
= r820t_multi_read(priv
);
1539 cross
[i
].value
= rc
;
1541 if (cross
[i
].value
< tmp
.value
)
1542 memcpy(&tmp
, &cross
[i
], sizeof(tmp
));
1545 if ((tmp
.phase_y
& 0x1f) == 1) { /* y-direction */
1548 iq_point
[0] = cross
[0];
1549 iq_point
[1] = cross
[1];
1550 iq_point
[2] = cross
[2];
1551 } else { /* (0,0) or x-direction */
1554 iq_point
[0] = cross
[0];
1555 iq_point
[1] = cross
[3];
1556 iq_point
[2] = cross
[4];
1561 static void r820t_compre_cor(struct r820t_sect_type iq
[3])
1565 for (i
= 3; i
> 0; i
--) {
1566 if (iq
[0].value
> iq
[i
- 1].value
)
1567 swap(iq
[0], iq
[i
- 1]);
1571 static int r820t_compre_step(struct r820t_priv
*priv
,
1572 struct r820t_sect_type iq
[3], u8 reg
)
1575 struct r820t_sect_type tmp
;
1578 * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare
1580 * new < min => update to min and continue
1584 /* min value already saved in iq[0] */
1585 tmp
.phase_y
= iq
[0].phase_y
;
1586 tmp
.gain_x
= iq
[0].gain_x
;
1588 while (((tmp
.gain_x
& 0x1f) < IMR_TRIAL
) &&
1589 ((tmp
.phase_y
& 0x1f) < IMR_TRIAL
)) {
1595 rc
= r820t_write_reg(priv
, 0x08, tmp
.gain_x
);
1599 rc
= r820t_write_reg(priv
, 0x09, tmp
.phase_y
);
1603 rc
= r820t_multi_read(priv
);
1608 if (tmp
.value
<= iq
[0].value
) {
1609 iq
[0].gain_x
= tmp
.gain_x
;
1610 iq
[0].phase_y
= tmp
.phase_y
;
1611 iq
[0].value
= tmp
.value
;
1621 static int r820t_iq_tree(struct r820t_priv
*priv
,
1622 struct r820t_sect_type iq
[3],
1623 u8 fix_val
, u8 var_val
, u8 fix_reg
)
1629 * record IMC results by input gain/phase location then adjust
1630 * gain or phase positive 1 step and negtive 1 step,
1631 * both record results
1634 if (fix_reg
== 0x08)
1639 for (i
= 0; i
< 3; i
++) {
1640 rc
= r820t_write_reg(priv
, fix_reg
, fix_val
);
1644 rc
= r820t_write_reg(priv
, var_reg
, var_val
);
1648 rc
= r820t_multi_read(priv
);
1653 if (fix_reg
== 0x08) {
1654 iq
[i
].gain_x
= fix_val
;
1655 iq
[i
].phase_y
= var_val
;
1657 iq
[i
].phase_y
= fix_val
;
1658 iq
[i
].gain_x
= var_val
;
1661 if (i
== 0) { /* try right-side point */
1663 } else if (i
== 1) { /* try left-side point */
1664 /* if absolute location is 1, change I/Q direction */
1665 if ((var_val
& 0x1f) < 0x02) {
1666 tmp
= 2 - (var_val
& 0x1f);
1668 /* b[5]:I/Q selection. 0:Q-path, 1:I-path */
1669 if (var_val
& 0x20) {
1673 var_val
|= 0x20 | tmp
;
1684 static int r820t_section(struct r820t_priv
*priv
,
1685 struct r820t_sect_type
*iq_point
)
1688 struct r820t_sect_type compare_iq
[3], compare_bet
[3];
1690 /* Try X-1 column and save min result to compare_bet[0] */
1691 if (!(iq_point
->gain_x
& 0x1f))
1692 compare_iq
[0].gain_x
= ((iq_point
->gain_x
) & 0xdf) + 1; /* Q-path, Gain=1 */
1694 compare_iq
[0].gain_x
= iq_point
->gain_x
- 1; /* left point */
1695 compare_iq
[0].phase_y
= iq_point
->phase_y
;
1698 rc
= r820t_iq_tree(priv
, compare_iq
, compare_iq
[0].gain_x
,
1699 compare_iq
[0].phase_y
, 0x08);
1703 r820t_compre_cor(compare_iq
);
1705 compare_bet
[0] = compare_iq
[0];
1707 /* Try X column and save min result to compare_bet[1] */
1708 compare_iq
[0].gain_x
= iq_point
->gain_x
;
1709 compare_iq
[0].phase_y
= iq_point
->phase_y
;
1711 rc
= r820t_iq_tree(priv
, compare_iq
, compare_iq
[0].gain_x
,
1712 compare_iq
[0].phase_y
, 0x08);
1716 r820t_compre_cor(compare_iq
);
1718 compare_bet
[1] = compare_iq
[0];
1720 /* Try X+1 column and save min result to compare_bet[2] */
1721 if ((iq_point
->gain_x
& 0x1f) == 0x00)
1722 compare_iq
[0].gain_x
= ((iq_point
->gain_x
) | 0x20) + 1; /* I-path, Gain=1 */
1724 compare_iq
[0].gain_x
= iq_point
->gain_x
+ 1;
1725 compare_iq
[0].phase_y
= iq_point
->phase_y
;
1727 rc
= r820t_iq_tree(priv
, compare_iq
, compare_iq
[0].gain_x
,
1728 compare_iq
[0].phase_y
, 0x08);
1732 r820t_compre_cor(compare_iq
);
1734 compare_bet
[2] = compare_iq
[0];
1736 r820t_compre_cor(compare_bet
);
1738 *iq_point
= compare_bet
[0];
1743 static int r820t_vga_adjust(struct r820t_priv
*priv
)
1748 /* increase vga power to let image significant */
1749 for (vga_count
= 12; vga_count
< 16; vga_count
++) {
1750 rc
= r820t_write_reg_mask(priv
, 0x0c, vga_count
, 0x0f);
1754 usleep_range(10000, 11000);
1756 rc
= r820t_multi_read(priv
);
1767 static int r820t_iq(struct r820t_priv
*priv
, struct r820t_sect_type
*iq_pont
)
1769 struct r820t_sect_type compare_iq
[3];
1771 u8 x_direction
= 0; /* 1:x, 0:y */
1772 u8 dir_reg
, other_reg
;
1774 r820t_vga_adjust(priv
);
1776 rc
= r820t_imr_cross(priv
, compare_iq
, &x_direction
);
1780 if (x_direction
== 1) {
1788 /* compare and find min of 3 points. determine i/q direction */
1789 r820t_compre_cor(compare_iq
);
1791 /* increase step to find min value of this direction */
1792 rc
= r820t_compre_step(priv
, compare_iq
, dir_reg
);
1796 /* the other direction */
1797 rc
= r820t_iq_tree(priv
, compare_iq
, compare_iq
[0].gain_x
,
1798 compare_iq
[0].phase_y
, dir_reg
);
1802 /* compare and find min of 3 points. determine i/q direction */
1803 r820t_compre_cor(compare_iq
);
1805 /* increase step to find min value on this direction */
1806 rc
= r820t_compre_step(priv
, compare_iq
, other_reg
);
1810 /* check 3 points again */
1811 rc
= r820t_iq_tree(priv
, compare_iq
, compare_iq
[0].gain_x
,
1812 compare_iq
[0].phase_y
, other_reg
);
1816 r820t_compre_cor(compare_iq
);
1818 /* section-9 check */
1819 rc
= r820t_section(priv
, compare_iq
);
1821 *iq_pont
= compare_iq
[0];
1823 /* reset gain/phase control setting */
1824 rc
= r820t_write_reg_mask(priv
, 0x08, 0, 0x3f);
1828 rc
= r820t_write_reg_mask(priv
, 0x09, 0, 0x3f);
1833 static int r820t_f_imr(struct r820t_priv
*priv
, struct r820t_sect_type
*iq_pont
)
1837 r820t_vga_adjust(priv
);
1840 * search surrounding points from previous point
1841 * try (x-1), (x), (x+1) columns, and find min IMR result point
1843 rc
= r820t_section(priv
, iq_pont
);
1850 static int r820t_imr(struct r820t_priv
*priv
, unsigned imr_mem
, bool im_flag
)
1852 struct r820t_sect_type imr_point
;
1854 u32 ring_vco
, ring_freq
, ring_ref
;
1856 int reg18
, reg19
, reg1f
;
1858 if (priv
->cfg
->xtal
> 24000000)
1859 ring_ref
= priv
->cfg
->xtal
/ 2;
1861 ring_ref
= priv
->cfg
->xtal
;
1863 for (n
= 0; n
< 16; n
++) {
1864 if ((16 + n
) * 8 * ring_ref
>= 3100000) {
1869 /* n_ring not found */
1874 reg18
= r820t_read_cache_reg(priv
, 0x18);
1875 reg19
= r820t_read_cache_reg(priv
, 0x19);
1876 reg1f
= r820t_read_cache_reg(priv
, 0x1f);
1878 reg18
&= 0xf0; /* set ring[3:0] */
1881 ring_vco
= (16 + n_ring
) * 8 * ring_ref
;
1883 reg18
&= 0xdf; /* clear ring_se23 */
1884 reg19
&= 0xfc; /* clear ring_seldiv */
1885 reg1f
&= 0xfc; /* clear ring_att */
1889 ring_freq
= ring_vco
/ 48;
1890 reg18
|= 0x20; /* ring_se23 = 1 */
1891 reg19
|= 0x03; /* ring_seldiv = 3 */
1892 reg1f
|= 0x02; /* ring_att 10 */
1895 ring_freq
= ring_vco
/ 16;
1896 reg18
|= 0x00; /* ring_se23 = 0 */
1897 reg19
|= 0x02; /* ring_seldiv = 2 */
1898 reg1f
|= 0x00; /* pw_ring 00 */
1901 ring_freq
= ring_vco
/ 8;
1902 reg18
|= 0x00; /* ring_se23 = 0 */
1903 reg19
|= 0x01; /* ring_seldiv = 1 */
1904 reg1f
|= 0x03; /* pw_ring 11 */
1907 ring_freq
= ring_vco
/ 6;
1908 reg18
|= 0x20; /* ring_se23 = 1 */
1909 reg19
|= 0x00; /* ring_seldiv = 0 */
1910 reg1f
|= 0x03; /* pw_ring 11 */
1913 ring_freq
= ring_vco
/ 4;
1914 reg18
|= 0x00; /* ring_se23 = 0 */
1915 reg19
|= 0x00; /* ring_seldiv = 0 */
1916 reg1f
|= 0x01; /* pw_ring 01 */
1919 ring_freq
= ring_vco
/ 4;
1920 reg18
|= 0x00; /* ring_se23 = 0 */
1921 reg19
|= 0x00; /* ring_seldiv = 0 */
1922 reg1f
|= 0x01; /* pw_ring 01 */
1927 /* write pw_ring, n_ring, ringdiv2 registers */
1929 /* n_ring, ring_se23 */
1930 rc
= r820t_write_reg(priv
, 0x18, reg18
);
1935 rc
= r820t_write_reg(priv
, 0x19, reg19
);
1940 rc
= r820t_write_reg(priv
, 0x1f, reg1f
);
1944 /* mux input freq ~ rf_in freq */
1945 rc
= r820t_set_mux(priv
, (ring_freq
- 5300) * 1000);
1949 rc
= r820t_set_pll(priv
, V4L2_TUNER_DIGITAL_TV
,
1950 (ring_freq
- 5300) * 1000);
1951 if (!priv
->has_lock
)
1957 rc
= r820t_iq(priv
, &imr_point
);
1959 imr_point
.gain_x
= priv
->imr_data
[3].gain_x
;
1960 imr_point
.phase_y
= priv
->imr_data
[3].phase_y
;
1961 imr_point
.value
= priv
->imr_data
[3].value
;
1963 rc
= r820t_f_imr(priv
, &imr_point
);
1968 /* save IMR value */
1971 priv
->imr_data
[0].gain_x
= imr_point
.gain_x
;
1972 priv
->imr_data
[0].phase_y
= imr_point
.phase_y
;
1973 priv
->imr_data
[0].value
= imr_point
.value
;
1976 priv
->imr_data
[1].gain_x
= imr_point
.gain_x
;
1977 priv
->imr_data
[1].phase_y
= imr_point
.phase_y
;
1978 priv
->imr_data
[1].value
= imr_point
.value
;
1981 priv
->imr_data
[2].gain_x
= imr_point
.gain_x
;
1982 priv
->imr_data
[2].phase_y
= imr_point
.phase_y
;
1983 priv
->imr_data
[2].value
= imr_point
.value
;
1986 priv
->imr_data
[3].gain_x
= imr_point
.gain_x
;
1987 priv
->imr_data
[3].phase_y
= imr_point
.phase_y
;
1988 priv
->imr_data
[3].value
= imr_point
.value
;
1991 priv
->imr_data
[4].gain_x
= imr_point
.gain_x
;
1992 priv
->imr_data
[4].phase_y
= imr_point
.phase_y
;
1993 priv
->imr_data
[4].value
= imr_point
.value
;
1996 priv
->imr_data
[4].gain_x
= imr_point
.gain_x
;
1997 priv
->imr_data
[4].phase_y
= imr_point
.phase_y
;
1998 priv
->imr_data
[4].value
= imr_point
.value
;
2005 static int r820t_imr_callibrate(struct r820t_priv
*priv
)
2010 if (priv
->init_done
)
2013 /* Detect Xtal capacitance */
2014 if ((priv
->cfg
->rafael_chip
== CHIP_R820T
) ||
2015 (priv
->cfg
->rafael_chip
== CHIP_R828S
) ||
2016 (priv
->cfg
->rafael_chip
== CHIP_R820C
)) {
2017 priv
->xtal_cap_sel
= XTAL_HIGH_CAP_0P
;
2019 /* Initialize registers */
2020 rc
= r820t_write(priv
, 0x05,
2021 r820t_init_array
, sizeof(r820t_init_array
));
2024 for (i
= 0; i
< 3; i
++) {
2025 rc
= r820t_xtal_check(priv
);
2028 if (!i
|| rc
> xtal_cap
)
2031 priv
->xtal_cap_sel
= xtal_cap
;
2035 * Disables IMR callibration. That emulates the same behaviour
2036 * as what is done by rtl-sdr userspace library. Useful for testing
2039 priv
->init_done
= true;
2044 /* Initialize registers */
2045 rc
= r820t_write(priv
, 0x05,
2046 r820t_init_array
, sizeof(r820t_init_array
));
2050 rc
= r820t_imr_prepare(priv
);
2054 rc
= r820t_imr(priv
, 3, true);
2057 rc
= r820t_imr(priv
, 1, false);
2060 rc
= r820t_imr(priv
, 0, false);
2063 rc
= r820t_imr(priv
, 2, false);
2066 rc
= r820t_imr(priv
, 4, false);
2070 priv
->init_done
= true;
2071 priv
->imr_done
= true;
2077 /* Not used, for now */
2078 static int r820t_gpio(struct r820t_priv
*priv
, bool enable
)
2080 return r820t_write_reg_mask(priv
, 0x0f, enable
? 1 : 0, 0x01);
2085 * r820t frontend operations and tuner attach code
2087 * All driver locks and i2c control are only in this part of the code
2090 static int r820t_init(struct dvb_frontend
*fe
)
2092 struct r820t_priv
*priv
= fe
->tuner_priv
;
2095 tuner_dbg("%s:\n", __func__
);
2097 mutex_lock(&priv
->lock
);
2098 if (fe
->ops
.i2c_gate_ctrl
)
2099 fe
->ops
.i2c_gate_ctrl(fe
, 1);
2101 rc
= r820t_imr_callibrate(priv
);
2105 /* Initialize registers */
2106 rc
= r820t_write(priv
, 0x05,
2107 r820t_init_array
, sizeof(r820t_init_array
));
2110 if (fe
->ops
.i2c_gate_ctrl
)
2111 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2112 mutex_unlock(&priv
->lock
);
2115 tuner_dbg("%s: failed=%d\n", __func__
, rc
);
2119 static int r820t_sleep(struct dvb_frontend
*fe
)
2121 struct r820t_priv
*priv
= fe
->tuner_priv
;
2124 tuner_dbg("%s:\n", __func__
);
2126 mutex_lock(&priv
->lock
);
2127 if (fe
->ops
.i2c_gate_ctrl
)
2128 fe
->ops
.i2c_gate_ctrl(fe
, 1);
2130 rc
= r820t_standby(priv
);
2132 if (fe
->ops
.i2c_gate_ctrl
)
2133 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2134 mutex_unlock(&priv
->lock
);
2136 tuner_dbg("%s: failed=%d\n", __func__
, rc
);
2140 static int r820t_set_analog_freq(struct dvb_frontend
*fe
,
2141 struct analog_parameters
*p
)
2143 struct r820t_priv
*priv
= fe
->tuner_priv
;
2147 tuner_dbg("%s called\n", __func__
);
2149 /* if std is not defined, choose one */
2151 p
->std
= V4L2_STD_MN
;
2153 if ((p
->std
== V4L2_STD_PAL_M
) || (p
->std
== V4L2_STD_NTSC
))
2158 mutex_lock(&priv
->lock
);
2159 if (fe
->ops
.i2c_gate_ctrl
)
2160 fe
->ops
.i2c_gate_ctrl(fe
, 1);
2162 rc
= generic_set_freq(fe
, 62500l * p
->frequency
, bw
,
2163 V4L2_TUNER_ANALOG_TV
, p
->std
, SYS_UNDEFINED
);
2165 if (fe
->ops
.i2c_gate_ctrl
)
2166 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2167 mutex_unlock(&priv
->lock
);
2172 static int r820t_set_params(struct dvb_frontend
*fe
)
2174 struct r820t_priv
*priv
= fe
->tuner_priv
;
2175 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
2179 tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
2180 __func__
, c
->delivery_system
, c
->frequency
, c
->bandwidth_hz
);
2182 mutex_lock(&priv
->lock
);
2183 if (fe
->ops
.i2c_gate_ctrl
)
2184 fe
->ops
.i2c_gate_ctrl(fe
, 1);
2186 bw
= (c
->bandwidth_hz
+ 500000) / 1000000;
2190 rc
= generic_set_freq(fe
, c
->frequency
, bw
,
2191 V4L2_TUNER_DIGITAL_TV
, 0, c
->delivery_system
);
2193 if (fe
->ops
.i2c_gate_ctrl
)
2194 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2195 mutex_unlock(&priv
->lock
);
2198 tuner_dbg("%s: failed=%d\n", __func__
, rc
);
2202 static int r820t_signal(struct dvb_frontend
*fe
, u16
*strength
)
2204 struct r820t_priv
*priv
= fe
->tuner_priv
;
2207 mutex_lock(&priv
->lock
);
2208 if (fe
->ops
.i2c_gate_ctrl
)
2209 fe
->ops
.i2c_gate_ctrl(fe
, 1);
2211 if (priv
->has_lock
) {
2212 rc
= r820t_read_gain(priv
);
2216 /* A higher gain at LNA means a lower signal strength */
2217 *strength
= (45 - rc
) << 4 | 0xff;
2218 if (*strength
== 0xff)
2225 if (fe
->ops
.i2c_gate_ctrl
)
2226 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2227 mutex_unlock(&priv
->lock
);
2229 tuner_dbg("%s: %s, gain=%d strength=%d\n",
2231 priv
->has_lock
? "PLL locked" : "no signal",
2237 static int r820t_get_if_frequency(struct dvb_frontend
*fe
, u32
*frequency
)
2239 struct r820t_priv
*priv
= fe
->tuner_priv
;
2241 tuner_dbg("%s:\n", __func__
);
2243 *frequency
= priv
->int_freq
;
2248 static int r820t_release(struct dvb_frontend
*fe
)
2250 struct r820t_priv
*priv
= fe
->tuner_priv
;
2252 tuner_dbg("%s:\n", __func__
);
2254 mutex_lock(&r820t_list_mutex
);
2257 hybrid_tuner_release_state(priv
);
2259 mutex_unlock(&r820t_list_mutex
);
2261 fe
->tuner_priv
= NULL
;
2263 kfree(fe
->tuner_priv
);
2268 static const struct dvb_tuner_ops r820t_tuner_ops
= {
2270 .name
= "Rafael Micro R820T",
2271 .frequency_min
= 42000000,
2272 .frequency_max
= 1002000000,
2275 .release
= r820t_release
,
2276 .sleep
= r820t_sleep
,
2277 .set_params
= r820t_set_params
,
2278 .set_analog_params
= r820t_set_analog_freq
,
2279 .get_if_frequency
= r820t_get_if_frequency
,
2280 .get_rf_strength
= r820t_signal
,
2283 struct dvb_frontend
*r820t_attach(struct dvb_frontend
*fe
,
2284 struct i2c_adapter
*i2c
,
2285 const struct r820t_config
*cfg
)
2287 struct r820t_priv
*priv
;
2292 mutex_lock(&r820t_list_mutex
);
2294 instance
= hybrid_tuner_request_state(struct r820t_priv
, priv
,
2295 hybrid_tuner_instance_list
,
2300 /* memory allocation failure */
2304 /* new tuner instance */
2307 mutex_init(&priv
->lock
);
2309 fe
->tuner_priv
= priv
;
2312 /* existing tuner instance */
2313 fe
->tuner_priv
= priv
;
2317 memcpy(&fe
->ops
.tuner_ops
, &r820t_tuner_ops
, sizeof(r820t_tuner_ops
));
2319 if (fe
->ops
.i2c_gate_ctrl
)
2320 fe
->ops
.i2c_gate_ctrl(fe
, 1);
2322 /* check if the tuner is there */
2323 rc
= r820t_read(priv
, 0x00, data
, sizeof(data
));
2327 rc
= r820t_sleep(fe
);
2331 tuner_info("Rafael Micro r820t successfully identified\n");
2333 fe
->tuner_priv
= priv
;
2334 memcpy(&fe
->ops
.tuner_ops
, &r820t_tuner_ops
,
2335 sizeof(struct dvb_tuner_ops
));
2337 if (fe
->ops
.i2c_gate_ctrl
)
2338 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2340 mutex_unlock(&r820t_list_mutex
);
2344 if (fe
->ops
.i2c_gate_ctrl
)
2345 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2348 mutex_unlock(&r820t_list_mutex
);
2350 tuner_info("%s: failed=%d\n", __func__
, rc
);
2354 EXPORT_SYMBOL_GPL(r820t_attach
);
2356 MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
2357 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2358 MODULE_LICENSE("GPL");