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[media] r820t: use the second table for 7MHz
[deliverable/linux.git] / drivers / media / tuners / r820t.c
1 /*
2 * Rafael Micro R820T driver
3 *
4 * Copyright (C) 2013 Mauro Carvalho Chehab <mchehab@redhat.com>
5 *
6 * This driver was written from scratch, based on an existing driver
7 * that it is part of rtl-sdr git tree, released under GPLv2:
8 * https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug
9 * https://github.com/n1gp/gr-baz
10 *
11 * From what I understood from the threads, the original driver was converted
12 * to userspace from a Realtek tree. I couldn't find the original tree.
13 * However, the original driver look awkward on my eyes. So, I decided to
14 * write a new version from it from the scratch, while trying to reproduce
15 * everything found there.
16 *
17 * TODO:
18 * After locking, the original driver seems to have some routines to
19 * improve reception. This was not implemented here yet.
20 *
21 * RF Gain set/get is not implemented.
22 *
23 * This program is free software; you can redistribute it and/or modify
24 * it under the terms of the GNU General Public License as published by
25 * the Free Software Foundation; either version 2 of the License, or
26 * (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 */
34
35 #include <linux/videodev2.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/bitrev.h>
39 #include <asm/div64.h>
40
41 #include "tuner-i2c.h"
42 #include "r820t.h"
43
44 /*
45 * FIXME: I think that there are only 32 registers, but better safe than
46 * sorry. After finishing the driver, we may review it.
47 */
48 #define REG_SHADOW_START 5
49 #define NUM_REGS 27
50
51 #define VER_NUM 49
52
53 static int debug;
54 module_param(debug, int, 0644);
55 MODULE_PARM_DESC(debug, "enable verbose debug messages");
56
57 /*
58 * enums and structures
59 */
60
61 enum xtal_cap_value {
62 XTAL_LOW_CAP_30P = 0,
63 XTAL_LOW_CAP_20P,
64 XTAL_LOW_CAP_10P,
65 XTAL_LOW_CAP_0P,
66 XTAL_HIGH_CAP_0P
67 };
68
69 struct r820t_priv {
70 struct list_head hybrid_tuner_instance_list;
71 const struct r820t_config *cfg;
72 struct tuner_i2c_props i2c_props;
73 struct mutex lock;
74
75 u8 regs[NUM_REGS];
76 u8 buf[NUM_REGS + 1];
77 enum xtal_cap_value xtal_cap_sel;
78 u16 pll; /* kHz */
79 u32 int_freq;
80 u8 fil_cal_code;
81 bool imr_done;
82
83 /* Store current mode */
84 u32 delsys;
85 enum v4l2_tuner_type type;
86 v4l2_std_id std;
87 u32 bw; /* in MHz */
88
89 bool has_lock;
90 };
91
92 struct r820t_freq_range {
93 u32 freq;
94 u8 open_d;
95 u8 rf_mux_ploy;
96 u8 tf_c;
97 u8 xtal_cap20p;
98 u8 xtal_cap10p;
99 u8 xtal_cap0p;
100 u8 imr_mem; /* Not used, currently */
101 };
102
103 #define VCO_POWER_REF 0x02
104
105 /*
106 * Static constants
107 */
108
109 static LIST_HEAD(hybrid_tuner_instance_list);
110 static DEFINE_MUTEX(r820t_list_mutex);
111
112 /* Those initial values start from REG_SHADOW_START */
113 static const u8 r820t_init_array[NUM_REGS] = {
114 0x83, 0x32, 0x75, /* 05 to 07 */
115 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */
116 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */
117 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */
118 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */
119 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */
120 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */
121 };
122
123 /* Tuner frequency ranges */
124 static const struct r820t_freq_range freq_ranges[] = {
125 {
126 .freq = 0,
127 .open_d = 0x08, /* low */
128 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
129 .tf_c = 0xdf, /* R27[7:0] band2,band0 */
130 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
131 .xtal_cap10p = 0x01,
132 .xtal_cap0p = 0x00,
133 .imr_mem = 0,
134 }, {
135 .freq = 50, /* Start freq, in MHz */
136 .open_d = 0x08, /* low */
137 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
138 .tf_c = 0xbe, /* R27[7:0] band4,band1 */
139 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
140 .xtal_cap10p = 0x01,
141 .xtal_cap0p = 0x00,
142 .imr_mem = 0,
143 }, {
144 .freq = 55, /* Start freq, in MHz */
145 .open_d = 0x08, /* low */
146 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
147 .tf_c = 0x8b, /* R27[7:0] band7,band4 */
148 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
149 .xtal_cap10p = 0x01,
150 .xtal_cap0p = 0x00,
151 .imr_mem = 0,
152 }, {
153 .freq = 60, /* Start freq, in MHz */
154 .open_d = 0x08, /* low */
155 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
156 .tf_c = 0x7b, /* R27[7:0] band8,band4 */
157 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
158 .xtal_cap10p = 0x01,
159 .xtal_cap0p = 0x00,
160 .imr_mem = 0,
161 }, {
162 .freq = 65, /* Start freq, in MHz */
163 .open_d = 0x08, /* low */
164 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
165 .tf_c = 0x69, /* R27[7:0] band9,band6 */
166 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
167 .xtal_cap10p = 0x01,
168 .xtal_cap0p = 0x00,
169 .imr_mem = 0,
170 }, {
171 .freq = 70, /* Start freq, in MHz */
172 .open_d = 0x08, /* low */
173 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
174 .tf_c = 0x58, /* R27[7:0] band10,band7 */
175 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
176 .xtal_cap10p = 0x01,
177 .xtal_cap0p = 0x00,
178 .imr_mem = 0,
179 }, {
180 .freq = 75, /* Start freq, in MHz */
181 .open_d = 0x00, /* high */
182 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
183 .tf_c = 0x44, /* R27[7:0] band11,band11 */
184 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
185 .xtal_cap10p = 0x01,
186 .xtal_cap0p = 0x00,
187 .imr_mem = 0,
188 }, {
189 .freq = 80, /* Start freq, in MHz */
190 .open_d = 0x00, /* high */
191 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
192 .tf_c = 0x44, /* R27[7:0] band11,band11 */
193 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
194 .xtal_cap10p = 0x01,
195 .xtal_cap0p = 0x00,
196 .imr_mem = 0,
197 }, {
198 .freq = 90, /* Start freq, in MHz */
199 .open_d = 0x00, /* high */
200 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
201 .tf_c = 0x34, /* R27[7:0] band12,band11 */
202 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
203 .xtal_cap10p = 0x01,
204 .xtal_cap0p = 0x00,
205 .imr_mem = 0,
206 }, {
207 .freq = 100, /* Start freq, in MHz */
208 .open_d = 0x00, /* high */
209 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
210 .tf_c = 0x34, /* R27[7:0] band12,band11 */
211 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
212 .xtal_cap10p = 0x01,
213 .xtal_cap0p = 0x00,
214 .imr_mem = 0,
215 }, {
216 .freq = 110, /* Start freq, in MHz */
217 .open_d = 0x00, /* high */
218 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
219 .tf_c = 0x24, /* R27[7:0] band13,band11 */
220 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
221 .xtal_cap10p = 0x01,
222 .xtal_cap0p = 0x00,
223 .imr_mem = 1,
224 }, {
225 .freq = 120, /* Start freq, in MHz */
226 .open_d = 0x00, /* high */
227 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
228 .tf_c = 0x24, /* R27[7:0] band13,band11 */
229 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
230 .xtal_cap10p = 0x01,
231 .xtal_cap0p = 0x00,
232 .imr_mem = 1,
233 }, {
234 .freq = 140, /* Start freq, in MHz */
235 .open_d = 0x00, /* high */
236 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
237 .tf_c = 0x14, /* R27[7:0] band14,band11 */
238 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
239 .xtal_cap10p = 0x01,
240 .xtal_cap0p = 0x00,
241 .imr_mem = 1,
242 }, {
243 .freq = 180, /* Start freq, in MHz */
244 .open_d = 0x00, /* high */
245 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
246 .tf_c = 0x13, /* R27[7:0] band14,band12 */
247 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
248 .xtal_cap10p = 0x00,
249 .xtal_cap0p = 0x00,
250 .imr_mem = 1,
251 }, {
252 .freq = 220, /* Start freq, in MHz */
253 .open_d = 0x00, /* high */
254 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
255 .tf_c = 0x13, /* R27[7:0] band14,band12 */
256 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
257 .xtal_cap10p = 0x00,
258 .xtal_cap0p = 0x00,
259 .imr_mem = 2,
260 }, {
261 .freq = 250, /* Start freq, in MHz */
262 .open_d = 0x00, /* high */
263 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
264 .tf_c = 0x11, /* R27[7:0] highest,highest */
265 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
266 .xtal_cap10p = 0x00,
267 .xtal_cap0p = 0x00,
268 .imr_mem = 2,
269 }, {
270 .freq = 280, /* Start freq, in MHz */
271 .open_d = 0x00, /* high */
272 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
273 .tf_c = 0x00, /* R27[7:0] highest,highest */
274 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
275 .xtal_cap10p = 0x00,
276 .xtal_cap0p = 0x00,
277 .imr_mem = 2,
278 }, {
279 .freq = 310, /* Start freq, in MHz */
280 .open_d = 0x00, /* high */
281 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
282 .tf_c = 0x00, /* R27[7:0] highest,highest */
283 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
284 .xtal_cap10p = 0x00,
285 .xtal_cap0p = 0x00,
286 .imr_mem = 2,
287 }, {
288 .freq = 450, /* Start freq, in MHz */
289 .open_d = 0x00, /* high */
290 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
291 .tf_c = 0x00, /* R27[7:0] highest,highest */
292 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
293 .xtal_cap10p = 0x00,
294 .xtal_cap0p = 0x00,
295 .imr_mem = 3,
296 }, {
297 .freq = 588, /* Start freq, in MHz */
298 .open_d = 0x00, /* high */
299 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
300 .tf_c = 0x00, /* R27[7:0] highest,highest */
301 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
302 .xtal_cap10p = 0x00,
303 .xtal_cap0p = 0x00,
304 .imr_mem = 3,
305 }, {
306 .freq = 650, /* Start freq, in MHz */
307 .open_d = 0x00, /* high */
308 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
309 .tf_c = 0x00, /* R27[7:0] highest,highest */
310 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
311 .xtal_cap10p = 0x00,
312 .xtal_cap0p = 0x00,
313 .imr_mem = 4,
314 }
315 };
316
317 static int r820t_xtal_capacitor[][2] = {
318 { 0x0b, XTAL_LOW_CAP_30P },
319 { 0x02, XTAL_LOW_CAP_20P },
320 { 0x01, XTAL_LOW_CAP_10P },
321 { 0x00, XTAL_LOW_CAP_0P },
322 { 0x10, XTAL_HIGH_CAP_0P },
323 };
324
325 /*
326 * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
327 * input power, for raw results see:
328 * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
329 */
330
331 static const int r820t_lna_gain_steps[] = {
332 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
333 };
334
335 static const int r820t_mixer_gain_steps[] = {
336 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
337 };
338
339 /*
340 * I2C read/write code and shadow registers logic
341 */
342 static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val,
343 int len)
344 {
345 int r = reg - REG_SHADOW_START;
346
347 if (r < 0) {
348 len += r;
349 r = 0;
350 }
351 if (len <= 0)
352 return;
353 if (len > NUM_REGS)
354 len = NUM_REGS;
355
356 tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n",
357 __func__, r + REG_SHADOW_START, len, len, val);
358
359 memcpy(&priv->regs[r], val, len);
360 }
361
362 static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val,
363 int len)
364 {
365 int rc, size, pos = 0;
366
367 /* Store the shadow registers */
368 shadow_store(priv, reg, val, len);
369
370 do {
371 if (len > priv->cfg->max_i2c_msg_len - 1)
372 size = priv->cfg->max_i2c_msg_len - 1;
373 else
374 size = len;
375
376 /* Fill I2C buffer */
377 priv->buf[0] = reg;
378 memcpy(&priv->buf[1], &val[pos], size);
379
380 rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1);
381 if (rc != size + 1) {
382 tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
383 __func__, rc, reg, size, size, &priv->buf[1]);
384 if (rc < 0)
385 return rc;
386 return -EREMOTEIO;
387 }
388 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
389 __func__, reg, size, size, &priv->buf[1]);
390
391 reg += size;
392 len -= size;
393 pos += size;
394 } while (len > 0);
395
396 return 0;
397 }
398
399 static int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val)
400 {
401 return r820t_write(priv, reg, &val, 1);
402 }
403
404 static int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val,
405 u8 bit_mask)
406 {
407 int r = reg - REG_SHADOW_START;
408
409 if (r >= 0 && r < NUM_REGS)
410 val = (priv->regs[r] & ~bit_mask) | (val & bit_mask);
411 else
412 return -EINVAL;
413
414 return r820t_write(priv, reg, &val, 1);
415 }
416
417 static int r820_read(struct r820t_priv *priv, u8 reg, u8 *val, int len)
418 {
419 int rc, i;
420 u8 *p = &priv->buf[1];
421
422 priv->buf[0] = reg;
423
424 rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len);
425 if (rc != len) {
426 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
427 __func__, rc, reg, len, len, p);
428 if (rc < 0)
429 return rc;
430 return -EREMOTEIO;
431 }
432 tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
433 __func__, reg, len, len, p);
434
435 /* Copy data to the output buffer */
436 for (i = 0; i < len; i++)
437 val[i] = bitrev8(p[i]);
438
439 return 0;
440 }
441
442 /*
443 * r820t tuning logic
444 */
445
446 static int r820t_set_mux(struct r820t_priv *priv, u32 freq)
447 {
448 const struct r820t_freq_range *range;
449 int i, rc;
450 u8 val;
451
452 /* Get the proper frequency range */
453 freq = freq / 1000000;
454 for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) {
455 if (freq < freq_ranges[i + 1].freq)
456 break;
457 }
458 range = &freq_ranges[i];
459
460 tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq);
461
462 /* Open Drain */
463 rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08);
464 if (rc < 0)
465 return rc;
466
467 /* RF_MUX,Polymux */
468 rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3);
469 if (rc < 0)
470 return rc;
471
472 /* TF BAND */
473 rc = r820t_write_reg(priv, 0x1b, range->tf_c);
474 if (rc < 0)
475 return rc;
476
477 /* XTAL CAP & Drive */
478 switch (priv->xtal_cap_sel) {
479 case XTAL_LOW_CAP_30P:
480 case XTAL_LOW_CAP_20P:
481 val = range->xtal_cap20p | 0x08;
482 break;
483 case XTAL_LOW_CAP_10P:
484 val = range->xtal_cap10p | 0x08;
485 break;
486 case XTAL_HIGH_CAP_0P:
487 val = range->xtal_cap0p | 0x00;
488 break;
489 default:
490 case XTAL_LOW_CAP_0P:
491 val = range->xtal_cap0p | 0x08;
492 break;
493 }
494 rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b);
495 if (rc < 0)
496 return rc;
497
498 /*
499 * FIXME: the original driver has a logic there with preserves
500 * gain/phase from registers 8 and 9 reading the data from the
501 * registers before writing, if "IMF done". That code was sort of
502 * commented there, as the flag is always false.
503 */
504 rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);
505 if (rc < 0)
506 return rc;
507
508 rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);
509
510 return rc;
511 }
512
513 static int r820t_set_pll(struct r820t_priv *priv, u32 freq)
514 {
515 u64 tmp64, vco_freq;
516 int rc, i;
517 u32 vco_fra; /* VCO contribution by SDM (kHz) */
518 u32 vco_min = 1770000;
519 u32 vco_max = vco_min * 2;
520 u32 pll_ref;
521 u16 n_sdm = 2;
522 u16 sdm = 0;
523 u8 mix_div = 2;
524 u8 div_buf = 0;
525 u8 div_num = 0;
526 u8 ni, si, nint, vco_fine_tune, val;
527 u8 data[5];
528
529 freq = freq / 1000; /* Frequency in kHz */
530
531 pll_ref = priv->cfg->xtal / 1000;
532
533 tuner_dbg("set r820t pll for frequency %d kHz = %d\n", freq, pll_ref);
534
535 /* FIXME: this seems to be a hack - probably it can be removed */
536 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x00);
537 if (rc < 0)
538 return rc;
539
540 /* set pll autotune = 128kHz */
541 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
542 if (rc < 0)
543 return rc;
544
545 /* set VCO current = 100 */
546 rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0);
547 if (rc < 0)
548 return rc;
549
550 /* Calculate divider */
551 while (mix_div <= 64) {
552 if (((freq * mix_div) >= vco_min) &&
553 ((freq * mix_div) < vco_max)) {
554 div_buf = mix_div;
555 while (div_buf > 2) {
556 div_buf = div_buf >> 1;
557 div_num++;
558 }
559 break;
560 }
561 mix_div = mix_div << 1;
562 }
563
564 rc = r820_read(priv, 0x00, data, sizeof(data));
565 if (rc < 0)
566 return rc;
567
568 vco_fine_tune = (data[4] & 0x30) >> 4;
569
570 if (vco_fine_tune > VCO_POWER_REF)
571 div_num = div_num - 1;
572 else if (vco_fine_tune < VCO_POWER_REF)
573 div_num = div_num + 1;
574
575 rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0);
576 if (rc < 0)
577 return rc;
578
579 vco_freq = (u64)(freq * (u64)mix_div);
580
581 tmp64 = vco_freq;
582 do_div(tmp64, 2 * pll_ref);
583 nint = (u8)tmp64;
584
585 tmp64 = vco_freq - ((u64)2) * pll_ref * nint;
586 do_div(tmp64, 1000);
587 vco_fra = (u16)(tmp64);
588
589 pll_ref /= 1000;
590
591 /* boundary spur prevention */
592 if (vco_fra < pll_ref / 64) {
593 vco_fra = 0;
594 } else if (vco_fra > pll_ref * 127 / 64) {
595 vco_fra = 0;
596 nint++;
597 } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) {
598 vco_fra = pll_ref * 127 / 128;
599 } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) {
600 vco_fra = pll_ref * 129 / 128;
601 }
602
603 if (nint > 63) {
604 tuner_info("No valid PLL values for %u kHz!\n", freq);
605 return -EINVAL;
606 }
607
608 ni = (nint - 13) / 4;
609 si = nint - 4 * ni - 13;
610
611 rc = r820t_write_reg(priv, 0x14, ni + (si << 6));
612 if (rc < 0)
613 return rc;
614
615 /* pw_sdm */
616 if (!vco_fra)
617 val = 0x08;
618 else
619 val = 0x00;
620
621 rc = r820t_write_reg_mask(priv, 0x12, val, 0x08);
622 if (rc < 0)
623 return rc;
624
625 /* sdm calculator */
626 while (vco_fra > 1) {
627 if (vco_fra > (2 * pll_ref / n_sdm)) {
628 sdm = sdm + 32768 / (n_sdm / 2);
629 vco_fra = vco_fra - 2 * pll_ref / n_sdm;
630 if (n_sdm >= 0x8000)
631 break;
632 }
633 n_sdm = n_sdm << 1;
634 }
635
636 rc = r820t_write_reg_mask(priv, 0x16, sdm >> 8, 0x08);
637 if (rc < 0)
638 return rc;
639 rc = r820t_write_reg_mask(priv, 0x15, sdm & 0xff, 0x08);
640 if (rc < 0)
641 return rc;
642
643 for (i = 0; i < 2; i++) {
644 /*
645 * FIXME: Rafael chips R620D, R828D and R828 seems to
646 * need 20 ms for analog TV
647 */
648 msleep(10);
649
650 /* Check if PLL has locked */
651 rc = r820_read(priv, 0x00, data, 3);
652 if (rc < 0)
653 return rc;
654 if (data[2] & 0x40)
655 break;
656
657 if (!i) {
658 /* Didn't lock. Increase VCO current */
659 rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0);
660 if (rc < 0)
661 return rc;
662 }
663 }
664
665 if (!(data[2] & 0x40)) {
666 priv->has_lock = false;
667 return 0;
668 }
669
670 priv->has_lock = true;
671 tuner_dbg("tuner has lock at frequency %d kHz\n", freq);
672
673 /* set pll autotune = 8kHz */
674 rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08);
675
676 return rc;
677 }
678
679 static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq,
680 enum v4l2_tuner_type type,
681 v4l2_std_id std,
682 u32 delsys)
683 {
684 int rc;
685 u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l;
686 u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur;
687
688 tuner_dbg("adjusting tuner parameters for the standard\n");
689
690 switch (delsys) {
691 case SYS_DVBT:
692 if ((freq == 506000000) || (freq == 666000000) ||
693 (freq == 818000000)) {
694 mixer_top = 0x14; /* mixer top:14 , top-1, low-discharge */
695 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
696 cp_cur = 0x28; /* 101, 0.2 */
697 div_buf_cur = 0x20; /* 10, 200u */
698 } else {
699 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
700 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
701 cp_cur = 0x38; /* 111, auto */
702 div_buf_cur = 0x30; /* 11, 150u */
703 }
704 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
705 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
706 air_cable1_in = 0x00;
707 cable2_in = 0x00;
708 pre_dect = 0x40;
709 lna_discharge = 14;
710 filter_cur = 0x40; /* 10, low */
711 break;
712 case SYS_DVBT2:
713 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
714 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
715 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
716 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
717 air_cable1_in = 0x00;
718 cable2_in = 0x00;
719 pre_dect = 0x40;
720 lna_discharge = 14;
721 cp_cur = 0x38; /* 111, auto */
722 div_buf_cur = 0x30; /* 11, 150u */
723 filter_cur = 0x40; /* 10, low */
724 break;
725 case SYS_ISDBT:
726 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
727 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
728 lna_vth_l = 0x75; /* lna vth 1.04 , vtl 0.84 */
729 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
730 air_cable1_in = 0x00;
731 cable2_in = 0x00;
732 pre_dect = 0x40;
733 lna_discharge = 14;
734 cp_cur = 0x38; /* 111, auto */
735 div_buf_cur = 0x30; /* 11, 150u */
736 filter_cur = 0x40; /* 10, low */
737 break;
738 default: /* DVB-T 8M */
739 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
740 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
741 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
742 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
743 air_cable1_in = 0x00;
744 cable2_in = 0x00;
745 pre_dect = 0x40;
746 lna_discharge = 14;
747 cp_cur = 0x38; /* 111, auto */
748 div_buf_cur = 0x30; /* 11, 150u */
749 filter_cur = 0x40; /* 10, low */
750 break;
751 }
752
753 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7);
754 if (rc < 0)
755 return rc;
756 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8);
757 if (rc < 0)
758 return rc;
759 rc = r820t_write_reg(priv, 0x0d, lna_vth_l);
760 if (rc < 0)
761 return rc;
762 rc = r820t_write_reg(priv, 0x0e, mixer_vth_l);
763 if (rc < 0)
764 return rc;
765
766 /* Air-IN only for Astrometa */
767 rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60);
768 if (rc < 0)
769 return rc;
770 rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08);
771 if (rc < 0)
772 return rc;
773
774 rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38);
775 if (rc < 0)
776 return rc;
777 rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30);
778 if (rc < 0)
779 return rc;
780 rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60);
781 if (rc < 0)
782 return rc;
783 /*
784 * Original driver initializes regs 0x05 and 0x06 with the
785 * same value again on this point. Probably, it is just an
786 * error there
787 */
788
789 /*
790 * Set LNA
791 */
792
793 tuner_dbg("adjusting LNA parameters\n");
794 if (type != V4L2_TUNER_ANALOG_TV) {
795 /* LNA TOP: lowest */
796 rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38);
797 if (rc < 0)
798 return rc;
799
800 /* 0: normal mode */
801 rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04);
802 if (rc < 0)
803 return rc;
804
805 /* 0: PRE_DECT off */
806 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
807 if (rc < 0)
808 return rc;
809
810 /* agc clk 250hz */
811 rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30);
812 if (rc < 0)
813 return rc;
814
815 msleep(250);
816
817 /* write LNA TOP = 3 */
818 rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38);
819 if (rc < 0)
820 return rc;
821
822 /*
823 * write discharge mode
824 * FIXME: IMHO, the mask here is wrong, but it matches
825 * what's there at the original driver
826 */
827 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
828 if (rc < 0)
829 return rc;
830
831 /* LNA discharge current */
832 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
833 if (rc < 0)
834 return rc;
835
836 /* agc clk 60hz */
837 rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30);
838 if (rc < 0)
839 return rc;
840 } else {
841 /* PRE_DECT off */
842 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
843 if (rc < 0)
844 return rc;
845
846 /* write LNA TOP */
847 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38);
848 if (rc < 0)
849 return rc;
850
851 /*
852 * write discharge mode
853 * FIXME: IMHO, the mask here is wrong, but it matches
854 * what's there at the original driver
855 */
856 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
857 if (rc < 0)
858 return rc;
859
860 /* LNA discharge current */
861 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
862 if (rc < 0)
863 return rc;
864
865 /* agc clk 1Khz, external det1 cap 1u */
866 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30);
867 if (rc < 0)
868 return rc;
869
870 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04);
871 if (rc < 0)
872 return rc;
873 }
874 return 0;
875 }
876
877 static int r820t_set_tv_standard(struct r820t_priv *priv,
878 unsigned bw,
879 enum v4l2_tuner_type type,
880 v4l2_std_id std, u32 delsys)
881
882 {
883 int rc, i;
884 u32 if_khz, filt_cal_lo;
885 u8 data[5], val;
886 u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through;
887 u8 lt_att, flt_ext_widest, polyfil_cur;
888 bool need_calibration;
889
890 tuner_dbg("selecting the delivery system\n");
891
892 if (delsys == SYS_ISDBT) {
893 if_khz = 4063;
894 filt_cal_lo = 59000;
895 filt_gain = 0x10; /* +3db, 6mhz on */
896 img_r = 0x00; /* image negative */
897 filt_q = 0x10; /* r10[4]:low q(1'b1) */
898 hp_cor = 0x6a; /* 1.7m disable, +2cap, 1.25mhz */
899 ext_enable = 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */
900 loop_through = 0x00; /* r5[7], lt on */
901 lt_att = 0x00; /* r31[7], lt att enable */
902 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
903 polyfil_cur = 0x60; /* r25[6:5]:min */
904 } else {
905 if (bw <= 6) {
906 if_khz = 3570;
907 filt_cal_lo = 56000; /* 52000->56000 */
908 filt_gain = 0x10; /* +3db, 6mhz on */
909 img_r = 0x00; /* image negative */
910 filt_q = 0x10; /* r10[4]:low q(1'b1) */
911 hp_cor = 0x6b; /* 1.7m disable, +2cap, 1.0mhz */
912 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
913 loop_through = 0x00; /* r5[7], lt on */
914 lt_att = 0x00; /* r31[7], lt att enable */
915 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
916 polyfil_cur = 0x60; /* r25[6:5]:min */
917 } else if (bw == 7) {
918 #if 0
919 /*
920 * There are two 7 MHz tables defined on the original
921 * driver, but just the second one seems to be visible
922 * by rtl2832. Keep this one here commented, as it
923 * might be needed in the future
924 */
925
926 if_khz = 4070;
927 filt_cal_lo = 60000;
928 filt_gain = 0x10; /* +3db, 6mhz on */
929 img_r = 0x00; /* image negative */
930 filt_q = 0x10; /* r10[4]:low q(1'b1) */
931 hp_cor = 0x2b; /* 1.7m disable, +1cap, 1.0mhz */
932 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
933 loop_through = 0x00; /* r5[7], lt on */
934 lt_att = 0x00; /* r31[7], lt att enable */
935 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
936 polyfil_cur = 0x60; /* r25[6:5]:min */
937 #endif
938 /* 7 MHz, second table */
939 if_khz = 4570;
940 filt_cal_lo = 63000;
941 filt_gain = 0x10; /* +3db, 6mhz on */
942 img_r = 0x00; /* image negative */
943 filt_q = 0x10; /* r10[4]:low q(1'b1) */
944 hp_cor = 0x2a; /* 1.7m disable, +1cap, 1.25mhz */
945 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
946 loop_through = 0x00; /* r5[7], lt on */
947 lt_att = 0x00; /* r31[7], lt att enable */
948 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
949 polyfil_cur = 0x60; /* r25[6:5]:min */
950 } else {
951 if_khz = 4570;
952 filt_cal_lo = 68500;
953 filt_gain = 0x10; /* +3db, 6mhz on */
954 img_r = 0x00; /* image negative */
955 filt_q = 0x10; /* r10[4]:low q(1'b1) */
956 hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */
957 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
958 loop_through = 0x00; /* r5[7], lt on */
959 lt_att = 0x00; /* r31[7], lt att enable */
960 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
961 polyfil_cur = 0x60; /* r25[6:5]:min */
962 }
963 }
964
965 /* Initialize the shadow registers */
966 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
967
968 /* Init Flag & Xtal_check Result */
969 if (priv->imr_done)
970 val = 1 | priv->xtal_cap_sel << 1;
971 else
972 val = 0;
973 rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f);
974 if (rc < 0)
975 return rc;
976
977 /* version */
978 rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f);
979 if (rc < 0)
980 return rc;
981
982 /* for LT Gain test */
983 if (type != V4L2_TUNER_ANALOG_TV) {
984 rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38);
985 if (rc < 0)
986 return rc;
987 msleep(1);
988 }
989 priv->int_freq = if_khz * 1000;
990
991 /* Check if standard changed. If so, filter calibration is needed */
992 if (type != priv->type)
993 need_calibration = true;
994 else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std))
995 need_calibration = true;
996 else if ((type == V4L2_TUNER_DIGITAL_TV) &&
997 ((delsys != priv->delsys) || bw != priv->bw))
998 need_calibration = true;
999 else
1000 need_calibration = false;
1001
1002 if (need_calibration) {
1003 tuner_dbg("calibrating the tuner\n");
1004 for (i = 0; i < 2; i++) {
1005 /* Set filt_cap */
1006 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60);
1007 if (rc < 0)
1008 return rc;
1009
1010 /* set cali clk =on */
1011 rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04);
1012 if (rc < 0)
1013 return rc;
1014
1015 /* X'tal cap 0pF for PLL */
1016 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03);
1017 if (rc < 0)
1018 return rc;
1019
1020 rc = r820t_set_pll(priv, filt_cal_lo);
1021 if (rc < 0 || !priv->has_lock)
1022 return rc;
1023
1024 /* Start Trigger */
1025 rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10);
1026 if (rc < 0)
1027 return rc;
1028
1029 msleep(1);
1030
1031 /* Stop Trigger */
1032 rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10);
1033 if (rc < 0)
1034 return rc;
1035
1036 /* set cali clk =off */
1037 rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04);
1038 if (rc < 0)
1039 return rc;
1040
1041 /* Check if calibration worked */
1042 rc = r820_read(priv, 0x00, data, sizeof(data));
1043 if (rc < 0)
1044 return rc;
1045
1046 priv->fil_cal_code = data[4] & 0x0f;
1047 if (priv->fil_cal_code && priv->fil_cal_code != 0x0f)
1048 break;
1049 }
1050 /* narrowest */
1051 if (priv->fil_cal_code == 0x0f)
1052 priv->fil_cal_code = 0;
1053 }
1054
1055 rc = r820t_write_reg_mask(priv, 0x0a,
1056 filt_q | priv->fil_cal_code, 0x1f);
1057 if (rc < 0)
1058 return rc;
1059
1060 /* Set BW, Filter_gain, & HP corner */
1061 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x10);
1062 if (rc < 0)
1063 return rc;
1064
1065
1066 /* Set Img_R */
1067 rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80);
1068 if (rc < 0)
1069 return rc;
1070
1071 /* Set filt_3dB, V6MHz */
1072 rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30);
1073 if (rc < 0)
1074 return rc;
1075
1076 /* channel filter extension */
1077 rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60);
1078 if (rc < 0)
1079 return rc;
1080
1081 /* Loop through */
1082 rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80);
1083 if (rc < 0)
1084 return rc;
1085
1086 /* Loop through attenuation */
1087 rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80);
1088 if (rc < 0)
1089 return rc;
1090
1091 /* filter extension widest */
1092 rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80);
1093 if (rc < 0)
1094 return rc;
1095
1096 /* RF poly filter current */
1097 rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60);
1098 if (rc < 0)
1099 return rc;
1100
1101 /* Store current standard. If it changes, re-calibrate the tuner */
1102 priv->delsys = delsys;
1103 priv->type = type;
1104 priv->std = std;
1105 priv->bw = bw;
1106
1107 return 0;
1108 }
1109
1110 static int r820t_read_gain(struct r820t_priv *priv)
1111 {
1112 u8 data[4];
1113 int rc;
1114
1115 rc = r820_read(priv, 0x00, data, sizeof(data));
1116 if (rc < 0)
1117 return rc;
1118
1119 return ((data[3] & 0x0f) << 1) + ((data[3] & 0xf0) >> 4);
1120 }
1121
1122 static int r820t_set_gain_mode(struct r820t_priv *priv,
1123 bool set_manual_gain,
1124 int gain)
1125 {
1126 int rc;
1127
1128 if (set_manual_gain) {
1129 int i, total_gain = 0;
1130 uint8_t mix_index = 0, lna_index = 0;
1131 u8 data[4];
1132
1133 /* LNA auto off */
1134 rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10);
1135 if (rc < 0)
1136 return rc;
1137
1138 /* Mixer auto off */
1139 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1140 if (rc < 0)
1141 return rc;
1142
1143 rc = r820_read(priv, 0x00, data, sizeof(data));
1144 if (rc < 0)
1145 return rc;
1146
1147 /* set fixed VGA gain for now (16.3 dB) */
1148 rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f);
1149 if (rc < 0)
1150 return rc;
1151
1152 for (i = 0; i < 15; i++) {
1153 if (total_gain >= gain)
1154 break;
1155
1156 total_gain += r820t_lna_gain_steps[++lna_index];
1157
1158 if (total_gain >= gain)
1159 break;
1160
1161 total_gain += r820t_mixer_gain_steps[++mix_index];
1162 }
1163
1164 /* set LNA gain */
1165 rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f);
1166 if (rc < 0)
1167 return rc;
1168
1169 /* set Mixer gain */
1170 rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f);
1171 if (rc < 0)
1172 return rc;
1173 } else {
1174 /* LNA */
1175 rc = r820t_write_reg_mask(priv, 0x05, 0, 0xef);
1176 if (rc < 0)
1177 return rc;
1178
1179 /* Mixer */
1180 rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0xef);
1181 if (rc < 0)
1182 return rc;
1183
1184 /* set fixed VGA gain for now (26.5 dB) */
1185 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1186 if (rc < 0)
1187 return rc;
1188 }
1189
1190 return 0;
1191 }
1192
1193
1194 static int generic_set_freq(struct dvb_frontend *fe,
1195 u32 freq /* in HZ */,
1196 unsigned bw,
1197 enum v4l2_tuner_type type,
1198 v4l2_std_id std, u32 delsys)
1199 {
1200 struct r820t_priv *priv = fe->tuner_priv;
1201 int rc = -EINVAL;
1202 u32 lo_freq;
1203
1204 tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
1205 freq / 1000, bw);
1206
1207 rc = r820t_set_tv_standard(priv, bw, type, std, delsys);
1208 if (rc < 0)
1209 goto err;
1210
1211 if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC))
1212 lo_freq = freq - priv->int_freq;
1213 else
1214 lo_freq = freq + priv->int_freq;
1215
1216 rc = r820t_set_mux(priv, lo_freq);
1217 if (rc < 0)
1218 goto err;
1219
1220 rc = r820t_set_gain_mode(priv, true, 0);
1221 if (rc < 0)
1222 goto err;
1223
1224 rc = r820t_set_pll(priv, lo_freq);
1225 if (rc < 0 || !priv->has_lock)
1226 goto err;
1227
1228 rc = r820t_sysfreq_sel(priv, freq, type, std, delsys);
1229 if (rc < 0)
1230 goto err;
1231
1232 tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
1233 __func__, freq, r820t_read_gain(priv));
1234
1235 err:
1236
1237 if (rc < 0)
1238 tuner_dbg("%s: failed=%d\n", __func__, rc);
1239 return rc;
1240 }
1241
1242 /*
1243 * r820t standby logic
1244 */
1245
1246 static int r820t_standby(struct r820t_priv *priv)
1247 {
1248 int rc;
1249
1250 rc = r820t_write_reg(priv, 0x06, 0xb1);
1251 if (rc < 0)
1252 return rc;
1253 rc = r820t_write_reg(priv, 0x05, 0x03);
1254 if (rc < 0)
1255 return rc;
1256 rc = r820t_write_reg(priv, 0x07, 0x3a);
1257 if (rc < 0)
1258 return rc;
1259 rc = r820t_write_reg(priv, 0x08, 0x40);
1260 if (rc < 0)
1261 return rc;
1262 rc = r820t_write_reg(priv, 0x09, 0xc0);
1263 if (rc < 0)
1264 return rc;
1265 rc = r820t_write_reg(priv, 0x0a, 0x36);
1266 if (rc < 0)
1267 return rc;
1268 rc = r820t_write_reg(priv, 0x0c, 0x35);
1269 if (rc < 0)
1270 return rc;
1271 rc = r820t_write_reg(priv, 0x0f, 0x68);
1272 if (rc < 0)
1273 return rc;
1274 rc = r820t_write_reg(priv, 0x11, 0x03);
1275 if (rc < 0)
1276 return rc;
1277 rc = r820t_write_reg(priv, 0x17, 0xf4);
1278 if (rc < 0)
1279 return rc;
1280 rc = r820t_write_reg(priv, 0x19, 0x0c);
1281
1282 /* Force initial calibration */
1283 priv->type = -1;
1284
1285 return rc;
1286 }
1287
1288 /*
1289 * r820t device init logic
1290 */
1291
1292 static int r820t_xtal_check(struct r820t_priv *priv)
1293 {
1294 int rc, i;
1295 u8 data[3], val;
1296
1297 /* Initialize the shadow registers */
1298 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1299
1300 /* cap 30pF & Drive Low */
1301 rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b);
1302 if (rc < 0)
1303 return rc;
1304
1305 /* set pll autotune = 128kHz */
1306 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
1307 if (rc < 0)
1308 return rc;
1309
1310 /* set manual initial reg = 111111; */
1311 rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f);
1312 if (rc < 0)
1313 return rc;
1314
1315 /* set auto */
1316 rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40);
1317 if (rc < 0)
1318 return rc;
1319
1320 /* Try several xtal capacitor alternatives */
1321 for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) {
1322 rc = r820t_write_reg_mask(priv, 0x10,
1323 r820t_xtal_capacitor[i][0], 0x1b);
1324 if (rc < 0)
1325 return rc;
1326
1327 msleep(5);
1328
1329 rc = r820_read(priv, 0x00, data, sizeof(data));
1330 if (rc < 0)
1331 return rc;
1332 if ((!data[2]) & 0x40)
1333 continue;
1334
1335 val = data[2] & 0x3f;
1336
1337 if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23))
1338 break;
1339
1340 if (val != 0x3f)
1341 break;
1342 }
1343
1344 if (i == ARRAY_SIZE(r820t_xtal_capacitor))
1345 return -EINVAL;
1346
1347 return r820t_xtal_capacitor[i][1];
1348 }
1349
1350 /*
1351 * r820t frontend operations and tuner attach code
1352 *
1353 * All driver locks and i2c control are only in this part of the code
1354 */
1355
1356 static int r820t_init(struct dvb_frontend *fe)
1357 {
1358 struct r820t_priv *priv = fe->tuner_priv;
1359 int rc, i;
1360 int xtal_cap = 0;
1361
1362 tuner_dbg("%s:\n", __func__);
1363
1364 mutex_lock(&priv->lock);
1365 if (fe->ops.i2c_gate_ctrl)
1366 fe->ops.i2c_gate_ctrl(fe, 1);
1367
1368 if ((priv->cfg->rafael_chip == CHIP_R820T) ||
1369 (priv->cfg->rafael_chip == CHIP_R828S) ||
1370 (priv->cfg->rafael_chip == CHIP_R820C)) {
1371 priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
1372 } else {
1373 for (i = 0; i < 3; i++) {
1374 rc = r820t_xtal_check(priv);
1375 if (rc < 0)
1376 goto err;
1377 if (!i || rc > xtal_cap)
1378 xtal_cap = rc;
1379 }
1380 priv->xtal_cap_sel = xtal_cap;
1381 }
1382
1383 /* Initialize registers */
1384 rc = r820t_write(priv, 0x05,
1385 r820t_init_array, sizeof(r820t_init_array));
1386
1387 err:
1388 if (fe->ops.i2c_gate_ctrl)
1389 fe->ops.i2c_gate_ctrl(fe, 0);
1390 mutex_unlock(&priv->lock);
1391
1392 if (rc < 0)
1393 tuner_dbg("%s: failed=%d\n", __func__, rc);
1394 return rc;
1395 }
1396
1397 static int r820t_sleep(struct dvb_frontend *fe)
1398 {
1399 struct r820t_priv *priv = fe->tuner_priv;
1400 int rc;
1401
1402 tuner_dbg("%s:\n", __func__);
1403
1404 mutex_lock(&priv->lock);
1405 if (fe->ops.i2c_gate_ctrl)
1406 fe->ops.i2c_gate_ctrl(fe, 1);
1407
1408 rc = r820t_standby(priv);
1409
1410 if (fe->ops.i2c_gate_ctrl)
1411 fe->ops.i2c_gate_ctrl(fe, 0);
1412 mutex_unlock(&priv->lock);
1413
1414 tuner_dbg("%s: failed=%d\n", __func__, rc);
1415 return rc;
1416 }
1417
1418 static int r820t_set_analog_freq(struct dvb_frontend *fe,
1419 struct analog_parameters *p)
1420 {
1421 struct r820t_priv *priv = fe->tuner_priv;
1422 unsigned bw;
1423 int rc;
1424
1425 tuner_dbg("%s called\n", __func__);
1426
1427 /* if std is not defined, choose one */
1428 if (!p->std)
1429 p->std = V4L2_STD_MN;
1430
1431 if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC))
1432 bw = 6;
1433 else
1434 bw = 8;
1435
1436 mutex_lock(&priv->lock);
1437 if (fe->ops.i2c_gate_ctrl)
1438 fe->ops.i2c_gate_ctrl(fe, 1);
1439
1440 rc = generic_set_freq(fe, 62500l * p->frequency, bw,
1441 V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED);
1442
1443 if (fe->ops.i2c_gate_ctrl)
1444 fe->ops.i2c_gate_ctrl(fe, 0);
1445 mutex_unlock(&priv->lock);
1446
1447 return rc;
1448 }
1449
1450 static int r820t_set_params(struct dvb_frontend *fe)
1451 {
1452 struct r820t_priv *priv = fe->tuner_priv;
1453 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1454 int rc;
1455 unsigned bw;
1456
1457 tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
1458 __func__, c->delivery_system, c->frequency, c->bandwidth_hz);
1459
1460 mutex_lock(&priv->lock);
1461 if (fe->ops.i2c_gate_ctrl)
1462 fe->ops.i2c_gate_ctrl(fe, 1);
1463
1464 bw = (c->bandwidth_hz + 500000) / 1000000;
1465 if (!bw)
1466 bw = 8;
1467
1468 rc = generic_set_freq(fe, c->frequency, bw,
1469 V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system);
1470
1471 if (fe->ops.i2c_gate_ctrl)
1472 fe->ops.i2c_gate_ctrl(fe, 0);
1473 mutex_unlock(&priv->lock);
1474
1475 if (rc)
1476 tuner_dbg("%s: failed=%d\n", __func__, rc);
1477 return rc;
1478 }
1479
1480 static int r820t_signal(struct dvb_frontend *fe, u16 *strength)
1481 {
1482 struct r820t_priv *priv = fe->tuner_priv;
1483 int rc = 0;
1484
1485 mutex_lock(&priv->lock);
1486 if (fe->ops.i2c_gate_ctrl)
1487 fe->ops.i2c_gate_ctrl(fe, 1);
1488
1489 if (priv->has_lock) {
1490 rc = r820t_read_gain(priv);
1491 if (rc < 0)
1492 goto err;
1493
1494 /* A higher gain at LNA means a lower signal strength */
1495 *strength = (45 - rc) << 4 | 0xff;
1496 } else {
1497 *strength = 0;
1498 }
1499
1500 err:
1501 if (fe->ops.i2c_gate_ctrl)
1502 fe->ops.i2c_gate_ctrl(fe, 0);
1503 mutex_unlock(&priv->lock);
1504
1505 tuner_dbg("%s: %s, gain=%d strength=%d\n",
1506 __func__,
1507 priv->has_lock ? "PLL locked" : "no signal",
1508 rc, *strength);
1509
1510 return 0;
1511 }
1512
1513 static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
1514 {
1515 struct r820t_priv *priv = fe->tuner_priv;
1516
1517 tuner_dbg("%s:\n", __func__);
1518
1519 *frequency = priv->int_freq;
1520
1521 return 0;
1522 }
1523
1524 static int r820t_release(struct dvb_frontend *fe)
1525 {
1526 struct r820t_priv *priv = fe->tuner_priv;
1527
1528 tuner_dbg("%s:\n", __func__);
1529
1530 mutex_lock(&r820t_list_mutex);
1531
1532 if (priv)
1533 hybrid_tuner_release_state(priv);
1534
1535 mutex_unlock(&r820t_list_mutex);
1536
1537 fe->tuner_priv = NULL;
1538
1539 kfree(fe->tuner_priv);
1540
1541 return 0;
1542 }
1543
1544 static const struct dvb_tuner_ops r820t_tuner_ops = {
1545 .info = {
1546 .name = "Rafael Micro R820T",
1547 .frequency_min = 42000000,
1548 .frequency_max = 1002000000,
1549 },
1550 .init = r820t_init,
1551 .release = r820t_release,
1552 .sleep = r820t_sleep,
1553 .set_params = r820t_set_params,
1554 .set_analog_params = r820t_set_analog_freq,
1555 .get_if_frequency = r820t_get_if_frequency,
1556 .get_rf_strength = r820t_signal,
1557 };
1558
1559 struct dvb_frontend *r820t_attach(struct dvb_frontend *fe,
1560 struct i2c_adapter *i2c,
1561 const struct r820t_config *cfg)
1562 {
1563 struct r820t_priv *priv;
1564 int rc = -ENODEV;
1565 u8 data[5];
1566 int instance;
1567
1568 mutex_lock(&r820t_list_mutex);
1569
1570 instance = hybrid_tuner_request_state(struct r820t_priv, priv,
1571 hybrid_tuner_instance_list,
1572 i2c, cfg->i2c_addr,
1573 "r820t");
1574 switch (instance) {
1575 case 0:
1576 /* memory allocation failure */
1577 goto err_no_gate;
1578 break;
1579 case 1:
1580 /* new tuner instance */
1581 priv->cfg = cfg;
1582
1583 mutex_init(&priv->lock);
1584
1585 fe->tuner_priv = priv;
1586 break;
1587 case 2:
1588 /* existing tuner instance */
1589 fe->tuner_priv = priv;
1590 break;
1591 }
1592
1593 memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops, sizeof(r820t_tuner_ops));
1594
1595 if (fe->ops.i2c_gate_ctrl)
1596 fe->ops.i2c_gate_ctrl(fe, 1);
1597
1598 /* check if the tuner is there */
1599 rc = r820_read(priv, 0x00, data, sizeof(data));
1600 if (rc < 0)
1601 goto err;
1602
1603 rc = r820t_sleep(fe);
1604 if (rc < 0)
1605 goto err;
1606
1607 tuner_info("Rafael Micro r820t successfully identified\n");
1608
1609 fe->tuner_priv = priv;
1610 memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops,
1611 sizeof(struct dvb_tuner_ops));
1612
1613 if (fe->ops.i2c_gate_ctrl)
1614 fe->ops.i2c_gate_ctrl(fe, 0);
1615
1616 mutex_unlock(&r820t_list_mutex);
1617
1618 return fe;
1619 err:
1620 if (fe->ops.i2c_gate_ctrl)
1621 fe->ops.i2c_gate_ctrl(fe, 0);
1622
1623 err_no_gate:
1624 mutex_unlock(&r820t_list_mutex);
1625
1626 tuner_info("%s: failed=%d\n", __func__, rc);
1627 r820t_release(fe);
1628 return NULL;
1629 }
1630 EXPORT_SYMBOL_GPL(r820t_attach);
1631
1632 MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
1633 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1634 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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