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[media] r820t: split the function that read cached regs
[deliverable/linux.git] / drivers / media / tuners / r820t.c
1 /*
2 * Rafael Micro R820T driver
3 *
4 * Copyright (C) 2013 Mauro Carvalho Chehab <mchehab@redhat.com>
5 *
6 * This driver was written from scratch, based on an existing driver
7 * that it is part of rtl-sdr git tree, released under GPLv2:
8 * https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug
9 * https://github.com/n1gp/gr-baz
10 *
11 * From what I understood from the threads, the original driver was converted
12 * to userspace from a Realtek tree. I couldn't find the original tree.
13 * However, the original driver look awkward on my eyes. So, I decided to
14 * write a new version from it from the scratch, while trying to reproduce
15 * everything found there.
16 *
17 * TODO:
18 * After locking, the original driver seems to have some routines to
19 * improve reception. This was not implemented here yet.
20 *
21 * RF Gain set/get is not implemented.
22 *
23 * This program is free software; you can redistribute it and/or modify
24 * it under the terms of the GNU General Public License as published by
25 * the Free Software Foundation; either version 2 of the License, or
26 * (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 */
34
35 #include <linux/videodev2.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/bitrev.h>
39 #include <asm/div64.h>
40
41 #include "tuner-i2c.h"
42 #include "r820t.h"
43
44 /*
45 * FIXME: I think that there are only 32 registers, but better safe than
46 * sorry. After finishing the driver, we may review it.
47 */
48 #define REG_SHADOW_START 5
49 #define NUM_REGS 27
50
51 #define VER_NUM 49
52
53 static int debug;
54 module_param(debug, int, 0644);
55 MODULE_PARM_DESC(debug, "enable verbose debug messages");
56
57 /*
58 * enums and structures
59 */
60
61 enum xtal_cap_value {
62 XTAL_LOW_CAP_30P = 0,
63 XTAL_LOW_CAP_20P,
64 XTAL_LOW_CAP_10P,
65 XTAL_LOW_CAP_0P,
66 XTAL_HIGH_CAP_0P
67 };
68
69 struct r820t_priv {
70 struct list_head hybrid_tuner_instance_list;
71 const struct r820t_config *cfg;
72 struct tuner_i2c_props i2c_props;
73 struct mutex lock;
74
75 u8 regs[NUM_REGS];
76 u8 buf[NUM_REGS + 1];
77 enum xtal_cap_value xtal_cap_sel;
78 u16 pll; /* kHz */
79 u32 int_freq;
80 u8 fil_cal_code;
81 bool imr_done;
82
83 /* Store current mode */
84 u32 delsys;
85 enum v4l2_tuner_type type;
86 v4l2_std_id std;
87 u32 bw; /* in MHz */
88
89 bool has_lock;
90 };
91
92 struct r820t_freq_range {
93 u32 freq;
94 u8 open_d;
95 u8 rf_mux_ploy;
96 u8 tf_c;
97 u8 xtal_cap20p;
98 u8 xtal_cap10p;
99 u8 xtal_cap0p;
100 u8 imr_mem; /* Not used, currently */
101 };
102
103 #define VCO_POWER_REF 0x02
104 #define DIP_FREQ 32000000
105
106 /*
107 * Static constants
108 */
109
110 static LIST_HEAD(hybrid_tuner_instance_list);
111 static DEFINE_MUTEX(r820t_list_mutex);
112
113 /* Those initial values start from REG_SHADOW_START */
114 static const u8 r820t_init_array[NUM_REGS] = {
115 0x83, 0x32, 0x75, /* 05 to 07 */
116 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */
117 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */
118 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */
119 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */
120 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */
121 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */
122 };
123
124 /* Tuner frequency ranges */
125 static const struct r820t_freq_range freq_ranges[] = {
126 {
127 .freq = 0,
128 .open_d = 0x08, /* low */
129 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
130 .tf_c = 0xdf, /* R27[7:0] band2,band0 */
131 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
132 .xtal_cap10p = 0x01,
133 .xtal_cap0p = 0x00,
134 .imr_mem = 0,
135 }, {
136 .freq = 50, /* Start freq, in MHz */
137 .open_d = 0x08, /* low */
138 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
139 .tf_c = 0xbe, /* R27[7:0] band4,band1 */
140 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
141 .xtal_cap10p = 0x01,
142 .xtal_cap0p = 0x00,
143 .imr_mem = 0,
144 }, {
145 .freq = 55, /* Start freq, in MHz */
146 .open_d = 0x08, /* low */
147 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
148 .tf_c = 0x8b, /* R27[7:0] band7,band4 */
149 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
150 .xtal_cap10p = 0x01,
151 .xtal_cap0p = 0x00,
152 .imr_mem = 0,
153 }, {
154 .freq = 60, /* Start freq, in MHz */
155 .open_d = 0x08, /* low */
156 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
157 .tf_c = 0x7b, /* R27[7:0] band8,band4 */
158 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
159 .xtal_cap10p = 0x01,
160 .xtal_cap0p = 0x00,
161 .imr_mem = 0,
162 }, {
163 .freq = 65, /* Start freq, in MHz */
164 .open_d = 0x08, /* low */
165 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
166 .tf_c = 0x69, /* R27[7:0] band9,band6 */
167 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
168 .xtal_cap10p = 0x01,
169 .xtal_cap0p = 0x00,
170 .imr_mem = 0,
171 }, {
172 .freq = 70, /* Start freq, in MHz */
173 .open_d = 0x08, /* low */
174 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
175 .tf_c = 0x58, /* R27[7:0] band10,band7 */
176 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
177 .xtal_cap10p = 0x01,
178 .xtal_cap0p = 0x00,
179 .imr_mem = 0,
180 }, {
181 .freq = 75, /* Start freq, in MHz */
182 .open_d = 0x00, /* high */
183 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
184 .tf_c = 0x44, /* R27[7:0] band11,band11 */
185 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
186 .xtal_cap10p = 0x01,
187 .xtal_cap0p = 0x00,
188 .imr_mem = 0,
189 }, {
190 .freq = 80, /* Start freq, in MHz */
191 .open_d = 0x00, /* high */
192 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
193 .tf_c = 0x44, /* R27[7:0] band11,band11 */
194 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
195 .xtal_cap10p = 0x01,
196 .xtal_cap0p = 0x00,
197 .imr_mem = 0,
198 }, {
199 .freq = 90, /* Start freq, in MHz */
200 .open_d = 0x00, /* high */
201 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
202 .tf_c = 0x34, /* R27[7:0] band12,band11 */
203 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
204 .xtal_cap10p = 0x01,
205 .xtal_cap0p = 0x00,
206 .imr_mem = 0,
207 }, {
208 .freq = 100, /* Start freq, in MHz */
209 .open_d = 0x00, /* high */
210 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
211 .tf_c = 0x34, /* R27[7:0] band12,band11 */
212 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
213 .xtal_cap10p = 0x01,
214 .xtal_cap0p = 0x00,
215 .imr_mem = 0,
216 }, {
217 .freq = 110, /* Start freq, in MHz */
218 .open_d = 0x00, /* high */
219 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
220 .tf_c = 0x24, /* R27[7:0] band13,band11 */
221 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
222 .xtal_cap10p = 0x01,
223 .xtal_cap0p = 0x00,
224 .imr_mem = 1,
225 }, {
226 .freq = 120, /* Start freq, in MHz */
227 .open_d = 0x00, /* high */
228 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
229 .tf_c = 0x24, /* R27[7:0] band13,band11 */
230 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
231 .xtal_cap10p = 0x01,
232 .xtal_cap0p = 0x00,
233 .imr_mem = 1,
234 }, {
235 .freq = 140, /* Start freq, in MHz */
236 .open_d = 0x00, /* high */
237 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
238 .tf_c = 0x14, /* R27[7:0] band14,band11 */
239 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
240 .xtal_cap10p = 0x01,
241 .xtal_cap0p = 0x00,
242 .imr_mem = 1,
243 }, {
244 .freq = 180, /* Start freq, in MHz */
245 .open_d = 0x00, /* high */
246 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
247 .tf_c = 0x13, /* R27[7:0] band14,band12 */
248 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
249 .xtal_cap10p = 0x00,
250 .xtal_cap0p = 0x00,
251 .imr_mem = 1,
252 }, {
253 .freq = 220, /* Start freq, in MHz */
254 .open_d = 0x00, /* high */
255 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
256 .tf_c = 0x13, /* R27[7:0] band14,band12 */
257 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
258 .xtal_cap10p = 0x00,
259 .xtal_cap0p = 0x00,
260 .imr_mem = 2,
261 }, {
262 .freq = 250, /* Start freq, in MHz */
263 .open_d = 0x00, /* high */
264 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
265 .tf_c = 0x11, /* R27[7:0] highest,highest */
266 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
267 .xtal_cap10p = 0x00,
268 .xtal_cap0p = 0x00,
269 .imr_mem = 2,
270 }, {
271 .freq = 280, /* Start freq, in MHz */
272 .open_d = 0x00, /* high */
273 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
274 .tf_c = 0x00, /* R27[7:0] highest,highest */
275 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
276 .xtal_cap10p = 0x00,
277 .xtal_cap0p = 0x00,
278 .imr_mem = 2,
279 }, {
280 .freq = 310, /* Start freq, in MHz */
281 .open_d = 0x00, /* high */
282 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
283 .tf_c = 0x00, /* R27[7:0] highest,highest */
284 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
285 .xtal_cap10p = 0x00,
286 .xtal_cap0p = 0x00,
287 .imr_mem = 2,
288 }, {
289 .freq = 450, /* Start freq, in MHz */
290 .open_d = 0x00, /* high */
291 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
292 .tf_c = 0x00, /* R27[7:0] highest,highest */
293 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
294 .xtal_cap10p = 0x00,
295 .xtal_cap0p = 0x00,
296 .imr_mem = 3,
297 }, {
298 .freq = 588, /* Start freq, in MHz */
299 .open_d = 0x00, /* high */
300 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
301 .tf_c = 0x00, /* R27[7:0] highest,highest */
302 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
303 .xtal_cap10p = 0x00,
304 .xtal_cap0p = 0x00,
305 .imr_mem = 3,
306 }, {
307 .freq = 650, /* Start freq, in MHz */
308 .open_d = 0x00, /* high */
309 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
310 .tf_c = 0x00, /* R27[7:0] highest,highest */
311 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
312 .xtal_cap10p = 0x00,
313 .xtal_cap0p = 0x00,
314 .imr_mem = 4,
315 }
316 };
317
318 static int r820t_xtal_capacitor[][2] = {
319 { 0x0b, XTAL_LOW_CAP_30P },
320 { 0x02, XTAL_LOW_CAP_20P },
321 { 0x01, XTAL_LOW_CAP_10P },
322 { 0x00, XTAL_LOW_CAP_0P },
323 { 0x10, XTAL_HIGH_CAP_0P },
324 };
325
326 /*
327 * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
328 * input power, for raw results see:
329 * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
330 */
331
332 static const int r820t_lna_gain_steps[] = {
333 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
334 };
335
336 static const int r820t_mixer_gain_steps[] = {
337 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
338 };
339
340 /*
341 * I2C read/write code and shadow registers logic
342 */
343 static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val,
344 int len)
345 {
346 int r = reg - REG_SHADOW_START;
347
348 if (r < 0) {
349 len += r;
350 r = 0;
351 }
352 if (len <= 0)
353 return;
354 if (len > NUM_REGS)
355 len = NUM_REGS;
356
357 tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n",
358 __func__, r + REG_SHADOW_START, len, len, val);
359
360 memcpy(&priv->regs[r], val, len);
361 }
362
363 static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val,
364 int len)
365 {
366 int rc, size, pos = 0;
367
368 /* Store the shadow registers */
369 shadow_store(priv, reg, val, len);
370
371 do {
372 if (len > priv->cfg->max_i2c_msg_len - 1)
373 size = priv->cfg->max_i2c_msg_len - 1;
374 else
375 size = len;
376
377 /* Fill I2C buffer */
378 priv->buf[0] = reg;
379 memcpy(&priv->buf[1], &val[pos], size);
380
381 rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1);
382 if (rc != size + 1) {
383 tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
384 __func__, rc, reg, size, size, &priv->buf[1]);
385 if (rc < 0)
386 return rc;
387 return -EREMOTEIO;
388 }
389 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
390 __func__, reg, size, size, &priv->buf[1]);
391
392 reg += size;
393 len -= size;
394 pos += size;
395 } while (len > 0);
396
397 return 0;
398 }
399
400 static int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val)
401 {
402 return r820t_write(priv, reg, &val, 1);
403 }
404
405 static int r820t_read_cache_reg(struct r820t_priv *priv, int reg)
406 {
407 reg -= REG_SHADOW_START;
408
409 if (reg >= 0 && reg < NUM_REGS)
410 return priv->regs[reg];
411 else
412 return -EINVAL;
413 }
414
415 static int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val,
416 u8 bit_mask)
417 {
418 int rc = r820t_read_cache_reg(priv, reg);
419
420 if (rc < 0)
421 return rc;
422
423 val = (rc & ~bit_mask) | (val & bit_mask);
424
425 return r820t_write(priv, reg, &val, 1);
426 }
427
428 static int r820_read(struct r820t_priv *priv, u8 reg, u8 *val, int len)
429 {
430 int rc, i;
431 u8 *p = &priv->buf[1];
432
433 priv->buf[0] = reg;
434
435 rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len);
436 if (rc != len) {
437 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
438 __func__, rc, reg, len, len, p);
439 if (rc < 0)
440 return rc;
441 return -EREMOTEIO;
442 }
443
444 /* Copy data to the output buffer */
445 for (i = 0; i < len; i++)
446 val[i] = bitrev8(p[i]);
447
448 tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
449 __func__, reg, len, len, val);
450
451 return 0;
452 }
453
454 /*
455 * r820t tuning logic
456 */
457
458 static int r820t_set_mux(struct r820t_priv *priv, u32 freq)
459 {
460 const struct r820t_freq_range *range;
461 int i, rc;
462 u8 val;
463
464 /* Get the proper frequency range */
465 freq = freq / 1000000;
466 for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) {
467 if (freq < freq_ranges[i + 1].freq)
468 break;
469 }
470 range = &freq_ranges[i];
471
472 tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq);
473
474 /* Open Drain */
475 rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08);
476 if (rc < 0)
477 return rc;
478
479 /* RF_MUX,Polymux */
480 rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3);
481 if (rc < 0)
482 return rc;
483
484 /* TF BAND */
485 rc = r820t_write_reg(priv, 0x1b, range->tf_c);
486 if (rc < 0)
487 return rc;
488
489 /* XTAL CAP & Drive */
490 switch (priv->xtal_cap_sel) {
491 case XTAL_LOW_CAP_30P:
492 case XTAL_LOW_CAP_20P:
493 val = range->xtal_cap20p | 0x08;
494 break;
495 case XTAL_LOW_CAP_10P:
496 val = range->xtal_cap10p | 0x08;
497 break;
498 case XTAL_HIGH_CAP_0P:
499 val = range->xtal_cap0p | 0x00;
500 break;
501 default:
502 case XTAL_LOW_CAP_0P:
503 val = range->xtal_cap0p | 0x08;
504 break;
505 }
506 rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b);
507 if (rc < 0)
508 return rc;
509
510 /*
511 * FIXME: the original driver has a logic there with preserves
512 * gain/phase from registers 8 and 9 reading the data from the
513 * registers before writing, if "IMF done". That code was sort of
514 * commented there, as the flag is always false.
515 */
516 rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);
517 if (rc < 0)
518 return rc;
519
520 rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);
521
522 return rc;
523 }
524
525 static int r820t_set_pll(struct r820t_priv *priv, u32 freq)
526 {
527 u64 tmp64, vco_freq;
528 int rc, i;
529 u32 vco_fra; /* VCO contribution by SDM (kHz) */
530 u32 vco_min = 1770000;
531 u32 vco_max = vco_min * 2;
532 u32 pll_ref;
533 u16 n_sdm = 2;
534 u16 sdm = 0;
535 u8 mix_div = 2;
536 u8 div_buf = 0;
537 u8 div_num = 0;
538 u8 ni, si, nint, vco_fine_tune, val;
539 u8 data[5];
540
541 freq = freq / 1000; /* Frequency in kHz */
542
543 pll_ref = priv->cfg->xtal / 1000;
544
545 tuner_dbg("set r820t pll for frequency %d kHz = %d\n", freq, pll_ref);
546
547 /* FIXME: this seems to be a hack - probably it can be removed */
548 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x00);
549 if (rc < 0)
550 return rc;
551
552 /* set pll autotune = 128kHz */
553 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
554 if (rc < 0)
555 return rc;
556
557 /* set VCO current = 100 */
558 rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0);
559 if (rc < 0)
560 return rc;
561
562 /* Calculate divider */
563 while (mix_div <= 64) {
564 if (((freq * mix_div) >= vco_min) &&
565 ((freq * mix_div) < vco_max)) {
566 div_buf = mix_div;
567 while (div_buf > 2) {
568 div_buf = div_buf >> 1;
569 div_num++;
570 }
571 break;
572 }
573 mix_div = mix_div << 1;
574 }
575
576 rc = r820_read(priv, 0x00, data, sizeof(data));
577 if (rc < 0)
578 return rc;
579
580 vco_fine_tune = (data[4] & 0x30) >> 4;
581
582 if (vco_fine_tune > VCO_POWER_REF)
583 div_num = div_num - 1;
584 else if (vco_fine_tune < VCO_POWER_REF)
585 div_num = div_num + 1;
586
587 rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0);
588 if (rc < 0)
589 return rc;
590
591 vco_freq = (u64)(freq * (u64)mix_div);
592
593 tmp64 = vco_freq;
594 do_div(tmp64, 2 * pll_ref);
595 nint = (u8)tmp64;
596
597 tmp64 = vco_freq - ((u64)2) * pll_ref * nint;
598 do_div(tmp64, 1000);
599 vco_fra = (u16)(tmp64);
600
601 pll_ref /= 1000;
602
603 /* boundary spur prevention */
604 if (vco_fra < pll_ref / 64) {
605 vco_fra = 0;
606 } else if (vco_fra > pll_ref * 127 / 64) {
607 vco_fra = 0;
608 nint++;
609 } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) {
610 vco_fra = pll_ref * 127 / 128;
611 } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) {
612 vco_fra = pll_ref * 129 / 128;
613 }
614
615 if (nint > 63) {
616 tuner_info("No valid PLL values for %u kHz!\n", freq);
617 return -EINVAL;
618 }
619
620 ni = (nint - 13) / 4;
621 si = nint - 4 * ni - 13;
622
623 rc = r820t_write_reg(priv, 0x14, ni + (si << 6));
624 if (rc < 0)
625 return rc;
626
627 /* pw_sdm */
628 if (!vco_fra)
629 val = 0x08;
630 else
631 val = 0x00;
632
633 rc = r820t_write_reg_mask(priv, 0x12, val, 0x08);
634 if (rc < 0)
635 return rc;
636
637 /* sdm calculator */
638 while (vco_fra > 1) {
639 if (vco_fra > (2 * pll_ref / n_sdm)) {
640 sdm = sdm + 32768 / (n_sdm / 2);
641 vco_fra = vco_fra - 2 * pll_ref / n_sdm;
642 if (n_sdm >= 0x8000)
643 break;
644 }
645 n_sdm = n_sdm << 1;
646 }
647
648 rc = r820t_write_reg_mask(priv, 0x16, sdm >> 8, 0x08);
649 if (rc < 0)
650 return rc;
651 rc = r820t_write_reg_mask(priv, 0x15, sdm & 0xff, 0x08);
652 if (rc < 0)
653 return rc;
654
655 for (i = 0; i < 2; i++) {
656 /*
657 * FIXME: Rafael chips R620D, R828D and R828 seems to
658 * need 20 ms for analog TV
659 */
660 msleep(10);
661
662 /* Check if PLL has locked */
663 rc = r820_read(priv, 0x00, data, 3);
664 if (rc < 0)
665 return rc;
666 if (data[2] & 0x40)
667 break;
668
669 if (!i) {
670 /* Didn't lock. Increase VCO current */
671 rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0);
672 if (rc < 0)
673 return rc;
674 }
675 }
676
677 if (!(data[2] & 0x40)) {
678 priv->has_lock = false;
679 return 0;
680 }
681
682 priv->has_lock = true;
683 tuner_dbg("tuner has lock at frequency %d kHz\n", freq);
684
685 /* set pll autotune = 8kHz */
686 rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08);
687
688 return rc;
689 }
690
691 static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq,
692 enum v4l2_tuner_type type,
693 v4l2_std_id std,
694 u32 delsys)
695 {
696 int rc;
697 u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l;
698 u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur;
699
700 tuner_dbg("adjusting tuner parameters for the standard\n");
701
702 switch (delsys) {
703 case SYS_DVBT:
704 if ((freq == 506000000) || (freq == 666000000) ||
705 (freq == 818000000)) {
706 mixer_top = 0x14; /* mixer top:14 , top-1, low-discharge */
707 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
708 cp_cur = 0x28; /* 101, 0.2 */
709 div_buf_cur = 0x20; /* 10, 200u */
710 } else {
711 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
712 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
713 cp_cur = 0x38; /* 111, auto */
714 div_buf_cur = 0x30; /* 11, 150u */
715 }
716 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
717 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
718 air_cable1_in = 0x00;
719 cable2_in = 0x00;
720 pre_dect = 0x40;
721 lna_discharge = 14;
722 filter_cur = 0x40; /* 10, low */
723 break;
724 case SYS_DVBT2:
725 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
726 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
727 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
728 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
729 air_cable1_in = 0x00;
730 cable2_in = 0x00;
731 pre_dect = 0x40;
732 lna_discharge = 14;
733 cp_cur = 0x38; /* 111, auto */
734 div_buf_cur = 0x30; /* 11, 150u */
735 filter_cur = 0x40; /* 10, low */
736 break;
737 case SYS_ISDBT:
738 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
739 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
740 lna_vth_l = 0x75; /* lna vth 1.04 , vtl 0.84 */
741 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
742 air_cable1_in = 0x00;
743 cable2_in = 0x00;
744 pre_dect = 0x40;
745 lna_discharge = 14;
746 cp_cur = 0x38; /* 111, auto */
747 div_buf_cur = 0x30; /* 11, 150u */
748 filter_cur = 0x40; /* 10, low */
749 break;
750 default: /* DVB-T 8M */
751 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
752 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
753 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
754 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
755 air_cable1_in = 0x00;
756 cable2_in = 0x00;
757 pre_dect = 0x40;
758 lna_discharge = 14;
759 cp_cur = 0x38; /* 111, auto */
760 div_buf_cur = 0x30; /* 11, 150u */
761 filter_cur = 0x40; /* 10, low */
762 break;
763 }
764
765 if (priv->cfg->use_diplexer &&
766 ((priv->cfg->rafael_chip == CHIP_R820T) ||
767 (priv->cfg->rafael_chip == CHIP_R828S) ||
768 (priv->cfg->rafael_chip == CHIP_R820C))) {
769 if (freq > DIP_FREQ)
770 air_cable1_in = 0x00;
771 else
772 air_cable1_in = 0x60;
773 cable2_in = 0x00;
774 }
775
776 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7);
777 if (rc < 0)
778 return rc;
779 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8);
780 if (rc < 0)
781 return rc;
782 rc = r820t_write_reg(priv, 0x0d, lna_vth_l);
783 if (rc < 0)
784 return rc;
785 rc = r820t_write_reg(priv, 0x0e, mixer_vth_l);
786 if (rc < 0)
787 return rc;
788
789 /* Air-IN only for Astrometa */
790 rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60);
791 if (rc < 0)
792 return rc;
793 rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08);
794 if (rc < 0)
795 return rc;
796
797 rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38);
798 if (rc < 0)
799 return rc;
800 rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30);
801 if (rc < 0)
802 return rc;
803 rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60);
804 if (rc < 0)
805 return rc;
806 /*
807 * Original driver initializes regs 0x05 and 0x06 with the
808 * same value again on this point. Probably, it is just an
809 * error there
810 */
811
812 /*
813 * Set LNA
814 */
815
816 tuner_dbg("adjusting LNA parameters\n");
817 if (type != V4L2_TUNER_ANALOG_TV) {
818 /* LNA TOP: lowest */
819 rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38);
820 if (rc < 0)
821 return rc;
822
823 /* 0: normal mode */
824 rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04);
825 if (rc < 0)
826 return rc;
827
828 /* 0: PRE_DECT off */
829 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
830 if (rc < 0)
831 return rc;
832
833 /* agc clk 250hz */
834 rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30);
835 if (rc < 0)
836 return rc;
837
838 msleep(250);
839
840 /* write LNA TOP = 3 */
841 rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38);
842 if (rc < 0)
843 return rc;
844
845 /*
846 * write discharge mode
847 * FIXME: IMHO, the mask here is wrong, but it matches
848 * what's there at the original driver
849 */
850 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
851 if (rc < 0)
852 return rc;
853
854 /* LNA discharge current */
855 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
856 if (rc < 0)
857 return rc;
858
859 /* agc clk 60hz */
860 rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30);
861 if (rc < 0)
862 return rc;
863 } else {
864 /* PRE_DECT off */
865 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
866 if (rc < 0)
867 return rc;
868
869 /* write LNA TOP */
870 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38);
871 if (rc < 0)
872 return rc;
873
874 /*
875 * write discharge mode
876 * FIXME: IMHO, the mask here is wrong, but it matches
877 * what's there at the original driver
878 */
879 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
880 if (rc < 0)
881 return rc;
882
883 /* LNA discharge current */
884 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
885 if (rc < 0)
886 return rc;
887
888 /* agc clk 1Khz, external det1 cap 1u */
889 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30);
890 if (rc < 0)
891 return rc;
892
893 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04);
894 if (rc < 0)
895 return rc;
896 }
897 return 0;
898 }
899
900 static int r820t_set_tv_standard(struct r820t_priv *priv,
901 unsigned bw,
902 enum v4l2_tuner_type type,
903 v4l2_std_id std, u32 delsys)
904
905 {
906 int rc, i;
907 u32 if_khz, filt_cal_lo;
908 u8 data[5], val;
909 u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through;
910 u8 lt_att, flt_ext_widest, polyfil_cur;
911 bool need_calibration;
912
913 tuner_dbg("selecting the delivery system\n");
914
915 if (delsys == SYS_ISDBT) {
916 if_khz = 4063;
917 filt_cal_lo = 59000;
918 filt_gain = 0x10; /* +3db, 6mhz on */
919 img_r = 0x00; /* image negative */
920 filt_q = 0x10; /* r10[4]:low q(1'b1) */
921 hp_cor = 0x6a; /* 1.7m disable, +2cap, 1.25mhz */
922 ext_enable = 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */
923 loop_through = 0x00; /* r5[7], lt on */
924 lt_att = 0x00; /* r31[7], lt att enable */
925 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
926 polyfil_cur = 0x60; /* r25[6:5]:min */
927 } else {
928 if (bw <= 6) {
929 if_khz = 3570;
930 filt_cal_lo = 56000; /* 52000->56000 */
931 filt_gain = 0x10; /* +3db, 6mhz on */
932 img_r = 0x00; /* image negative */
933 filt_q = 0x10; /* r10[4]:low q(1'b1) */
934 hp_cor = 0x6b; /* 1.7m disable, +2cap, 1.0mhz */
935 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
936 loop_through = 0x00; /* r5[7], lt on */
937 lt_att = 0x00; /* r31[7], lt att enable */
938 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
939 polyfil_cur = 0x60; /* r25[6:5]:min */
940 } else if (bw == 7) {
941 #if 0
942 /*
943 * There are two 7 MHz tables defined on the original
944 * driver, but just the second one seems to be visible
945 * by rtl2832. Keep this one here commented, as it
946 * might be needed in the future
947 */
948
949 if_khz = 4070;
950 filt_cal_lo = 60000;
951 filt_gain = 0x10; /* +3db, 6mhz on */
952 img_r = 0x00; /* image negative */
953 filt_q = 0x10; /* r10[4]:low q(1'b1) */
954 hp_cor = 0x2b; /* 1.7m disable, +1cap, 1.0mhz */
955 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
956 loop_through = 0x00; /* r5[7], lt on */
957 lt_att = 0x00; /* r31[7], lt att enable */
958 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
959 polyfil_cur = 0x60; /* r25[6:5]:min */
960 #endif
961 /* 7 MHz, second table */
962 if_khz = 4570;
963 filt_cal_lo = 63000;
964 filt_gain = 0x10; /* +3db, 6mhz on */
965 img_r = 0x00; /* image negative */
966 filt_q = 0x10; /* r10[4]:low q(1'b1) */
967 hp_cor = 0x2a; /* 1.7m disable, +1cap, 1.25mhz */
968 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
969 loop_through = 0x00; /* r5[7], lt on */
970 lt_att = 0x00; /* r31[7], lt att enable */
971 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
972 polyfil_cur = 0x60; /* r25[6:5]:min */
973 } else {
974 if_khz = 4570;
975 filt_cal_lo = 68500;
976 filt_gain = 0x10; /* +3db, 6mhz on */
977 img_r = 0x00; /* image negative */
978 filt_q = 0x10; /* r10[4]:low q(1'b1) */
979 hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */
980 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
981 loop_through = 0x00; /* r5[7], lt on */
982 lt_att = 0x00; /* r31[7], lt att enable */
983 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
984 polyfil_cur = 0x60; /* r25[6:5]:min */
985 }
986 }
987
988 /* Initialize the shadow registers */
989 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
990
991 /* Init Flag & Xtal_check Result */
992 if (priv->imr_done)
993 val = 1 | priv->xtal_cap_sel << 1;
994 else
995 val = 0;
996 rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f);
997 if (rc < 0)
998 return rc;
999
1000 /* version */
1001 rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f);
1002 if (rc < 0)
1003 return rc;
1004
1005 /* for LT Gain test */
1006 if (type != V4L2_TUNER_ANALOG_TV) {
1007 rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38);
1008 if (rc < 0)
1009 return rc;
1010 msleep(1);
1011 }
1012 priv->int_freq = if_khz * 1000;
1013
1014 /* Check if standard changed. If so, filter calibration is needed */
1015 if (type != priv->type)
1016 need_calibration = true;
1017 else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std))
1018 need_calibration = true;
1019 else if ((type == V4L2_TUNER_DIGITAL_TV) &&
1020 ((delsys != priv->delsys) || bw != priv->bw))
1021 need_calibration = true;
1022 else
1023 need_calibration = false;
1024
1025 if (need_calibration) {
1026 tuner_dbg("calibrating the tuner\n");
1027 for (i = 0; i < 2; i++) {
1028 /* Set filt_cap */
1029 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60);
1030 if (rc < 0)
1031 return rc;
1032
1033 /* set cali clk =on */
1034 rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04);
1035 if (rc < 0)
1036 return rc;
1037
1038 /* X'tal cap 0pF for PLL */
1039 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03);
1040 if (rc < 0)
1041 return rc;
1042
1043 rc = r820t_set_pll(priv, filt_cal_lo);
1044 if (rc < 0 || !priv->has_lock)
1045 return rc;
1046
1047 /* Start Trigger */
1048 rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10);
1049 if (rc < 0)
1050 return rc;
1051
1052 msleep(1);
1053
1054 /* Stop Trigger */
1055 rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10);
1056 if (rc < 0)
1057 return rc;
1058
1059 /* set cali clk =off */
1060 rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04);
1061 if (rc < 0)
1062 return rc;
1063
1064 /* Check if calibration worked */
1065 rc = r820_read(priv, 0x00, data, sizeof(data));
1066 if (rc < 0)
1067 return rc;
1068
1069 priv->fil_cal_code = data[4] & 0x0f;
1070 if (priv->fil_cal_code && priv->fil_cal_code != 0x0f)
1071 break;
1072 }
1073 /* narrowest */
1074 if (priv->fil_cal_code == 0x0f)
1075 priv->fil_cal_code = 0;
1076 }
1077
1078 rc = r820t_write_reg_mask(priv, 0x0a,
1079 filt_q | priv->fil_cal_code, 0x1f);
1080 if (rc < 0)
1081 return rc;
1082
1083 /* Set BW, Filter_gain, & HP corner */
1084 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x10);
1085 if (rc < 0)
1086 return rc;
1087
1088
1089 /* Set Img_R */
1090 rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80);
1091 if (rc < 0)
1092 return rc;
1093
1094 /* Set filt_3dB, V6MHz */
1095 rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30);
1096 if (rc < 0)
1097 return rc;
1098
1099 /* channel filter extension */
1100 rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60);
1101 if (rc < 0)
1102 return rc;
1103
1104 /* Loop through */
1105 rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80);
1106 if (rc < 0)
1107 return rc;
1108
1109 /* Loop through attenuation */
1110 rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80);
1111 if (rc < 0)
1112 return rc;
1113
1114 /* filter extension widest */
1115 rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80);
1116 if (rc < 0)
1117 return rc;
1118
1119 /* RF poly filter current */
1120 rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60);
1121 if (rc < 0)
1122 return rc;
1123
1124 /* Store current standard. If it changes, re-calibrate the tuner */
1125 priv->delsys = delsys;
1126 priv->type = type;
1127 priv->std = std;
1128 priv->bw = bw;
1129
1130 return 0;
1131 }
1132
1133 static int r820t_read_gain(struct r820t_priv *priv)
1134 {
1135 u8 data[4];
1136 int rc;
1137
1138 rc = r820_read(priv, 0x00, data, sizeof(data));
1139 if (rc < 0)
1140 return rc;
1141
1142 return ((data[3] & 0x0f) << 1) + ((data[3] & 0xf0) >> 4);
1143 }
1144
1145 static int r820t_set_gain_mode(struct r820t_priv *priv,
1146 bool set_manual_gain,
1147 int gain)
1148 {
1149 int rc;
1150
1151 if (set_manual_gain) {
1152 int i, total_gain = 0;
1153 uint8_t mix_index = 0, lna_index = 0;
1154 u8 data[4];
1155
1156 /* LNA auto off */
1157 rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10);
1158 if (rc < 0)
1159 return rc;
1160
1161 /* Mixer auto off */
1162 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1163 if (rc < 0)
1164 return rc;
1165
1166 rc = r820_read(priv, 0x00, data, sizeof(data));
1167 if (rc < 0)
1168 return rc;
1169
1170 /* set fixed VGA gain for now (16.3 dB) */
1171 rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f);
1172 if (rc < 0)
1173 return rc;
1174
1175 for (i = 0; i < 15; i++) {
1176 if (total_gain >= gain)
1177 break;
1178
1179 total_gain += r820t_lna_gain_steps[++lna_index];
1180
1181 if (total_gain >= gain)
1182 break;
1183
1184 total_gain += r820t_mixer_gain_steps[++mix_index];
1185 }
1186
1187 /* set LNA gain */
1188 rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f);
1189 if (rc < 0)
1190 return rc;
1191
1192 /* set Mixer gain */
1193 rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f);
1194 if (rc < 0)
1195 return rc;
1196 } else {
1197 /* LNA */
1198 rc = r820t_write_reg_mask(priv, 0x05, 0, 0xef);
1199 if (rc < 0)
1200 return rc;
1201
1202 /* Mixer */
1203 rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0xef);
1204 if (rc < 0)
1205 return rc;
1206
1207 /* set fixed VGA gain for now (26.5 dB) */
1208 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1209 if (rc < 0)
1210 return rc;
1211 }
1212
1213 return 0;
1214 }
1215
1216
1217 static int generic_set_freq(struct dvb_frontend *fe,
1218 u32 freq /* in HZ */,
1219 unsigned bw,
1220 enum v4l2_tuner_type type,
1221 v4l2_std_id std, u32 delsys)
1222 {
1223 struct r820t_priv *priv = fe->tuner_priv;
1224 int rc = -EINVAL;
1225 u32 lo_freq;
1226
1227 tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
1228 freq / 1000, bw);
1229
1230 rc = r820t_set_tv_standard(priv, bw, type, std, delsys);
1231 if (rc < 0)
1232 goto err;
1233
1234 if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC))
1235 lo_freq = freq - priv->int_freq;
1236 else
1237 lo_freq = freq + priv->int_freq;
1238
1239 rc = r820t_set_mux(priv, lo_freq);
1240 if (rc < 0)
1241 goto err;
1242
1243 rc = r820t_set_gain_mode(priv, true, 0);
1244 if (rc < 0)
1245 goto err;
1246
1247 rc = r820t_set_pll(priv, lo_freq);
1248 if (rc < 0 || !priv->has_lock)
1249 goto err;
1250
1251 rc = r820t_sysfreq_sel(priv, freq, type, std, delsys);
1252 if (rc < 0)
1253 goto err;
1254
1255 tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
1256 __func__, freq, r820t_read_gain(priv));
1257
1258 err:
1259
1260 if (rc < 0)
1261 tuner_dbg("%s: failed=%d\n", __func__, rc);
1262 return rc;
1263 }
1264
1265 /*
1266 * r820t standby logic
1267 */
1268
1269 static int r820t_standby(struct r820t_priv *priv)
1270 {
1271 int rc;
1272
1273 rc = r820t_write_reg(priv, 0x06, 0xb1);
1274 if (rc < 0)
1275 return rc;
1276 rc = r820t_write_reg(priv, 0x05, 0x03);
1277 if (rc < 0)
1278 return rc;
1279 rc = r820t_write_reg(priv, 0x07, 0x3a);
1280 if (rc < 0)
1281 return rc;
1282 rc = r820t_write_reg(priv, 0x08, 0x40);
1283 if (rc < 0)
1284 return rc;
1285 rc = r820t_write_reg(priv, 0x09, 0xc0);
1286 if (rc < 0)
1287 return rc;
1288 rc = r820t_write_reg(priv, 0x0a, 0x36);
1289 if (rc < 0)
1290 return rc;
1291 rc = r820t_write_reg(priv, 0x0c, 0x35);
1292 if (rc < 0)
1293 return rc;
1294 rc = r820t_write_reg(priv, 0x0f, 0x68);
1295 if (rc < 0)
1296 return rc;
1297 rc = r820t_write_reg(priv, 0x11, 0x03);
1298 if (rc < 0)
1299 return rc;
1300 rc = r820t_write_reg(priv, 0x17, 0xf4);
1301 if (rc < 0)
1302 return rc;
1303 rc = r820t_write_reg(priv, 0x19, 0x0c);
1304
1305 /* Force initial calibration */
1306 priv->type = -1;
1307
1308 return rc;
1309 }
1310
1311 /*
1312 * r820t device init logic
1313 */
1314
1315 static int r820t_xtal_check(struct r820t_priv *priv)
1316 {
1317 int rc, i;
1318 u8 data[3], val;
1319
1320 /* Initialize the shadow registers */
1321 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1322
1323 /* cap 30pF & Drive Low */
1324 rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b);
1325 if (rc < 0)
1326 return rc;
1327
1328 /* set pll autotune = 128kHz */
1329 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
1330 if (rc < 0)
1331 return rc;
1332
1333 /* set manual initial reg = 111111; */
1334 rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f);
1335 if (rc < 0)
1336 return rc;
1337
1338 /* set auto */
1339 rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40);
1340 if (rc < 0)
1341 return rc;
1342
1343 /* Try several xtal capacitor alternatives */
1344 for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) {
1345 rc = r820t_write_reg_mask(priv, 0x10,
1346 r820t_xtal_capacitor[i][0], 0x1b);
1347 if (rc < 0)
1348 return rc;
1349
1350 msleep(5);
1351
1352 rc = r820_read(priv, 0x00, data, sizeof(data));
1353 if (rc < 0)
1354 return rc;
1355 if ((!data[2]) & 0x40)
1356 continue;
1357
1358 val = data[2] & 0x3f;
1359
1360 if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23))
1361 break;
1362
1363 if (val != 0x3f)
1364 break;
1365 }
1366
1367 if (i == ARRAY_SIZE(r820t_xtal_capacitor))
1368 return -EINVAL;
1369
1370 return r820t_xtal_capacitor[i][1];
1371 }
1372
1373 /*
1374 * r820t frontend operations and tuner attach code
1375 *
1376 * All driver locks and i2c control are only in this part of the code
1377 */
1378
1379 static int r820t_init(struct dvb_frontend *fe)
1380 {
1381 struct r820t_priv *priv = fe->tuner_priv;
1382 int rc, i;
1383 int xtal_cap = 0;
1384
1385 tuner_dbg("%s:\n", __func__);
1386
1387 mutex_lock(&priv->lock);
1388 if (fe->ops.i2c_gate_ctrl)
1389 fe->ops.i2c_gate_ctrl(fe, 1);
1390
1391 if ((priv->cfg->rafael_chip == CHIP_R820T) ||
1392 (priv->cfg->rafael_chip == CHIP_R828S) ||
1393 (priv->cfg->rafael_chip == CHIP_R820C)) {
1394 priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
1395 } else {
1396 for (i = 0; i < 3; i++) {
1397 rc = r820t_xtal_check(priv);
1398 if (rc < 0)
1399 goto err;
1400 if (!i || rc > xtal_cap)
1401 xtal_cap = rc;
1402 }
1403 priv->xtal_cap_sel = xtal_cap;
1404 }
1405
1406 /* Initialize registers */
1407 rc = r820t_write(priv, 0x05,
1408 r820t_init_array, sizeof(r820t_init_array));
1409
1410 err:
1411 if (fe->ops.i2c_gate_ctrl)
1412 fe->ops.i2c_gate_ctrl(fe, 0);
1413 mutex_unlock(&priv->lock);
1414
1415 if (rc < 0)
1416 tuner_dbg("%s: failed=%d\n", __func__, rc);
1417 return rc;
1418 }
1419
1420 static int r820t_sleep(struct dvb_frontend *fe)
1421 {
1422 struct r820t_priv *priv = fe->tuner_priv;
1423 int rc;
1424
1425 tuner_dbg("%s:\n", __func__);
1426
1427 mutex_lock(&priv->lock);
1428 if (fe->ops.i2c_gate_ctrl)
1429 fe->ops.i2c_gate_ctrl(fe, 1);
1430
1431 rc = r820t_standby(priv);
1432
1433 if (fe->ops.i2c_gate_ctrl)
1434 fe->ops.i2c_gate_ctrl(fe, 0);
1435 mutex_unlock(&priv->lock);
1436
1437 tuner_dbg("%s: failed=%d\n", __func__, rc);
1438 return rc;
1439 }
1440
1441 static int r820t_set_analog_freq(struct dvb_frontend *fe,
1442 struct analog_parameters *p)
1443 {
1444 struct r820t_priv *priv = fe->tuner_priv;
1445 unsigned bw;
1446 int rc;
1447
1448 tuner_dbg("%s called\n", __func__);
1449
1450 /* if std is not defined, choose one */
1451 if (!p->std)
1452 p->std = V4L2_STD_MN;
1453
1454 if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC))
1455 bw = 6;
1456 else
1457 bw = 8;
1458
1459 mutex_lock(&priv->lock);
1460 if (fe->ops.i2c_gate_ctrl)
1461 fe->ops.i2c_gate_ctrl(fe, 1);
1462
1463 rc = generic_set_freq(fe, 62500l * p->frequency, bw,
1464 V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED);
1465
1466 if (fe->ops.i2c_gate_ctrl)
1467 fe->ops.i2c_gate_ctrl(fe, 0);
1468 mutex_unlock(&priv->lock);
1469
1470 return rc;
1471 }
1472
1473 static int r820t_set_params(struct dvb_frontend *fe)
1474 {
1475 struct r820t_priv *priv = fe->tuner_priv;
1476 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1477 int rc;
1478 unsigned bw;
1479
1480 tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
1481 __func__, c->delivery_system, c->frequency, c->bandwidth_hz);
1482
1483 mutex_lock(&priv->lock);
1484 if (fe->ops.i2c_gate_ctrl)
1485 fe->ops.i2c_gate_ctrl(fe, 1);
1486
1487 bw = (c->bandwidth_hz + 500000) / 1000000;
1488 if (!bw)
1489 bw = 8;
1490
1491 rc = generic_set_freq(fe, c->frequency, bw,
1492 V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system);
1493
1494 if (fe->ops.i2c_gate_ctrl)
1495 fe->ops.i2c_gate_ctrl(fe, 0);
1496 mutex_unlock(&priv->lock);
1497
1498 if (rc)
1499 tuner_dbg("%s: failed=%d\n", __func__, rc);
1500 return rc;
1501 }
1502
1503 static int r820t_signal(struct dvb_frontend *fe, u16 *strength)
1504 {
1505 struct r820t_priv *priv = fe->tuner_priv;
1506 int rc = 0;
1507
1508 mutex_lock(&priv->lock);
1509 if (fe->ops.i2c_gate_ctrl)
1510 fe->ops.i2c_gate_ctrl(fe, 1);
1511
1512 if (priv->has_lock) {
1513 rc = r820t_read_gain(priv);
1514 if (rc < 0)
1515 goto err;
1516
1517 /* A higher gain at LNA means a lower signal strength */
1518 *strength = (45 - rc) << 4 | 0xff;
1519 if (*strength == 0xff)
1520 *strength = 0;
1521 } else {
1522 *strength = 0;
1523 }
1524
1525 err:
1526 if (fe->ops.i2c_gate_ctrl)
1527 fe->ops.i2c_gate_ctrl(fe, 0);
1528 mutex_unlock(&priv->lock);
1529
1530 tuner_dbg("%s: %s, gain=%d strength=%d\n",
1531 __func__,
1532 priv->has_lock ? "PLL locked" : "no signal",
1533 rc, *strength);
1534
1535 return 0;
1536 }
1537
1538 static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
1539 {
1540 struct r820t_priv *priv = fe->tuner_priv;
1541
1542 tuner_dbg("%s:\n", __func__);
1543
1544 *frequency = priv->int_freq;
1545
1546 return 0;
1547 }
1548
1549 static int r820t_release(struct dvb_frontend *fe)
1550 {
1551 struct r820t_priv *priv = fe->tuner_priv;
1552
1553 tuner_dbg("%s:\n", __func__);
1554
1555 mutex_lock(&r820t_list_mutex);
1556
1557 if (priv)
1558 hybrid_tuner_release_state(priv);
1559
1560 mutex_unlock(&r820t_list_mutex);
1561
1562 fe->tuner_priv = NULL;
1563
1564 kfree(fe->tuner_priv);
1565
1566 return 0;
1567 }
1568
1569 static const struct dvb_tuner_ops r820t_tuner_ops = {
1570 .info = {
1571 .name = "Rafael Micro R820T",
1572 .frequency_min = 42000000,
1573 .frequency_max = 1002000000,
1574 },
1575 .init = r820t_init,
1576 .release = r820t_release,
1577 .sleep = r820t_sleep,
1578 .set_params = r820t_set_params,
1579 .set_analog_params = r820t_set_analog_freq,
1580 .get_if_frequency = r820t_get_if_frequency,
1581 .get_rf_strength = r820t_signal,
1582 };
1583
1584 struct dvb_frontend *r820t_attach(struct dvb_frontend *fe,
1585 struct i2c_adapter *i2c,
1586 const struct r820t_config *cfg)
1587 {
1588 struct r820t_priv *priv;
1589 int rc = -ENODEV;
1590 u8 data[5];
1591 int instance;
1592
1593 mutex_lock(&r820t_list_mutex);
1594
1595 instance = hybrid_tuner_request_state(struct r820t_priv, priv,
1596 hybrid_tuner_instance_list,
1597 i2c, cfg->i2c_addr,
1598 "r820t");
1599 switch (instance) {
1600 case 0:
1601 /* memory allocation failure */
1602 goto err_no_gate;
1603 break;
1604 case 1:
1605 /* new tuner instance */
1606 priv->cfg = cfg;
1607
1608 mutex_init(&priv->lock);
1609
1610 fe->tuner_priv = priv;
1611 break;
1612 case 2:
1613 /* existing tuner instance */
1614 fe->tuner_priv = priv;
1615 break;
1616 }
1617
1618 memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops, sizeof(r820t_tuner_ops));
1619
1620 if (fe->ops.i2c_gate_ctrl)
1621 fe->ops.i2c_gate_ctrl(fe, 1);
1622
1623 /* check if the tuner is there */
1624 rc = r820_read(priv, 0x00, data, sizeof(data));
1625 if (rc < 0)
1626 goto err;
1627
1628 rc = r820t_sleep(fe);
1629 if (rc < 0)
1630 goto err;
1631
1632 tuner_info("Rafael Micro r820t successfully identified\n");
1633
1634 fe->tuner_priv = priv;
1635 memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops,
1636 sizeof(struct dvb_tuner_ops));
1637
1638 if (fe->ops.i2c_gate_ctrl)
1639 fe->ops.i2c_gate_ctrl(fe, 0);
1640
1641 mutex_unlock(&r820t_list_mutex);
1642
1643 return fe;
1644 err:
1645 if (fe->ops.i2c_gate_ctrl)
1646 fe->ops.i2c_gate_ctrl(fe, 0);
1647
1648 err_no_gate:
1649 mutex_unlock(&r820t_list_mutex);
1650
1651 tuner_info("%s: failed=%d\n", __func__, rc);
1652 r820t_release(fe);
1653 return NULL;
1654 }
1655 EXPORT_SYMBOL_GPL(r820t_attach);
1656
1657 MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
1658 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1659 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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