2 * Rafael Micro R820T driver
4 * Copyright (C) 2013 Mauro Carvalho Chehab <mchehab@redhat.com>
6 * This driver was written from scratch, based on an existing driver
7 * that it is part of rtl-sdr git tree, released under GPLv2:
8 * https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug
9 * https://github.com/n1gp/gr-baz
11 * From what I understood from the threads, the original driver was converted
12 * to userspace from a Realtek tree. I couldn't find the original tree.
13 * However, the original driver look awkward on my eyes. So, I decided to
14 * write a new version from it from the scratch, while trying to reproduce
15 * everything found there.
18 * After locking, the original driver seems to have some routines to
19 * improve reception. This was not implemented here yet.
21 * RF Gain set/get is not implemented.
23 * This program is free software; you can redistribute it and/or modify
24 * it under the terms of the GNU General Public License as published by
25 * the Free Software Foundation; either version 2 of the License, or
26 * (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
35 #include <linux/videodev2.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include "tuner-i2c.h"
39 #include <asm/div64.h>
43 * FIXME: I think that there are only 32 registers, but better safe than
44 * sorry. After finishing the driver, we may review it.
46 #define REG_SHADOW_START 5
52 module_param(debug
, int, 0644);
53 MODULE_PARM_DESC(debug
, "enable verbose debug messages");
56 * enums and structures
68 struct list_head hybrid_tuner_instance_list
;
69 const struct r820t_config
*cfg
;
70 struct tuner_i2c_props i2c_props
;
75 enum xtal_cap_value xtal_cap_sel
;
81 /* Store current mode */
83 enum v4l2_tuner_type type
;
90 struct r820t_freq_range
{
98 u8 imr_mem
; /* Not used, currently */
101 #define VCO_POWER_REF 0x02
107 static LIST_HEAD(hybrid_tuner_instance_list
);
108 static DEFINE_MUTEX(r820t_list_mutex
);
110 /* Those initial values start from REG_SHADOW_START */
111 static const u8 r820t_init_array
[NUM_REGS
] = {
112 0x83, 0x32, 0x75, /* 05 to 07 */
113 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */
114 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */
115 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */
116 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */
117 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */
118 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */
121 /* Tuner frequency ranges */
122 static const struct r820t_freq_range freq_ranges
[] = {
125 .open_d
= 0x08, /* low */
126 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
127 .tf_c
= 0xdf, /* R27[7:0] band2,band0 */
128 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
133 .freq
= 50, /* Start freq, in MHz */
134 .open_d
= 0x08, /* low */
135 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
136 .tf_c
= 0xbe, /* R27[7:0] band4,band1 */
137 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
142 .freq
= 55, /* Start freq, in MHz */
143 .open_d
= 0x08, /* low */
144 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
145 .tf_c
= 0x8b, /* R27[7:0] band7,band4 */
146 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
151 .freq
= 60, /* Start freq, in MHz */
152 .open_d
= 0x08, /* low */
153 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
154 .tf_c
= 0x7b, /* R27[7:0] band8,band4 */
155 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
160 .freq
= 65, /* Start freq, in MHz */
161 .open_d
= 0x08, /* low */
162 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
163 .tf_c
= 0x69, /* R27[7:0] band9,band6 */
164 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
169 .freq
= 70, /* Start freq, in MHz */
170 .open_d
= 0x08, /* low */
171 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
172 .tf_c
= 0x58, /* R27[7:0] band10,band7 */
173 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
178 .freq
= 75, /* Start freq, in MHz */
179 .open_d
= 0x00, /* high */
180 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
181 .tf_c
= 0x44, /* R27[7:0] band11,band11 */
182 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
187 .freq
= 80, /* Start freq, in MHz */
188 .open_d
= 0x00, /* high */
189 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
190 .tf_c
= 0x44, /* R27[7:0] band11,band11 */
191 .xtal_cap20p
= 0x02, /* R16[1:0] 20pF (10) */
196 .freq
= 90, /* Start freq, in MHz */
197 .open_d
= 0x00, /* high */
198 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
199 .tf_c
= 0x34, /* R27[7:0] band12,band11 */
200 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
205 .freq
= 100, /* Start freq, in MHz */
206 .open_d
= 0x00, /* high */
207 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
208 .tf_c
= 0x34, /* R27[7:0] band12,band11 */
209 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
214 .freq
= 110, /* Start freq, in MHz */
215 .open_d
= 0x00, /* high */
216 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
217 .tf_c
= 0x24, /* R27[7:0] band13,band11 */
218 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
223 .freq
= 120, /* Start freq, in MHz */
224 .open_d
= 0x00, /* high */
225 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
226 .tf_c
= 0x24, /* R27[7:0] band13,band11 */
227 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
232 .freq
= 140, /* Start freq, in MHz */
233 .open_d
= 0x00, /* high */
234 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
235 .tf_c
= 0x14, /* R27[7:0] band14,band11 */
236 .xtal_cap20p
= 0x01, /* R16[1:0] 10pF (01) */
241 .freq
= 180, /* Start freq, in MHz */
242 .open_d
= 0x00, /* high */
243 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
244 .tf_c
= 0x13, /* R27[7:0] band14,band12 */
245 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
250 .freq
= 220, /* Start freq, in MHz */
251 .open_d
= 0x00, /* high */
252 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
253 .tf_c
= 0x13, /* R27[7:0] band14,band12 */
254 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
259 .freq
= 250, /* Start freq, in MHz */
260 .open_d
= 0x00, /* high */
261 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
262 .tf_c
= 0x11, /* R27[7:0] highest,highest */
263 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
268 .freq
= 280, /* Start freq, in MHz */
269 .open_d
= 0x00, /* high */
270 .rf_mux_ploy
= 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
271 .tf_c
= 0x00, /* R27[7:0] highest,highest */
272 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
277 .freq
= 310, /* Start freq, in MHz */
278 .open_d
= 0x00, /* high */
279 .rf_mux_ploy
= 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
280 .tf_c
= 0x00, /* R27[7:0] highest,highest */
281 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
286 .freq
= 450, /* Start freq, in MHz */
287 .open_d
= 0x00, /* high */
288 .rf_mux_ploy
= 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
289 .tf_c
= 0x00, /* R27[7:0] highest,highest */
290 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
295 .freq
= 588, /* Start freq, in MHz */
296 .open_d
= 0x00, /* high */
297 .rf_mux_ploy
= 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
298 .tf_c
= 0x00, /* R27[7:0] highest,highest */
299 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
304 .freq
= 650, /* Start freq, in MHz */
305 .open_d
= 0x00, /* high */
306 .rf_mux_ploy
= 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
307 .tf_c
= 0x00, /* R27[7:0] highest,highest */
308 .xtal_cap20p
= 0x00, /* R16[1:0] 0pF (00) */
315 static int r820t_xtal_capacitor
[][2] = {
316 { 0x0b, XTAL_LOW_CAP_30P
},
317 { 0x02, XTAL_LOW_CAP_20P
},
318 { 0x01, XTAL_LOW_CAP_10P
},
319 { 0x00, XTAL_LOW_CAP_0P
},
320 { 0x10, XTAL_HIGH_CAP_0P
},
324 * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
325 * input power, for raw results see:
326 * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
329 static const int r820t_lna_gain_steps
[] = {
330 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
333 static const int r820t_mixer_gain_steps
[] = {
334 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
338 * I2C read/write code and shadow registers logic
340 static void shadow_store(struct r820t_priv
*priv
, u8 reg
, const u8
*val
,
343 int r
= reg
- REG_SHADOW_START
;
354 tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n",
355 __func__
, r
+ REG_SHADOW_START
, len
, len
, val
);
357 memcpy(&priv
->regs
[r
], val
, len
);
360 static int r820t_write(struct r820t_priv
*priv
, u8 reg
, const u8
*val
,
363 int rc
, size
, pos
= 0;
365 /* Store the shadow registers */
366 shadow_store(priv
, reg
, val
, len
);
369 if (len
> priv
->cfg
->max_i2c_msg_len
- 1)
370 size
= priv
->cfg
->max_i2c_msg_len
- 1;
374 /* Fill I2C buffer */
376 memcpy(&priv
->buf
[1], &val
[pos
], size
);
378 rc
= tuner_i2c_xfer_send(&priv
->i2c_props
, priv
->buf
, size
+ 1);
379 if (rc
!= size
+ 1) {
380 tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
381 __func__
, rc
, reg
, size
, size
, &priv
->buf
[1]);
386 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
387 __func__
, reg
, size
, size
, &priv
->buf
[1]);
397 static int r820t_write_reg(struct r820t_priv
*priv
, u8 reg
, u8 val
)
399 return r820t_write(priv
, reg
, &val
, 1);
402 static int r820t_write_reg_mask(struct r820t_priv
*priv
, u8 reg
, u8 val
,
405 int r
= reg
- REG_SHADOW_START
;
407 if (r
>= 0 && r
< NUM_REGS
)
408 val
= (priv
->regs
[r
] & ~bit_mask
) | (val
& bit_mask
);
412 return r820t_write(priv
, reg
, &val
, 1);
415 static int r820_read(struct r820t_priv
*priv
, u8 reg
, u8
*val
, int len
)
418 u8
*p
= &priv
->buf
[1];
422 rc
= tuner_i2c_xfer_send_recv(&priv
->i2c_props
, priv
->buf
, 1, p
, len
);
424 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
425 __func__
, rc
, reg
, len
, len
, p
);
430 tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
431 __func__
, reg
, len
, len
, p
);
433 /* Copy data to the output buffer */
443 static int r820t_set_mux(struct r820t_priv
*priv
, u32 freq
)
445 const struct r820t_freq_range
*range
;
449 /* Get the proper frequency range */
450 freq
= freq
/ 1000000;
451 for (i
= 0; i
< ARRAY_SIZE(freq_ranges
) - 1; i
++) {
452 if (freq
< freq_ranges
[i
+ 1].freq
)
455 range
= &freq_ranges
[i
];
457 tuner_dbg("set r820t range#%d for frequency %d MHz\n", i
, freq
);
460 rc
= r820t_write_reg_mask(priv
, 0x17, range
->open_d
, 0x08);
465 rc
= r820t_write_reg_mask(priv
, 0x1a, range
->rf_mux_ploy
, 0xc3);
470 rc
= r820t_write_reg(priv
, 0x1b, range
->tf_c
);
474 /* XTAL CAP & Drive */
475 switch (priv
->xtal_cap_sel
) {
476 case XTAL_LOW_CAP_30P
:
477 case XTAL_LOW_CAP_20P
:
478 val
= range
->xtal_cap20p
| 0x08;
480 case XTAL_LOW_CAP_10P
:
481 val
= range
->xtal_cap10p
| 0x08;
483 case XTAL_HIGH_CAP_0P
:
484 val
= range
->xtal_cap0p
| 0x00;
487 case XTAL_LOW_CAP_0P
:
488 val
= range
->xtal_cap0p
| 0x08;
491 rc
= r820t_write_reg_mask(priv
, 0x10, val
, 0x0b);
496 * FIXME: the original driver has a logic there with preserves
497 * gain/phase from registers 8 and 9 reading the data from the
498 * registers before writing, if "IMF done". That code was sort of
499 * commented there, as the flag is always false.
501 rc
= r820t_write_reg_mask(priv
, 0x08, 0, 0x3f);
505 rc
= r820t_write_reg_mask(priv
, 0x09, 0, 0x3f);
510 static int r820t_set_pll(struct r820t_priv
*priv
, u32 freq
)
514 u32 vco_fra
; /* VCO contribution by SDM (kHz) */
515 u32 vco_min
= 1770000;
516 u32 vco_max
= vco_min
* 2;
523 u8 ni
, si
, nint
, vco_fine_tune
, val
;
526 freq
= freq
/ 1000; /* Frequency in kHz */
528 pll_ref
= priv
->cfg
->xtal
/ 1000;
530 tuner_dbg("set r820t pll for frequency %d kHz = %d\n", freq
, pll_ref
);
532 /* FIXME: this seems to be a hack - probably it can be removed */
533 rc
= r820t_write_reg_mask(priv
, 0x10, 0x00, 0x00);
537 /* set pll autotune = 128kHz */
538 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x00, 0x0c);
542 /* set VCO current = 100 */
543 rc
= r820t_write_reg_mask(priv
, 0x12, 0x80, 0xe0);
547 /* Calculate divider */
548 while (mix_div
<= 64) {
549 if (((freq
* mix_div
) >= vco_min
) &&
550 ((freq
* mix_div
) < vco_max
)) {
552 while (div_buf
> 2) {
553 div_buf
= div_buf
>> 1;
558 mix_div
= mix_div
<< 1;
561 rc
= r820_read(priv
, 0x00, data
, sizeof(data
));
565 vco_fine_tune
= (data
[4] & 0x30) >> 4;
567 if (vco_fine_tune
> VCO_POWER_REF
)
568 div_num
= div_num
- 1;
569 else if (vco_fine_tune
< VCO_POWER_REF
)
570 div_num
= div_num
+ 1;
572 rc
= r820t_write_reg_mask(priv
, 0x10, div_num
<< 5, 0xe0);
576 vco_freq
= (u64
)(freq
* (u64
)mix_div
);
579 do_div(tmp64
, 2 * pll_ref
);
582 tmp64
= vco_freq
- ((u64
)2) * pll_ref
* nint
;
584 vco_fra
= (u16
)(tmp64
);
588 /* boundary spur prevention */
589 if (vco_fra
< pll_ref
/ 64) {
591 } else if (vco_fra
> pll_ref
* 127 / 64) {
594 } else if ((vco_fra
> pll_ref
* 127 / 128) && (vco_fra
< pll_ref
)) {
595 vco_fra
= pll_ref
* 127 / 128;
596 } else if ((vco_fra
> pll_ref
) && (vco_fra
< pll_ref
* 129 / 128)) {
597 vco_fra
= pll_ref
* 129 / 128;
601 tuner_info("No valid PLL values for %u kHz!\n", freq
);
605 ni
= (nint
- 13) / 4;
606 si
= nint
- 4 * ni
- 13;
608 rc
= r820t_write_reg(priv
, 0x14, ni
+ (si
<< 6));
618 rc
= r820t_write_reg_mask(priv
, 0x12, val
, 0x08);
623 while (vco_fra
> 1) {
624 if (vco_fra
> (2 * pll_ref
/ n_sdm
)) {
625 sdm
= sdm
+ 32768 / (n_sdm
/ 2);
626 vco_fra
= vco_fra
- 2 * pll_ref
/ n_sdm
;
633 rc
= r820t_write_reg_mask(priv
, 0x16, sdm
>> 8, 0x08);
636 rc
= r820t_write_reg_mask(priv
, 0x15, sdm
& 0xff, 0x08);
640 for (i
= 0; i
< 2; i
++) {
642 * FIXME: Rafael chips R620D, R828D and R828 seems to
643 * need 20 ms for analog TV
647 /* Check if PLL has locked */
648 rc
= r820_read(priv
, 0x00, data
, 3);
655 /* Didn't lock. Increase VCO current */
656 rc
= r820t_write_reg_mask(priv
, 0x12, 0x60, 0xe0);
662 if (!(data
[2] & 0x40)) {
663 priv
->has_lock
= false;
667 priv
->has_lock
= true;
668 tuner_dbg("tuner has lock at frequency %d kHz\n", freq
);
670 /* set pll autotune = 8kHz */
671 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x08, 0x08);
676 static int r820t_sysfreq_sel(struct r820t_priv
*priv
, u32 freq
,
677 enum v4l2_tuner_type type
,
682 u8 mixer_top
, lna_top
, cp_cur
, div_buf_cur
, lna_vth_l
, mixer_vth_l
;
683 u8 air_cable1_in
, cable2_in
, pre_dect
, lna_discharge
, filter_cur
;
685 tuner_dbg("adjusting tuner parameters for the standard\n");
689 if ((freq
== 506000000) || (freq
== 666000000) ||
690 (freq
== 818000000)) {
691 mixer_top
= 0x14; /* mixer top:14 , top-1, low-discharge */
692 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
693 cp_cur
= 0x28; /* 101, 0.2 */
694 div_buf_cur
= 0x20; /* 10, 200u */
696 mixer_top
= 0x24; /* mixer top:13 , top-1, low-discharge */
697 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
698 cp_cur
= 0x38; /* 111, auto */
699 div_buf_cur
= 0x30; /* 11, 150u */
701 lna_vth_l
= 0x53; /* lna vth 0.84 , vtl 0.64 */
702 mixer_vth_l
= 0x75; /* mixer vth 1.04, vtl 0.84 */
703 air_cable1_in
= 0x00;
707 filter_cur
= 0x40; /* 10, low */
710 mixer_top
= 0x24; /* mixer top:13 , top-1, low-discharge */
711 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
712 lna_vth_l
= 0x53; /* lna vth 0.84 , vtl 0.64 */
713 mixer_vth_l
= 0x75; /* mixer vth 1.04, vtl 0.84 */
714 air_cable1_in
= 0x00;
718 cp_cur
= 0x38; /* 111, auto */
719 div_buf_cur
= 0x30; /* 11, 150u */
720 filter_cur
= 0x40; /* 10, low */
723 mixer_top
= 0x24; /* mixer top:13 , top-1, low-discharge */
724 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
725 lna_vth_l
= 0x75; /* lna vth 1.04 , vtl 0.84 */
726 mixer_vth_l
= 0x75; /* mixer vth 1.04, vtl 0.84 */
727 air_cable1_in
= 0x00;
731 cp_cur
= 0x38; /* 111, auto */
732 div_buf_cur
= 0x30; /* 11, 150u */
733 filter_cur
= 0x40; /* 10, low */
735 default: /* DVB-T 8M */
736 mixer_top
= 0x24; /* mixer top:13 , top-1, low-discharge */
737 lna_top
= 0xe5; /* detect bw 3, lna top:4, predet top:2 */
738 lna_vth_l
= 0x53; /* lna vth 0.84 , vtl 0.64 */
739 mixer_vth_l
= 0x75; /* mixer vth 1.04, vtl 0.84 */
740 air_cable1_in
= 0x00;
744 cp_cur
= 0x38; /* 111, auto */
745 div_buf_cur
= 0x30; /* 11, 150u */
746 filter_cur
= 0x40; /* 10, low */
750 rc
= r820t_write_reg_mask(priv
, 0x1d, lna_top
, 0xc7);
753 rc
= r820t_write_reg_mask(priv
, 0x1c, mixer_top
, 0xf8);
756 rc
= r820t_write_reg(priv
, 0x0d, lna_vth_l
);
759 rc
= r820t_write_reg(priv
, 0x0e, mixer_vth_l
);
763 /* Air-IN only for Astrometa */
764 rc
= r820t_write_reg_mask(priv
, 0x05, air_cable1_in
, 0x60);
767 rc
= r820t_write_reg_mask(priv
, 0x06, cable2_in
, 0x08);
771 rc
= r820t_write_reg_mask(priv
, 0x11, cp_cur
, 0x38);
774 rc
= r820t_write_reg_mask(priv
, 0x17, div_buf_cur
, 0x30);
777 rc
= r820t_write_reg_mask(priv
, 0x0a, filter_cur
, 0x60);
781 * Original driver initializes regs 0x05 and 0x06 with the
782 * same value again on this point. Probably, it is just an
790 tuner_dbg("adjusting LNA parameters\n");
791 if (type
!= V4L2_TUNER_ANALOG_TV
) {
792 /* LNA TOP: lowest */
793 rc
= r820t_write_reg_mask(priv
, 0x1d, 0, 0x38);
798 rc
= r820t_write_reg_mask(priv
, 0x1c, 0, 0x04);
802 /* 0: PRE_DECT off */
803 rc
= r820t_write_reg_mask(priv
, 0x06, 0, 0x40);
808 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x30, 0x30);
814 /* write LNA TOP = 3 */
815 rc
= r820t_write_reg_mask(priv
, 0x1d, 0x18, 0x38);
820 * write discharge mode
821 * FIXME: IMHO, the mask here is wrong, but it matches
822 * what's there at the original driver
824 rc
= r820t_write_reg_mask(priv
, 0x1c, mixer_top
, 0x04);
828 /* LNA discharge current */
829 rc
= r820t_write_reg_mask(priv
, 0x1e, lna_discharge
, 0x1f);
834 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x20, 0x30);
839 rc
= r820t_write_reg_mask(priv
, 0x06, 0, 0x40);
844 rc
= r820t_write_reg_mask(priv
, 0x1d, lna_top
, 0x38);
849 * write discharge mode
850 * FIXME: IMHO, the mask here is wrong, but it matches
851 * what's there at the original driver
853 rc
= r820t_write_reg_mask(priv
, 0x1c, mixer_top
, 0x04);
857 /* LNA discharge current */
858 rc
= r820t_write_reg_mask(priv
, 0x1e, lna_discharge
, 0x1f);
862 /* agc clk 1Khz, external det1 cap 1u */
863 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x00, 0x30);
867 rc
= r820t_write_reg_mask(priv
, 0x10, 0x00, 0x04);
874 static int r820t_set_tv_standard(struct r820t_priv
*priv
,
876 enum v4l2_tuner_type type
,
877 v4l2_std_id std
, u32 delsys
)
881 u32 if_khz
, filt_cal_lo
;
883 u8 filt_gain
, img_r
, filt_q
, hp_cor
, ext_enable
, loop_through
;
884 u8 lt_att
, flt_ext_widest
, polyfil_cur
;
885 bool need_calibration
;
887 tuner_dbg("selecting the delivery system\n");
889 if (delsys
== SYS_ISDBT
) {
892 filt_gain
= 0x10; /* +3db, 6mhz on */
893 img_r
= 0x00; /* image negative */
894 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
895 hp_cor
= 0x6a; /* 1.7m disable, +2cap, 1.25mhz */
896 ext_enable
= 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */
897 loop_through
= 0x00; /* r5[7], lt on */
898 lt_att
= 0x00; /* r31[7], lt att enable */
899 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
900 polyfil_cur
= 0x60; /* r25[6:5]:min */
904 filt_cal_lo
= 56000; /* 52000->56000 */
905 filt_gain
= 0x10; /* +3db, 6mhz on */
906 img_r
= 0x00; /* image negative */
907 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
908 hp_cor
= 0x6b; /* 1.7m disable, +2cap, 1.0mhz */
909 ext_enable
= 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
910 loop_through
= 0x00; /* r5[7], lt on */
911 lt_att
= 0x00; /* r31[7], lt att enable */
912 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
913 polyfil_cur
= 0x60; /* r25[6:5]:min */
914 } else if (bw
== 7) {
917 filt_gain
= 0x10; /* +3db, 6mhz on */
918 img_r
= 0x00; /* image negative */
919 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
920 hp_cor
= 0x2b; /* 1.7m disable, +1cap, 1.0mhz */
921 ext_enable
= 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
922 loop_through
= 0x00; /* r5[7], lt on */
923 lt_att
= 0x00; /* r31[7], lt att enable */
924 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
925 polyfil_cur
= 0x60; /* r25[6:5]:min */
926 #if 0 /* 7 MHz type 2 - nor sure why/where this is used - Perhaps Australia? */
929 filt_gain
= 0x10; /* +3db, 6mhz on */
930 img_r
= 0x00; /* image negative */
931 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
932 hp_cor
= 0x2a; /* 1.7m disable, +1cap, 1.25mhz */
933 ext_enable
= 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
934 loop_through
= 0x00; /* r5[7], lt on */
935 lt_att
= 0x00; /* r31[7], lt att enable */
936 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
937 polyfil_cur
= 0x60; /* r25[6:5]:min */
942 filt_gain
= 0x10; /* +3db, 6mhz on */
943 img_r
= 0x00; /* image negative */
944 filt_q
= 0x10; /* r10[4]:low q(1'b1) */
945 hp_cor
= 0x0b; /* 1.7m disable, +0cap, 1.0mhz */
946 ext_enable
= 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
947 loop_through
= 0x00; /* r5[7], lt on */
948 lt_att
= 0x00; /* r31[7], lt att enable */
949 flt_ext_widest
= 0x00; /* r15[7]: flt_ext_wide off */
950 polyfil_cur
= 0x60; /* r25[6:5]:min */
954 /* Initialize the shadow registers */
955 memcpy(priv
->regs
, r820t_init_array
, sizeof(r820t_init_array
));
957 /* Init Flag & Xtal_check Result */
959 val
= 1 | priv
->xtal_cap_sel
<< 1;
962 rc
= r820t_write_reg_mask(priv
, 0x0c, val
, 0x0f);
967 rc
= r820t_write_reg_mask(priv
, 0x13, VER_NUM
, 0x3f);
971 /* for LT Gain test */
972 if (type
!= V4L2_TUNER_ANALOG_TV
) {
973 rc
= r820t_write_reg_mask(priv
, 0x1d, 0x00, 0x38);
978 priv
->int_freq
= if_khz
* 1000;
980 /* Check if standard changed. If so, filter calibration is needed */
981 if (type
!= priv
->type
)
982 need_calibration
= true;
983 else if ((type
== V4L2_TUNER_ANALOG_TV
) && (std
!= priv
->std
))
984 need_calibration
= true;
985 else if ((type
== V4L2_TUNER_DIGITAL_TV
) &&
986 ((delsys
!= priv
->delsys
) || bw
!= priv
->bw
))
987 need_calibration
= true;
989 need_calibration
= false;
991 if (need_calibration
) {
992 tuner_dbg("calibrating the tuner\n");
993 for (i
= 0; i
< 2; i
++) {
995 rc
= r820t_write_reg_mask(priv
, 0x0b, hp_cor
, 0x60);
999 /* set cali clk =on */
1000 rc
= r820t_write_reg_mask(priv
, 0x0f, 0x04, 0x04);
1004 /* X'tal cap 0pF for PLL */
1005 rc
= r820t_write_reg_mask(priv
, 0x10, 0x00, 0x03);
1009 rc
= r820t_set_pll(priv
, filt_cal_lo
);
1010 if (rc
< 0 || !priv
->has_lock
)
1014 rc
= r820t_write_reg_mask(priv
, 0x0b, 0x10, 0x10);
1021 rc
= r820t_write_reg_mask(priv
, 0x0b, 0x00, 0x10);
1025 /* set cali clk =off */
1026 rc
= r820t_write_reg_mask(priv
, 0x0f, 0x00, 0x04);
1030 /* Check if calibration worked */
1031 rc
= r820_read(priv
, 0x00, data
, sizeof(data
));
1035 priv
->fil_cal_code
= data
[4] & 0x0f;
1036 if (priv
->fil_cal_code
&& priv
->fil_cal_code
!= 0x0f)
1040 if (priv
->fil_cal_code
== 0x0f)
1041 priv
->fil_cal_code
= 0;
1044 rc
= r820t_write_reg_mask(priv
, 0x0a,
1045 filt_q
| priv
->fil_cal_code
, 0x1f);
1049 /* Set BW, Filter_gain, & HP corner */
1050 rc
= r820t_write_reg_mask(priv
, 0x0b, hp_cor
, 0x10);
1056 rc
= r820t_write_reg_mask(priv
, 0x07, img_r
, 0x80);
1060 /* Set filt_3dB, V6MHz */
1061 rc
= r820t_write_reg_mask(priv
, 0x06, filt_gain
, 0x30);
1065 /* channel filter extension */
1066 rc
= r820t_write_reg_mask(priv
, 0x1e, ext_enable
, 0x60);
1071 rc
= r820t_write_reg_mask(priv
, 0x05, loop_through
, 0x80);
1075 /* Loop through attenuation */
1076 rc
= r820t_write_reg_mask(priv
, 0x1f, lt_att
, 0x80);
1080 /* filter extension widest */
1081 rc
= r820t_write_reg_mask(priv
, 0x0f, flt_ext_widest
, 0x80);
1085 /* RF poly filter current */
1086 rc
= r820t_write_reg_mask(priv
, 0x19, polyfil_cur
, 0x60);
1090 /* Store current standard. If it changes, re-calibrate the tuner */
1091 priv
->delsys
= delsys
;
1099 static int r820t_read_gain(struct r820t_priv
*priv
)
1104 rc
= r820_read(priv
, 0x00, data
, sizeof(data
));
1108 return ((data
[3] & 0x0f) << 1) + ((data
[3] & 0xf0) >> 4);
1111 static int r820t_set_gain_mode(struct r820t_priv
*priv
,
1112 bool set_manual_gain
,
1117 if (set_manual_gain
) {
1118 int i
, total_gain
= 0;
1119 uint8_t mix_index
= 0, lna_index
= 0;
1123 rc
= r820t_write_reg_mask(priv
, 0x05, 0x10, 0x10);
1127 /* Mixer auto off */
1128 rc
= r820t_write_reg_mask(priv
, 0x07, 0, 0x10);
1132 rc
= r820_read(priv
, 0x00, data
, sizeof(data
));
1136 /* set fixed VGA gain for now (16.3 dB) */
1137 rc
= r820t_write_reg_mask(priv
, 0x0c, 0x08, 0x9f);
1141 for (i
= 0; i
< 15; i
++) {
1142 if (total_gain
>= gain
)
1145 total_gain
+= r820t_lna_gain_steps
[++lna_index
];
1147 if (total_gain
>= gain
)
1150 total_gain
+= r820t_mixer_gain_steps
[++mix_index
];
1154 rc
= r820t_write_reg_mask(priv
, 0x05, lna_index
, 0x0f);
1158 /* set Mixer gain */
1159 rc
= r820t_write_reg_mask(priv
, 0x07, mix_index
, 0x0f);
1164 rc
= r820t_write_reg_mask(priv
, 0x05, 0, 0xef);
1169 rc
= r820t_write_reg_mask(priv
, 0x07, 0x10, 0xef);
1173 /* set fixed VGA gain for now (26.5 dB) */
1174 rc
= r820t_write_reg_mask(priv
, 0x0c, 0x0b, 0x9f);
1183 static int generic_set_freq(struct dvb_frontend
*fe
,
1184 u32 freq
/* in HZ */,
1186 enum v4l2_tuner_type type
,
1187 v4l2_std_id std
, u32 delsys
)
1189 struct r820t_priv
*priv
= fe
->tuner_priv
;
1193 tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
1196 if ((type
== V4L2_TUNER_ANALOG_TV
) && (std
== V4L2_STD_SECAM_LC
))
1197 lo_freq
= freq
- priv
->int_freq
;
1199 lo_freq
= freq
+ priv
->int_freq
;
1201 rc
= r820t_set_tv_standard(priv
, bw
, type
, std
, delsys
);
1205 rc
= r820t_set_mux(priv
, lo_freq
);
1209 rc
= r820t_set_gain_mode(priv
, true, 0);
1213 rc
= r820t_set_pll(priv
, lo_freq
);
1214 if (rc
< 0 || !priv
->has_lock
)
1217 rc
= r820t_sysfreq_sel(priv
, freq
, type
, std
, delsys
);
1221 tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
1222 __func__
, freq
, r820t_read_gain(priv
));
1227 tuner_dbg("%s: failed=%d\n", __func__
, rc
);
1232 * r820t standby logic
1235 static int r820t_standby(struct r820t_priv
*priv
)
1239 rc
= r820t_write_reg(priv
, 0x06, 0xb1);
1242 rc
= r820t_write_reg(priv
, 0x05, 0x03);
1245 rc
= r820t_write_reg(priv
, 0x07, 0x3a);
1248 rc
= r820t_write_reg(priv
, 0x08, 0x40);
1251 rc
= r820t_write_reg(priv
, 0x09, 0xc0);
1254 rc
= r820t_write_reg(priv
, 0x0a, 0x36);
1257 rc
= r820t_write_reg(priv
, 0x0c, 0x35);
1260 rc
= r820t_write_reg(priv
, 0x0f, 0x68);
1263 rc
= r820t_write_reg(priv
, 0x11, 0x03);
1266 rc
= r820t_write_reg(priv
, 0x17, 0xf4);
1269 rc
= r820t_write_reg(priv
, 0x19, 0x0c);
1271 /* Force initial calibration */
1278 * r820t device init logic
1281 static int r820t_xtal_check(struct r820t_priv
*priv
)
1286 /* Initialize the shadow registers */
1287 memcpy(priv
->regs
, r820t_init_array
, sizeof(r820t_init_array
));
1289 /* cap 30pF & Drive Low */
1290 rc
= r820t_write_reg_mask(priv
, 0x10, 0x0b, 0x0b);
1294 /* set pll autotune = 128kHz */
1295 rc
= r820t_write_reg_mask(priv
, 0x1a, 0x00, 0x0c);
1299 /* set manual initial reg = 111111; */
1300 rc
= r820t_write_reg_mask(priv
, 0x13, 0x7f, 0x7f);
1305 rc
= r820t_write_reg_mask(priv
, 0x13, 0x00, 0x40);
1309 /* Try several xtal capacitor alternatives */
1310 for (i
= 0; i
< ARRAY_SIZE(r820t_xtal_capacitor
); i
++) {
1311 rc
= r820t_write_reg_mask(priv
, 0x10,
1312 r820t_xtal_capacitor
[i
][0], 0x1b);
1318 rc
= r820_read(priv
, 0x00, data
, sizeof(data
));
1321 if ((!data
[2]) & 0x40)
1324 val
= data
[2] & 0x3f;
1326 if (priv
->cfg
->xtal
== 16000000 && (val
> 29 || val
< 23))
1333 if (i
== ARRAY_SIZE(r820t_xtal_capacitor
))
1336 return r820t_xtal_capacitor
[i
][1];
1340 * r820t frontend operations and tuner attach code
1342 * All driver locks and i2c control are only in this part of the code
1345 static int r820t_init(struct dvb_frontend
*fe
)
1347 struct r820t_priv
*priv
= fe
->tuner_priv
;
1351 tuner_dbg("%s:\n", __func__
);
1353 mutex_lock(&priv
->lock
);
1354 if (fe
->ops
.i2c_gate_ctrl
)
1355 fe
->ops
.i2c_gate_ctrl(fe
, 1);
1357 if ((priv
->cfg
->rafael_chip
== CHIP_R820T
) ||
1358 (priv
->cfg
->rafael_chip
== CHIP_R828S
) ||
1359 (priv
->cfg
->rafael_chip
== CHIP_R820C
)) {
1360 priv
->xtal_cap_sel
= XTAL_HIGH_CAP_0P
;
1362 for (i
= 0; i
< 3; i
++) {
1363 rc
= r820t_xtal_check(priv
);
1366 if (!i
|| rc
> xtal_cap
)
1369 priv
->xtal_cap_sel
= xtal_cap
;
1372 /* Initialize registers */
1373 rc
= r820t_write(priv
, 0x05,
1374 r820t_init_array
, sizeof(r820t_init_array
));
1377 if (fe
->ops
.i2c_gate_ctrl
)
1378 fe
->ops
.i2c_gate_ctrl(fe
, 0);
1379 mutex_unlock(&priv
->lock
);
1382 tuner_dbg("%s: failed=%d\n", __func__
, rc
);
1386 static int r820t_sleep(struct dvb_frontend
*fe
)
1388 struct r820t_priv
*priv
= fe
->tuner_priv
;
1391 tuner_dbg("%s:\n", __func__
);
1393 mutex_lock(&priv
->lock
);
1394 if (fe
->ops
.i2c_gate_ctrl
)
1395 fe
->ops
.i2c_gate_ctrl(fe
, 1);
1397 rc
= r820t_standby(priv
);
1399 if (fe
->ops
.i2c_gate_ctrl
)
1400 fe
->ops
.i2c_gate_ctrl(fe
, 0);
1401 mutex_unlock(&priv
->lock
);
1403 tuner_dbg("%s: failed=%d\n", __func__
, rc
);
1407 static int r820t_set_analog_freq(struct dvb_frontend
*fe
,
1408 struct analog_parameters
*p
)
1410 struct r820t_priv
*priv
= fe
->tuner_priv
;
1414 tuner_dbg("%s called\n", __func__
);
1416 /* if std is not defined, choose one */
1418 p
->std
= V4L2_STD_MN
;
1420 if ((p
->std
== V4L2_STD_PAL_M
) || (p
->std
== V4L2_STD_NTSC
))
1425 mutex_lock(&priv
->lock
);
1426 if (fe
->ops
.i2c_gate_ctrl
)
1427 fe
->ops
.i2c_gate_ctrl(fe
, 1);
1429 rc
= generic_set_freq(fe
, 62500l * p
->frequency
, bw
,
1430 V4L2_TUNER_ANALOG_TV
, p
->std
, SYS_UNDEFINED
);
1432 if (fe
->ops
.i2c_gate_ctrl
)
1433 fe
->ops
.i2c_gate_ctrl(fe
, 0);
1434 mutex_unlock(&priv
->lock
);
1439 static int r820t_set_params(struct dvb_frontend
*fe
)
1441 struct r820t_priv
*priv
= fe
->tuner_priv
;
1442 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
1446 tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
1447 __func__
, c
->delivery_system
, c
->frequency
, c
->bandwidth_hz
);
1449 mutex_lock(&priv
->lock
);
1450 if (fe
->ops
.i2c_gate_ctrl
)
1451 fe
->ops
.i2c_gate_ctrl(fe
, 1);
1453 bw
= (c
->bandwidth_hz
+ 500000) / 1000000;
1457 rc
= generic_set_freq(fe
, c
->frequency
, bw
,
1458 V4L2_TUNER_DIGITAL_TV
, 0, c
->delivery_system
);
1460 if (fe
->ops
.i2c_gate_ctrl
)
1461 fe
->ops
.i2c_gate_ctrl(fe
, 0);
1462 mutex_unlock(&priv
->lock
);
1465 tuner_dbg("%s: failed=%d\n", __func__
, rc
);
1469 static int r820t_signal(struct dvb_frontend
*fe
, u16
*strength
)
1471 struct r820t_priv
*priv
= fe
->tuner_priv
;
1474 mutex_lock(&priv
->lock
);
1475 if (fe
->ops
.i2c_gate_ctrl
)
1476 fe
->ops
.i2c_gate_ctrl(fe
, 1);
1478 if (priv
->has_lock
) {
1479 rc
= r820t_read_gain(priv
);
1483 /* A higher gain at LNA means a lower signal strength */
1484 *strength
= (45 - rc
) << 4 | 0xff;
1490 if (fe
->ops
.i2c_gate_ctrl
)
1491 fe
->ops
.i2c_gate_ctrl(fe
, 0);
1492 mutex_unlock(&priv
->lock
);
1494 tuner_dbg("%s: %s, gain=%d strength=%d\n",
1496 priv
->has_lock
? "PLL locked" : "no signal",
1502 static int r820t_get_if_frequency(struct dvb_frontend
*fe
, u32
*frequency
)
1504 struct r820t_priv
*priv
= fe
->tuner_priv
;
1506 tuner_dbg("%s:\n", __func__
);
1508 *frequency
= priv
->int_freq
;
1513 static int r820t_release(struct dvb_frontend
*fe
)
1515 struct r820t_priv
*priv
= fe
->tuner_priv
;
1517 tuner_dbg("%s:\n", __func__
);
1519 mutex_lock(&r820t_list_mutex
);
1522 hybrid_tuner_release_state(priv
);
1524 mutex_unlock(&r820t_list_mutex
);
1526 fe
->tuner_priv
= NULL
;
1528 kfree(fe
->tuner_priv
);
1533 static const struct dvb_tuner_ops r820t_tuner_ops
= {
1535 .name
= "Rafael Micro R820T",
1536 .frequency_min
= 42000000,
1537 .frequency_max
= 1002000000,
1540 .release
= r820t_release
,
1541 .sleep
= r820t_sleep
,
1542 .set_params
= r820t_set_params
,
1543 .set_analog_params
= r820t_set_analog_freq
,
1544 .get_if_frequency
= r820t_get_if_frequency
,
1545 .get_rf_strength
= r820t_signal
,
1548 struct dvb_frontend
*r820t_attach(struct dvb_frontend
*fe
,
1549 struct i2c_adapter
*i2c
,
1550 const struct r820t_config
*cfg
)
1552 struct r820t_priv
*priv
;
1557 mutex_lock(&r820t_list_mutex
);
1559 instance
= hybrid_tuner_request_state(struct r820t_priv
, priv
,
1560 hybrid_tuner_instance_list
,
1565 /* memory allocation failure */
1569 /* new tuner instance */
1572 mutex_init(&priv
->lock
);
1574 fe
->tuner_priv
= priv
;
1577 /* existing tuner instance */
1578 fe
->tuner_priv
= priv
;
1582 memcpy(&fe
->ops
.tuner_ops
, &r820t_tuner_ops
, sizeof(r820t_tuner_ops
));
1584 if (fe
->ops
.i2c_gate_ctrl
)
1585 fe
->ops
.i2c_gate_ctrl(fe
, 1);
1587 /* check if the tuner is there */
1588 rc
= r820_read(priv
, 0x00, data
, sizeof(data
));
1592 rc
= r820t_sleep(fe
);
1596 tuner_info("Rafael Micro r820t successfully identified\n");
1598 fe
->tuner_priv
= priv
;
1599 memcpy(&fe
->ops
.tuner_ops
, &r820t_tuner_ops
,
1600 sizeof(struct dvb_tuner_ops
));
1602 if (fe
->ops
.i2c_gate_ctrl
)
1603 fe
->ops
.i2c_gate_ctrl(fe
, 0);
1605 mutex_unlock(&r820t_list_mutex
);
1609 if (fe
->ops
.i2c_gate_ctrl
)
1610 fe
->ops
.i2c_gate_ctrl(fe
, 0);
1613 mutex_unlock(&r820t_list_mutex
);
1615 tuner_info("%s: failed=%d\n", __func__
, rc
);
1619 EXPORT_SYMBOL_GPL(r820t_attach
);
1621 MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
1622 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1623 MODULE_LICENSE("GPL");