drivers/media/video/mt9t112.c

   1 /*
   2  * mt9t112 Camera Driver
   3  *
   4  * Copyright (C) 2009 Renesas Solutions Corp.
   5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   6  *
   7  * Based on ov772x driver, mt9m111 driver,
   8  *
   9  * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
  10  * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
  11  * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  12  * Copyright (C) 2008 Magnus Damm
  13  * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/i2c.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/v4l2-mediabus.h>
  26 #include <linux/videodev2.h>
  27
  28 #include <media/mt9t112.h>
  29 #include <media/soc_camera.h>
  30 #include <media/v4l2-chip-ident.h>
  31 #include <media/v4l2-common.h>
  32
  33 /* you can check PLL/clock info */
  34 /* #define EXT_CLOCK 24000000 */
  35
  36 /************************************************************************
  37                         macro
  38 ************************************************************************/
  39 /*
  40  * frame size
  41  */
  42 #define MAX_WIDTH   2048
  43 #define MAX_HEIGHT  1536
  44
  45 #define VGA_WIDTH   640
  46 #define VGA_HEIGHT  480
  47
  48 /*
  49  * macro of read/write
  50  */
  51 #define ECHECKER(ret, x)                \
  52         do {                            \
  53                 (ret) = (x);            \
  54                 if ((ret) < 0)          \
  55                         return (ret);   \
  56         } while (0)
  57
  58 #define mt9t112_reg_write(ret, client, a, b) \
  59         ECHECKER(ret, __mt9t112_reg_write(client, a, b))
  60 #define mt9t112_mcu_write(ret, client, a, b) \
  61         ECHECKER(ret, __mt9t112_mcu_write(client, a, b))
  62
  63 #define mt9t112_reg_mask_set(ret, client, a, b, c) \
  64         ECHECKER(ret, __mt9t112_reg_mask_set(client, a, b, c))
  65 #define mt9t112_mcu_mask_set(ret, client, a, b, c) \
  66         ECHECKER(ret, __mt9t112_mcu_mask_set(client, a, b, c))
  67
  68 #define mt9t112_reg_read(ret, client, a) \
  69         ECHECKER(ret, __mt9t112_reg_read(client, a))
  70
  71 /*
  72  * Logical address
  73  */
  74 #define _VAR(id, offset, base)  (base | (id & 0x1f) << 10 | (offset & 0x3ff))
  75 #define VAR(id, offset)  _VAR(id, offset, 0x0000)
  76 #define VAR8(id, offset) _VAR(id, offset, 0x8000)
  77
  78 /************************************************************************
  79                         struct
  80 ************************************************************************/
  81 struct mt9t112_format {
  82         enum v4l2_mbus_pixelcode code;
  83         enum v4l2_colorspace colorspace;
  84         u16 fmt;
  85         u16 order;
  86 };
  87
  88 struct mt9t112_priv {
  89         struct v4l2_subdev               subdev;
  90         struct mt9t112_camera_info      *info;
  91         struct i2c_client               *client;
  92         struct v4l2_rect                 frame;
  93         const struct mt9t112_format     *format;
  94         int                              model;
  95         u32                              flags;
  96 /* for flags */
  97 #define INIT_DONE       (1 << 0)
  98 #define PCLK_RISING     (1 << 1)
  99 };
 100
 101 /************************************************************************
 102                         supported format
 103 ************************************************************************/
 104
 105 static const struct mt9t112_format mt9t112_cfmts[] = {
 106         {
 107                 .code           = V4L2_MBUS_FMT_UYVY8_2X8,
 108                 .colorspace     = V4L2_COLORSPACE_JPEG,
 109                 .fmt            = 1,
 110                 .order          = 0,
 111         }, {
 112                 .code           = V4L2_MBUS_FMT_VYUY8_2X8,
 113                 .colorspace     = V4L2_COLORSPACE_JPEG,
 114                 .fmt            = 1,
 115                 .order          = 1,
 116         }, {
 117                 .code           = V4L2_MBUS_FMT_YUYV8_2X8,
 118                 .colorspace     = V4L2_COLORSPACE_JPEG,
 119                 .fmt            = 1,
 120                 .order          = 2,
 121         }, {
 122                 .code           = V4L2_MBUS_FMT_YVYU8_2X8,
 123                 .colorspace     = V4L2_COLORSPACE_JPEG,
 124                 .fmt            = 1,
 125                 .order          = 3,
 126         }, {
 127                 .code           = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
 128                 .colorspace     = V4L2_COLORSPACE_SRGB,
 129                 .fmt            = 8,
 130                 .order          = 2,
 131         }, {
 132                 .code           = V4L2_MBUS_FMT_RGB565_2X8_LE,
 133                 .colorspace     = V4L2_COLORSPACE_SRGB,
 134                 .fmt            = 4,
 135                 .order          = 2,
 136         },
 137 };
 138
 139 /************************************************************************
 140                         general function
 141 ************************************************************************/
 142 static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client)
 143 {
 144         return container_of(i2c_get_clientdata(client),
 145                             struct mt9t112_priv,
 146                             subdev);
 147 }
 148
 149 static int __mt9t112_reg_read(const struct i2c_client *client, u16 command)
 150 {
 151         struct i2c_msg msg[2];
 152         u8 buf[2];
 153         int ret;
 154
 155         command = swab16(command);
 156
 157         msg[0].addr  = client->addr;
 158         msg[0].flags = 0;
 159         msg[0].len   = 2;
 160         msg[0].buf   = (u8 *)&command;
 161
 162         msg[1].addr  = client->addr;
 163         msg[1].flags = I2C_M_RD;
 164         msg[1].len   = 2;
 165         msg[1].buf   = buf;
 166
 167         /*
 168          * if return value of this function is < 0,
 169          * it mean error.
 170          * else, under 16bit is valid data.
 171          */
 172         ret = i2c_transfer(client->adapter, msg, 2);
 173         if (ret < 0)
 174                 return ret;
 175
 176         memcpy(&ret, buf, 2);
 177         return swab16(ret);
 178 }
 179
 180 static int __mt9t112_reg_write(const struct i2c_client *client,
 181                                u16 command, u16 data)
 182 {
 183         struct i2c_msg msg;
 184         u8 buf[4];
 185         int ret;
 186
 187         command = swab16(command);
 188         data = swab16(data);
 189
 190         memcpy(buf + 0, &command, 2);
 191         memcpy(buf + 2, &data,    2);
 192
 193         msg.addr  = client->addr;
 194         msg.flags = 0;
 195         msg.len   = 4;
 196         msg.buf   = buf;
 197
 198         /*
 199          * i2c_transfer return message length,
 200          * but this function should return 0 if correct case
 201          */
 202         ret = i2c_transfer(client->adapter, &msg, 1);
 203         if (ret >= 0)
 204                 ret = 0;
 205
 206         return ret;
 207 }
 208
 209 static int __mt9t112_reg_mask_set(const struct i2c_client *client,
 210                                   u16  command,
 211                                   u16  mask,
 212                                   u16  set)
 213 {
 214         int val = __mt9t112_reg_read(client, command);
 215         if (val < 0)
 216                 return val;
 217
 218         val &= ~mask;
 219         val |= set & mask;
 220
 221         return __mt9t112_reg_write(client, command, val);
 222 }
 223
 224 /* mcu access */
 225 static int __mt9t112_mcu_read(const struct i2c_client *client, u16 command)
 226 {
 227         int ret;
 228
 229         ret = __mt9t112_reg_write(client, 0x098E, command);
 230         if (ret < 0)
 231                 return ret;
 232
 233         return __mt9t112_reg_read(client, 0x0990);
 234 }
 235
 236 static int __mt9t112_mcu_write(const struct i2c_client *client,
 237                                u16 command, u16 data)
 238 {
 239         int ret;
 240
 241         ret = __mt9t112_reg_write(client, 0x098E, command);
 242         if (ret < 0)
 243                 return ret;
 244
 245         return __mt9t112_reg_write(client, 0x0990, data);
 246 }
 247
 248 static int __mt9t112_mcu_mask_set(const struct i2c_client *client,
 249                                   u16  command,
 250                                   u16  mask,
 251                                   u16  set)
 252 {
 253         int val = __mt9t112_mcu_read(client, command);
 254         if (val < 0)
 255                 return val;
 256
 257         val &= ~mask;
 258         val |= set & mask;
 259
 260         return __mt9t112_mcu_write(client, command, val);
 261 }
 262
 263 static int mt9t112_reset(const struct i2c_client *client)
 264 {
 265         int ret;
 266
 267         mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0001);
 268         msleep(1);
 269         mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0000);
 270
 271         return ret;
 272 }
 273
 274 #ifndef EXT_CLOCK
 275 #define CLOCK_INFO(a, b)
 276 #else
 277 #define CLOCK_INFO(a, b) mt9t112_clock_info(a, b)
 278 static int mt9t112_clock_info(const struct i2c_client *client, u32 ext)
 279 {
 280         int m, n, p1, p2, p3, p4, p5, p6, p7;
 281         u32 vco, clk;
 282         char *enable;
 283
 284         ext /= 1000; /* kbyte order */
 285
 286         mt9t112_reg_read(n, client, 0x0012);
 287         p1 = n & 0x000f;
 288         n = n >> 4;
 289         p2 = n & 0x000f;
 290         n = n >> 4;
 291         p3 = n & 0x000f;
 292
 293         mt9t112_reg_read(n, client, 0x002a);
 294         p4 = n & 0x000f;
 295         n = n >> 4;
 296         p5 = n & 0x000f;
 297         n = n >> 4;
 298         p6 = n & 0x000f;
 299
 300         mt9t112_reg_read(n, client, 0x002c);
 301         p7 = n & 0x000f;
 302
 303         mt9t112_reg_read(n, client, 0x0010);
 304         m = n & 0x00ff;
 305         n = (n >> 8) & 0x003f;
 306
 307         enable = ((6000 > ext) || (54000 < ext)) ? "X" : "";
 308         dev_dbg(&client->dev, "EXTCLK          : %10u K %s\n", ext, enable);
 309
 310         vco = 2 * m * ext / (n+1);
 311         enable = ((384000 > vco) || (768000 < vco)) ? "X" : "";
 312         dev_dbg(&client->dev, "VCO             : %10u K %s\n", vco, enable);
 313
 314         clk = vco / (p1+1) / (p2+1);
 315         enable = (96000 < clk) ? "X" : "";
 316         dev_dbg(&client->dev, "PIXCLK          : %10u K %s\n", clk, enable);
 317
 318         clk = vco / (p3+1);
 319         enable = (768000 < clk) ? "X" : "";
 320         dev_dbg(&client->dev, "MIPICLK         : %10u K %s\n", clk, enable);
 321
 322         clk = vco / (p6+1);
 323         enable = (96000 < clk) ? "X" : "";
 324         dev_dbg(&client->dev, "MCU CLK         : %10u K %s\n", clk, enable);
 325
 326         clk = vco / (p5+1);
 327         enable = (54000 < clk) ? "X" : "";
 328         dev_dbg(&client->dev, "SOC CLK         : %10u K %s\n", clk, enable);
 329
 330         clk = vco / (p4+1);
 331         enable = (70000 < clk) ? "X" : "";
 332         dev_dbg(&client->dev, "Sensor CLK      : %10u K %s\n", clk, enable);
 333
 334         clk = vco / (p7+1);
 335         dev_dbg(&client->dev, "External sensor : %10u K\n", clk);
 336
 337         clk = ext / (n+1);
 338         enable = ((2000 > clk) || (24000 < clk)) ? "X" : "";
 339         dev_dbg(&client->dev, "PFD             : %10u K %s\n", clk, enable);
 340
 341         return 0;
 342 }
 343 #endif
 344
 345 static void mt9t112_frame_check(u32 *width, u32 *height, u32 *left, u32 *top)
 346 {
 347         soc_camera_limit_side(left, width, 0, 0, MAX_WIDTH);
 348         soc_camera_limit_side(top, height, 0, 0, MAX_HEIGHT);
 349 }
 350
 351 static int mt9t112_set_a_frame_size(const struct i2c_client *client,
 352                                    u16 width,
 353                                    u16 height)
 354 {
 355         int ret;
 356         u16 wstart = (MAX_WIDTH - width) / 2;
 357         u16 hstart = (MAX_HEIGHT - height) / 2;
 358
 359         /* (Context A) Image Width/Height */
 360         mt9t112_mcu_write(ret, client, VAR(26, 0), width);
 361         mt9t112_mcu_write(ret, client, VAR(26, 2), height);
 362
 363         /* (Context A) Output Width/Height */
 364         mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width);
 365         mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height);
 366
 367         /* (Context A) Start Row/Column */
 368         mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart);
 369         mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart);
 370
 371         /* (Context A) End Row/Column */
 372         mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart);
 373         mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width  + wstart);
 374
 375         mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
 376
 377         return ret;
 378 }
 379
 380 static int mt9t112_set_pll_dividers(const struct i2c_client *client,
 381                                     u8 m, u8 n,
 382                                     u8 p1, u8 p2, u8 p3,
 383                                     u8 p4, u8 p5, u8 p6,
 384                                     u8 p7)
 385 {
 386         int ret;
 387         u16 val;
 388
 389         /* N/M */
 390         val = (n << 8) |
 391               (m << 0);
 392         mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val);
 393
 394         /* P1/P2/P3 */
 395         val = ((p3 & 0x0F) << 8) |
 396               ((p2 & 0x0F) << 4) |
 397               ((p1 & 0x0F) << 0);
 398         mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val);
 399
 400         /* P4/P5/P6 */
 401         val = (0x7         << 12) |
 402               ((p6 & 0x0F) <<  8) |
 403               ((p5 & 0x0F) <<  4) |
 404               ((p4 & 0x0F) <<  0);
 405         mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val);
 406
 407         /* P7 */
 408         val = (0x1         << 12) |
 409               ((p7 & 0x0F) <<  0);
 410         mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val);
 411
 412         return ret;
 413 }
 414
 415 static int mt9t112_init_pll(const struct i2c_client *client)
 416 {
 417         struct mt9t112_priv *priv = to_mt9t112(client);
 418         int data, i, ret;
 419
 420         mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001);
 421
 422         /* PLL control: BYPASS PLL = 8517 */
 423         mt9t112_reg_write(ret, client, 0x0014, 0x2145);
 424
 425         /* Replace these registers when new timing parameters are generated */
 426         mt9t112_set_pll_dividers(client,
 427                                  priv->info->divider.m,
 428                                  priv->info->divider.n,
 429                                  priv->info->divider.p1,
 430                                  priv->info->divider.p2,
 431                                  priv->info->divider.p3,
 432                                  priv->info->divider.p4,
 433                                  priv->info->divider.p5,
 434                                  priv->info->divider.p6,
 435                                  priv->info->divider.p7);
 436
 437         /*
 438          * TEST_BYPASS  on
 439          * PLL_ENABLE   on
 440          * SEL_LOCK_DET on
 441          * TEST_BYPASS  off
 442          */
 443         mt9t112_reg_write(ret, client, 0x0014, 0x2525);
 444         mt9t112_reg_write(ret, client, 0x0014, 0x2527);
 445         mt9t112_reg_write(ret, client, 0x0014, 0x3427);
 446         mt9t112_reg_write(ret, client, 0x0014, 0x3027);
 447
 448         mdelay(10);
 449
 450         /*
 451          * PLL_BYPASS off
 452          * Reference clock count
 453          * I2C Master Clock Divider
 454          */
 455         mt9t112_reg_write(ret, client, 0x0014, 0x3046);
 456         mt9t112_reg_write(ret, client, 0x0022, 0x0190);
 457         mt9t112_reg_write(ret, client, 0x3B84, 0x0212);
 458
 459         /* External sensor clock is PLL bypass */
 460         mt9t112_reg_write(ret, client, 0x002E, 0x0500);
 461
 462         mt9t112_reg_mask_set(ret, client, 0x0018, 0x0002, 0x0002);
 463         mt9t112_reg_mask_set(ret, client, 0x3B82, 0x0004, 0x0004);
 464
 465         /* MCU disabled */
 466         mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0x0004);
 467
 468         /* out of standby */
 469         mt9t112_reg_mask_set(ret, client, 0x0018, 0x0001, 0);
 470
 471         mdelay(50);
 472
 473         /*
 474          * Standby Workaround
 475          * Disable Secondary I2C Pads
 476          */
 477         mt9t112_reg_write(ret, client, 0x0614, 0x0001);
 478         mdelay(1);
 479         mt9t112_reg_write(ret, client, 0x0614, 0x0001);
 480         mdelay(1);
 481         mt9t112_reg_write(ret, client, 0x0614, 0x0001);
 482         mdelay(1);
 483         mt9t112_reg_write(ret, client, 0x0614, 0x0001);
 484         mdelay(1);
 485         mt9t112_reg_write(ret, client, 0x0614, 0x0001);
 486         mdelay(1);
 487         mt9t112_reg_write(ret, client, 0x0614, 0x0001);
 488         mdelay(1);
 489
 490         /* poll to verify out of standby. Must Poll this bit */
 491         for (i = 0; i < 100; i++) {
 492                 mt9t112_reg_read(data, client, 0x0018);
 493                 if (!(0x4000 & data))
 494                         break;
 495
 496                 mdelay(10);
 497         }
 498
 499         return ret;
 500 }
 501
 502 static int mt9t112_init_setting(const struct i2c_client *client)
 503 {
 504
 505         int ret;
 506
 507         /* Adaptive Output Clock (A) */
 508         mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000);
 509
 510         /* Read Mode (A) */
 511         mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024);
 512
 513         /* Fine Correction (A) */
 514         mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC);
 515
 516         /* Fine IT Min (A) */
 517         mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1);
 518
 519         /* Fine IT Max Margin (A) */
 520         mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF);
 521
 522         /* Base Frame Lines (A) */
 523         mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D);
 524
 525         /* Min Line Length (A) */
 526         mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a);
 527
 528         /* Line Length (A) */
 529         mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0);
 530
 531         /* Adaptive Output Clock (B) */
 532         mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000);
 533
 534         /* Row Start (B) */
 535         mt9t112_mcu_write(ret, client, VAR(18, 74), 0x004);
 536
 537         /* Column Start (B) */
 538         mt9t112_mcu_write(ret, client, VAR(18, 76), 0x004);
 539
 540         /* Row End (B) */
 541         mt9t112_mcu_write(ret, client, VAR(18, 78), 0x60B);
 542
 543         /* Column End (B) */
 544         mt9t112_mcu_write(ret, client, VAR(18, 80), 0x80B);
 545
 546         /* Fine Correction (B) */
 547         mt9t112_mcu_write(ret, client, VAR(18, 87), 0x008C);
 548
 549         /* Fine IT Min (B) */
 550         mt9t112_mcu_write(ret, client, VAR(18, 89), 0x01F1);
 551
 552         /* Fine IT Max Margin (B) */
 553         mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF);
 554
 555         /* Base Frame Lines (B) */
 556         mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668);
 557
 558         /* Min Line Length (B) */
 559         mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0);
 560
 561         /* Line Length (B) */
 562         mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0);
 563
 564         /*
 565          * Flicker Dectection registers
 566          * This section should be replaced whenever new Timing file is generated
 567          * All the following registers need to be replaced
 568          * Following registers are generated from Register Wizard but user can
 569          * modify them. For detail see auto flicker detection tuning
 570          */
 571
 572         /* FD_FDPERIOD_SELECT */
 573         mt9t112_mcu_write(ret, client, VAR8(8, 5), 0x01);
 574
 575         /* PRI_B_CONFIG_FD_ALGO_RUN */
 576         mt9t112_mcu_write(ret, client, VAR(27, 17), 0x0003);
 577
 578         /* PRI_A_CONFIG_FD_ALGO_RUN */
 579         mt9t112_mcu_write(ret, client, VAR(26, 17), 0x0003);
 580
 581         /*
 582          * AFD range detection tuning registers
 583          */
 584
 585         /* search_f1_50 */
 586         mt9t112_mcu_write(ret, client, VAR8(18, 165), 0x25);
 587
 588         /* search_f2_50 */
 589         mt9t112_mcu_write(ret, client, VAR8(18, 166), 0x28);
 590
 591         /* search_f1_60 */
 592         mt9t112_mcu_write(ret, client, VAR8(18, 167), 0x2C);
 593
 594         /* search_f2_60 */
 595         mt9t112_mcu_write(ret, client, VAR8(18, 168), 0x2F);
 596
 597         /* period_50Hz (A) */
 598         mt9t112_mcu_write(ret, client, VAR8(18, 68), 0xBA);
 599
 600         /* secret register by aptina */
 601         /* period_50Hz (A MSB) */
 602         mt9t112_mcu_write(ret, client, VAR8(18, 303), 0x00);
 603
 604         /* period_60Hz (A) */
 605         mt9t112_mcu_write(ret, client, VAR8(18, 69), 0x9B);
 606
 607         /* secret register by aptina */
 608         /* period_60Hz (A MSB) */
 609         mt9t112_mcu_write(ret, client, VAR8(18, 301), 0x00);
 610
 611         /* period_50Hz (B) */
 612         mt9t112_mcu_write(ret, client, VAR8(18, 140), 0x82);
 613
 614         /* secret register by aptina */
 615         /* period_50Hz (B) MSB */
 616         mt9t112_mcu_write(ret, client, VAR8(18, 304), 0x00);
 617
 618         /* period_60Hz (B) */
 619         mt9t112_mcu_write(ret, client, VAR8(18, 141), 0x6D);
 620
 621         /* secret register by aptina */
 622         /* period_60Hz (B) MSB */
 623         mt9t112_mcu_write(ret, client, VAR8(18, 302), 0x00);
 624
 625         /* FD Mode */
 626         mt9t112_mcu_write(ret, client, VAR8(8, 2), 0x10);
 627
 628         /* Stat_min */
 629         mt9t112_mcu_write(ret, client, VAR8(8, 9), 0x02);
 630
 631         /* Stat_max */
 632         mt9t112_mcu_write(ret, client, VAR8(8, 10), 0x03);
 633
 634         /* Min_amplitude */
 635         mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A);
 636
 637         /* RX FIFO Watermark (A) */
 638         mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014);
 639
 640         /* RX FIFO Watermark (B) */
 641         mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014);
 642
 643         /* MCLK: 16MHz
 644          * PCLK: 73MHz
 645          * CorePixCLK: 36.5 MHz
 646          */
 647         mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133);
 648         mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110);
 649         mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130);
 650         mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108);
 651
 652         mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27);
 653         mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30);
 654         mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32);
 655         mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35);
 656
 657         return ret;
 658 }
 659
 660 static int mt9t112_auto_focus_setting(const struct i2c_client *client)
 661 {
 662         int ret;
 663
 664         mt9t112_mcu_write(ret, client, VAR(12, 13),     0x000F);
 665         mt9t112_mcu_write(ret, client, VAR(12, 23),     0x0F0F);
 666         mt9t112_mcu_write(ret, client, VAR8(1, 0),      0x06);
 667
 668         mt9t112_reg_write(ret, client, 0x0614, 0x0000);
 669
 670         mt9t112_mcu_write(ret, client, VAR8(1, 0),      0x05);
 671         mt9t112_mcu_write(ret, client, VAR8(12, 2),     0x02);
 672         mt9t112_mcu_write(ret, client, VAR(12, 3),      0x0002);
 673         mt9t112_mcu_write(ret, client, VAR(17, 3),      0x8001);
 674         mt9t112_mcu_write(ret, client, VAR(17, 11),     0x0025);
 675         mt9t112_mcu_write(ret, client, VAR(17, 13),     0x0193);
 676         mt9t112_mcu_write(ret, client, VAR8(17, 33),    0x18);
 677         mt9t112_mcu_write(ret, client, VAR8(1, 0),      0x05);
 678
 679         return ret;
 680 }
 681
 682 static int mt9t112_auto_focus_trigger(const struct i2c_client *client)
 683 {
 684         int ret;
 685
 686         mt9t112_mcu_write(ret, client, VAR8(12, 25), 0x01);
 687
 688         return ret;
 689 }
 690
 691 static int mt9t112_init_camera(const struct i2c_client *client)
 692 {
 693         int ret;
 694
 695         ECHECKER(ret, mt9t112_reset(client));
 696
 697         ECHECKER(ret, mt9t112_init_pll(client));
 698
 699         ECHECKER(ret, mt9t112_init_setting(client));
 700
 701         ECHECKER(ret, mt9t112_auto_focus_setting(client));
 702
 703         mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0);
 704
 705         /* Analog setting B */
 706         mt9t112_reg_write(ret, client, 0x3084, 0x2409);
 707         mt9t112_reg_write(ret, client, 0x3092, 0x0A49);
 708         mt9t112_reg_write(ret, client, 0x3094, 0x4949);
 709         mt9t112_reg_write(ret, client, 0x3096, 0x4950);
 710
 711         /*
 712          * Disable adaptive clock
 713          * PRI_A_CONFIG_JPEG_OB_TX_CONTROL_VAR
 714          * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR
 715          */
 716         mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E);
 717         mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E);
 718
 719         /* Configure STatus in Status_before_length Format and enable header */
 720         /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */
 721         mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4);
 722
 723         /* Enable JPEG in context B */
 724         /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */
 725         mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01);
 726
 727         /* Disable Dac_TXLO */
 728         mt9t112_reg_write(ret, client, 0x316C, 0x350F);
 729
 730         /* Set max slew rates */
 731         mt9t112_reg_write(ret, client, 0x1E, 0x777);
 732
 733         return ret;
 734 }
 735
 736 /************************************************************************
 737                         v4l2_subdev_core_ops
 738 ************************************************************************/
 739 static int mt9t112_g_chip_ident(struct v4l2_subdev *sd,
 740                                 struct v4l2_dbg_chip_ident *id)
 741 {
 742         struct i2c_client *client = v4l2_get_subdevdata(sd);
 743         struct mt9t112_priv *priv = to_mt9t112(client);
 744
 745         id->ident    = priv->model;
 746         id->revision = 0;
 747
 748         return 0;
 749 }
 750
 751 #ifdef CONFIG_VIDEO_ADV_DEBUG
 752 static int mt9t112_g_register(struct v4l2_subdev *sd,
 753                               struct v4l2_dbg_register *reg)
 754 {
 755         struct i2c_client *client = v4l2_get_subdevdata(sd);
 756         int                ret;
 757
 758         reg->size = 2;
 759         mt9t112_reg_read(ret, client, reg->reg);
 760
 761         reg->val = (__u64)ret;
 762
 763         return 0;
 764 }
 765
 766 static int mt9t112_s_register(struct v4l2_subdev *sd,
 767                               struct v4l2_dbg_register *reg)
 768 {
 769         struct i2c_client *client = v4l2_get_subdevdata(sd);
 770         int ret;
 771
 772         mt9t112_reg_write(ret, client, reg->reg, reg->val);
 773
 774         return ret;
 775 }
 776 #endif
 777
 778 static struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = {
 779         .g_chip_ident   = mt9t112_g_chip_ident,
 780 #ifdef CONFIG_VIDEO_ADV_DEBUG
 781         .g_register     = mt9t112_g_register,
 782         .s_register     = mt9t112_s_register,
 783 #endif
 784 };
 785
 786
 787 /************************************************************************
 788                         v4l2_subdev_video_ops
 789 ************************************************************************/
 790 static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable)
 791 {
 792         struct i2c_client *client = v4l2_get_subdevdata(sd);
 793         struct mt9t112_priv *priv = to_mt9t112(client);
 794         int ret = 0;
 795
 796         if (!enable) {
 797                 /* FIXME
 798                  *
 799                  * If user selected large output size,
 800                  * and used it long time,
 801                  * mt9t112 camera will be very warm.
 802                  *
 803                  * But current driver can not stop mt9t112 camera.
 804                  * So, set small size here to solve this problem.
 805                  */
 806                 mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT);
 807                 return ret;
 808         }
 809
 810         if (!(priv->flags & INIT_DONE)) {
 811                 u16 param = PCLK_RISING & priv->flags ? 0x0001 : 0x0000;
 812
 813                 ECHECKER(ret, mt9t112_init_camera(client));
 814
 815                 /* Invert PCLK (Data sampled on falling edge of pixclk) */
 816                 mt9t112_reg_write(ret, client, 0x3C20, param);
 817
 818                 mdelay(5);
 819
 820                 priv->flags |= INIT_DONE;
 821         }
 822
 823         mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt);
 824         mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order);
 825         mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
 826
 827         mt9t112_set_a_frame_size(client,
 828                                  priv->frame.width,
 829                                  priv->frame.height);
 830
 831         ECHECKER(ret, mt9t112_auto_focus_trigger(client));
 832
 833         dev_dbg(&client->dev, "format : %d\n", priv->format->code);
 834         dev_dbg(&client->dev, "size   : %d x %d\n",
 835                 priv->frame.width,
 836                 priv->frame.height);
 837
 838         CLOCK_INFO(client, EXT_CLOCK);
 839
 840         return ret;
 841 }
 842
 843 static int mt9t112_set_params(struct mt9t112_priv *priv,
 844                               const struct v4l2_rect *rect,
 845                               enum v4l2_mbus_pixelcode code)
 846 {
 847         int i;
 848
 849         /*
 850          * get color format
 851          */
 852         for (i = 0; i < ARRAY_SIZE(mt9t112_cfmts); i++)
 853                 if (mt9t112_cfmts[i].code == code)
 854                         break;
 855
 856         if (i == ARRAY_SIZE(mt9t112_cfmts))
 857                 return -EINVAL;
 858
 859         priv->frame  = *rect;
 860
 861         /*
 862          * frame size check
 863          */
 864         mt9t112_frame_check(&priv->frame.width, &priv->frame.height,
 865                             &priv->frame.left, &priv->frame.top);
 866
 867         priv->format = mt9t112_cfmts + i;
 868
 869         return 0;
 870 }
 871
 872 static int mt9t112_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
 873 {
 874         a->bounds.left                  = 0;
 875         a->bounds.top                   = 0;
 876         a->bounds.width                 = MAX_WIDTH;
 877         a->bounds.height                = MAX_HEIGHT;
 878         a->defrect.left                 = 0;
 879         a->defrect.top                  = 0;
 880         a->defrect.width                = VGA_WIDTH;
 881         a->defrect.height               = VGA_HEIGHT;
 882         a->type                         = V4L2_BUF_TYPE_VIDEO_CAPTURE;
 883         a->pixelaspect.numerator        = 1;
 884         a->pixelaspect.denominator      = 1;
 885
 886         return 0;
 887 }
 888
 889 static int mt9t112_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
 890 {
 891         struct i2c_client *client = v4l2_get_subdevdata(sd);
 892         struct mt9t112_priv *priv = to_mt9t112(client);
 893
 894         a->c    = priv->frame;
 895         a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
 896
 897         return 0;
 898 }
 899
 900 static int mt9t112_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
 901 {
 902         struct i2c_client *client = v4l2_get_subdevdata(sd);
 903         struct mt9t112_priv *priv = to_mt9t112(client);
 904         struct v4l2_rect *rect = &a->c;
 905
 906         return mt9t112_set_params(priv, rect, priv->format->code);
 907 }
 908
 909 static int mt9t112_g_fmt(struct v4l2_subdev *sd,
 910                          struct v4l2_mbus_framefmt *mf)
 911 {
 912         struct i2c_client *client = v4l2_get_subdevdata(sd);
 913         struct mt9t112_priv *priv = to_mt9t112(client);
 914
 915         mf->width       = priv->frame.width;
 916         mf->height      = priv->frame.height;
 917         mf->colorspace  = priv->format->colorspace;
 918         mf->code        = priv->format->code;
 919         mf->field       = V4L2_FIELD_NONE;
 920
 921         return 0;
 922 }
 923
 924 static int mt9t112_s_fmt(struct v4l2_subdev *sd,
 925                          struct v4l2_mbus_framefmt *mf)
 926 {
 927         struct i2c_client *client = v4l2_get_subdevdata(sd);
 928         struct mt9t112_priv *priv = to_mt9t112(client);
 929         struct v4l2_rect rect = {
 930                 .width = mf->width,
 931                 .height = mf->height,
 932                 .left = priv->frame.left,
 933                 .top = priv->frame.top,
 934         };
 935         int ret;
 936
 937         ret = mt9t112_set_params(priv, &rect, mf->code);
 938
 939         if (!ret)
 940                 mf->colorspace = priv->format->colorspace;
 941
 942         return ret;
 943 }
 944
 945 static int mt9t112_try_fmt(struct v4l2_subdev *sd,
 946                            struct v4l2_mbus_framefmt *mf)
 947 {
 948         unsigned int top, left;
 949         int i;
 950
 951         for (i = 0; i < ARRAY_SIZE(mt9t112_cfmts); i++)
 952                 if (mt9t112_cfmts[i].code == mf->code)
 953                         break;
 954
 955         if (i == ARRAY_SIZE(mt9t112_cfmts)) {
 956                 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
 957                 mf->colorspace = V4L2_COLORSPACE_JPEG;
 958         } else {
 959                 mf->colorspace  = mt9t112_cfmts[i].colorspace;
 960         }
 961
 962         mt9t112_frame_check(&mf->width, &mf->height, &left, &top);
 963
 964         mf->field = V4L2_FIELD_NONE;
 965
 966         return 0;
 967 }
 968
 969 static int mt9t112_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
 970                            enum v4l2_mbus_pixelcode *code)
 971 {
 972         if (index >= ARRAY_SIZE(mt9t112_cfmts))
 973                 return -EINVAL;
 974
 975         *code = mt9t112_cfmts[index].code;
 976
 977         return 0;
 978 }
 979
 980 static int mt9t112_g_mbus_config(struct v4l2_subdev *sd,
 981                                  struct v4l2_mbus_config *cfg)
 982 {
 983         struct i2c_client *client = v4l2_get_subdevdata(sd);
 984         struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
 985
 986         cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
 987                 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_DATA_ACTIVE_HIGH |
 988                 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING;
 989         cfg->type = V4L2_MBUS_PARALLEL;
 990         cfg->flags = soc_camera_apply_board_flags(icl, cfg);
 991
 992         return 0;
 993 }
 994
 995 static int mt9t112_s_mbus_config(struct v4l2_subdev *sd,
 996                                  const struct v4l2_mbus_config *cfg)
 997 {
 998         struct i2c_client *client = v4l2_get_subdevdata(sd);
 999         struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1000         struct mt9t112_priv *priv = to_mt9t112(client);
1001
1002         if (soc_camera_apply_board_flags(icl, cfg) & V4L2_MBUS_PCLK_SAMPLE_RISING)
1003                 priv->flags |= PCLK_RISING;
1004
1005         return 0;
1006 }
1007
1008 static struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = {
1009         .s_stream       = mt9t112_s_stream,
1010         .g_mbus_fmt     = mt9t112_g_fmt,
1011         .s_mbus_fmt     = mt9t112_s_fmt,
1012         .try_mbus_fmt   = mt9t112_try_fmt,
1013         .cropcap        = mt9t112_cropcap,
1014         .g_crop         = mt9t112_g_crop,
1015         .s_crop         = mt9t112_s_crop,
1016         .enum_mbus_fmt  = mt9t112_enum_fmt,
1017         .g_mbus_config  = mt9t112_g_mbus_config,
1018         .s_mbus_config  = mt9t112_s_mbus_config,
1019 };
1020
1021 /************************************************************************
1022                         i2c driver
1023 ************************************************************************/
1024 static struct v4l2_subdev_ops mt9t112_subdev_ops = {
1025         .core   = &mt9t112_subdev_core_ops,
1026         .video  = &mt9t112_subdev_video_ops,
1027 };
1028
1029 static int mt9t112_camera_probe(struct i2c_client *client)
1030 {
1031         struct mt9t112_priv *priv = to_mt9t112(client);
1032         const char          *devname;
1033         int                  chipid;
1034
1035         /*
1036          * check and show chip ID
1037          */
1038         mt9t112_reg_read(chipid, client, 0x0000);
1039
1040         switch (chipid) {
1041         case 0x2680:
1042                 devname = "mt9t111";
1043                 priv->model = V4L2_IDENT_MT9T111;
1044                 break;
1045         case 0x2682:
1046                 devname = "mt9t112";
1047                 priv->model = V4L2_IDENT_MT9T112;
1048                 break;
1049         default:
1050                 dev_err(&client->dev, "Product ID error %04x\n", chipid);
1051                 return -ENODEV;
1052         }
1053
1054         dev_info(&client->dev, "%s chip ID %04x\n", devname, chipid);
1055
1056         return 0;
1057 }
1058
1059 static int mt9t112_probe(struct i2c_client *client,
1060                          const struct i2c_device_id *did)
1061 {
1062         struct mt9t112_priv *priv;
1063         struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1064         struct v4l2_rect rect = {
1065                 .width = VGA_WIDTH,
1066                 .height = VGA_HEIGHT,
1067                 .left = (MAX_WIDTH - VGA_WIDTH) / 2,
1068                 .top = (MAX_HEIGHT - VGA_HEIGHT) / 2,
1069         };
1070         int ret;
1071
1072         if (!icl || !icl->priv) {
1073                 dev_err(&client->dev, "mt9t112: missing platform data!\n");
1074                 return -EINVAL;
1075         }
1076
1077         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1078         if (!priv)
1079                 return -ENOMEM;
1080
1081         priv->info = icl->priv;
1082
1083         v4l2_i2c_subdev_init(&priv->subdev, client, &mt9t112_subdev_ops);
1084
1085         ret = mt9t112_camera_probe(client);
1086         if (ret)
1087                 kfree(priv);
1088
1089         /* Cannot fail: using the default supported pixel code */
1090         mt9t112_set_params(priv, &rect, V4L2_MBUS_FMT_UYVY8_2X8);
1091
1092         return ret;
1093 }
1094
1095 static int mt9t112_remove(struct i2c_client *client)
1096 {
1097         struct mt9t112_priv *priv = to_mt9t112(client);
1098
1099         kfree(priv);
1100         return 0;
1101 }
1102
1103 static const struct i2c_device_id mt9t112_id[] = {
1104         { "mt9t112", 0 },
1105         { }
1106 };
1107 MODULE_DEVICE_TABLE(i2c, mt9t112_id);
1108
1109 static struct i2c_driver mt9t112_i2c_driver = {
1110         .driver = {
1111                 .name = "mt9t112",
1112         },
1113         .probe    = mt9t112_probe,
1114         .remove   = mt9t112_remove,
1115         .id_table = mt9t112_id,
1116 };
1117
1118 /************************************************************************
1119                         module function
1120 ************************************************************************/
1121 static int __init mt9t112_module_init(void)
1122 {
1123         return i2c_add_driver(&mt9t112_i2c_driver);
1124 }
1125
1126 static void __exit mt9t112_module_exit(void)
1127 {
1128         i2c_del_driver(&mt9t112_i2c_driver);
1129 }
1130
1131 module_init(mt9t112_module_init);
1132 module_exit(mt9t112_module_exit);
1133
1134 MODULE_DESCRIPTION("SoC Camera driver for mt9t112");
1135 MODULE_AUTHOR("Kuninori Morimoto");
1136 MODULE_LICENSE("GPL v2");