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ecd83faf90380fbec2389e53b725ac605df2903f
[deliverable/linux.git] / drivers / media / video / mx2_camera.c
1 /*
2 * V4L2 Driver for i.MX27/i.MX25 camera host
3 *
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/errno.h>
21 #include <linux/fs.h>
22 #include <linux/gcd.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/moduleparam.h>
27 #include <linux/time.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/mutex.h>
31 #include <linux/clk.h>
32
33 #include <media/v4l2-common.h>
34 #include <media/v4l2-dev.h>
35 #include <media/videobuf2-core.h>
36 #include <media/videobuf2-dma-contig.h>
37 #include <media/soc_camera.h>
38 #include <media/soc_mediabus.h>
39
40 #include <linux/videodev2.h>
41
42 #include <mach/mx2_cam.h>
43 #include <mach/hardware.h>
44
45 #include <asm/dma.h>
46
47 #define MX2_CAM_DRV_NAME "mx2-camera"
48 #define MX2_CAM_VERSION "0.0.6"
49 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
50
51 /* reset values */
52 #define CSICR1_RESET_VAL 0x40000800
53 #define CSICR2_RESET_VAL 0x0
54 #define CSICR3_RESET_VAL 0x0
55
56 /* csi control reg 1 */
57 #define CSICR1_SWAP16_EN (1 << 31)
58 #define CSICR1_EXT_VSYNC (1 << 30)
59 #define CSICR1_EOF_INTEN (1 << 29)
60 #define CSICR1_PRP_IF_EN (1 << 28)
61 #define CSICR1_CCIR_MODE (1 << 27)
62 #define CSICR1_COF_INTEN (1 << 26)
63 #define CSICR1_SF_OR_INTEN (1 << 25)
64 #define CSICR1_RF_OR_INTEN (1 << 24)
65 #define CSICR1_STATFF_LEVEL (3 << 22)
66 #define CSICR1_STATFF_INTEN (1 << 21)
67 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
68 #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
69 #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
70 #define CSICR1_RXFF_INTEN (1 << 18)
71 #define CSICR1_SOF_POL (1 << 17)
72 #define CSICR1_SOF_INTEN (1 << 16)
73 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
74 #define CSICR1_HSYNC_POL (1 << 11)
75 #define CSICR1_CCIR_EN (1 << 10)
76 #define CSICR1_MCLKEN (1 << 9)
77 #define CSICR1_FCC (1 << 8)
78 #define CSICR1_PACK_DIR (1 << 7)
79 #define CSICR1_CLR_STATFIFO (1 << 6)
80 #define CSICR1_CLR_RXFIFO (1 << 5)
81 #define CSICR1_GCLK_MODE (1 << 4)
82 #define CSICR1_INV_DATA (1 << 3)
83 #define CSICR1_INV_PCLK (1 << 2)
84 #define CSICR1_REDGE (1 << 1)
85
86 #define SHIFT_STATFF_LEVEL 22
87 #define SHIFT_RXFF_LEVEL 19
88 #define SHIFT_MCLKDIV 12
89
90 /* control reg 3 */
91 #define CSICR3_FRMCNT (0xFFFF << 16)
92 #define CSICR3_FRMCNT_RST (1 << 15)
93 #define CSICR3_DMA_REFLASH_RFF (1 << 14)
94 #define CSICR3_DMA_REFLASH_SFF (1 << 13)
95 #define CSICR3_DMA_REQ_EN_RFF (1 << 12)
96 #define CSICR3_DMA_REQ_EN_SFF (1 << 11)
97 #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
98 #define CSICR3_CSI_SUP (1 << 3)
99 #define CSICR3_ZERO_PACK_EN (1 << 2)
100 #define CSICR3_ECC_INT_EN (1 << 1)
101 #define CSICR3_ECC_AUTO_EN (1 << 0)
102
103 #define SHIFT_FRMCNT 16
104
105 /* csi status reg */
106 #define CSISR_SFF_OR_INT (1 << 25)
107 #define CSISR_RFF_OR_INT (1 << 24)
108 #define CSISR_STATFF_INT (1 << 21)
109 #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
110 #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
111 #define CSISR_RXFF_INT (1 << 18)
112 #define CSISR_EOF_INT (1 << 17)
113 #define CSISR_SOF_INT (1 << 16)
114 #define CSISR_F2_INT (1 << 15)
115 #define CSISR_F1_INT (1 << 14)
116 #define CSISR_COF_INT (1 << 13)
117 #define CSISR_ECC_INT (1 << 1)
118 #define CSISR_DRDY (1 << 0)
119
120 #define CSICR1 0x00
121 #define CSICR2 0x04
122 #define CSISR (cpu_is_mx27() ? 0x08 : 0x18)
123 #define CSISTATFIFO 0x0c
124 #define CSIRFIFO 0x10
125 #define CSIRXCNT 0x14
126 #define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08)
127 #define CSIDMASA_STATFIFO 0x20
128 #define CSIDMATA_STATFIFO 0x24
129 #define CSIDMASA_FB1 0x28
130 #define CSIDMASA_FB2 0x2c
131 #define CSIFBUF_PARA 0x30
132 #define CSIIMAG_PARA 0x34
133
134 /* EMMA PrP */
135 #define PRP_CNTL 0x00
136 #define PRP_INTR_CNTL 0x04
137 #define PRP_INTRSTATUS 0x08
138 #define PRP_SOURCE_Y_PTR 0x0c
139 #define PRP_SOURCE_CB_PTR 0x10
140 #define PRP_SOURCE_CR_PTR 0x14
141 #define PRP_DEST_RGB1_PTR 0x18
142 #define PRP_DEST_RGB2_PTR 0x1c
143 #define PRP_DEST_Y_PTR 0x20
144 #define PRP_DEST_CB_PTR 0x24
145 #define PRP_DEST_CR_PTR 0x28
146 #define PRP_SRC_FRAME_SIZE 0x2c
147 #define PRP_DEST_CH1_LINE_STRIDE 0x30
148 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
149 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
150 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
151 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
152 #define PRP_SRC_LINE_STRIDE 0x44
153 #define PRP_CSC_COEF_012 0x48
154 #define PRP_CSC_COEF_345 0x4c
155 #define PRP_CSC_COEF_678 0x50
156 #define PRP_CH1_RZ_HORI_COEF1 0x54
157 #define PRP_CH1_RZ_HORI_COEF2 0x58
158 #define PRP_CH1_RZ_HORI_VALID 0x5c
159 #define PRP_CH1_RZ_VERT_COEF1 0x60
160 #define PRP_CH1_RZ_VERT_COEF2 0x64
161 #define PRP_CH1_RZ_VERT_VALID 0x68
162 #define PRP_CH2_RZ_HORI_COEF1 0x6c
163 #define PRP_CH2_RZ_HORI_COEF2 0x70
164 #define PRP_CH2_RZ_HORI_VALID 0x74
165 #define PRP_CH2_RZ_VERT_COEF1 0x78
166 #define PRP_CH2_RZ_VERT_COEF2 0x7c
167 #define PRP_CH2_RZ_VERT_VALID 0x80
168
169 #define PRP_CNTL_CH1EN (1 << 0)
170 #define PRP_CNTL_CH2EN (1 << 1)
171 #define PRP_CNTL_CSIEN (1 << 2)
172 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
173 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
174 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
175 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
176 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
177 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
178 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
179 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
180 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
181 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
182 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
183 #define PRP_CNTL_CH1_LEN (1 << 9)
184 #define PRP_CNTL_CH2_LEN (1 << 10)
185 #define PRP_CNTL_SKIP_FRAME (1 << 11)
186 #define PRP_CNTL_SWRST (1 << 12)
187 #define PRP_CNTL_CLKEN (1 << 13)
188 #define PRP_CNTL_WEN (1 << 14)
189 #define PRP_CNTL_CH1BYP (1 << 15)
190 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
191 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
192 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
193 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
194 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
195 #define PRP_CNTL_CH2B1EN (1 << 29)
196 #define PRP_CNTL_CH2B2EN (1 << 30)
197 #define PRP_CNTL_CH2FEN (1 << 31)
198
199 /* IRQ Enable and status register */
200 #define PRP_INTR_RDERR (1 << 0)
201 #define PRP_INTR_CH1WERR (1 << 1)
202 #define PRP_INTR_CH2WERR (1 << 2)
203 #define PRP_INTR_CH1FC (1 << 3)
204 #define PRP_INTR_CH2FC (1 << 5)
205 #define PRP_INTR_LBOVF (1 << 7)
206 #define PRP_INTR_CH2OVF (1 << 8)
207
208 /* Resizing registers */
209 #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
210 #define PRP_RZ_VALID_BILINEAR (1 << 31)
211
212 #define MAX_VIDEO_MEM 16
213
214 #define RESIZE_NUM_MIN 1
215 #define RESIZE_NUM_MAX 20
216 #define BC_COEF 3
217 #define SZ_COEF (1 << BC_COEF)
218
219 #define RESIZE_DIR_H 0
220 #define RESIZE_DIR_V 1
221
222 #define RESIZE_ALGO_BILINEAR 0
223 #define RESIZE_ALGO_AVERAGING 1
224
225 struct mx2_prp_cfg {
226 int channel;
227 u32 in_fmt;
228 u32 out_fmt;
229 u32 src_pixel;
230 u32 ch1_pixel;
231 u32 irq_flags;
232 };
233
234 /* prp resizing parameters */
235 struct emma_prp_resize {
236 int algo; /* type of algorithm used */
237 int len; /* number of coefficients */
238 unsigned char s[RESIZE_NUM_MAX]; /* table of coefficients */
239 };
240
241 /* prp configuration for a client-host fmt pair */
242 struct mx2_fmt_cfg {
243 enum v4l2_mbus_pixelcode in_fmt;
244 u32 out_fmt;
245 struct mx2_prp_cfg cfg;
246 };
247
248 enum mx2_buffer_state {
249 MX2_STATE_QUEUED,
250 MX2_STATE_ACTIVE,
251 MX2_STATE_DONE,
252 };
253
254 struct mx2_buf_internal {
255 struct list_head queue;
256 int bufnum;
257 bool discard;
258 };
259
260 /* buffer for one video frame */
261 struct mx2_buffer {
262 /* common v4l buffer stuff -- must be first */
263 struct vb2_buffer vb;
264 enum mx2_buffer_state state;
265 struct mx2_buf_internal internal;
266 };
267
268 struct mx2_camera_dev {
269 struct device *dev;
270 struct soc_camera_host soc_host;
271 struct soc_camera_device *icd;
272 struct clk *clk_csi, *clk_emma;
273
274 unsigned int irq_csi, irq_emma;
275 void __iomem *base_csi, *base_emma;
276 unsigned long base_dma;
277
278 struct mx2_camera_platform_data *pdata;
279 struct resource *res_csi, *res_emma;
280 unsigned long platform_flags;
281
282 struct list_head capture;
283 struct list_head active_bufs;
284 struct list_head discard;
285
286 spinlock_t lock;
287
288 int dma;
289 struct mx2_buffer *active;
290 struct mx2_buffer *fb1_active;
291 struct mx2_buffer *fb2_active;
292
293 u32 csicr1;
294
295 struct mx2_buf_internal buf_discard[2];
296 void *discard_buffer;
297 dma_addr_t discard_buffer_dma;
298 size_t discard_size;
299 struct mx2_fmt_cfg *emma_prp;
300 struct emma_prp_resize resizing[2];
301 unsigned int s_width, s_height;
302 u32 frame_count;
303 struct vb2_alloc_ctx *alloc_ctx;
304 };
305
306 static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf)
307 {
308 return container_of(int_buf, struct mx2_buffer, internal);
309 }
310
311 static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
312 /*
313 * This is a generic configuration which is valid for most
314 * prp input-output format combinations.
315 * We set the incomming and outgoing pixelformat to a
316 * 16 Bit wide format and adjust the bytesperline
317 * accordingly. With this configuration the inputdata
318 * will not be changed by the emma and could be any type
319 * of 16 Bit Pixelformat.
320 */
321 {
322 .in_fmt = 0,
323 .out_fmt = 0,
324 .cfg = {
325 .channel = 1,
326 .in_fmt = PRP_CNTL_DATA_IN_RGB16,
327 .out_fmt = PRP_CNTL_CH1_OUT_RGB16,
328 .src_pixel = 0x2ca00565, /* RGB565 */
329 .ch1_pixel = 0x2ca00565, /* RGB565 */
330 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
331 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
332 }
333 },
334 {
335 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
336 .out_fmt = V4L2_PIX_FMT_YUV420,
337 .cfg = {
338 .channel = 2,
339 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
340 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
341 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
342 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
343 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
344 PRP_INTR_CH2OVF,
345 }
346 },
347 {
348 .in_fmt = V4L2_MBUS_FMT_UYVY8_2X8,
349 .out_fmt = V4L2_PIX_FMT_YUV420,
350 .cfg = {
351 .channel = 2,
352 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
353 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
354 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
355 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
356 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
357 PRP_INTR_CH2OVF,
358 }
359 },
360 };
361
362 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
363 enum v4l2_mbus_pixelcode in_fmt,
364 u32 out_fmt)
365 {
366 int i;
367
368 for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
369 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
370 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
371 return &mx27_emma_prp_table[i];
372 }
373 /* If no match return the most generic configuration */
374 return &mx27_emma_prp_table[0];
375 };
376
377 static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
378 unsigned long phys, int bufnum)
379 {
380 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
381
382 if (prp->cfg.channel == 1) {
383 writel(phys, pcdev->base_emma +
384 PRP_DEST_RGB1_PTR + 4 * bufnum);
385 } else {
386 writel(phys, pcdev->base_emma +
387 PRP_DEST_Y_PTR - 0x14 * bufnum);
388 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
389 u32 imgsize = pcdev->icd->user_height *
390 pcdev->icd->user_width;
391
392 writel(phys + imgsize, pcdev->base_emma +
393 PRP_DEST_CB_PTR - 0x14 * bufnum);
394 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
395 PRP_DEST_CR_PTR - 0x14 * bufnum);
396 }
397 }
398 }
399
400 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
401 {
402 unsigned long flags;
403
404 clk_disable(pcdev->clk_csi);
405 writel(0, pcdev->base_csi + CSICR1);
406 if (cpu_is_mx27()) {
407 writel(0, pcdev->base_emma + PRP_CNTL);
408 } else if (cpu_is_mx25()) {
409 spin_lock_irqsave(&pcdev->lock, flags);
410 pcdev->fb1_active = NULL;
411 pcdev->fb2_active = NULL;
412 writel(0, pcdev->base_csi + CSIDMASA_FB1);
413 writel(0, pcdev->base_csi + CSIDMASA_FB2);
414 spin_unlock_irqrestore(&pcdev->lock, flags);
415 }
416 }
417
418 /*
419 * The following two functions absolutely depend on the fact, that
420 * there can be only one camera on mx2 camera sensor interface
421 */
422 static int mx2_camera_add_device(struct soc_camera_device *icd)
423 {
424 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
425 struct mx2_camera_dev *pcdev = ici->priv;
426 int ret;
427 u32 csicr1;
428
429 if (pcdev->icd)
430 return -EBUSY;
431
432 ret = clk_enable(pcdev->clk_csi);
433 if (ret < 0)
434 return ret;
435
436 csicr1 = CSICR1_MCLKEN;
437
438 if (cpu_is_mx27()) {
439 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
440 CSICR1_RXFF_LEVEL(0);
441 } else if (cpu_is_mx27())
442 csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2);
443
444 pcdev->csicr1 = csicr1;
445 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
446
447 pcdev->icd = icd;
448 pcdev->frame_count = 0;
449
450 dev_info(icd->parent, "Camera driver attached to camera %d\n",
451 icd->devnum);
452
453 return 0;
454 }
455
456 static void mx2_camera_remove_device(struct soc_camera_device *icd)
457 {
458 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
459 struct mx2_camera_dev *pcdev = ici->priv;
460
461 BUG_ON(icd != pcdev->icd);
462
463 dev_info(icd->parent, "Camera driver detached from camera %d\n",
464 icd->devnum);
465
466 mx2_camera_deactivate(pcdev);
467
468 pcdev->icd = NULL;
469 }
470
471 static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
472 int state)
473 {
474 struct vb2_buffer *vb;
475 struct mx2_buffer *buf;
476 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
477 &pcdev->fb2_active;
478 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
479 unsigned long flags;
480
481 spin_lock_irqsave(&pcdev->lock, flags);
482
483 if (*fb_active == NULL)
484 goto out;
485
486 vb = &(*fb_active)->vb;
487 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__,
488 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
489
490 do_gettimeofday(&vb->v4l2_buf.timestamp);
491 vb->v4l2_buf.sequence++;
492 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
493
494 if (list_empty(&pcdev->capture)) {
495 buf = NULL;
496 writel(0, pcdev->base_csi + fb_reg);
497 } else {
498 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
499 internal.queue);
500 vb = &buf->vb;
501 list_del(&buf->internal.queue);
502 buf->state = MX2_STATE_ACTIVE;
503 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
504 pcdev->base_csi + fb_reg);
505 }
506
507 *fb_active = buf;
508
509 out:
510 spin_unlock_irqrestore(&pcdev->lock, flags);
511 }
512
513 static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
514 {
515 struct mx2_camera_dev *pcdev = data;
516 u32 status = readl(pcdev->base_csi + CSISR);
517
518 if (status & CSISR_DMA_TSF_FB1_INT)
519 mx25_camera_frame_done(pcdev, 1, MX2_STATE_DONE);
520 else if (status & CSISR_DMA_TSF_FB2_INT)
521 mx25_camera_frame_done(pcdev, 2, MX2_STATE_DONE);
522
523 /* FIXME: handle CSISR_RFF_OR_INT */
524
525 writel(status, pcdev->base_csi + CSISR);
526
527 return IRQ_HANDLED;
528 }
529
530 /*
531 * Videobuf operations
532 */
533 static int mx2_videobuf_setup(struct vb2_queue *vq,
534 const struct v4l2_format *fmt,
535 unsigned int *count, unsigned int *num_planes,
536 unsigned int sizes[], void *alloc_ctxs[])
537 {
538 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
539 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
540 struct mx2_camera_dev *pcdev = ici->priv;
541
542 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
543
544 /* TODO: support for VIDIOC_CREATE_BUFS not ready */
545 if (fmt != NULL)
546 return -ENOTTY;
547
548 alloc_ctxs[0] = pcdev->alloc_ctx;
549
550 sizes[0] = icd->sizeimage;
551
552 if (0 == *count)
553 *count = 32;
554 if (!*num_planes &&
555 sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
556 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
557
558 *num_planes = 1;
559
560 return 0;
561 }
562
563 static int mx2_videobuf_prepare(struct vb2_buffer *vb)
564 {
565 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
566 int ret = 0;
567
568 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
569 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
570
571 #ifdef DEBUG
572 /*
573 * This can be useful if you want to see if we actually fill
574 * the buffer with something
575 */
576 memset((void *)vb2_plane_vaddr(vb, 0),
577 0xaa, vb2_get_plane_payload(vb, 0));
578 #endif
579
580 vb2_set_plane_payload(vb, 0, icd->sizeimage);
581 if (vb2_plane_vaddr(vb, 0) &&
582 vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
583 ret = -EINVAL;
584 goto out;
585 }
586
587 return 0;
588
589 out:
590 return ret;
591 }
592
593 static void mx2_videobuf_queue(struct vb2_buffer *vb)
594 {
595 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
596 struct soc_camera_host *ici =
597 to_soc_camera_host(icd->parent);
598 struct mx2_camera_dev *pcdev = ici->priv;
599 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
600 unsigned long flags;
601
602 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
603 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
604
605 spin_lock_irqsave(&pcdev->lock, flags);
606
607 buf->state = MX2_STATE_QUEUED;
608 list_add_tail(&buf->internal.queue, &pcdev->capture);
609
610 if (cpu_is_mx25()) {
611 u32 csicr3, dma_inten = 0;
612
613 if (pcdev->fb1_active == NULL) {
614 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
615 pcdev->base_csi + CSIDMASA_FB1);
616 pcdev->fb1_active = buf;
617 dma_inten = CSICR1_FB1_DMA_INTEN;
618 } else if (pcdev->fb2_active == NULL) {
619 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
620 pcdev->base_csi + CSIDMASA_FB2);
621 pcdev->fb2_active = buf;
622 dma_inten = CSICR1_FB2_DMA_INTEN;
623 }
624
625 if (dma_inten) {
626 list_del(&buf->internal.queue);
627 buf->state = MX2_STATE_ACTIVE;
628
629 csicr3 = readl(pcdev->base_csi + CSICR3);
630
631 /* Reflash DMA */
632 writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
633 pcdev->base_csi + CSICR3);
634
635 /* clear & enable interrupts */
636 writel(dma_inten, pcdev->base_csi + CSISR);
637 pcdev->csicr1 |= dma_inten;
638 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
639
640 /* enable DMA */
641 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
642 writel(csicr3, pcdev->base_csi + CSICR3);
643 }
644 }
645
646 spin_unlock_irqrestore(&pcdev->lock, flags);
647 }
648
649 static void mx2_videobuf_release(struct vb2_buffer *vb)
650 {
651 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
652 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
653 struct mx2_camera_dev *pcdev = ici->priv;
654 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
655 unsigned long flags;
656
657 #ifdef DEBUG
658 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
659 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
660
661 switch (buf->state) {
662 case MX2_STATE_ACTIVE:
663 dev_info(icd->parent, "%s (active)\n", __func__);
664 break;
665 case MX2_STATE_QUEUED:
666 dev_info(icd->parent, "%s (queued)\n", __func__);
667 break;
668 default:
669 dev_info(icd->parent, "%s (unknown) %d\n", __func__,
670 buf->state);
671 break;
672 }
673 #endif
674
675 /*
676 * Terminate only queued but inactive buffers. Active buffers are
677 * released when they become inactive after videobuf_waiton().
678 *
679 * FIXME: implement forced termination of active buffers for mx27 and
680 * mx27 eMMA, so that the user won't get stuck in an uninterruptible
681 * state. This requires a specific handling for each of the these DMA
682 * types.
683 */
684
685 spin_lock_irqsave(&pcdev->lock, flags);
686 if (cpu_is_mx25() && buf->state == MX2_STATE_ACTIVE) {
687 if (pcdev->fb1_active == buf) {
688 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN;
689 writel(0, pcdev->base_csi + CSIDMASA_FB1);
690 pcdev->fb1_active = NULL;
691 } else if (pcdev->fb2_active == buf) {
692 pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN;
693 writel(0, pcdev->base_csi + CSIDMASA_FB2);
694 pcdev->fb2_active = NULL;
695 }
696 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
697 }
698 spin_unlock_irqrestore(&pcdev->lock, flags);
699 }
700
701 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
702 int bytesperline)
703 {
704 struct soc_camera_host *ici =
705 to_soc_camera_host(icd->parent);
706 struct mx2_camera_dev *pcdev = ici->priv;
707 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
708
709 writel((pcdev->s_width << 16) | pcdev->s_height,
710 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
711 writel(prp->cfg.src_pixel,
712 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
713 if (prp->cfg.channel == 1) {
714 writel((icd->user_width << 16) | icd->user_height,
715 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
716 writel(bytesperline,
717 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
718 writel(prp->cfg.ch1_pixel,
719 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
720 } else { /* channel 2 */
721 writel((icd->user_width << 16) | icd->user_height,
722 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
723 }
724
725 /* Enable interrupts */
726 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
727 }
728
729 static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev)
730 {
731 int dir;
732
733 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
734 unsigned char *s = pcdev->resizing[dir].s;
735 int len = pcdev->resizing[dir].len;
736 unsigned int coeff[2] = {0, 0};
737 unsigned int valid = 0;
738 int i;
739
740 if (len == 0)
741 continue;
742
743 for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) {
744 int j;
745
746 j = i > 9 ? 1 : 0;
747 coeff[j] = (coeff[j] << BC_COEF) |
748 (s[i] & (SZ_COEF - 1));
749
750 if (i == 5 || i == 15)
751 coeff[j] <<= 1;
752
753 valid = (valid << 1) | (s[i] >> BC_COEF);
754 }
755
756 valid |= PRP_RZ_VALID_TBL_LEN(len);
757
758 if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR)
759 valid |= PRP_RZ_VALID_BILINEAR;
760
761 if (pcdev->emma_prp->cfg.channel == 1) {
762 if (dir == RESIZE_DIR_H) {
763 writel(coeff[0], pcdev->base_emma +
764 PRP_CH1_RZ_HORI_COEF1);
765 writel(coeff[1], pcdev->base_emma +
766 PRP_CH1_RZ_HORI_COEF2);
767 writel(valid, pcdev->base_emma +
768 PRP_CH1_RZ_HORI_VALID);
769 } else {
770 writel(coeff[0], pcdev->base_emma +
771 PRP_CH1_RZ_VERT_COEF1);
772 writel(coeff[1], pcdev->base_emma +
773 PRP_CH1_RZ_VERT_COEF2);
774 writel(valid, pcdev->base_emma +
775 PRP_CH1_RZ_VERT_VALID);
776 }
777 } else {
778 if (dir == RESIZE_DIR_H) {
779 writel(coeff[0], pcdev->base_emma +
780 PRP_CH2_RZ_HORI_COEF1);
781 writel(coeff[1], pcdev->base_emma +
782 PRP_CH2_RZ_HORI_COEF2);
783 writel(valid, pcdev->base_emma +
784 PRP_CH2_RZ_HORI_VALID);
785 } else {
786 writel(coeff[0], pcdev->base_emma +
787 PRP_CH2_RZ_VERT_COEF1);
788 writel(coeff[1], pcdev->base_emma +
789 PRP_CH2_RZ_VERT_COEF2);
790 writel(valid, pcdev->base_emma +
791 PRP_CH2_RZ_VERT_VALID);
792 }
793 }
794 }
795 }
796
797 static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
798 {
799 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
800 struct soc_camera_host *ici =
801 to_soc_camera_host(icd->parent);
802 struct mx2_camera_dev *pcdev = ici->priv;
803 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
804 struct vb2_buffer *vb;
805 struct mx2_buffer *buf;
806 unsigned long phys;
807 int bytesperline;
808
809 if (cpu_is_mx27()) {
810 unsigned long flags;
811 if (count < 2)
812 return -EINVAL;
813
814 spin_lock_irqsave(&pcdev->lock, flags);
815
816 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
817 internal.queue);
818 buf->internal.bufnum = 0;
819 vb = &buf->vb;
820 buf->state = MX2_STATE_ACTIVE;
821
822 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
823 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
824 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
825
826 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
827 internal.queue);
828 buf->internal.bufnum = 1;
829 vb = &buf->vb;
830 buf->state = MX2_STATE_ACTIVE;
831
832 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
833 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
834 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
835
836 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
837 icd->current_fmt->host_fmt);
838 if (bytesperline < 0)
839 return bytesperline;
840
841 /*
842 * I didn't manage to properly enable/disable the prp
843 * on a per frame basis during running transfers,
844 * thus we allocate a buffer here and use it to
845 * discard frames when no buffer is available.
846 * Feel free to work on this ;)
847 */
848 pcdev->discard_size = icd->user_height * bytesperline;
849 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
850 pcdev->discard_size, &pcdev->discard_buffer_dma,
851 GFP_KERNEL);
852 if (!pcdev->discard_buffer)
853 return -ENOMEM;
854
855 pcdev->buf_discard[0].discard = true;
856 list_add_tail(&pcdev->buf_discard[0].queue,
857 &pcdev->discard);
858
859 pcdev->buf_discard[1].discard = true;
860 list_add_tail(&pcdev->buf_discard[1].queue,
861 &pcdev->discard);
862
863 mx2_prp_resize_commit(pcdev);
864
865 mx27_camera_emma_buf_init(icd, bytesperline);
866
867 if (prp->cfg.channel == 1) {
868 writel(PRP_CNTL_CH1EN |
869 PRP_CNTL_CSIEN |
870 prp->cfg.in_fmt |
871 prp->cfg.out_fmt |
872 PRP_CNTL_CH1_LEN |
873 PRP_CNTL_CH1BYP |
874 PRP_CNTL_CH1_TSKIP(0) |
875 PRP_CNTL_IN_TSKIP(0),
876 pcdev->base_emma + PRP_CNTL);
877 } else {
878 writel(PRP_CNTL_CH2EN |
879 PRP_CNTL_CSIEN |
880 prp->cfg.in_fmt |
881 prp->cfg.out_fmt |
882 PRP_CNTL_CH2_LEN |
883 PRP_CNTL_CH2_TSKIP(0) |
884 PRP_CNTL_IN_TSKIP(0),
885 pcdev->base_emma + PRP_CNTL);
886 }
887 spin_unlock_irqrestore(&pcdev->lock, flags);
888 }
889
890 return 0;
891 }
892
893 static int mx2_stop_streaming(struct vb2_queue *q)
894 {
895 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
896 struct soc_camera_host *ici =
897 to_soc_camera_host(icd->parent);
898 struct mx2_camera_dev *pcdev = ici->priv;
899 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
900 unsigned long flags;
901 void *b;
902 u32 cntl;
903
904 if (cpu_is_mx27()) {
905 spin_lock_irqsave(&pcdev->lock, flags);
906
907 cntl = readl(pcdev->base_emma + PRP_CNTL);
908 if (prp->cfg.channel == 1) {
909 writel(cntl & ~PRP_CNTL_CH1EN,
910 pcdev->base_emma + PRP_CNTL);
911 } else {
912 writel(cntl & ~PRP_CNTL_CH2EN,
913 pcdev->base_emma + PRP_CNTL);
914 }
915 INIT_LIST_HEAD(&pcdev->capture);
916 INIT_LIST_HEAD(&pcdev->active_bufs);
917 INIT_LIST_HEAD(&pcdev->discard);
918
919 b = pcdev->discard_buffer;
920 pcdev->discard_buffer = NULL;
921
922 spin_unlock_irqrestore(&pcdev->lock, flags);
923
924 dma_free_coherent(ici->v4l2_dev.dev,
925 pcdev->discard_size, b, pcdev->discard_buffer_dma);
926 }
927
928 return 0;
929 }
930
931 static struct vb2_ops mx2_videobuf_ops = {
932 .queue_setup = mx2_videobuf_setup,
933 .buf_prepare = mx2_videobuf_prepare,
934 .buf_queue = mx2_videobuf_queue,
935 .buf_cleanup = mx2_videobuf_release,
936 .start_streaming = mx2_start_streaming,
937 .stop_streaming = mx2_stop_streaming,
938 };
939
940 static int mx2_camera_init_videobuf(struct vb2_queue *q,
941 struct soc_camera_device *icd)
942 {
943 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
944 q->io_modes = VB2_MMAP | VB2_USERPTR;
945 q->drv_priv = icd;
946 q->ops = &mx2_videobuf_ops;
947 q->mem_ops = &vb2_dma_contig_memops;
948 q->buf_struct_size = sizeof(struct mx2_buffer);
949
950 return vb2_queue_init(q);
951 }
952
953 #define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
954 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
955 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
956 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
957 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
958 V4L2_MBUS_PCLK_SAMPLE_RISING | \
959 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
960 V4L2_MBUS_DATA_ACTIVE_HIGH | \
961 V4L2_MBUS_DATA_ACTIVE_LOW)
962
963 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
964 {
965 u32 cntl;
966 int count = 0;
967
968 cntl = readl(pcdev->base_emma + PRP_CNTL);
969 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
970 while (count++ < 100) {
971 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
972 return 0;
973 barrier();
974 udelay(1);
975 }
976
977 return -ETIMEDOUT;
978 }
979
980 static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
981 {
982 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
983 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
984 struct mx2_camera_dev *pcdev = ici->priv;
985 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
986 const struct soc_camera_format_xlate *xlate;
987 unsigned long common_flags;
988 int ret;
989 int bytesperline;
990 u32 csicr1 = pcdev->csicr1;
991
992 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
993 if (!ret) {
994 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
995 if (!common_flags) {
996 dev_warn(icd->parent,
997 "Flags incompatible: camera 0x%x, host 0x%x\n",
998 cfg.flags, MX2_BUS_FLAGS);
999 return -EINVAL;
1000 }
1001 } else if (ret != -ENOIOCTLCMD) {
1002 return ret;
1003 } else {
1004 common_flags = MX2_BUS_FLAGS;
1005 }
1006
1007 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1008 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1009 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
1010 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1011 else
1012 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1013 }
1014
1015 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1016 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1017 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
1018 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1019 else
1020 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1021 }
1022
1023 cfg.flags = common_flags;
1024 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1025 if (ret < 0 && ret != -ENOIOCTLCMD) {
1026 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
1027 common_flags, ret);
1028 return ret;
1029 }
1030
1031 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1032 if (!xlate) {
1033 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1034 return -EINVAL;
1035 }
1036
1037 if (xlate->code == V4L2_MBUS_FMT_YUYV8_2X8) {
1038 csicr1 |= CSICR1_PACK_DIR;
1039 csicr1 &= ~CSICR1_SWAP16_EN;
1040 dev_dbg(icd->parent, "already yuyv format, don't convert\n");
1041 } else if (xlate->code == V4L2_MBUS_FMT_UYVY8_2X8) {
1042 csicr1 &= ~CSICR1_PACK_DIR;
1043 csicr1 |= CSICR1_SWAP16_EN;
1044 dev_dbg(icd->parent, "convert uyvy mbus format into yuyv\n");
1045 } else {
1046 dev_warn(icd->parent, "mbus format not supported\n");
1047 return -EINVAL;
1048 }
1049
1050 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1051 csicr1 |= CSICR1_REDGE;
1052 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
1053 csicr1 |= CSICR1_SOF_POL;
1054 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1055 csicr1 |= CSICR1_HSYNC_POL;
1056 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
1057 csicr1 |= CSICR1_EXT_VSYNC;
1058 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
1059 csicr1 |= CSICR1_CCIR_EN;
1060 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
1061 csicr1 |= CSICR1_CCIR_MODE;
1062 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
1063 csicr1 |= CSICR1_GCLK_MODE;
1064 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
1065 csicr1 |= CSICR1_INV_DATA;
1066
1067 pcdev->csicr1 = csicr1;
1068
1069 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
1070 icd->current_fmt->host_fmt);
1071 if (bytesperline < 0)
1072 return bytesperline;
1073
1074 if (cpu_is_mx27()) {
1075 ret = mx27_camera_emma_prp_reset(pcdev);
1076 if (ret)
1077 return ret;
1078 } else if (cpu_is_mx25()) {
1079 writel((bytesperline * icd->user_height) >> 2,
1080 pcdev->base_csi + CSIRXCNT);
1081 writel((bytesperline << 16) | icd->user_height,
1082 pcdev->base_csi + CSIIMAG_PARA);
1083 }
1084
1085 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
1086
1087 return 0;
1088 }
1089
1090 static int mx2_camera_set_crop(struct soc_camera_device *icd,
1091 struct v4l2_crop *a)
1092 {
1093 struct v4l2_rect *rect = &a->c;
1094 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1095 struct v4l2_mbus_framefmt mf;
1096 int ret;
1097
1098 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
1099 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
1100
1101 ret = v4l2_subdev_call(sd, video, s_crop, a);
1102 if (ret < 0)
1103 return ret;
1104
1105 /* The capture device might have changed its output */
1106 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
1107 if (ret < 0)
1108 return ret;
1109
1110 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
1111 mf.width, mf.height);
1112
1113 icd->user_width = mf.width;
1114 icd->user_height = mf.height;
1115
1116 return ret;
1117 }
1118
1119 static int mx2_camera_get_formats(struct soc_camera_device *icd,
1120 unsigned int idx,
1121 struct soc_camera_format_xlate *xlate)
1122 {
1123 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1124 const struct soc_mbus_pixelfmt *fmt;
1125 struct device *dev = icd->parent;
1126 enum v4l2_mbus_pixelcode code;
1127 int ret, formats = 0;
1128
1129 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1130 if (ret < 0)
1131 /* no more formats */
1132 return 0;
1133
1134 fmt = soc_mbus_get_fmtdesc(code);
1135 if (!fmt) {
1136 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
1137 return 0;
1138 }
1139
1140 if (code == V4L2_MBUS_FMT_YUYV8_2X8 ||
1141 code == V4L2_MBUS_FMT_UYVY8_2X8) {
1142 formats++;
1143 if (xlate) {
1144 /*
1145 * CH2 can output YUV420 which is a standard format in
1146 * soc_mediabus.c
1147 */
1148 xlate->host_fmt =
1149 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8);
1150 xlate->code = code;
1151 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1152 xlate->host_fmt->name, code);
1153 xlate++;
1154 }
1155 }
1156
1157 if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
1158 formats++;
1159 if (xlate) {
1160 xlate->host_fmt =
1161 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_2X8);
1162 xlate->code = code;
1163 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1164 xlate->host_fmt->name, code);
1165 xlate++;
1166 }
1167 }
1168
1169 /* Generic pass-trough */
1170 formats++;
1171 if (xlate) {
1172 xlate->host_fmt = fmt;
1173 xlate->code = code;
1174 xlate++;
1175 }
1176 return formats;
1177 }
1178
1179 static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev,
1180 struct v4l2_mbus_framefmt *mf_in,
1181 struct v4l2_pix_format *pix_out, bool apply)
1182 {
1183 int num, den;
1184 unsigned long m;
1185 int i, dir;
1186
1187 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
1188 struct emma_prp_resize tmprsz;
1189 unsigned char *s = tmprsz.s;
1190 int len = 0;
1191 int in, out;
1192
1193 if (dir == RESIZE_DIR_H) {
1194 in = mf_in->width;
1195 out = pix_out->width;
1196 } else {
1197 in = mf_in->height;
1198 out = pix_out->height;
1199 }
1200
1201 if (in < out)
1202 return -EINVAL;
1203 else if (in == out)
1204 continue;
1205
1206 /* Calculate ratio */
1207 m = gcd(in, out);
1208 num = in / m;
1209 den = out / m;
1210 if (num > RESIZE_NUM_MAX)
1211 return -EINVAL;
1212
1213 if ((num >= 2 * den) && (den == 1) &&
1214 (num < 9) && (!(num & 0x01))) {
1215 int sum = 0;
1216 int j;
1217
1218 /* Average scaling for >= 2:1 ratios */
1219 /* Support can be added for num >=9 and odd values */
1220
1221 tmprsz.algo = RESIZE_ALGO_AVERAGING;
1222 len = num;
1223
1224 for (i = 0; i < (len / 2); i++)
1225 s[i] = 8;
1226
1227 do {
1228 for (i = 0; i < (len / 2); i++) {
1229 s[i] = s[i] >> 1;
1230 sum = 0;
1231 for (j = 0; j < (len / 2); j++)
1232 sum += s[j];
1233 if (sum == 4)
1234 break;
1235 }
1236 } while (sum != 4);
1237
1238 for (i = (len / 2); i < len; i++)
1239 s[i] = s[len - i - 1];
1240
1241 s[len - 1] |= SZ_COEF;
1242 } else {
1243 /* bilinear scaling for < 2:1 ratios */
1244 int v; /* overflow counter */
1245 int coeff, nxt; /* table output */
1246 int in_pos_inc = 2 * den;
1247 int out_pos = num;
1248 int out_pos_inc = 2 * num;
1249 int init_carry = num - den;
1250 int carry = init_carry;
1251
1252 tmprsz.algo = RESIZE_ALGO_BILINEAR;
1253 v = den + in_pos_inc;
1254 do {
1255 coeff = v - out_pos;
1256 out_pos += out_pos_inc;
1257 carry += out_pos_inc;
1258 for (nxt = 0; v < out_pos; nxt++) {
1259 v += in_pos_inc;
1260 carry -= in_pos_inc;
1261 }
1262
1263 if (len > RESIZE_NUM_MAX)
1264 return -EINVAL;
1265
1266 coeff = ((coeff << BC_COEF) +
1267 (in_pos_inc >> 1)) / in_pos_inc;
1268
1269 if (coeff >= (SZ_COEF - 1))
1270 coeff--;
1271
1272 coeff |= SZ_COEF;
1273 s[len] = (unsigned char)coeff;
1274 len++;
1275
1276 for (i = 1; i < nxt; i++) {
1277 if (len >= RESIZE_NUM_MAX)
1278 return -EINVAL;
1279 s[len] = 0;
1280 len++;
1281 }
1282 } while (carry != init_carry);
1283 }
1284 tmprsz.len = len;
1285 if (dir == RESIZE_DIR_H)
1286 mf_in->width = pix_out->width;
1287 else
1288 mf_in->height = pix_out->height;
1289
1290 if (apply)
1291 memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz));
1292 }
1293 return 0;
1294 }
1295
1296 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1297 struct v4l2_format *f)
1298 {
1299 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1300 struct mx2_camera_dev *pcdev = ici->priv;
1301 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1302 const struct soc_camera_format_xlate *xlate;
1303 struct v4l2_pix_format *pix = &f->fmt.pix;
1304 struct v4l2_mbus_framefmt mf;
1305 int ret;
1306
1307 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1308 __func__, pix->width, pix->height);
1309
1310 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1311 if (!xlate) {
1312 dev_warn(icd->parent, "Format %x not found\n",
1313 pix->pixelformat);
1314 return -EINVAL;
1315 }
1316
1317 mf.width = pix->width;
1318 mf.height = pix->height;
1319 mf.field = pix->field;
1320 mf.colorspace = pix->colorspace;
1321 mf.code = xlate->code;
1322
1323 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1324 if (ret < 0 && ret != -ENOIOCTLCMD)
1325 return ret;
1326
1327 /* Store width and height returned by the sensor for resizing */
1328 pcdev->s_width = mf.width;
1329 pcdev->s_height = mf.height;
1330 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1331 __func__, pcdev->s_width, pcdev->s_height);
1332
1333 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1334 xlate->host_fmt->fourcc);
1335
1336 memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1337 if ((mf.width != pix->width || mf.height != pix->height) &&
1338 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1339 if (mx2_emmaprp_resize(pcdev, &mf, pix, true) < 0)
1340 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1341 }
1342
1343 if (mf.code != xlate->code)
1344 return -EINVAL;
1345
1346 pix->width = mf.width;
1347 pix->height = mf.height;
1348 pix->field = mf.field;
1349 pix->colorspace = mf.colorspace;
1350 icd->current_fmt = xlate;
1351
1352 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1353 __func__, pix->width, pix->height);
1354
1355 return 0;
1356 }
1357
1358 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1359 struct v4l2_format *f)
1360 {
1361 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1362 const struct soc_camera_format_xlate *xlate;
1363 struct v4l2_pix_format *pix = &f->fmt.pix;
1364 struct v4l2_mbus_framefmt mf;
1365 __u32 pixfmt = pix->pixelformat;
1366 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1367 struct mx2_camera_dev *pcdev = ici->priv;
1368 unsigned int width_limit;
1369 int ret;
1370
1371 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1372 __func__, pix->width, pix->height);
1373
1374 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1375 if (pixfmt && !xlate) {
1376 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1377 return -EINVAL;
1378 }
1379
1380 /* FIXME: implement MX27 limits */
1381
1382 /* limit to MX25 hardware capabilities */
1383 if (cpu_is_mx25()) {
1384 if (xlate->host_fmt->bits_per_sample <= 8)
1385 width_limit = 0xffff * 4;
1386 else
1387 width_limit = 0xffff * 2;
1388 /* CSIIMAG_PARA limit */
1389 if (pix->width > width_limit)
1390 pix->width = width_limit;
1391 if (pix->height > 0xffff)
1392 pix->height = 0xffff;
1393
1394 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1395 xlate->host_fmt);
1396 if (pix->bytesperline < 0)
1397 return pix->bytesperline;
1398 pix->sizeimage = soc_mbus_image_size(xlate->host_fmt,
1399 pix->bytesperline, pix->height);
1400 /* Check against the CSIRXCNT limit */
1401 if (pix->sizeimage > 4 * 0x3ffff) {
1402 /* Adjust geometry, preserve aspect ratio */
1403 unsigned int new_height = int_sqrt(4 * 0x3ffff *
1404 pix->height / pix->bytesperline);
1405 pix->width = new_height * pix->width / pix->height;
1406 pix->height = new_height;
1407 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1408 xlate->host_fmt);
1409 BUG_ON(pix->bytesperline < 0);
1410 pix->sizeimage = soc_mbus_image_size(xlate->host_fmt,
1411 pix->bytesperline, pix->height);
1412 }
1413 }
1414
1415 /* limit to sensor capabilities */
1416 mf.width = pix->width;
1417 mf.height = pix->height;
1418 mf.field = pix->field;
1419 mf.colorspace = pix->colorspace;
1420 mf.code = xlate->code;
1421
1422 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1423 if (ret < 0)
1424 return ret;
1425
1426 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1427 __func__, pcdev->s_width, pcdev->s_height);
1428
1429 /* If the sensor does not support image size try PrP resizing */
1430 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1431 xlate->host_fmt->fourcc);
1432
1433 memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1434 if ((mf.width != pix->width || mf.height != pix->height) &&
1435 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1436 if (mx2_emmaprp_resize(pcdev, &mf, pix, false) < 0)
1437 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1438 }
1439
1440 if (mf.field == V4L2_FIELD_ANY)
1441 mf.field = V4L2_FIELD_NONE;
1442 /*
1443 * Driver supports interlaced images provided they have
1444 * both fields so that they can be processed as if they
1445 * were progressive.
1446 */
1447 if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) {
1448 dev_err(icd->parent, "Field type %d unsupported.\n",
1449 mf.field);
1450 return -EINVAL;
1451 }
1452
1453 pix->width = mf.width;
1454 pix->height = mf.height;
1455 pix->field = mf.field;
1456 pix->colorspace = mf.colorspace;
1457
1458 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1459 __func__, pix->width, pix->height);
1460
1461 return 0;
1462 }
1463
1464 static int mx2_camera_querycap(struct soc_camera_host *ici,
1465 struct v4l2_capability *cap)
1466 {
1467 /* cap->name is set by the friendly caller:-> */
1468 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1469 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1470
1471 return 0;
1472 }
1473
1474 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1475 {
1476 struct soc_camera_device *icd = file->private_data;
1477
1478 return vb2_poll(&icd->vb2_vidq, file, pt);
1479 }
1480
1481 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1482 .owner = THIS_MODULE,
1483 .add = mx2_camera_add_device,
1484 .remove = mx2_camera_remove_device,
1485 .set_fmt = mx2_camera_set_fmt,
1486 .set_crop = mx2_camera_set_crop,
1487 .get_formats = mx2_camera_get_formats,
1488 .try_fmt = mx2_camera_try_fmt,
1489 .init_videobuf2 = mx2_camera_init_videobuf,
1490 .poll = mx2_camera_poll,
1491 .querycap = mx2_camera_querycap,
1492 .set_bus_param = mx2_camera_set_bus_param,
1493 };
1494
1495 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1496 int bufnum, bool err)
1497 {
1498 #ifdef DEBUG
1499 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1500 #endif
1501 struct mx2_buf_internal *ibuf;
1502 struct mx2_buffer *buf;
1503 struct vb2_buffer *vb;
1504 unsigned long phys;
1505
1506 ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal,
1507 queue);
1508
1509 BUG_ON(ibuf->bufnum != bufnum);
1510
1511 if (ibuf->discard) {
1512 /*
1513 * Discard buffer must not be returned to user space.
1514 * Just return it to the discard queue.
1515 */
1516 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1517 } else {
1518 buf = mx2_ibuf_to_buf(ibuf);
1519
1520 vb = &buf->vb;
1521 #ifdef DEBUG
1522 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1523 if (prp->cfg.channel == 1) {
1524 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1525 4 * bufnum) != phys) {
1526 dev_err(pcdev->dev, "%lx != %x\n", phys,
1527 readl(pcdev->base_emma +
1528 PRP_DEST_RGB1_PTR + 4 * bufnum));
1529 }
1530 } else {
1531 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1532 0x14 * bufnum) != phys) {
1533 dev_err(pcdev->dev, "%lx != %x\n", phys,
1534 readl(pcdev->base_emma +
1535 PRP_DEST_Y_PTR - 0x14 * bufnum));
1536 }
1537 }
1538 #endif
1539 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1540 vb2_plane_vaddr(vb, 0),
1541 vb2_get_plane_payload(vb, 0));
1542
1543 list_del_init(&buf->internal.queue);
1544 do_gettimeofday(&vb->v4l2_buf.timestamp);
1545 vb->v4l2_buf.sequence = pcdev->frame_count;
1546 if (err)
1547 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1548 else
1549 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1550 }
1551
1552 pcdev->frame_count++;
1553
1554 if (list_empty(&pcdev->capture)) {
1555 if (list_empty(&pcdev->discard)) {
1556 dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1557 __func__);
1558 return;
1559 }
1560
1561 ibuf = list_first_entry(&pcdev->discard,
1562 struct mx2_buf_internal, queue);
1563 ibuf->bufnum = bufnum;
1564
1565 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1566 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1567 return;
1568 }
1569
1570 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
1571 internal.queue);
1572
1573 buf->internal.bufnum = bufnum;
1574
1575 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1576
1577 vb = &buf->vb;
1578 buf->state = MX2_STATE_ACTIVE;
1579
1580 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1581 mx27_update_emma_buf(pcdev, phys, bufnum);
1582 }
1583
1584 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1585 {
1586 struct mx2_camera_dev *pcdev = data;
1587 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1588 struct mx2_buf_internal *ibuf;
1589
1590 spin_lock(&pcdev->lock);
1591
1592 if (list_empty(&pcdev->active_bufs)) {
1593 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1594 __func__);
1595
1596 if (!status) {
1597 spin_unlock(&pcdev->lock);
1598 return IRQ_NONE;
1599 }
1600 }
1601
1602 if (status & (1 << 7)) { /* overflow */
1603 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1604 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1605 pcdev->base_emma + PRP_CNTL);
1606 writel(cntl, pcdev->base_emma + PRP_CNTL);
1607
1608 ibuf = list_first_entry(&pcdev->active_bufs,
1609 struct mx2_buf_internal, queue);
1610 mx27_camera_frame_done_emma(pcdev,
1611 ibuf->bufnum, true);
1612
1613 status &= ~(1 << 7);
1614 } else if (((status & (3 << 5)) == (3 << 5)) ||
1615 ((status & (3 << 3)) == (3 << 3))) {
1616 /*
1617 * Both buffers have triggered, process the one we're expecting
1618 * to first
1619 */
1620 ibuf = list_first_entry(&pcdev->active_bufs,
1621 struct mx2_buf_internal, queue);
1622 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false);
1623 status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */
1624 } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1625 mx27_camera_frame_done_emma(pcdev, 0, false);
1626 } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1627 mx27_camera_frame_done_emma(pcdev, 1, false);
1628 }
1629
1630 spin_unlock(&pcdev->lock);
1631 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1632
1633 return IRQ_HANDLED;
1634 }
1635
1636 static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev)
1637 {
1638 struct resource *res_emma = pcdev->res_emma;
1639 int err = 0;
1640
1641 if (!request_mem_region(res_emma->start, resource_size(res_emma),
1642 MX2_CAM_DRV_NAME)) {
1643 err = -EBUSY;
1644 goto out;
1645 }
1646
1647 pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma));
1648 if (!pcdev->base_emma) {
1649 err = -ENOMEM;
1650 goto exit_release;
1651 }
1652
1653 err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0,
1654 MX2_CAM_DRV_NAME, pcdev);
1655 if (err) {
1656 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
1657 goto exit_iounmap;
1658 }
1659
1660 pcdev->clk_emma = clk_get(NULL, "emma");
1661 if (IS_ERR(pcdev->clk_emma)) {
1662 err = PTR_ERR(pcdev->clk_emma);
1663 goto exit_free_irq;
1664 }
1665
1666 clk_enable(pcdev->clk_emma);
1667
1668 err = mx27_camera_emma_prp_reset(pcdev);
1669 if (err)
1670 goto exit_clk_emma_put;
1671
1672 return err;
1673
1674 exit_clk_emma_put:
1675 clk_disable(pcdev->clk_emma);
1676 clk_put(pcdev->clk_emma);
1677 exit_free_irq:
1678 free_irq(pcdev->irq_emma, pcdev);
1679 exit_iounmap:
1680 iounmap(pcdev->base_emma);
1681 exit_release:
1682 release_mem_region(res_emma->start, resource_size(res_emma));
1683 out:
1684 return err;
1685 }
1686
1687 static int __devinit mx2_camera_probe(struct platform_device *pdev)
1688 {
1689 struct mx2_camera_dev *pcdev;
1690 struct resource *res_csi, *res_emma;
1691 void __iomem *base_csi;
1692 int irq_csi, irq_emma;
1693 int err = 0;
1694
1695 dev_dbg(&pdev->dev, "initialising\n");
1696
1697 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1698 irq_csi = platform_get_irq(pdev, 0);
1699 if (res_csi == NULL || irq_csi < 0) {
1700 dev_err(&pdev->dev, "Missing platform resources data\n");
1701 err = -ENODEV;
1702 goto exit;
1703 }
1704
1705 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1706 if (!pcdev) {
1707 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1708 err = -ENOMEM;
1709 goto exit;
1710 }
1711
1712 pcdev->clk_csi = clk_get(&pdev->dev, NULL);
1713 if (IS_ERR(pcdev->clk_csi)) {
1714 dev_err(&pdev->dev, "Could not get csi clock\n");
1715 err = PTR_ERR(pcdev->clk_csi);
1716 goto exit_kfree;
1717 }
1718
1719 pcdev->res_csi = res_csi;
1720 pcdev->pdata = pdev->dev.platform_data;
1721 if (pcdev->pdata) {
1722 long rate;
1723
1724 pcdev->platform_flags = pcdev->pdata->flags;
1725
1726 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
1727 if (rate <= 0) {
1728 err = -ENODEV;
1729 goto exit_dma_free;
1730 }
1731 err = clk_set_rate(pcdev->clk_csi, rate);
1732 if (err < 0)
1733 goto exit_dma_free;
1734 }
1735
1736 INIT_LIST_HEAD(&pcdev->capture);
1737 INIT_LIST_HEAD(&pcdev->active_bufs);
1738 INIT_LIST_HEAD(&pcdev->discard);
1739 spin_lock_init(&pcdev->lock);
1740
1741 /*
1742 * Request the regions.
1743 */
1744 if (!request_mem_region(res_csi->start, resource_size(res_csi),
1745 MX2_CAM_DRV_NAME)) {
1746 err = -EBUSY;
1747 goto exit_dma_free;
1748 }
1749
1750 base_csi = ioremap(res_csi->start, resource_size(res_csi));
1751 if (!base_csi) {
1752 err = -ENOMEM;
1753 goto exit_release;
1754 }
1755 pcdev->irq_csi = irq_csi;
1756 pcdev->base_csi = base_csi;
1757 pcdev->base_dma = res_csi->start;
1758 pcdev->dev = &pdev->dev;
1759
1760 if (cpu_is_mx25()) {
1761 err = request_irq(pcdev->irq_csi, mx25_camera_irq, 0,
1762 MX2_CAM_DRV_NAME, pcdev);
1763 if (err) {
1764 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1765 goto exit_iounmap;
1766 }
1767 }
1768
1769 if (cpu_is_mx27()) {
1770 /* EMMA support */
1771 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1772 irq_emma = platform_get_irq(pdev, 1);
1773
1774 if (!res_emma || !irq_emma) {
1775 dev_err(&pdev->dev, "no EMMA resources\n");
1776 goto exit_free_irq;
1777 }
1778
1779 pcdev->res_emma = res_emma;
1780 pcdev->irq_emma = irq_emma;
1781 if (mx27_camera_emma_init(pcdev))
1782 goto exit_free_irq;
1783 }
1784
1785 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1786 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1787 pcdev->soc_host.priv = pcdev;
1788 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1789 pcdev->soc_host.nr = pdev->id;
1790 if (cpu_is_mx25())
1791 pcdev->soc_host.capabilities = SOCAM_HOST_CAP_STRIDE;
1792
1793 pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1794 if (IS_ERR(pcdev->alloc_ctx)) {
1795 err = PTR_ERR(pcdev->alloc_ctx);
1796 goto eallocctx;
1797 }
1798 err = soc_camera_host_register(&pcdev->soc_host);
1799 if (err)
1800 goto exit_free_emma;
1801
1802 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1803 clk_get_rate(pcdev->clk_csi));
1804
1805 return 0;
1806
1807 exit_free_emma:
1808 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1809 eallocctx:
1810 if (cpu_is_mx27()) {
1811 free_irq(pcdev->irq_emma, pcdev);
1812 clk_disable(pcdev->clk_emma);
1813 clk_put(pcdev->clk_emma);
1814 iounmap(pcdev->base_emma);
1815 release_mem_region(pcdev->res_emma->start, resource_size(pcdev->res_emma));
1816 }
1817 exit_free_irq:
1818 if (cpu_is_mx25())
1819 free_irq(pcdev->irq_csi, pcdev);
1820 exit_iounmap:
1821 iounmap(base_csi);
1822 exit_release:
1823 release_mem_region(res_csi->start, resource_size(res_csi));
1824 exit_dma_free:
1825 clk_put(pcdev->clk_csi);
1826 exit_kfree:
1827 kfree(pcdev);
1828 exit:
1829 return err;
1830 }
1831
1832 static int __devexit mx2_camera_remove(struct platform_device *pdev)
1833 {
1834 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1835 struct mx2_camera_dev *pcdev = container_of(soc_host,
1836 struct mx2_camera_dev, soc_host);
1837 struct resource *res;
1838
1839 clk_put(pcdev->clk_csi);
1840 if (cpu_is_mx25())
1841 free_irq(pcdev->irq_csi, pcdev);
1842 if (cpu_is_mx27())
1843 free_irq(pcdev->irq_emma, pcdev);
1844
1845 soc_camera_host_unregister(&pcdev->soc_host);
1846
1847 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1848
1849 iounmap(pcdev->base_csi);
1850
1851 if (cpu_is_mx27()) {
1852 clk_disable(pcdev->clk_emma);
1853 clk_put(pcdev->clk_emma);
1854 iounmap(pcdev->base_emma);
1855 res = pcdev->res_emma;
1856 release_mem_region(res->start, resource_size(res));
1857 }
1858
1859 res = pcdev->res_csi;
1860 release_mem_region(res->start, resource_size(res));
1861
1862 kfree(pcdev);
1863
1864 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1865
1866 return 0;
1867 }
1868
1869 static struct platform_driver mx2_camera_driver = {
1870 .driver = {
1871 .name = MX2_CAM_DRV_NAME,
1872 },
1873 .remove = __devexit_p(mx2_camera_remove),
1874 };
1875
1876
1877 static int __init mx2_camera_init(void)
1878 {
1879 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
1880 }
1881
1882 static void __exit mx2_camera_exit(void)
1883 {
1884 return platform_driver_unregister(&mx2_camera_driver);
1885 }
1886
1887 module_init(mx2_camera_init);
1888 module_exit(mx2_camera_exit);
1889
1890 MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1891 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1892 MODULE_LICENSE("GPL");
1893 MODULE_VERSION(MX2_CAM_VERSION);
Linux kernel - Deliverables
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