2 * V4L2 Driver for PXA camera host
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/mutex.h>
29 #include <linux/clk.h>
31 #include <media/v4l2-common.h>
32 #include <media/v4l2-dev.h>
33 #include <media/soc_camera.h>
35 #include <linux/videodev2.h>
38 #include <asm/arch/pxa-regs.h>
39 #include <asm/arch/camera.h>
41 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
42 #define PXA_CAM_DRV_NAME "pxa27x-camera"
44 #define CICR0_SIM_MP (0 << 24)
45 #define CICR0_SIM_SP (1 << 24)
46 #define CICR0_SIM_MS (2 << 24)
47 #define CICR0_SIM_EP (3 << 24)
48 #define CICR0_SIM_ES (4 << 24)
50 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
51 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
52 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
53 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
54 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
56 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
57 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
58 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
59 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
60 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
62 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
63 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
64 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
65 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
67 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
68 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
69 CICR0_EOFM | CICR0_FOM)
71 static DEFINE_MUTEX(camera_lock
);
76 enum pxa_camera_active_dma
{
82 /* descriptor needed for the PXA DMA engine */
85 struct pxa_dma_desc
*sg_cpu
;
90 /* buffer for one video frame */
92 /* common v4l buffer stuff -- must be first */
93 struct videobuf_buffer vb
;
95 const struct soc_camera_data_format
*fmt
;
97 /* our descriptor lists for Y, U and V channels */
98 struct pxa_cam_dma dmas
[3];
102 enum pxa_camera_active_dma active_dma
;
105 struct pxa_framebuffer_queue
{
106 dma_addr_t sg_last_dma
;
107 struct pxa_dma_desc
*sg_last_cpu
;
110 struct pxa_camera_dev
{
112 /* PXA27x is only supposed to handle one camera on its Quick Capture
113 * interface. If anyone ever builds hardware to enable more than
114 * one camera, they will have to modify this driver too */
115 struct soc_camera_device
*icd
;
122 unsigned int dma_chans
[3];
124 struct pxacamera_platform_data
*pdata
;
125 struct resource
*res
;
126 unsigned long platform_flags
;
127 unsigned long platform_mclk_10khz
;
129 struct list_head capture
;
133 struct pxa_buffer
*active
;
136 static const char *pxa_cam_driver_description
= "PXA_Camera";
138 static unsigned int vid_limit
= 16; /* Video memory limit, in Mb */
141 * Videobuf operations
143 static int pxa_videobuf_setup(struct videobuf_queue
*vq
, unsigned int *count
,
146 struct soc_camera_device
*icd
= vq
->priv_data
;
148 dev_dbg(&icd
->dev
, "count=%d, size=%d\n", *count
, *size
);
150 /* planar capture requires Y, U and V buffers to be page aligned */
151 if (icd
->current_fmt
->fourcc
== V4L2_PIX_FMT_YUV422P
) {
152 *size
= PAGE_ALIGN(icd
->width
* icd
->height
); /* Y pages */
153 *size
+= PAGE_ALIGN(icd
->width
* icd
->height
/ 2); /* U pages */
154 *size
+= PAGE_ALIGN(icd
->width
* icd
->height
/ 2); /* V pages */
156 *size
= icd
->width
* icd
->height
*
157 ((icd
->current_fmt
->depth
+ 7) >> 3);
162 while (*size
* *count
> vid_limit
* 1024 * 1024)
168 static void free_buffer(struct videobuf_queue
*vq
, struct pxa_buffer
*buf
)
170 struct soc_camera_device
*icd
= vq
->priv_data
;
171 struct soc_camera_host
*ici
=
172 to_soc_camera_host(icd
->dev
.parent
);
173 struct pxa_camera_dev
*pcdev
= ici
->priv
;
174 struct videobuf_dmabuf
*dma
= videobuf_to_dma(&buf
->vb
);
177 BUG_ON(in_interrupt());
179 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
180 &buf
->vb
, buf
->vb
.baddr
, buf
->vb
.bsize
);
182 /* This waits until this buffer is out of danger, i.e., until it is no
183 * longer in STATE_QUEUED or STATE_ACTIVE */
184 videobuf_waiton(&buf
->vb
, 0, 0);
185 videobuf_dma_unmap(vq
, dma
);
186 videobuf_dma_free(dma
);
188 for (i
= 0; i
< ARRAY_SIZE(buf
->dmas
); i
++) {
189 if (buf
->dmas
[i
].sg_cpu
)
190 dma_free_coherent(pcdev
->dev
, buf
->dmas
[i
].sg_size
,
192 buf
->dmas
[i
].sg_dma
);
193 buf
->dmas
[i
].sg_cpu
= NULL
;
196 buf
->vb
.state
= VIDEOBUF_NEEDS_INIT
;
199 static int pxa_init_dma_channel(struct pxa_camera_dev
*pcdev
,
200 struct pxa_buffer
*buf
,
201 struct videobuf_dmabuf
*dma
, int channel
,
202 int sglen
, int sg_start
, int cibr
,
205 struct pxa_cam_dma
*pxa_dma
= &buf
->dmas
[channel
];
209 dma_free_coherent(pcdev
->dev
, pxa_dma
->sg_size
,
210 pxa_dma
->sg_cpu
, pxa_dma
->sg_dma
);
212 pxa_dma
->sg_size
= (sglen
+ 1) * sizeof(struct pxa_dma_desc
);
213 pxa_dma
->sg_cpu
= dma_alloc_coherent(pcdev
->dev
, pxa_dma
->sg_size
,
214 &pxa_dma
->sg_dma
, GFP_KERNEL
);
215 if (!pxa_dma
->sg_cpu
)
218 pxa_dma
->sglen
= sglen
;
220 for (i
= 0; i
< sglen
; i
++) {
221 int sg_i
= sg_start
+ i
;
222 struct scatterlist
*sg
= dma
->sglist
;
223 unsigned int dma_len
= sg_dma_len(&sg
[sg_i
]), xfer_len
;
225 pxa_dma
->sg_cpu
[i
].dsadr
= pcdev
->res
->start
+ cibr
;
226 pxa_dma
->sg_cpu
[i
].dtadr
= sg_dma_address(&sg
[sg_i
]);
228 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
229 xfer_len
= (min(dma_len
, size
) + 7) & ~7;
231 pxa_dma
->sg_cpu
[i
].dcmd
=
232 DCMD_FLOWSRC
| DCMD_BURST8
| DCMD_INCTRGADDR
| xfer_len
;
234 pxa_dma
->sg_cpu
[i
].ddadr
=
235 pxa_dma
->sg_dma
+ (i
+ 1) * sizeof(struct pxa_dma_desc
);
238 pxa_dma
->sg_cpu
[sglen
- 1].ddadr
= DDADR_STOP
;
239 pxa_dma
->sg_cpu
[sglen
- 1].dcmd
|= DCMD_ENDIRQEN
;
244 static int pxa_videobuf_prepare(struct videobuf_queue
*vq
,
245 struct videobuf_buffer
*vb
, enum v4l2_field field
)
247 struct soc_camera_device
*icd
= vq
->priv_data
;
248 struct soc_camera_host
*ici
=
249 to_soc_camera_host(icd
->dev
.parent
);
250 struct pxa_camera_dev
*pcdev
= ici
->priv
;
251 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
253 int sglen_y
, sglen_yu
= 0, sglen_u
= 0, sglen_v
= 0;
254 int size_y
, size_u
= 0, size_v
= 0;
256 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
257 vb
, vb
->baddr
, vb
->bsize
);
259 /* Added list head initialization on alloc */
260 WARN_ON(!list_empty(&vb
->queue
));
263 /* This can be useful if you want to see if we actually fill
264 * the buffer with something */
265 memset((void *)vb
->baddr
, 0xaa, vb
->bsize
);
268 BUG_ON(NULL
== icd
->current_fmt
);
270 /* I think, in buf_prepare you only have to protect global data,
271 * the actual buffer is yours */
274 if (buf
->fmt
!= icd
->current_fmt
||
275 vb
->width
!= icd
->width
||
276 vb
->height
!= icd
->height
||
277 vb
->field
!= field
) {
278 buf
->fmt
= icd
->current_fmt
;
279 vb
->width
= icd
->width
;
280 vb
->height
= icd
->height
;
282 vb
->state
= VIDEOBUF_NEEDS_INIT
;
285 vb
->size
= vb
->width
* vb
->height
* ((buf
->fmt
->depth
+ 7) >> 3);
286 if (0 != vb
->baddr
&& vb
->bsize
< vb
->size
) {
291 if (vb
->state
== VIDEOBUF_NEEDS_INIT
) {
292 unsigned int size
= vb
->size
;
293 struct videobuf_dmabuf
*dma
= videobuf_to_dma(vb
);
295 ret
= videobuf_iolock(vq
, vb
, NULL
);
299 if (buf
->fmt
->fourcc
== V4L2_PIX_FMT_YUV422P
) {
300 /* FIXME the calculations should be more precise */
301 sglen_y
= dma
->sglen
/ 2;
302 sglen_u
= sglen_v
= dma
->sglen
/ 4 + 1;
303 sglen_yu
= sglen_y
+ sglen_u
;
305 size_u
= size_v
= size
/ 4;
307 sglen_y
= dma
->sglen
;
311 /* init DMA for Y channel */
312 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 0, sglen_y
,
317 "DMA initialization for Y/RGB failed\n");
321 if (buf
->fmt
->fourcc
== V4L2_PIX_FMT_YUV422P
) {
322 /* init DMA for U channel */
323 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 1, sglen_u
,
324 sglen_y
, 0x30, size_u
);
327 "DMA initialization for U failed\n");
331 /* init DMA for V channel */
332 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 2, sglen_v
,
333 sglen_yu
, 0x38, size_v
);
336 "DMA initialization for V failed\n");
341 vb
->state
= VIDEOBUF_PREPARED
;
345 buf
->active_dma
= DMA_Y
;
346 if (buf
->fmt
->fourcc
== V4L2_PIX_FMT_YUV422P
)
347 buf
->active_dma
|= DMA_U
| DMA_V
;
352 dma_free_coherent(pcdev
->dev
, buf
->dmas
[1].sg_size
,
353 buf
->dmas
[1].sg_cpu
, buf
->dmas
[1].sg_dma
);
355 dma_free_coherent(pcdev
->dev
, buf
->dmas
[0].sg_size
,
356 buf
->dmas
[0].sg_cpu
, buf
->dmas
[0].sg_dma
);
358 free_buffer(vq
, buf
);
364 static void pxa_videobuf_queue(struct videobuf_queue
*vq
,
365 struct videobuf_buffer
*vb
)
367 struct soc_camera_device
*icd
= vq
->priv_data
;
368 struct soc_camera_host
*ici
=
369 to_soc_camera_host(icd
->dev
.parent
);
370 struct pxa_camera_dev
*pcdev
= ici
->priv
;
371 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
372 struct pxa_buffer
*active
;
375 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
376 vb
, vb
->baddr
, vb
->bsize
);
377 spin_lock_irqsave(&pcdev
->lock
, flags
);
379 list_add_tail(&vb
->queue
, &pcdev
->capture
);
381 vb
->state
= VIDEOBUF_ACTIVE
;
382 active
= pcdev
->active
;
385 CIFR
|= CIFR_RESET_F
;
386 DDADR(pcdev
->dma_chans
[0]) = buf
->dmas
[0].sg_dma
;
387 DCSR(pcdev
->dma_chans
[0]) = DCSR_RUN
;
389 if (buf
->fmt
->fourcc
== V4L2_PIX_FMT_YUV422P
) {
390 DDADR(pcdev
->dma_chans
[1]) = buf
->dmas
[1].sg_dma
;
391 DCSR(pcdev
->dma_chans
[1]) = DCSR_RUN
;
393 DDADR(pcdev
->dma_chans
[2]) = buf
->dmas
[2].sg_dma
;
394 DCSR(pcdev
->dma_chans
[2]) = DCSR_RUN
;
400 struct pxa_cam_dma
*buf_dma
;
401 struct pxa_cam_dma
*act_dma
;
405 for (i
= 0; i
< pcdev
->channels
; i
++) {
406 buf_dma
= &buf
->dmas
[i
];
407 act_dma
= &active
->dmas
[i
];
408 nents
= buf_dma
->sglen
;
410 /* Stop DMA engine */
411 DCSR(pcdev
->dma_chans
[i
]) = 0;
413 /* Add the descriptors we just initialized to
414 the currently running chain */
415 act_dma
->sg_cpu
[act_dma
->sglen
- 1].ddadr
=
418 /* Setup a dummy descriptor with the DMA engines current
421 buf_dma
->sg_cpu
[nents
].dsadr
=
422 pcdev
->res
->start
+ 0x28 + i
*8; /* CIBRx */
423 buf_dma
->sg_cpu
[nents
].dtadr
=
424 DTADR(pcdev
->dma_chans
[i
]);
425 buf_dma
->sg_cpu
[nents
].dcmd
=
426 DCMD(pcdev
->dma_chans
[i
]);
428 if (DDADR(pcdev
->dma_chans
[i
]) == DDADR_STOP
) {
429 /* The DMA engine is on the last
430 descriptor, set the next descriptors
431 address to the descriptors we just
433 buf_dma
->sg_cpu
[nents
].ddadr
= buf_dma
->sg_dma
;
435 buf_dma
->sg_cpu
[nents
].ddadr
=
436 DDADR(pcdev
->dma_chans
[i
]);
439 /* The next descriptor is the dummy descriptor */
440 DDADR(pcdev
->dma_chans
[i
]) = buf_dma
->sg_dma
+ nents
*
441 sizeof(struct pxa_dma_desc
);
443 DCSR(pcdev
->dma_chans
[i
]) = DCSR_RUN
;
447 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
450 static void pxa_videobuf_release(struct videobuf_queue
*vq
,
451 struct videobuf_buffer
*vb
)
453 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
455 struct soc_camera_device
*icd
= vq
->priv_data
;
457 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
458 vb
, vb
->baddr
, vb
->bsize
);
461 case VIDEOBUF_ACTIVE
:
462 dev_dbg(&icd
->dev
, "%s (active)\n", __func__
);
464 case VIDEOBUF_QUEUED
:
465 dev_dbg(&icd
->dev
, "%s (queued)\n", __func__
);
467 case VIDEOBUF_PREPARED
:
468 dev_dbg(&icd
->dev
, "%s (prepared)\n", __func__
);
471 dev_dbg(&icd
->dev
, "%s (unknown)\n", __func__
);
476 free_buffer(vq
, buf
);
479 static void pxa_camera_wakeup(struct pxa_camera_dev
*pcdev
,
480 struct videobuf_buffer
*vb
,
481 struct pxa_buffer
*buf
)
483 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
484 list_del_init(&vb
->queue
);
485 vb
->state
= VIDEOBUF_DONE
;
486 do_gettimeofday(&vb
->ts
);
490 if (list_empty(&pcdev
->capture
)) {
491 pcdev
->active
= NULL
;
492 DCSR(pcdev
->dma_chans
[0]) = 0;
493 DCSR(pcdev
->dma_chans
[1]) = 0;
494 DCSR(pcdev
->dma_chans
[2]) = 0;
499 pcdev
->active
= list_entry(pcdev
->capture
.next
,
500 struct pxa_buffer
, vb
.queue
);
503 static void pxa_camera_dma_irq(int channel
, struct pxa_camera_dev
*pcdev
,
504 enum pxa_camera_active_dma act_dma
)
506 struct pxa_buffer
*buf
;
508 u32 status
, camera_status
, overrun
;
509 struct videobuf_buffer
*vb
;
511 spin_lock_irqsave(&pcdev
->lock
, flags
);
513 status
= DCSR(channel
);
514 DCSR(channel
) = status
| DCSR_ENDINTR
;
516 if (status
& DCSR_BUSERR
) {
517 dev_err(pcdev
->dev
, "DMA Bus Error IRQ!\n");
521 if (!(status
& DCSR_ENDINTR
)) {
522 dev_err(pcdev
->dev
, "Unknown DMA IRQ source, "
523 "status: 0x%08x\n", status
);
527 if (!pcdev
->active
) {
528 dev_err(pcdev
->dev
, "DMA End IRQ with no active buffer!\n");
532 camera_status
= CISR
;
533 overrun
= CISR_IFO_0
;
534 if (pcdev
->channels
== 3)
535 overrun
|= CISR_IFO_1
| CISR_IFO_2
;
536 if (camera_status
& overrun
) {
537 dev_dbg(pcdev
->dev
, "FIFO overrun! CISR: %x\n", camera_status
);
538 /* Stop the Capture Interface */
542 /* Reset the FIFOs */
543 CIFR
|= CIFR_RESET_F
;
544 /* Enable End-Of-Frame Interrupt */
545 CICR0
&= ~CICR0_EOFM
;
546 /* Restart the Capture Interface */
551 vb
= &pcdev
->active
->vb
;
552 buf
= container_of(vb
, struct pxa_buffer
, vb
);
553 WARN_ON(buf
->inwork
|| list_empty(&vb
->queue
));
554 dev_dbg(pcdev
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
555 vb
, vb
->baddr
, vb
->bsize
);
557 buf
->active_dma
&= ~act_dma
;
558 if (!buf
->active_dma
)
559 pxa_camera_wakeup(pcdev
, vb
, buf
);
562 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
565 static void pxa_camera_dma_irq_y(int channel
, void *data
)
567 struct pxa_camera_dev
*pcdev
= data
;
568 pxa_camera_dma_irq(channel
, pcdev
, DMA_Y
);
571 static void pxa_camera_dma_irq_u(int channel
, void *data
)
573 struct pxa_camera_dev
*pcdev
= data
;
574 pxa_camera_dma_irq(channel
, pcdev
, DMA_U
);
577 static void pxa_camera_dma_irq_v(int channel
, void *data
)
579 struct pxa_camera_dev
*pcdev
= data
;
580 pxa_camera_dma_irq(channel
, pcdev
, DMA_V
);
583 static struct videobuf_queue_ops pxa_videobuf_ops
= {
584 .buf_setup
= pxa_videobuf_setup
,
585 .buf_prepare
= pxa_videobuf_prepare
,
586 .buf_queue
= pxa_videobuf_queue
,
587 .buf_release
= pxa_videobuf_release
,
590 static int mclk_get_divisor(struct pxa_camera_dev
*pcdev
)
592 unsigned int mclk_10khz
= pcdev
->platform_mclk_10khz
;
594 unsigned long lcdclk
;
596 lcdclk
= clk_get_rate(pcdev
->clk
) / 10000;
598 /* We verify platform_mclk_10khz != 0, so if anyone breaks it, here
599 * they get a nice Oops */
600 div
= (lcdclk
+ 2 * mclk_10khz
- 1) / (2 * mclk_10khz
) - 1;
602 dev_dbg(pcdev
->dev
, "LCD clock %lukHz, target freq %dkHz, "
603 "divisor %lu\n", lcdclk
* 10, mclk_10khz
* 10, div
);
608 static void pxa_camera_activate(struct pxa_camera_dev
*pcdev
)
610 struct pxacamera_platform_data
*pdata
= pcdev
->pdata
;
613 dev_dbg(pcdev
->dev
, "Registered platform device at %p data %p\n",
616 if (pdata
&& pdata
->init
) {
617 dev_dbg(pcdev
->dev
, "%s: Init gpios\n", __func__
);
618 pdata
->init(pcdev
->dev
);
621 if (pdata
&& pdata
->power
) {
622 dev_dbg(pcdev
->dev
, "%s: Power on camera\n", __func__
);
623 pdata
->power(pcdev
->dev
, 1);
626 if (pdata
&& pdata
->reset
) {
627 dev_dbg(pcdev
->dev
, "%s: Releasing camera reset\n",
629 pdata
->reset(pcdev
->dev
, 1);
632 CICR0
= 0x3FF; /* disable all interrupts */
634 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
635 cicr4
|= CICR4_PCLK_EN
;
636 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
637 cicr4
|= CICR4_MCLK_EN
;
638 if (pcdev
->platform_flags
& PXA_CAMERA_PCP
)
640 if (pcdev
->platform_flags
& PXA_CAMERA_HSP
)
642 if (pcdev
->platform_flags
& PXA_CAMERA_VSP
)
645 CICR4
= mclk_get_divisor(pcdev
) | cicr4
;
647 clk_enable(pcdev
->clk
);
650 static void pxa_camera_deactivate(struct pxa_camera_dev
*pcdev
)
652 struct pxacamera_platform_data
*board
= pcdev
->pdata
;
654 clk_disable(pcdev
->clk
);
656 if (board
&& board
->reset
) {
657 dev_dbg(pcdev
->dev
, "%s: Asserting camera reset\n",
659 board
->reset(pcdev
->dev
, 0);
662 if (board
&& board
->power
) {
663 dev_dbg(pcdev
->dev
, "%s: Power off camera\n", __func__
);
664 board
->power(pcdev
->dev
, 0);
668 static irqreturn_t
pxa_camera_irq(int irq
, void *data
)
670 struct pxa_camera_dev
*pcdev
= data
;
671 unsigned int status
= CISR
;
673 dev_dbg(pcdev
->dev
, "Camera interrupt status 0x%x\n", status
);
680 if (status
& CISR_EOF
) {
682 for (i
= 0; i
< pcdev
->channels
; i
++) {
683 DDADR(pcdev
->dma_chans
[i
]) =
684 pcdev
->active
->dmas
[i
].sg_dma
;
685 DCSR(pcdev
->dma_chans
[i
]) = DCSR_RUN
;
693 /* The following two functions absolutely depend on the fact, that
694 * there can be only one camera on PXA quick capture interface */
695 static int pxa_camera_add_device(struct soc_camera_device
*icd
)
697 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
698 struct pxa_camera_dev
*pcdev
= ici
->priv
;
701 mutex_lock(&camera_lock
);
708 dev_info(&icd
->dev
, "PXA Camera driver attached to camera %d\n",
711 pxa_camera_activate(pcdev
);
712 ret
= icd
->ops
->init(icd
);
718 mutex_unlock(&camera_lock
);
723 static void pxa_camera_remove_device(struct soc_camera_device
*icd
)
725 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
726 struct pxa_camera_dev
*pcdev
= ici
->priv
;
728 BUG_ON(icd
!= pcdev
->icd
);
730 dev_info(&icd
->dev
, "PXA Camera driver detached from camera %d\n",
733 /* disable capture, disable interrupts */
736 /* Stop DMA engine */
737 DCSR(pcdev
->dma_chans
[0]) = 0;
738 DCSR(pcdev
->dma_chans
[1]) = 0;
739 DCSR(pcdev
->dma_chans
[2]) = 0;
741 icd
->ops
->release(icd
);
743 pxa_camera_deactivate(pcdev
);
748 static int test_platform_param(struct pxa_camera_dev
*pcdev
,
749 unsigned char buswidth
, unsigned long *flags
)
752 * Platform specified synchronization and pixel clock polarities are
753 * only a recommendation and are only used during probing. The PXA270
754 * quick capture interface supports both.
756 *flags
= (pcdev
->platform_flags
& PXA_CAMERA_MASTER
?
757 SOCAM_MASTER
: SOCAM_SLAVE
) |
758 SOCAM_HSYNC_ACTIVE_HIGH
|
759 SOCAM_HSYNC_ACTIVE_LOW
|
760 SOCAM_VSYNC_ACTIVE_HIGH
|
761 SOCAM_VSYNC_ACTIVE_LOW
|
762 SOCAM_PCLK_SAMPLE_RISING
|
763 SOCAM_PCLK_SAMPLE_FALLING
;
765 /* If requested data width is supported by the platform, use it */
768 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_10
))
770 *flags
|= SOCAM_DATAWIDTH_10
;
773 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_9
))
775 *flags
|= SOCAM_DATAWIDTH_9
;
778 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_8
))
780 *flags
|= SOCAM_DATAWIDTH_8
;
786 static int pxa_camera_set_bus_param(struct soc_camera_device
*icd
, __u32 pixfmt
)
788 struct soc_camera_host
*ici
=
789 to_soc_camera_host(icd
->dev
.parent
);
790 struct pxa_camera_dev
*pcdev
= ici
->priv
;
791 unsigned long dw
, bpp
, bus_flags
, camera_flags
, common_flags
;
792 u32 cicr0
, cicr1
, cicr4
= 0;
793 int ret
= test_platform_param(pcdev
, icd
->buswidth
, &bus_flags
);
798 camera_flags
= icd
->ops
->query_bus_param(icd
);
800 common_flags
= soc_camera_bus_param_compatible(camera_flags
, bus_flags
);
806 /* Make choises, based on platform preferences */
807 if ((common_flags
& SOCAM_HSYNC_ACTIVE_HIGH
) &&
808 (common_flags
& SOCAM_HSYNC_ACTIVE_LOW
)) {
809 if (pcdev
->platform_flags
& PXA_CAMERA_HSP
)
810 common_flags
&= ~SOCAM_HSYNC_ACTIVE_HIGH
;
812 common_flags
&= ~SOCAM_HSYNC_ACTIVE_LOW
;
815 if ((common_flags
& SOCAM_VSYNC_ACTIVE_HIGH
) &&
816 (common_flags
& SOCAM_VSYNC_ACTIVE_LOW
)) {
817 if (pcdev
->platform_flags
& PXA_CAMERA_VSP
)
818 common_flags
&= ~SOCAM_VSYNC_ACTIVE_HIGH
;
820 common_flags
&= ~SOCAM_VSYNC_ACTIVE_LOW
;
823 if ((common_flags
& SOCAM_PCLK_SAMPLE_RISING
) &&
824 (common_flags
& SOCAM_PCLK_SAMPLE_FALLING
)) {
825 if (pcdev
->platform_flags
& PXA_CAMERA_PCP
)
826 common_flags
&= ~SOCAM_PCLK_SAMPLE_RISING
;
828 common_flags
&= ~SOCAM_PCLK_SAMPLE_FALLING
;
831 ret
= icd
->ops
->set_bus_param(icd
, common_flags
);
835 /* Datawidth is now guaranteed to be equal to one of the three values.
836 * We fix bit-per-pixel equal to data-width... */
837 switch (common_flags
& SOCAM_DATAWIDTH_MASK
) {
838 case SOCAM_DATAWIDTH_10
:
843 case SOCAM_DATAWIDTH_9
:
849 /* Actually it can only be 8 now,
850 * default is just to silence compiler warnings */
851 case SOCAM_DATAWIDTH_8
:
857 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
858 cicr4
|= CICR4_PCLK_EN
;
859 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
860 cicr4
|= CICR4_MCLK_EN
;
861 if (common_flags
& SOCAM_PCLK_SAMPLE_FALLING
)
863 if (common_flags
& SOCAM_HSYNC_ACTIVE_LOW
)
865 if (common_flags
& SOCAM_VSYNC_ACTIVE_LOW
)
869 if (cicr0
& CICR0_ENB
)
870 CICR0
= cicr0
& ~CICR0_ENB
;
872 cicr1
= CICR1_PPL_VAL(icd
->width
- 1) | bpp
| dw
;
875 case V4L2_PIX_FMT_YUV422P
:
877 cicr1
|= CICR1_YCBCR_F
;
878 case V4L2_PIX_FMT_YUYV
:
879 cicr1
|= CICR1_COLOR_SP_VAL(2);
881 case V4L2_PIX_FMT_RGB555
:
882 cicr1
|= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
883 CICR1_TBIT
| CICR1_COLOR_SP_VAL(1);
885 case V4L2_PIX_FMT_RGB565
:
886 cicr1
|= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
892 CICR3
= CICR3_LPF_VAL(icd
->height
- 1) |
893 CICR3_BFW_VAL(min((unsigned short)255, icd
->y_skip_top
));
894 CICR4
= mclk_get_divisor(pcdev
) | cicr4
;
896 /* CIF interrupts are not used, only DMA */
897 CICR0
= (pcdev
->platform_flags
& PXA_CAMERA_MASTER
?
898 CICR0_SIM_MP
: (CICR0_SL_CAP_EN
| CICR0_SIM_SP
)) |
899 CICR0_DMAEN
| CICR0_IRQ_MASK
| (cicr0
& CICR0_ENB
);
904 static int pxa_camera_try_bus_param(struct soc_camera_device
*icd
, __u32 pixfmt
)
906 struct soc_camera_host
*ici
=
907 to_soc_camera_host(icd
->dev
.parent
);
908 struct pxa_camera_dev
*pcdev
= ici
->priv
;
909 unsigned long bus_flags
, camera_flags
;
910 int ret
= test_platform_param(pcdev
, icd
->buswidth
, &bus_flags
);
915 camera_flags
= icd
->ops
->query_bus_param(icd
);
917 return soc_camera_bus_param_compatible(camera_flags
, bus_flags
) ? 0 : -EINVAL
;
920 static int pxa_camera_set_fmt_cap(struct soc_camera_device
*icd
,
921 __u32 pixfmt
, struct v4l2_rect
*rect
)
923 return icd
->ops
->set_fmt_cap(icd
, pixfmt
, rect
);
926 static int pxa_camera_try_fmt_cap(struct soc_camera_device
*icd
,
927 struct v4l2_format
*f
)
929 /* limit to pxa hardware capabilities */
930 if (f
->fmt
.pix
.height
< 32)
931 f
->fmt
.pix
.height
= 32;
932 if (f
->fmt
.pix
.height
> 2048)
933 f
->fmt
.pix
.height
= 2048;
934 if (f
->fmt
.pix
.width
< 48)
935 f
->fmt
.pix
.width
= 48;
936 if (f
->fmt
.pix
.width
> 2048)
937 f
->fmt
.pix
.width
= 2048;
938 f
->fmt
.pix
.width
&= ~0x01;
940 /* limit to sensor capabilities */
941 return icd
->ops
->try_fmt_cap(icd
, f
);
944 static int pxa_camera_reqbufs(struct soc_camera_file
*icf
,
945 struct v4l2_requestbuffers
*p
)
949 /* This is for locking debugging only. I removed spinlocks and now I
950 * check whether .prepare is ever called on a linked buffer, or whether
951 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
952 * it hadn't triggered */
953 for (i
= 0; i
< p
->count
; i
++) {
954 struct pxa_buffer
*buf
= container_of(icf
->vb_vidq
.bufs
[i
],
955 struct pxa_buffer
, vb
);
957 INIT_LIST_HEAD(&buf
->vb
.queue
);
963 static unsigned int pxa_camera_poll(struct file
*file
, poll_table
*pt
)
965 struct soc_camera_file
*icf
= file
->private_data
;
966 struct pxa_buffer
*buf
;
968 buf
= list_entry(icf
->vb_vidq
.stream
.next
, struct pxa_buffer
,
971 poll_wait(file
, &buf
->vb
.done
, pt
);
973 if (buf
->vb
.state
== VIDEOBUF_DONE
||
974 buf
->vb
.state
== VIDEOBUF_ERROR
)
975 return POLLIN
|POLLRDNORM
;
980 static int pxa_camera_querycap(struct soc_camera_host
*ici
,
981 struct v4l2_capability
*cap
)
983 /* cap->name is set by the firendly caller:-> */
984 strlcpy(cap
->card
, pxa_cam_driver_description
, sizeof(cap
->card
));
985 cap
->version
= PXA_CAM_VERSION_CODE
;
986 cap
->capabilities
= V4L2_CAP_VIDEO_CAPTURE
| V4L2_CAP_STREAMING
;
991 static spinlock_t
*pxa_camera_spinlock_alloc(struct soc_camera_file
*icf
)
993 struct soc_camera_host
*ici
=
994 to_soc_camera_host(icf
->icd
->dev
.parent
);
995 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1000 static struct soc_camera_host_ops pxa_soc_camera_host_ops
= {
1001 .owner
= THIS_MODULE
,
1002 .add
= pxa_camera_add_device
,
1003 .remove
= pxa_camera_remove_device
,
1004 .set_fmt_cap
= pxa_camera_set_fmt_cap
,
1005 .try_fmt_cap
= pxa_camera_try_fmt_cap
,
1006 .reqbufs
= pxa_camera_reqbufs
,
1007 .poll
= pxa_camera_poll
,
1008 .querycap
= pxa_camera_querycap
,
1009 .try_bus_param
= pxa_camera_try_bus_param
,
1010 .set_bus_param
= pxa_camera_set_bus_param
,
1011 .spinlock_alloc
= pxa_camera_spinlock_alloc
,
1014 /* Should be allocated dynamically too, but we have only one. */
1015 static struct soc_camera_host pxa_soc_camera_host
= {
1016 .drv_name
= PXA_CAM_DRV_NAME
,
1017 .vbq_ops
= &pxa_videobuf_ops
,
1018 .msize
= sizeof(struct pxa_buffer
),
1019 .ops
= &pxa_soc_camera_host_ops
,
1022 static int pxa_camera_probe(struct platform_device
*pdev
)
1024 struct pxa_camera_dev
*pcdev
;
1025 struct resource
*res
;
1030 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1031 irq
= platform_get_irq(pdev
, 0);
1037 pcdev
= kzalloc(sizeof(*pcdev
), GFP_KERNEL
);
1039 dev_err(&pdev
->dev
, "Could not allocate pcdev\n");
1044 pcdev
->clk
= clk_get(&pdev
->dev
, "CAMCLK");
1045 if (IS_ERR(pcdev
->clk
)) {
1046 err
= PTR_ERR(pcdev
->clk
);
1050 dev_set_drvdata(&pdev
->dev
, pcdev
);
1053 pcdev
->pdata
= pdev
->dev
.platform_data
;
1054 pcdev
->platform_flags
= pcdev
->pdata
->flags
;
1055 if (!(pcdev
->platform_flags
& (PXA_CAMERA_DATAWIDTH_8
|
1056 PXA_CAMERA_DATAWIDTH_9
| PXA_CAMERA_DATAWIDTH_10
))) {
1057 /* Platform hasn't set available data widths. This is bad.
1058 * Warn and use a default. */
1059 dev_warn(&pdev
->dev
, "WARNING! Platform hasn't set available "
1060 "data widths, using default 10 bit\n");
1061 pcdev
->platform_flags
|= PXA_CAMERA_DATAWIDTH_10
;
1063 pcdev
->platform_mclk_10khz
= pcdev
->pdata
->mclk_10khz
;
1064 if (!pcdev
->platform_mclk_10khz
) {
1065 dev_warn(&pdev
->dev
,
1066 "mclk_10khz == 0! Please, fix your platform data. "
1067 "Using default 20MHz\n");
1068 pcdev
->platform_mclk_10khz
= 2000;
1071 INIT_LIST_HEAD(&pcdev
->capture
);
1072 spin_lock_init(&pcdev
->lock
);
1075 * Request the regions.
1077 if (!request_mem_region(res
->start
, res
->end
- res
->start
+ 1,
1078 PXA_CAM_DRV_NAME
)) {
1083 base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
1090 pcdev
->dev
= &pdev
->dev
;
1093 pcdev
->dma_chans
[0] = pxa_request_dma("CI_Y", DMA_PRIO_HIGH
,
1094 pxa_camera_dma_irq_y
, pcdev
);
1095 if (pcdev
->dma_chans
[0] < 0) {
1096 dev_err(pcdev
->dev
, "Can't request DMA for Y\n");
1100 dev_dbg(pcdev
->dev
, "got DMA channel %d\n", pcdev
->dma_chans
[0]);
1102 pcdev
->dma_chans
[1] = pxa_request_dma("CI_U", DMA_PRIO_HIGH
,
1103 pxa_camera_dma_irq_u
, pcdev
);
1104 if (pcdev
->dma_chans
[1] < 0) {
1105 dev_err(pcdev
->dev
, "Can't request DMA for U\n");
1107 goto exit_free_dma_y
;
1109 dev_dbg(pcdev
->dev
, "got DMA channel (U) %d\n", pcdev
->dma_chans
[1]);
1111 pcdev
->dma_chans
[2] = pxa_request_dma("CI_V", DMA_PRIO_HIGH
,
1112 pxa_camera_dma_irq_v
, pcdev
);
1113 if (pcdev
->dma_chans
[0] < 0) {
1114 dev_err(pcdev
->dev
, "Can't request DMA for V\n");
1116 goto exit_free_dma_u
;
1118 dev_dbg(pcdev
->dev
, "got DMA channel (V) %d\n", pcdev
->dma_chans
[2]);
1120 DRCMR68
= pcdev
->dma_chans
[0] | DRCMR_MAPVLD
;
1121 DRCMR69
= pcdev
->dma_chans
[1] | DRCMR_MAPVLD
;
1122 DRCMR70
= pcdev
->dma_chans
[2] | DRCMR_MAPVLD
;
1125 err
= request_irq(pcdev
->irq
, pxa_camera_irq
, 0, PXA_CAM_DRV_NAME
,
1128 dev_err(pcdev
->dev
, "Camera interrupt register failed \n");
1132 pxa_soc_camera_host
.priv
= pcdev
;
1133 pxa_soc_camera_host
.dev
.parent
= &pdev
->dev
;
1134 pxa_soc_camera_host
.nr
= pdev
->id
;
1135 err
= soc_camera_host_register(&pxa_soc_camera_host
);
1142 free_irq(pcdev
->irq
, pcdev
);
1144 pxa_free_dma(pcdev
->dma_chans
[2]);
1146 pxa_free_dma(pcdev
->dma_chans
[1]);
1148 pxa_free_dma(pcdev
->dma_chans
[0]);
1152 release_mem_region(res
->start
, res
->end
- res
->start
+ 1);
1154 clk_put(pcdev
->clk
);
1161 static int __devexit
pxa_camera_remove(struct platform_device
*pdev
)
1163 struct pxa_camera_dev
*pcdev
= platform_get_drvdata(pdev
);
1164 struct resource
*res
;
1166 clk_put(pcdev
->clk
);
1168 pxa_free_dma(pcdev
->dma_chans
[0]);
1169 pxa_free_dma(pcdev
->dma_chans
[1]);
1170 pxa_free_dma(pcdev
->dma_chans
[2]);
1171 free_irq(pcdev
->irq
, pcdev
);
1173 soc_camera_host_unregister(&pxa_soc_camera_host
);
1175 iounmap(pcdev
->base
);
1178 release_mem_region(res
->start
, res
->end
- res
->start
+ 1);
1182 dev_info(&pdev
->dev
, "PXA Camera driver unloaded\n");
1187 static struct platform_driver pxa_camera_driver
= {
1189 .name
= PXA_CAM_DRV_NAME
,
1191 .probe
= pxa_camera_probe
,
1192 .remove
= __exit_p(pxa_camera_remove
),
1196 static int __devinit
pxa_camera_init(void)
1198 return platform_driver_register(&pxa_camera_driver
);
1201 static void __exit
pxa_camera_exit(void)
1203 return platform_driver_unregister(&pxa_camera_driver
);
1206 module_init(pxa_camera_init
);
1207 module_exit(pxa_camera_exit
);
1209 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1210 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1211 MODULE_LICENSE("GPL");