6 bool "Memory Controller drivers"
11 bool "Atmel (Multi-port DDR-)SDRAM Controller"
13 depends on ARCH_AT91 && OF
15 This driver is for Atmel SDRAM Controller or Atmel Multi-port
16 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
17 Starting with the at91sam9g45, this controller supports SDR, DDR and
21 tristate "Texas Instruments AEMIF driver"
22 depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
24 This driver is for the AEMIF module available in Texas Instruments
25 SoCs. AEMIF stands for Asynchronous External Memory Interface and
26 is intended to provide a glue-less interface to a variety of
27 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
28 of 256M bytes of any of these memories can be accessed at a given
29 time via four chip selects with 64M byte access per chip select.
32 tristate "Texas Instruments EMIF driver"
33 depends on ARCH_OMAP2PLUS
36 This driver is for the EMIF module available in Texas Instruments
37 SoCs. EMIF is an SDRAM controller that, based on its revision,
38 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
39 This driver takes care of only LPDDR2 memories presently. The
40 functions of the driver includes re-configuring AC timing
41 parameters and other settings during frequency, voltage and
45 bool "Marvell EBU Device Bus Controller"
47 depends on PLAT_ORION && OF
49 This driver is for the Device Bus controller available in some
50 Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
51 Armada 370 and Armada XP. This controller allows to handle flash
52 devices such as NOR, NAND, SRAM, and FPGA.
55 bool "Tegra20 Memory Controller(MC) driver"
57 depends on ARCH_TEGRA_2x_SOC
59 This driver is for the Memory Controller(MC) module available
60 in Tegra20 SoCs, mainly for a address translation fault
61 analysis, especially for IOMMU/GART(Graphics Address
62 Relocation Table) module.
65 bool "Tegra30 Memory Controller(MC) driver"
67 depends on ARCH_TEGRA_3x_SOC
69 This driver is for the Memory Controller(MC) module available
70 in Tegra30 SoCs, mainly for a address translation fault
71 analysis, especially for IOMMU/SMMU(System Memory Management
75 tristate "Freescale CoreNet Error Reporting"
76 depends on FSL_SOC_BOOKE
78 Say Y for reporting of errors from the Freescale CoreNet
79 Coherency Fabric. Errors reported include accesses to
80 physical addresses that mapped by no local access window
81 (LAW) or an invalid LAW, as well as bad cache state that
82 represents a coherency violation.