2 * Marvell EBU SoC Device Bus Controller
3 * (memory controller for NOR/NAND/SRAM/FPGA devices)
5 * Copyright (C) 2013 Marvell
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/err.h>
26 #include <linux/clk.h>
27 #include <linux/mbus.h>
28 #include <linux/of_platform.h>
29 #include <linux/of_address.h>
30 #include <linux/platform_device.h>
32 /* Register definitions */
33 #define DEV_WIDTH_BIT 30
34 #define BADR_SKEW_BIT 28
35 #define RD_HOLD_BIT 23
36 #define ACC_NEXT_BIT 17
37 #define RD_SETUP_BIT 12
38 #define ACC_FIRST_BIT 6
40 #define SYNC_ENABLE_BIT 24
41 #define WR_HIGH_BIT 16
44 #define READ_PARAM_OFFSET 0x0
45 #define WRITE_PARAM_OFFSET 0x4
47 static const char * const devbus_wins
[] = {
55 struct devbus_read_params
{
65 struct devbus_write_params
{
75 unsigned long tick_ps
;
78 static int get_timing_param_ps(struct devbus
*devbus
,
79 struct device_node
*node
,
86 err
= of_property_read_u32(node
, name
, &time_ps
);
88 dev_err(devbus
->dev
, "%s has no '%s' property\n",
89 name
, node
->full_name
);
93 *ticks
= (time_ps
+ devbus
->tick_ps
- 1) / devbus
->tick_ps
;
95 dev_dbg(devbus
->dev
, "%s: %u ps -> 0x%x\n",
96 name
, time_ps
, *ticks
);
100 static int devbus_set_timing_params(struct devbus
*devbus
,
101 struct device_node
*node
)
103 struct devbus_read_params r
;
104 struct devbus_write_params w
;
108 dev_dbg(devbus
->dev
, "Setting timing parameter, tick is %lu ps\n",
111 /* Get read timings */
112 err
= of_property_read_u32(node
, "devbus,bus-width", &r
.bus_width
);
115 "%s has no 'devbus,bus-width' property\n",
119 /* Convert bit width to byte width */
122 err
= get_timing_param_ps(devbus
, node
, "devbus,badr-skew-ps",
127 err
= get_timing_param_ps(devbus
, node
, "devbus,turn-off-ps",
132 err
= get_timing_param_ps(devbus
, node
, "devbus,acc-first-ps",
137 err
= get_timing_param_ps(devbus
, node
, "devbus,acc-next-ps",
142 err
= get_timing_param_ps(devbus
, node
, "devbus,rd-setup-ps",
147 err
= get_timing_param_ps(devbus
, node
, "devbus,rd-hold-ps",
152 /* Get write timings */
153 err
= of_property_read_u32(node
, "devbus,sync-enable",
157 "%s has no 'devbus,sync-enable' property\n",
162 err
= get_timing_param_ps(devbus
, node
, "devbus,ale-wr-ps",
167 err
= get_timing_param_ps(devbus
, node
, "devbus,wr-low-ps",
172 err
= get_timing_param_ps(devbus
, node
, "devbus,wr-high-ps",
177 /* Set read timings */
178 value
= r
.bus_width
<< DEV_WIDTH_BIT
|
179 r
.badr_skew
<< BADR_SKEW_BIT
|
180 r
.rd_hold
<< RD_HOLD_BIT
|
181 r
.acc_next
<< ACC_NEXT_BIT
|
182 r
.rd_setup
<< RD_SETUP_BIT
|
183 r
.acc_first
<< ACC_FIRST_BIT
|
186 dev_dbg(devbus
->dev
, "read parameters register 0x%p = 0x%x\n",
187 devbus
->base
+ READ_PARAM_OFFSET
,
190 writel(value
, devbus
->base
+ READ_PARAM_OFFSET
);
192 /* Set write timings */
193 value
= w
.sync_enable
<< SYNC_ENABLE_BIT
|
194 w
.wr_low
<< WR_LOW_BIT
|
195 w
.wr_high
<< WR_HIGH_BIT
|
198 dev_dbg(devbus
->dev
, "write parameters register: 0x%p = 0x%x\n",
199 devbus
->base
+ WRITE_PARAM_OFFSET
,
202 writel(value
, devbus
->base
+ WRITE_PARAM_OFFSET
);
207 static int mvebu_devbus_probe(struct platform_device
*pdev
)
209 struct device
*dev
= &pdev
->dev
;
210 struct device_node
*node
= pdev
->dev
.of_node
;
211 struct device_node
*parent
;
212 struct devbus
*devbus
;
213 struct resource
*res
;
216 const __be32
*ranges
;
218 int addr_cells
, p_addr_cells
, size_cells
;
219 int ranges_len
, tuple_len
;
222 devbus
= devm_kzalloc(&pdev
->dev
, sizeof(struct devbus
), GFP_KERNEL
);
227 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
228 devbus
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
229 if (IS_ERR(devbus
->base
))
230 return PTR_ERR(devbus
->base
);
232 clk
= devm_clk_get(&pdev
->dev
, NULL
);
235 clk_prepare_enable(clk
);
238 * Obtain clock period in picoseconds,
239 * we need this in order to convert timing
240 * parameters from cycles to picoseconds.
242 rate
= clk_get_rate(clk
) / 1000;
243 devbus
->tick_ps
= 1000000000 / rate
;
245 /* Read the device tree node and set the new timing parameters */
246 err
= devbus_set_timing_params(devbus
, node
);
251 * Allocate an address window for this device.
252 * If the device probing fails, then we won't be able to
253 * remove the allocated address decoding window.
255 * FIXME: This is only a temporary hack! We need to do this here
256 * because we still don't have device tree bindings for mbus.
257 * Once that support is added, we will declare these address windows
258 * statically in the device tree, and remove the window configuration
263 * Get the CS to choose the window string.
264 * This is a bit hacky, but it will be removed once the
265 * address windows are declared in the device tree.
267 cs
= (((unsigned long)devbus
->base
) % 0x400) / 8;
270 * Parse 'ranges' property to obtain a (base,size) window tuple.
271 * This will be removed once the address windows
272 * are declared in the device tree.
274 parent
= of_get_parent(node
);
278 p_addr_cells
= of_n_addr_cells(parent
);
281 addr_cells
= of_n_addr_cells(node
);
282 size_cells
= of_n_size_cells(node
);
283 tuple_len
= (p_addr_cells
+ addr_cells
+ size_cells
) * sizeof(__be32
);
285 ranges
= of_get_property(node
, "ranges", &ranges_len
);
286 if (ranges
== NULL
|| ranges_len
!= tuple_len
)
289 base
= of_translate_address(node
, ranges
+ addr_cells
);
290 if (base
== OF_BAD_ADDR
)
292 size
= of_read_number(ranges
+ addr_cells
+ p_addr_cells
, size_cells
);
295 * Create an mbus address windows.
296 * FIXME: Remove this, together with the above code, once the
297 * address windows are declared in the device tree.
299 err
= mvebu_mbus_add_window(devbus_wins
[cs
], base
, size
);
304 * We need to create a child device explicitly from here to
305 * guarantee that the child will be probed after the timing
306 * parameters for the bus are written.
308 err
= of_platform_populate(node
, NULL
, NULL
, dev
);
310 mvebu_mbus_del_window(base
, size
);
317 static const struct of_device_id mvebu_devbus_of_match
[] = {
318 { .compatible
= "marvell,mvebu-devbus" },
321 MODULE_DEVICE_TABLE(of
, mvebu_devbus_of_match
);
323 static struct platform_driver mvebu_devbus_driver
= {
324 .probe
= mvebu_devbus_probe
,
326 .name
= "mvebu-devbus",
327 .owner
= THIS_MODULE
,
328 .of_match_table
= mvebu_devbus_of_match
,
332 static int __init
mvebu_devbus_init(void)
334 return platform_driver_register(&mvebu_devbus_driver
);
336 module_init(mvebu_devbus_init
);
338 MODULE_LICENSE("GPL v2");
339 MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@free-electrons.com>");
340 MODULE_DESCRIPTION("Marvell EBU SoC Device Bus controller");