2 * Tegra20 Memory Controller
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/ratelimit.h>
23 #include <linux/platform_device.h>
24 #include <linux/interrupt.h>
27 #define DRV_NAME "tegra20-mc"
29 #define MC_INTSTATUS 0x0
30 #define MC_INTMASK 0x4
32 #define MC_INT_ERR_SHIFT 6
33 #define MC_INT_ERR_MASK (0x1f << MC_INT_ERR_SHIFT)
34 #define MC_INT_DECERR_EMEM BIT(MC_INT_ERR_SHIFT)
35 #define MC_INT_INVALID_GART_PAGE BIT(MC_INT_ERR_SHIFT + 1)
36 #define MC_INT_SECURITY_VIOLATION BIT(MC_INT_ERR_SHIFT + 2)
37 #define MC_INT_ARBITRATION_EMEM BIT(MC_INT_ERR_SHIFT + 3)
39 #define MC_GART_ERROR_REQ 0x30
40 #define MC_DECERR_EMEM_OTHERS_STATUS 0x58
41 #define MC_SECURITY_VIOLATION_STATUS 0x74
43 #define SECURITY_VIOLATION_TYPE BIT(30) /* 0=TRUSTZONE, 1=CARVEOUT */
45 #define MC_CLIENT_ID_MASK 0x3f
47 #define NUM_MC_REG_BANKS 2
50 void __iomem
*regs
[NUM_MC_REG_BANKS
];
54 static inline u32
mc_readl(struct tegra20_mc
*mc
, u32 offs
)
59 val
= readl(mc
->regs
[0] + offs
);
60 else if (offs
< 0x400)
61 val
= readl(mc
->regs
[1] + offs
- 0x3c);
66 static inline void mc_writel(struct tegra20_mc
*mc
, u32 val
, u32 offs
)
69 writel(val
, mc
->regs
[0] + offs
);
70 else if (offs
< 0x400)
71 writel(val
, mc
->regs
[1] + offs
- 0x3c);
74 static const char * const tegra20_mc_client
[] = {
129 static void tegra20_mc_decode(struct tegra20_mc
*mc
, int n
)
132 const char *client
= "Unknown";
134 const struct reg_info
{
136 u32 write_bit
; /* 0=READ, 1=WRITE */
141 .offset
= MC_DECERR_EMEM_OTHERS_STATUS
,
143 .message
= "MC_DECERR",
146 .offset
= MC_GART_ERROR_REQ
,
148 .message
= "MC_GART_ERR",
152 .offset
= MC_SECURITY_VIOLATION_STATUS
,
154 .message
= "MC_SECURITY_ERR",
158 idx
= n
- MC_INT_ERR_SHIFT
;
159 if ((idx
< 0) || (idx
>= ARRAY_SIZE(reg
))) {
160 dev_err_ratelimited(mc
->dev
, "Unknown interrupt status %08lx\n",
165 req
= mc_readl(mc
, reg
[idx
].offset
);
166 cid
= (req
>> reg
[idx
].cid_shift
) & MC_CLIENT_ID_MASK
;
167 if (cid
< ARRAY_SIZE(tegra20_mc_client
))
168 client
= tegra20_mc_client
[cid
];
170 addr
= mc_readl(mc
, reg
[idx
].offset
+ sizeof(u32
));
172 dev_err_ratelimited(mc
->dev
, "%s (0x%08x): 0x%08x %s (%s %s)\n",
173 reg
[idx
].message
, req
, addr
, client
,
174 (req
& BIT(reg
[idx
].write_bit
)) ? "write" : "read",
175 (reg
[idx
].offset
== MC_SECURITY_VIOLATION_STATUS
) ?
176 ((req
& SECURITY_VIOLATION_TYPE
) ?
177 "carveout" : "trustzone") : "");
180 static const struct of_device_id tegra20_mc_of_match
[] = {
181 { .compatible
= "nvidia,tegra20-mc", },
185 static irqreturn_t
tegra20_mc_isr(int irq
, void *data
)
188 struct tegra20_mc
*mc
= data
;
190 stat
= mc_readl(mc
, MC_INTSTATUS
);
191 mask
= mc_readl(mc
, MC_INTMASK
);
195 while ((bit
= ffs(mask
)) != 0)
196 tegra20_mc_decode(mc
, bit
- 1);
197 mc_writel(mc
, stat
, MC_INTSTATUS
);
201 static int tegra20_mc_probe(struct platform_device
*pdev
)
203 struct resource
*irq
;
204 struct tegra20_mc
*mc
;
208 mc
= devm_kzalloc(&pdev
->dev
, sizeof(*mc
), GFP_KERNEL
);
211 mc
->dev
= &pdev
->dev
;
213 for (i
= 0; i
< ARRAY_SIZE(mc
->regs
); i
++) {
214 struct resource
*res
;
216 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, i
);
219 mc
->regs
[i
] = devm_request_and_ioremap(&pdev
->dev
, res
);
224 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
227 err
= devm_request_irq(&pdev
->dev
, irq
->start
, tegra20_mc_isr
,
228 IRQF_SHARED
, dev_name(&pdev
->dev
), mc
);
232 platform_set_drvdata(pdev
, mc
);
234 intmask
= MC_INT_INVALID_GART_PAGE
|
235 MC_INT_DECERR_EMEM
| MC_INT_SECURITY_VIOLATION
;
236 mc_writel(mc
, intmask
, MC_INTMASK
);
240 static struct platform_driver tegra20_mc_driver
= {
241 .probe
= tegra20_mc_probe
,
244 .owner
= THIS_MODULE
,
245 .of_match_table
= tegra20_mc_of_match
,
248 module_platform_driver(tegra20_mc_driver
);
250 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
251 MODULE_DESCRIPTION("Tegra20 MC driver");
252 MODULE_LICENSE("GPL v2");
253 MODULE_ALIAS("platform:" DRV_NAME
);