2 * Intel Sunrisepoint LPSS core support.
4 * Copyright (C) 2015, Intel Corporation
6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * Heikki Krogerus <heikki.krogerus@linux.intel.com>
9 * Jarkko Nikula <jarkko.nikula@linux.intel.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/clk.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk-provider.h>
19 #include <linux/debugfs.h>
20 #include <linux/idr.h>
21 #include <linux/ioport.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/mfd/core.h>
25 #include <linux/pm_qos.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/seq_file.h>
29 #include "intel-lpss.h"
31 #define LPSS_DEV_OFFSET 0x000
32 #define LPSS_DEV_SIZE 0x200
33 #define LPSS_PRIV_OFFSET 0x200
34 #define LPSS_PRIV_SIZE 0x100
35 #define LPSS_IDMA64_OFFSET 0x800
36 #define LPSS_IDMA64_SIZE 0x800
38 /* Offsets from lpss->priv */
39 #define LPSS_PRIV_RESETS 0x04
40 #define LPSS_PRIV_RESETS_FUNC BIT(2)
41 #define LPSS_PRIV_RESETS_IDMA 0x3
43 #define LPSS_PRIV_ACTIVELTR 0x10
44 #define LPSS_PRIV_IDLELTR 0x14
46 #define LPSS_PRIV_LTR_REQ BIT(15)
47 #define LPSS_PRIV_LTR_SCALE_MASK 0xc00
48 #define LPSS_PRIV_LTR_SCALE_1US 0x800
49 #define LPSS_PRIV_LTR_SCALE_32US 0xc00
50 #define LPSS_PRIV_LTR_VALUE_MASK 0x3ff
52 #define LPSS_PRIV_SSP_REG 0x20
53 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
55 #define LPSS_PRIV_REMAP_ADDR_LO 0x40
56 #define LPSS_PRIV_REMAP_ADDR_HI 0x44
58 #define LPSS_PRIV_CAPS 0xfc
59 #define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
60 #define LPSS_PRIV_CAPS_TYPE_SHIFT 4
61 #define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
63 /* This matches the type field in CAPS register */
64 enum intel_lpss_dev_type
{
71 const struct intel_lpss_platform_info
*info
;
72 enum intel_lpss_dev_type type
;
74 struct clk_lookup
*clock
;
75 const struct mfd_cell
*cell
;
82 struct dentry
*debugfs
;
85 static const struct resource intel_lpss_dev_resources
[] = {
86 DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET
, LPSS_DEV_SIZE
, "lpss_dev"),
87 DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET
, LPSS_PRIV_SIZE
, "lpss_priv"),
91 static const struct resource intel_lpss_idma64_resources
[] = {
92 DEFINE_RES_MEM(LPSS_IDMA64_OFFSET
, LPSS_IDMA64_SIZE
),
96 #define LPSS_IDMA64_DRIVER_NAME "idma64"
99 * Cells needs to be ordered so that the iDMA is created first. This is
100 * because we need to be sure the DMA is available when the host controller
103 static const struct mfd_cell intel_lpss_idma64_cell
= {
104 .name
= LPSS_IDMA64_DRIVER_NAME
,
105 .num_resources
= ARRAY_SIZE(intel_lpss_idma64_resources
),
106 .resources
= intel_lpss_idma64_resources
,
109 static const struct mfd_cell intel_lpss_i2c_cell
= {
110 .name
= "i2c_designware",
111 .num_resources
= ARRAY_SIZE(intel_lpss_dev_resources
),
112 .resources
= intel_lpss_dev_resources
,
115 static const struct mfd_cell intel_lpss_uart_cell
= {
116 .name
= "dw-apb-uart",
117 .num_resources
= ARRAY_SIZE(intel_lpss_dev_resources
),
118 .resources
= intel_lpss_dev_resources
,
121 static const struct mfd_cell intel_lpss_spi_cell
= {
122 .name
= "pxa2xx-spi",
123 .num_resources
= ARRAY_SIZE(intel_lpss_dev_resources
),
124 .resources
= intel_lpss_dev_resources
,
127 static DEFINE_IDA(intel_lpss_devid_ida
);
128 static struct dentry
*intel_lpss_debugfs
;
130 static int intel_lpss_request_dma_module(const char *name
)
132 static bool intel_lpss_dma_requested
;
134 if (intel_lpss_dma_requested
)
137 intel_lpss_dma_requested
= true;
138 return request_module("%s", name
);
141 static void intel_lpss_cache_ltr(struct intel_lpss
*lpss
)
143 lpss
->active_ltr
= readl(lpss
->priv
+ LPSS_PRIV_ACTIVELTR
);
144 lpss
->idle_ltr
= readl(lpss
->priv
+ LPSS_PRIV_IDLELTR
);
147 static int intel_lpss_debugfs_add(struct intel_lpss
*lpss
)
151 dir
= debugfs_create_dir(dev_name(lpss
->dev
), intel_lpss_debugfs
);
155 /* Cache the values into lpss structure */
156 intel_lpss_cache_ltr(lpss
);
158 debugfs_create_x32("capabilities", S_IRUGO
, dir
, &lpss
->caps
);
159 debugfs_create_x32("active_ltr", S_IRUGO
, dir
, &lpss
->active_ltr
);
160 debugfs_create_x32("idle_ltr", S_IRUGO
, dir
, &lpss
->idle_ltr
);
166 static void intel_lpss_debugfs_remove(struct intel_lpss
*lpss
)
168 debugfs_remove_recursive(lpss
->debugfs
);
171 static void intel_lpss_ltr_set(struct device
*dev
, s32 val
)
173 struct intel_lpss
*lpss
= dev_get_drvdata(dev
);
177 * Program latency tolerance (LTR) accordingly what has been asked
178 * by the PM QoS layer or disable it in case we were passed
179 * negative value or PM_QOS_LATENCY_ANY.
181 ltr
= readl(lpss
->priv
+ LPSS_PRIV_ACTIVELTR
);
183 if (val
== PM_QOS_LATENCY_ANY
|| val
< 0) {
184 ltr
&= ~LPSS_PRIV_LTR_REQ
;
186 ltr
|= LPSS_PRIV_LTR_REQ
;
187 ltr
&= ~LPSS_PRIV_LTR_SCALE_MASK
;
188 ltr
&= ~LPSS_PRIV_LTR_VALUE_MASK
;
190 if (val
> LPSS_PRIV_LTR_VALUE_MASK
)
191 ltr
|= LPSS_PRIV_LTR_SCALE_32US
| val
>> 5;
193 ltr
|= LPSS_PRIV_LTR_SCALE_1US
| val
;
196 if (ltr
== lpss
->active_ltr
)
199 writel(ltr
, lpss
->priv
+ LPSS_PRIV_ACTIVELTR
);
200 writel(ltr
, lpss
->priv
+ LPSS_PRIV_IDLELTR
);
202 /* Cache the values into lpss structure */
203 intel_lpss_cache_ltr(lpss
);
206 static void intel_lpss_ltr_expose(struct intel_lpss
*lpss
)
208 lpss
->dev
->power
.set_latency_tolerance
= intel_lpss_ltr_set
;
209 dev_pm_qos_expose_latency_tolerance(lpss
->dev
);
212 static void intel_lpss_ltr_hide(struct intel_lpss
*lpss
)
214 dev_pm_qos_hide_latency_tolerance(lpss
->dev
);
215 lpss
->dev
->power
.set_latency_tolerance
= NULL
;
218 static int intel_lpss_assign_devs(struct intel_lpss
*lpss
)
222 type
= lpss
->caps
& LPSS_PRIV_CAPS_TYPE_MASK
;
223 type
>>= LPSS_PRIV_CAPS_TYPE_SHIFT
;
227 lpss
->cell
= &intel_lpss_i2c_cell
;
230 lpss
->cell
= &intel_lpss_uart_cell
;
233 lpss
->cell
= &intel_lpss_spi_cell
;
244 static bool intel_lpss_has_idma(const struct intel_lpss
*lpss
)
246 return (lpss
->caps
& LPSS_PRIV_CAPS_NO_IDMA
) == 0;
249 static void intel_lpss_set_remap_addr(const struct intel_lpss
*lpss
)
251 resource_size_t addr
= lpss
->info
->mem
->start
;
253 writel(addr
, lpss
->priv
+ LPSS_PRIV_REMAP_ADDR_LO
);
254 #if BITS_PER_LONG > 32
255 writel(addr
>> 32, lpss
->priv
+ LPSS_PRIV_REMAP_ADDR_HI
);
257 writel(0, lpss
->priv
+ LPSS_PRIV_REMAP_ADDR_HI
);
261 static void intel_lpss_deassert_reset(const struct intel_lpss
*lpss
)
263 u32 value
= LPSS_PRIV_RESETS_FUNC
| LPSS_PRIV_RESETS_IDMA
;
265 /* Bring out the device from reset */
266 writel(value
, lpss
->priv
+ LPSS_PRIV_RESETS
);
269 static void intel_lpss_init_dev(const struct intel_lpss
*lpss
)
271 u32 value
= LPSS_PRIV_SSP_REG_DIS_DMA_FIN
;
273 intel_lpss_deassert_reset(lpss
);
275 if (!intel_lpss_has_idma(lpss
))
278 intel_lpss_set_remap_addr(lpss
);
280 /* Make sure that SPI multiblock DMA transfers are re-enabled */
281 if (lpss
->type
== LPSS_DEV_SPI
)
282 writel(value
, lpss
->priv
+ LPSS_PRIV_SSP_REG
);
285 static void intel_lpss_unregister_clock_tree(struct clk
*clk
)
290 parent
= clk_get_parent(clk
);
296 static int intel_lpss_register_clock_divider(struct intel_lpss
*lpss
,
301 struct clk
*tmp
= *clk
;
303 snprintf(name
, sizeof(name
), "%s-enable", devname
);
304 tmp
= clk_register_gate(NULL
, name
, __clk_get_name(tmp
), 0,
305 lpss
->priv
, 0, 0, NULL
);
309 snprintf(name
, sizeof(name
), "%s-div", devname
);
310 tmp
= clk_register_fractional_divider(NULL
, name
, __clk_get_name(tmp
),
311 0, lpss
->priv
, 1, 15, 16, 15, 0,
317 snprintf(name
, sizeof(name
), "%s-update", devname
);
318 tmp
= clk_register_gate(NULL
, name
, __clk_get_name(tmp
),
319 CLK_SET_RATE_PARENT
, lpss
->priv
, 31, 0, NULL
);
327 static int intel_lpss_register_clock(struct intel_lpss
*lpss
)
329 const struct mfd_cell
*cell
= lpss
->cell
;
334 if (!lpss
->info
->clk_rate
)
338 clk
= clk_register_fixed_rate(NULL
, dev_name(lpss
->dev
), NULL
,
339 CLK_IS_ROOT
, lpss
->info
->clk_rate
);
343 snprintf(devname
, sizeof(devname
), "%s.%d", cell
->name
, lpss
->devid
);
346 * Support for clock divider only if it has some preset value.
347 * Otherwise we assume that the divider is not used.
349 if (lpss
->type
!= LPSS_DEV_I2C
) {
350 ret
= intel_lpss_register_clock_divider(lpss
, devname
, &clk
);
352 goto err_clk_register
;
357 /* Clock for the host controller */
358 lpss
->clock
= clkdev_create(clk
, lpss
->info
->clk_con_id
, "%s", devname
);
360 goto err_clk_register
;
367 intel_lpss_unregister_clock_tree(clk
);
372 static void intel_lpss_unregister_clock(struct intel_lpss
*lpss
)
374 if (IS_ERR_OR_NULL(lpss
->clk
))
377 clkdev_drop(lpss
->clock
);
378 intel_lpss_unregister_clock_tree(lpss
->clk
);
381 int intel_lpss_probe(struct device
*dev
,
382 const struct intel_lpss_platform_info
*info
)
384 struct intel_lpss
*lpss
;
387 if (!info
|| !info
->mem
|| info
->irq
<= 0)
390 lpss
= devm_kzalloc(dev
, sizeof(*lpss
), GFP_KERNEL
);
394 lpss
->priv
= devm_ioremap(dev
, info
->mem
->start
+ LPSS_PRIV_OFFSET
,
401 lpss
->caps
= readl(lpss
->priv
+ LPSS_PRIV_CAPS
);
403 dev_set_drvdata(dev
, lpss
);
405 ret
= intel_lpss_assign_devs(lpss
);
409 intel_lpss_init_dev(lpss
);
411 lpss
->devid
= ida_simple_get(&intel_lpss_devid_ida
, 0, 0, GFP_KERNEL
);
415 ret
= intel_lpss_register_clock(lpss
);
417 goto err_clk_register
;
419 intel_lpss_ltr_expose(lpss
);
421 ret
= intel_lpss_debugfs_add(lpss
);
423 dev_warn(dev
, "Failed to create debugfs entries\n");
425 if (intel_lpss_has_idma(lpss
)) {
427 * Ensure the DMA driver is loaded before the host
428 * controller device appears, so that the host controller
429 * driver can request its DMA channels as early as
432 * If the DMA module is not there that's OK as well.
434 intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME
);
436 ret
= mfd_add_devices(dev
, lpss
->devid
, &intel_lpss_idma64_cell
,
437 1, info
->mem
, info
->irq
, NULL
);
439 dev_warn(dev
, "Failed to add %s, fallback to PIO\n",
440 LPSS_IDMA64_DRIVER_NAME
);
443 ret
= mfd_add_devices(dev
, lpss
->devid
, lpss
->cell
,
444 1, info
->mem
, info
->irq
, NULL
);
451 intel_lpss_debugfs_remove(lpss
);
452 intel_lpss_ltr_hide(lpss
);
455 ida_simple_remove(&intel_lpss_devid_ida
, lpss
->devid
);
459 EXPORT_SYMBOL_GPL(intel_lpss_probe
);
461 void intel_lpss_remove(struct device
*dev
)
463 struct intel_lpss
*lpss
= dev_get_drvdata(dev
);
465 mfd_remove_devices(dev
);
466 intel_lpss_debugfs_remove(lpss
);
467 intel_lpss_ltr_hide(lpss
);
468 intel_lpss_unregister_clock(lpss
);
469 ida_simple_remove(&intel_lpss_devid_ida
, lpss
->devid
);
471 EXPORT_SYMBOL_GPL(intel_lpss_remove
);
473 static int resume_lpss_device(struct device
*dev
, void *data
)
475 pm_runtime_resume(dev
);
479 int intel_lpss_prepare(struct device
*dev
)
482 * Resume both child devices before entering system sleep. This
483 * ensures that they are in proper state before they get suspended.
485 device_for_each_child_reverse(dev
, NULL
, resume_lpss_device
);
488 EXPORT_SYMBOL_GPL(intel_lpss_prepare
);
490 int intel_lpss_suspend(struct device
*dev
)
494 EXPORT_SYMBOL_GPL(intel_lpss_suspend
);
496 int intel_lpss_resume(struct device
*dev
)
498 struct intel_lpss
*lpss
= dev_get_drvdata(dev
);
500 intel_lpss_init_dev(lpss
);
504 EXPORT_SYMBOL_GPL(intel_lpss_resume
);
506 static int __init
intel_lpss_init(void)
508 intel_lpss_debugfs
= debugfs_create_dir("intel_lpss", NULL
);
511 module_init(intel_lpss_init
);
513 static void __exit
intel_lpss_exit(void)
515 debugfs_remove(intel_lpss_debugfs
);
517 module_exit(intel_lpss_exit
);
519 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
520 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
521 MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
522 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
523 MODULE_DESCRIPTION("Intel LPSS core driver");
524 MODULE_LICENSE("GPL v2");