2 * lpc_ich.c - LPC interface for Intel ICH
4 * LPC bridge function of the Intel ICH contains many other
5 * functional units, such as Interrupt controllers, Timers,
6 * Power Management, System Management, GPIO, RTC, and LPC
7 * Configuration Registers.
9 * This driver is derived from lpc_sch.
11 * Copyright (c) 2011 Extreme Engineering Solution, Inc.
12 * Author: Aaron Sierra <asierra@xes-inc.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License 2 as published
16 * by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING. If not, write to
25 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * This driver supports the following I/O Controller hubs:
28 * (See the intel documentation on http://developer.intel.com.)
29 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
30 * document number 290687-002, 298242-027: 82801BA (ICH2)
31 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
32 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
33 * document number 290744-001, 290745-025: 82801DB (ICH4)
34 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
35 * document number 273599-001, 273645-002: 82801E (C-ICH)
36 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
37 * document number 300641-004, 300884-013: 6300ESB
38 * document number 301473-002, 301474-026: 82801F (ICH6)
39 * document number 313082-001, 313075-006: 631xESB, 632xESB
40 * document number 307013-003, 307014-024: 82801G (ICH7)
41 * document number 322896-001, 322897-001: NM10
42 * document number 313056-003, 313057-017: 82801H (ICH8)
43 * document number 316972-004, 316973-012: 82801I (ICH9)
44 * document number 319973-002, 319974-002: 82801J (ICH10)
45 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
46 * document number 320066-003, 320257-008: EP80597 (IICH)
47 * document number 324645-001, 324646-001: Cougar Point (CPT)
48 * document number TBD : Patsburg (PBG)
49 * document number TBD : DH89xxCC
50 * document number TBD : Panther Point
51 * document number TBD : Lynx Point
52 * document number TBD : Lynx Point-LP
55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
57 #include <linux/init.h>
58 #include <linux/kernel.h>
59 #include <linux/module.h>
60 #include <linux/errno.h>
61 #include <linux/acpi.h>
62 #include <linux/pci.h>
63 #include <linux/mfd/core.h>
64 #include <linux/mfd/lpc_ich.h>
67 #define ACPIBASE_GPE_OFF 0x28
68 #define ACPIBASE_GPE_END 0x2f
69 #define ACPIBASE_SMI_OFF 0x30
70 #define ACPIBASE_SMI_END 0x33
71 #define ACPIBASE_TCO_OFF 0x60
72 #define ACPIBASE_TCO_END 0x7f
75 #define ACPIBASE_GCS_OFF 0x3410
76 #define ACPIBASE_GCS_END 0x3414
83 #define wdt_io_res(i) wdt_res(0, i)
84 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
85 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
87 static int lpc_ich_acpi_save
= -1;
88 static int lpc_ich_gpio_save
= -1;
90 static struct resource wdt_ich_res
[] = {
93 .flags
= IORESOURCE_IO
,
97 .flags
= IORESOURCE_IO
,
101 .flags
= IORESOURCE_MEM
,
105 static struct resource gpio_ich_res
[] = {
108 .flags
= IORESOURCE_IO
,
112 .flags
= IORESOURCE_IO
,
121 static struct mfd_cell lpc_ich_cells
[] = {
124 .num_resources
= ARRAY_SIZE(wdt_ich_res
),
125 .resources
= wdt_ich_res
,
126 .ignore_resource_conflicts
= true,
130 .num_resources
= ARRAY_SIZE(gpio_ich_res
),
131 .resources
= gpio_ich_res
,
132 .ignore_resource_conflicts
= true,
136 /* chipset related info */
138 LPC_ICH
= 0, /* ICH */
141 LPC_ICH2M
, /* ICH2-M */
142 LPC_ICH3
, /* ICH3-S */
143 LPC_ICH3M
, /* ICH3-M */
145 LPC_ICH4M
, /* ICH4-M */
146 LPC_CICH
, /* C-ICH */
147 LPC_ICH5
, /* ICH5 & ICH5R */
148 LPC_6300ESB
, /* 6300ESB */
149 LPC_ICH6
, /* ICH6 & ICH6R */
150 LPC_ICH6M
, /* ICH6-M */
151 LPC_ICH6W
, /* ICH6W & ICH6RW */
152 LPC_631XESB
, /* 631xESB/632xESB */
153 LPC_ICH7
, /* ICH7 & ICH7R */
154 LPC_ICH7DH
, /* ICH7DH */
155 LPC_ICH7M
, /* ICH7-M & ICH7-U */
156 LPC_ICH7MDH
, /* ICH7-M DH */
158 LPC_ICH8
, /* ICH8 & ICH8R */
159 LPC_ICH8DH
, /* ICH8DH */
160 LPC_ICH8DO
, /* ICH8DO */
161 LPC_ICH8M
, /* ICH8M */
162 LPC_ICH8ME
, /* ICH8M-E */
164 LPC_ICH9R
, /* ICH9R */
165 LPC_ICH9DH
, /* ICH9DH */
166 LPC_ICH9DO
, /* ICH9DO */
167 LPC_ICH9M
, /* ICH9M */
168 LPC_ICH9ME
, /* ICH9M-E */
169 LPC_ICH10
, /* ICH10 */
170 LPC_ICH10R
, /* ICH10R */
171 LPC_ICH10D
, /* ICH10D */
172 LPC_ICH10DO
, /* ICH10DO */
173 LPC_PCH
, /* PCH Desktop Full Featured */
174 LPC_PCHM
, /* PCH Mobile Full Featured */
183 LPC_PCHMSFF
, /* PCH Mobile SFF Full Featured */
188 LPC_EP80579
, /* EP80579 */
189 LPC_CPT
, /* Cougar Point */
190 LPC_CPTD
, /* Cougar Point Desktop */
191 LPC_CPTM
, /* Cougar Point Mobile */
192 LPC_PBG
, /* Patsburg */
193 LPC_DH89XXCC
, /* DH89xxCC */
194 LPC_PPT
, /* Panther Point */
195 LPC_LPT
, /* Lynx Point */
196 LPC_LPT_LP
, /* Lynx Point-LP */
199 struct lpc_ich_info lpc_chipset_info
[] __devinitdata
= {
237 .name
= "ICH5 or ICH5R",
245 .name
= "ICH6 or ICH6R",
247 .gpio_version
= ICH_V6_GPIO
,
252 .gpio_version
= ICH_V6_GPIO
,
255 .name
= "ICH6W or ICH6RW",
257 .gpio_version
= ICH_V6_GPIO
,
260 .name
= "631xESB/632xESB",
262 .gpio_version
= ICH_V6_GPIO
,
265 .name
= "ICH7 or ICH7R",
267 .gpio_version
= ICH_V7_GPIO
,
272 .gpio_version
= ICH_V7_GPIO
,
275 .name
= "ICH7-M or ICH7-U",
277 .gpio_version
= ICH_V7_GPIO
,
282 .gpio_version
= ICH_V7_GPIO
,
289 .name
= "ICH8 or ICH8R",
291 .gpio_version
= ICH_V7_GPIO
,
296 .gpio_version
= ICH_V7_GPIO
,
301 .gpio_version
= ICH_V7_GPIO
,
306 .gpio_version
= ICH_V7_GPIO
,
311 .gpio_version
= ICH_V7_GPIO
,
316 .gpio_version
= ICH_V9_GPIO
,
321 .gpio_version
= ICH_V9_GPIO
,
326 .gpio_version
= ICH_V9_GPIO
,
331 .gpio_version
= ICH_V9_GPIO
,
336 .gpio_version
= ICH_V9_GPIO
,
341 .gpio_version
= ICH_V9_GPIO
,
346 .gpio_version
= ICH_V10CONS_GPIO
,
351 .gpio_version
= ICH_V10CONS_GPIO
,
356 .gpio_version
= ICH_V10CORP_GPIO
,
361 .gpio_version
= ICH_V10CORP_GPIO
,
364 .name
= "PCH Desktop Full Featured",
366 .gpio_version
= ICH_V5_GPIO
,
369 .name
= "PCH Mobile Full Featured",
371 .gpio_version
= ICH_V5_GPIO
,
376 .gpio_version
= ICH_V5_GPIO
,
381 .gpio_version
= ICH_V5_GPIO
,
386 .gpio_version
= ICH_V5_GPIO
,
391 .gpio_version
= ICH_V5_GPIO
,
396 .gpio_version
= ICH_V5_GPIO
,
401 .gpio_version
= ICH_V5_GPIO
,
406 .gpio_version
= ICH_V5_GPIO
,
411 .gpio_version
= ICH_V5_GPIO
,
414 .name
= "PCH Mobile SFF Full Featured",
416 .gpio_version
= ICH_V5_GPIO
,
421 .gpio_version
= ICH_V5_GPIO
,
426 .gpio_version
= ICH_V5_GPIO
,
431 .gpio_version
= ICH_V5_GPIO
,
436 .gpio_version
= ICH_V5_GPIO
,
443 .name
= "Cougar Point",
445 .gpio_version
= ICH_V5_GPIO
,
448 .name
= "Cougar Point Desktop",
450 .gpio_version
= ICH_V5_GPIO
,
453 .name
= "Cougar Point Mobile",
455 .gpio_version
= ICH_V5_GPIO
,
466 .name
= "Panther Point",
470 .name
= "Lynx Point",
474 .name
= "Lynx Point_LP",
480 * This data only exists for exporting the supported PCI ids
481 * via MODULE_DEVICE_TABLE. We do not actually register a
482 * pci_driver, because the I/O Controller Hub has also other
483 * functions that probably will be registered by other drivers.
485 static DEFINE_PCI_DEVICE_TABLE(lpc_ich_ids
) = {
486 { PCI_VDEVICE(INTEL
, 0x2410), LPC_ICH
},
487 { PCI_VDEVICE(INTEL
, 0x2420), LPC_ICH0
},
488 { PCI_VDEVICE(INTEL
, 0x2440), LPC_ICH2
},
489 { PCI_VDEVICE(INTEL
, 0x244c), LPC_ICH2M
},
490 { PCI_VDEVICE(INTEL
, 0x2480), LPC_ICH3
},
491 { PCI_VDEVICE(INTEL
, 0x248c), LPC_ICH3M
},
492 { PCI_VDEVICE(INTEL
, 0x24c0), LPC_ICH4
},
493 { PCI_VDEVICE(INTEL
, 0x24cc), LPC_ICH4M
},
494 { PCI_VDEVICE(INTEL
, 0x2450), LPC_CICH
},
495 { PCI_VDEVICE(INTEL
, 0x24d0), LPC_ICH5
},
496 { PCI_VDEVICE(INTEL
, 0x25a1), LPC_6300ESB
},
497 { PCI_VDEVICE(INTEL
, 0x2640), LPC_ICH6
},
498 { PCI_VDEVICE(INTEL
, 0x2641), LPC_ICH6M
},
499 { PCI_VDEVICE(INTEL
, 0x2642), LPC_ICH6W
},
500 { PCI_VDEVICE(INTEL
, 0x2670), LPC_631XESB
},
501 { PCI_VDEVICE(INTEL
, 0x2671), LPC_631XESB
},
502 { PCI_VDEVICE(INTEL
, 0x2672), LPC_631XESB
},
503 { PCI_VDEVICE(INTEL
, 0x2673), LPC_631XESB
},
504 { PCI_VDEVICE(INTEL
, 0x2674), LPC_631XESB
},
505 { PCI_VDEVICE(INTEL
, 0x2675), LPC_631XESB
},
506 { PCI_VDEVICE(INTEL
, 0x2676), LPC_631XESB
},
507 { PCI_VDEVICE(INTEL
, 0x2677), LPC_631XESB
},
508 { PCI_VDEVICE(INTEL
, 0x2678), LPC_631XESB
},
509 { PCI_VDEVICE(INTEL
, 0x2679), LPC_631XESB
},
510 { PCI_VDEVICE(INTEL
, 0x267a), LPC_631XESB
},
511 { PCI_VDEVICE(INTEL
, 0x267b), LPC_631XESB
},
512 { PCI_VDEVICE(INTEL
, 0x267c), LPC_631XESB
},
513 { PCI_VDEVICE(INTEL
, 0x267d), LPC_631XESB
},
514 { PCI_VDEVICE(INTEL
, 0x267e), LPC_631XESB
},
515 { PCI_VDEVICE(INTEL
, 0x267f), LPC_631XESB
},
516 { PCI_VDEVICE(INTEL
, 0x27b8), LPC_ICH7
},
517 { PCI_VDEVICE(INTEL
, 0x27b0), LPC_ICH7DH
},
518 { PCI_VDEVICE(INTEL
, 0x27b9), LPC_ICH7M
},
519 { PCI_VDEVICE(INTEL
, 0x27bd), LPC_ICH7MDH
},
520 { PCI_VDEVICE(INTEL
, 0x27bc), LPC_NM10
},
521 { PCI_VDEVICE(INTEL
, 0x2810), LPC_ICH8
},
522 { PCI_VDEVICE(INTEL
, 0x2812), LPC_ICH8DH
},
523 { PCI_VDEVICE(INTEL
, 0x2814), LPC_ICH8DO
},
524 { PCI_VDEVICE(INTEL
, 0x2815), LPC_ICH8M
},
525 { PCI_VDEVICE(INTEL
, 0x2811), LPC_ICH8ME
},
526 { PCI_VDEVICE(INTEL
, 0x2918), LPC_ICH9
},
527 { PCI_VDEVICE(INTEL
, 0x2916), LPC_ICH9R
},
528 { PCI_VDEVICE(INTEL
, 0x2912), LPC_ICH9DH
},
529 { PCI_VDEVICE(INTEL
, 0x2914), LPC_ICH9DO
},
530 { PCI_VDEVICE(INTEL
, 0x2919), LPC_ICH9M
},
531 { PCI_VDEVICE(INTEL
, 0x2917), LPC_ICH9ME
},
532 { PCI_VDEVICE(INTEL
, 0x3a18), LPC_ICH10
},
533 { PCI_VDEVICE(INTEL
, 0x3a16), LPC_ICH10R
},
534 { PCI_VDEVICE(INTEL
, 0x3a1a), LPC_ICH10D
},
535 { PCI_VDEVICE(INTEL
, 0x3a14), LPC_ICH10DO
},
536 { PCI_VDEVICE(INTEL
, 0x3b00), LPC_PCH
},
537 { PCI_VDEVICE(INTEL
, 0x3b01), LPC_PCHM
},
538 { PCI_VDEVICE(INTEL
, 0x3b02), LPC_P55
},
539 { PCI_VDEVICE(INTEL
, 0x3b03), LPC_PM55
},
540 { PCI_VDEVICE(INTEL
, 0x3b06), LPC_H55
},
541 { PCI_VDEVICE(INTEL
, 0x3b07), LPC_QM57
},
542 { PCI_VDEVICE(INTEL
, 0x3b08), LPC_H57
},
543 { PCI_VDEVICE(INTEL
, 0x3b09), LPC_HM55
},
544 { PCI_VDEVICE(INTEL
, 0x3b0a), LPC_Q57
},
545 { PCI_VDEVICE(INTEL
, 0x3b0b), LPC_HM57
},
546 { PCI_VDEVICE(INTEL
, 0x3b0d), LPC_PCHMSFF
},
547 { PCI_VDEVICE(INTEL
, 0x3b0f), LPC_QS57
},
548 { PCI_VDEVICE(INTEL
, 0x3b12), LPC_3400
},
549 { PCI_VDEVICE(INTEL
, 0x3b14), LPC_3420
},
550 { PCI_VDEVICE(INTEL
, 0x3b16), LPC_3450
},
551 { PCI_VDEVICE(INTEL
, 0x5031), LPC_EP80579
},
552 { PCI_VDEVICE(INTEL
, 0x1c41), LPC_CPT
},
553 { PCI_VDEVICE(INTEL
, 0x1c42), LPC_CPTD
},
554 { PCI_VDEVICE(INTEL
, 0x1c43), LPC_CPTM
},
555 { PCI_VDEVICE(INTEL
, 0x1c44), LPC_CPT
},
556 { PCI_VDEVICE(INTEL
, 0x1c45), LPC_CPT
},
557 { PCI_VDEVICE(INTEL
, 0x1c46), LPC_CPT
},
558 { PCI_VDEVICE(INTEL
, 0x1c47), LPC_CPT
},
559 { PCI_VDEVICE(INTEL
, 0x1c48), LPC_CPT
},
560 { PCI_VDEVICE(INTEL
, 0x1c49), LPC_CPT
},
561 { PCI_VDEVICE(INTEL
, 0x1c4a), LPC_CPT
},
562 { PCI_VDEVICE(INTEL
, 0x1c4b), LPC_CPT
},
563 { PCI_VDEVICE(INTEL
, 0x1c4c), LPC_CPT
},
564 { PCI_VDEVICE(INTEL
, 0x1c4d), LPC_CPT
},
565 { PCI_VDEVICE(INTEL
, 0x1c4e), LPC_CPT
},
566 { PCI_VDEVICE(INTEL
, 0x1c4f), LPC_CPT
},
567 { PCI_VDEVICE(INTEL
, 0x1c50), LPC_CPT
},
568 { PCI_VDEVICE(INTEL
, 0x1c51), LPC_CPT
},
569 { PCI_VDEVICE(INTEL
, 0x1c52), LPC_CPT
},
570 { PCI_VDEVICE(INTEL
, 0x1c53), LPC_CPT
},
571 { PCI_VDEVICE(INTEL
, 0x1c54), LPC_CPT
},
572 { PCI_VDEVICE(INTEL
, 0x1c55), LPC_CPT
},
573 { PCI_VDEVICE(INTEL
, 0x1c56), LPC_CPT
},
574 { PCI_VDEVICE(INTEL
, 0x1c57), LPC_CPT
},
575 { PCI_VDEVICE(INTEL
, 0x1c58), LPC_CPT
},
576 { PCI_VDEVICE(INTEL
, 0x1c59), LPC_CPT
},
577 { PCI_VDEVICE(INTEL
, 0x1c5a), LPC_CPT
},
578 { PCI_VDEVICE(INTEL
, 0x1c5b), LPC_CPT
},
579 { PCI_VDEVICE(INTEL
, 0x1c5c), LPC_CPT
},
580 { PCI_VDEVICE(INTEL
, 0x1c5d), LPC_CPT
},
581 { PCI_VDEVICE(INTEL
, 0x1c5e), LPC_CPT
},
582 { PCI_VDEVICE(INTEL
, 0x1c5f), LPC_CPT
},
583 { PCI_VDEVICE(INTEL
, 0x1d40), LPC_PBG
},
584 { PCI_VDEVICE(INTEL
, 0x1d41), LPC_PBG
},
585 { PCI_VDEVICE(INTEL
, 0x2310), LPC_DH89XXCC
},
586 { PCI_VDEVICE(INTEL
, 0x1e40), LPC_PPT
},
587 { PCI_VDEVICE(INTEL
, 0x1e41), LPC_PPT
},
588 { PCI_VDEVICE(INTEL
, 0x1e42), LPC_PPT
},
589 { PCI_VDEVICE(INTEL
, 0x1e43), LPC_PPT
},
590 { PCI_VDEVICE(INTEL
, 0x1e44), LPC_PPT
},
591 { PCI_VDEVICE(INTEL
, 0x1e45), LPC_PPT
},
592 { PCI_VDEVICE(INTEL
, 0x1e46), LPC_PPT
},
593 { PCI_VDEVICE(INTEL
, 0x1e47), LPC_PPT
},
594 { PCI_VDEVICE(INTEL
, 0x1e48), LPC_PPT
},
595 { PCI_VDEVICE(INTEL
, 0x1e49), LPC_PPT
},
596 { PCI_VDEVICE(INTEL
, 0x1e4a), LPC_PPT
},
597 { PCI_VDEVICE(INTEL
, 0x1e4b), LPC_PPT
},
598 { PCI_VDEVICE(INTEL
, 0x1e4c), LPC_PPT
},
599 { PCI_VDEVICE(INTEL
, 0x1e4d), LPC_PPT
},
600 { PCI_VDEVICE(INTEL
, 0x1e4e), LPC_PPT
},
601 { PCI_VDEVICE(INTEL
, 0x1e4f), LPC_PPT
},
602 { PCI_VDEVICE(INTEL
, 0x1e50), LPC_PPT
},
603 { PCI_VDEVICE(INTEL
, 0x1e51), LPC_PPT
},
604 { PCI_VDEVICE(INTEL
, 0x1e52), LPC_PPT
},
605 { PCI_VDEVICE(INTEL
, 0x1e53), LPC_PPT
},
606 { PCI_VDEVICE(INTEL
, 0x1e54), LPC_PPT
},
607 { PCI_VDEVICE(INTEL
, 0x1e55), LPC_PPT
},
608 { PCI_VDEVICE(INTEL
, 0x1e56), LPC_PPT
},
609 { PCI_VDEVICE(INTEL
, 0x1e57), LPC_PPT
},
610 { PCI_VDEVICE(INTEL
, 0x1e58), LPC_PPT
},
611 { PCI_VDEVICE(INTEL
, 0x1e59), LPC_PPT
},
612 { PCI_VDEVICE(INTEL
, 0x1e5a), LPC_PPT
},
613 { PCI_VDEVICE(INTEL
, 0x1e5b), LPC_PPT
},
614 { PCI_VDEVICE(INTEL
, 0x1e5c), LPC_PPT
},
615 { PCI_VDEVICE(INTEL
, 0x1e5d), LPC_PPT
},
616 { PCI_VDEVICE(INTEL
, 0x1e5e), LPC_PPT
},
617 { PCI_VDEVICE(INTEL
, 0x1e5f), LPC_PPT
},
618 { PCI_VDEVICE(INTEL
, 0x8c40), LPC_LPT
},
619 { PCI_VDEVICE(INTEL
, 0x8c41), LPC_LPT
},
620 { PCI_VDEVICE(INTEL
, 0x8c42), LPC_LPT
},
621 { PCI_VDEVICE(INTEL
, 0x8c43), LPC_LPT
},
622 { PCI_VDEVICE(INTEL
, 0x8c44), LPC_LPT
},
623 { PCI_VDEVICE(INTEL
, 0x8c45), LPC_LPT
},
624 { PCI_VDEVICE(INTEL
, 0x8c46), LPC_LPT
},
625 { PCI_VDEVICE(INTEL
, 0x8c47), LPC_LPT
},
626 { PCI_VDEVICE(INTEL
, 0x8c48), LPC_LPT
},
627 { PCI_VDEVICE(INTEL
, 0x8c49), LPC_LPT
},
628 { PCI_VDEVICE(INTEL
, 0x8c4a), LPC_LPT
},
629 { PCI_VDEVICE(INTEL
, 0x8c4b), LPC_LPT
},
630 { PCI_VDEVICE(INTEL
, 0x8c4c), LPC_LPT
},
631 { PCI_VDEVICE(INTEL
, 0x8c4d), LPC_LPT
},
632 { PCI_VDEVICE(INTEL
, 0x8c4e), LPC_LPT
},
633 { PCI_VDEVICE(INTEL
, 0x8c4f), LPC_LPT
},
634 { PCI_VDEVICE(INTEL
, 0x8c50), LPC_LPT
},
635 { PCI_VDEVICE(INTEL
, 0x8c51), LPC_LPT
},
636 { PCI_VDEVICE(INTEL
, 0x8c52), LPC_LPT
},
637 { PCI_VDEVICE(INTEL
, 0x8c53), LPC_LPT
},
638 { PCI_VDEVICE(INTEL
, 0x8c54), LPC_LPT
},
639 { PCI_VDEVICE(INTEL
, 0x8c55), LPC_LPT
},
640 { PCI_VDEVICE(INTEL
, 0x8c56), LPC_LPT
},
641 { PCI_VDEVICE(INTEL
, 0x8c57), LPC_LPT
},
642 { PCI_VDEVICE(INTEL
, 0x8c58), LPC_LPT
},
643 { PCI_VDEVICE(INTEL
, 0x8c59), LPC_LPT
},
644 { PCI_VDEVICE(INTEL
, 0x8c5a), LPC_LPT
},
645 { PCI_VDEVICE(INTEL
, 0x8c5b), LPC_LPT
},
646 { PCI_VDEVICE(INTEL
, 0x8c5c), LPC_LPT
},
647 { PCI_VDEVICE(INTEL
, 0x8c5d), LPC_LPT
},
648 { PCI_VDEVICE(INTEL
, 0x8c5e), LPC_LPT
},
649 { PCI_VDEVICE(INTEL
, 0x8c5f), LPC_LPT
},
650 { PCI_VDEVICE(INTEL
, 0x9c40), LPC_LPT_LP
},
651 { PCI_VDEVICE(INTEL
, 0x9c41), LPC_LPT_LP
},
652 { PCI_VDEVICE(INTEL
, 0x9c42), LPC_LPT_LP
},
653 { PCI_VDEVICE(INTEL
, 0x9c43), LPC_LPT_LP
},
654 { PCI_VDEVICE(INTEL
, 0x9c44), LPC_LPT_LP
},
655 { PCI_VDEVICE(INTEL
, 0x9c45), LPC_LPT_LP
},
656 { PCI_VDEVICE(INTEL
, 0x9c46), LPC_LPT_LP
},
657 { PCI_VDEVICE(INTEL
, 0x9c47), LPC_LPT_LP
},
658 { 0, }, /* End of list */
660 MODULE_DEVICE_TABLE(pci
, lpc_ich_ids
);
662 static void lpc_ich_restore_config_space(struct pci_dev
*dev
)
664 if (lpc_ich_acpi_save
>= 0) {
665 pci_write_config_byte(dev
, ACPICTRL
, lpc_ich_acpi_save
);
666 lpc_ich_acpi_save
= -1;
669 if (lpc_ich_gpio_save
>= 0) {
670 pci_write_config_byte(dev
, GPIOCTRL
, lpc_ich_gpio_save
);
671 lpc_ich_gpio_save
= -1;
675 static void lpc_ich_enable_acpi_space(struct pci_dev
*dev
)
679 pci_read_config_byte(dev
, ACPICTRL
, ®_save
);
680 pci_write_config_byte(dev
, ACPICTRL
, reg_save
| 0x10);
681 lpc_ich_acpi_save
= reg_save
;
684 static void lpc_ich_enable_gpio_space(struct pci_dev
*dev
)
688 pci_read_config_byte(dev
, GPIOCTRL
, ®_save
);
689 pci_write_config_byte(dev
, GPIOCTRL
, reg_save
| 0x10);
690 lpc_ich_gpio_save
= reg_save
;
693 static void lpc_ich_finalize_cell(struct mfd_cell
*cell
,
694 const struct pci_device_id
*id
)
696 cell
->platform_data
= &lpc_chipset_info
[id
->driver_data
];
697 cell
->pdata_size
= sizeof(struct lpc_ich_info
);
701 * We don't check for resource conflict globally. There are 2 or 3 independent
702 * GPIO groups and it's enough to have access to one of these to instantiate
705 static int lpc_ich_check_conflict_gpio(struct resource
*res
)
710 if (resource_size(res
) >= 0x50 &&
711 !acpi_check_region(res
->start
+ 0x40, 0x10, "LPC ICH GPIO3"))
714 if (!acpi_check_region(res
->start
+ 0x30, 0x10, "LPC ICH GPIO2"))
717 ret
= acpi_check_region(res
->start
+ 0x00, 0x30, "LPC ICH GPIO1");
721 return use_gpio
? use_gpio
: ret
;
724 static int lpc_ich_init_gpio(struct pci_dev
*dev
,
725 const struct pci_device_id
*id
)
730 bool acpi_conflict
= false;
731 struct resource
*res
;
733 /* Setup power management base register */
734 pci_read_config_dword(dev
, ACPIBASE
, &base_addr_cfg
);
735 base_addr
= base_addr_cfg
& 0x0000ff80;
737 dev_err(&dev
->dev
, "I/O space for ACPI uninitialized\n");
738 lpc_ich_cells
[LPC_GPIO
].num_resources
--;
742 res
= &gpio_ich_res
[ICH_RES_GPE0
];
743 res
->start
= base_addr
+ ACPIBASE_GPE_OFF
;
744 res
->end
= base_addr
+ ACPIBASE_GPE_END
;
745 ret
= acpi_check_resource_conflict(res
);
748 * This isn't fatal for the GPIO, but we have to make sure that
749 * the platform_device subsystem doesn't see this resource
750 * or it will register an invalid region.
752 lpc_ich_cells
[LPC_GPIO
].num_resources
--;
753 acpi_conflict
= true;
755 lpc_ich_enable_acpi_space(dev
);
759 /* Setup GPIO base register */
760 pci_read_config_dword(dev
, GPIOBASE
, &base_addr_cfg
);
761 base_addr
= base_addr_cfg
& 0x0000ff80;
763 dev_err(&dev
->dev
, "I/O space for GPIO uninitialized\n");
768 /* Older devices provide fewer GPIO and have a smaller resource size. */
769 res
= &gpio_ich_res
[ICH_RES_GPIO
];
770 res
->start
= base_addr
;
771 switch (lpc_chipset_info
[id
->driver_data
].gpio_version
) {
773 case ICH_V10CORP_GPIO
:
774 res
->end
= res
->start
+ 128 - 1;
777 res
->end
= res
->start
+ 64 - 1;
781 ret
= lpc_ich_check_conflict_gpio(res
);
783 /* this isn't necessarily fatal for the GPIO */
784 acpi_conflict
= true;
787 lpc_chipset_info
[id
->driver_data
].use_gpio
= ret
;
788 lpc_ich_enable_gpio_space(dev
);
790 lpc_ich_finalize_cell(&lpc_ich_cells
[LPC_GPIO
], id
);
791 ret
= mfd_add_devices(&dev
->dev
, -1, &lpc_ich_cells
[LPC_GPIO
],
796 pr_warn("Resource conflict(s) found affecting %s\n",
797 lpc_ich_cells
[LPC_GPIO
].name
);
801 static int lpc_ich_init_wdt(struct pci_dev
*dev
,
802 const struct pci_device_id
*id
)
807 struct resource
*res
;
809 /* Setup power management base register */
810 pci_read_config_dword(dev
, ACPIBASE
, &base_addr_cfg
);
811 base_addr
= base_addr_cfg
& 0x0000ff80;
813 dev_err(&dev
->dev
, "I/O space for ACPI uninitialized\n");
818 res
= wdt_io_res(ICH_RES_IO_TCO
);
819 res
->start
= base_addr
+ ACPIBASE_TCO_OFF
;
820 res
->end
= base_addr
+ ACPIBASE_TCO_END
;
822 res
= wdt_io_res(ICH_RES_IO_SMI
);
823 res
->start
= base_addr
+ ACPIBASE_SMI_OFF
;
824 res
->end
= base_addr
+ ACPIBASE_SMI_END
;
826 lpc_ich_enable_acpi_space(dev
);
829 * Get the Memory-Mapped GCS register. To get access to it
830 * we have to read RCBA from PCI Config space 0xf0 and use
831 * it as base. GCS = RCBA + ICH6_GCS(0x3410).
833 if (lpc_chipset_info
[id
->driver_data
].iTCO_version
== 2) {
834 pci_read_config_dword(dev
, RCBABASE
, &base_addr_cfg
);
835 base_addr
= base_addr_cfg
& 0xffffc000;
836 if (!(base_addr_cfg
& 1)) {
837 pr_err("RCBA is disabled by hardware/BIOS, "
838 "device disabled\n");
842 res
= wdt_mem_res(ICH_RES_MEM_GCS
);
843 res
->start
= base_addr
+ ACPIBASE_GCS_OFF
;
844 res
->end
= base_addr
+ ACPIBASE_GCS_END
;
847 lpc_ich_finalize_cell(&lpc_ich_cells
[LPC_WDT
], id
);
848 ret
= mfd_add_devices(&dev
->dev
, -1, &lpc_ich_cells
[LPC_WDT
],
855 static int lpc_ich_probe(struct pci_dev
*dev
,
856 const struct pci_device_id
*id
)
859 bool cell_added
= false;
861 ret
= lpc_ich_init_wdt(dev
, id
);
865 ret
= lpc_ich_init_gpio(dev
, id
);
870 * We only care if at least one or none of the cells registered
874 lpc_ich_restore_config_space(dev
);
881 static void __devexit
lpc_ich_remove(struct pci_dev
*dev
)
883 mfd_remove_devices(&dev
->dev
);
884 lpc_ich_restore_config_space(dev
);
887 static struct pci_driver lpc_ich_driver
= {
889 .id_table
= lpc_ich_ids
,
890 .probe
= lpc_ich_probe
,
891 .remove
= lpc_ich_remove
,
894 static int __init
lpc_ich_init(void)
896 return pci_register_driver(&lpc_ich_driver
);
899 static void __exit
lpc_ich_exit(void)
901 pci_unregister_driver(&lpc_ich_driver
);
904 module_init(lpc_ich_init
);
905 module_exit(lpc_ich_exit
);
907 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
908 MODULE_DESCRIPTION("LPC interface for Intel ICH");
909 MODULE_LICENSE("GPL");