drivers/mfd/mc13xxx-core.c

   1 /*
   2  * Copyright 2009-2010 Pengutronix
   3  * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
   4  *
   5  * loosely based on an earlier driver that has
   6  * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it under
   9  * the terms of the GNU General Public License version 2 as published by the
  10  * Free Software Foundation.
  11  */
  12
  13 #include <linux/slab.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/mutex.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/mfd/core.h>
  19 #include <linux/mfd/mc13xxx.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_gpio.h>
  23
  24 #include "mc13xxx.h"
  25
  26 #define MC13XXX_IRQSTAT0        0
  27 #define MC13XXX_IRQSTAT0_ADCDONEI       (1 << 0)
  28 #define MC13XXX_IRQSTAT0_ADCBISDONEI    (1 << 1)
  29 #define MC13XXX_IRQSTAT0_TSI            (1 << 2)
  30 #define MC13783_IRQSTAT0_WHIGHI         (1 << 3)
  31 #define MC13783_IRQSTAT0_WLOWI          (1 << 4)
  32 #define MC13XXX_IRQSTAT0_CHGDETI        (1 << 6)
  33 #define MC13783_IRQSTAT0_CHGOVI         (1 << 7)
  34 #define MC13XXX_IRQSTAT0_CHGREVI        (1 << 8)
  35 #define MC13XXX_IRQSTAT0_CHGSHORTI      (1 << 9)
  36 #define MC13XXX_IRQSTAT0_CCCVI          (1 << 10)
  37 #define MC13XXX_IRQSTAT0_CHGCURRI       (1 << 11)
  38 #define MC13XXX_IRQSTAT0_BPONI          (1 << 12)
  39 #define MC13XXX_IRQSTAT0_LOBATLI        (1 << 13)
  40 #define MC13XXX_IRQSTAT0_LOBATHI        (1 << 14)
  41 #define MC13783_IRQSTAT0_UDPI           (1 << 15)
  42 #define MC13783_IRQSTAT0_USBI           (1 << 16)
  43 #define MC13783_IRQSTAT0_IDI            (1 << 19)
  44 #define MC13783_IRQSTAT0_SE1I           (1 << 21)
  45 #define MC13783_IRQSTAT0_CKDETI         (1 << 22)
  46 #define MC13783_IRQSTAT0_UDMI           (1 << 23)
  47
  48 #define MC13XXX_IRQMASK0        1
  49 #define MC13XXX_IRQMASK0_ADCDONEM       MC13XXX_IRQSTAT0_ADCDONEI
  50 #define MC13XXX_IRQMASK0_ADCBISDONEM    MC13XXX_IRQSTAT0_ADCBISDONEI
  51 #define MC13XXX_IRQMASK0_TSM            MC13XXX_IRQSTAT0_TSI
  52 #define MC13783_IRQMASK0_WHIGHM         MC13783_IRQSTAT0_WHIGHI
  53 #define MC13783_IRQMASK0_WLOWM          MC13783_IRQSTAT0_WLOWI
  54 #define MC13XXX_IRQMASK0_CHGDETM        MC13XXX_IRQSTAT0_CHGDETI
  55 #define MC13783_IRQMASK0_CHGOVM         MC13783_IRQSTAT0_CHGOVI
  56 #define MC13XXX_IRQMASK0_CHGREVM        MC13XXX_IRQSTAT0_CHGREVI
  57 #define MC13XXX_IRQMASK0_CHGSHORTM      MC13XXX_IRQSTAT0_CHGSHORTI
  58 #define MC13XXX_IRQMASK0_CCCVM          MC13XXX_IRQSTAT0_CCCVI
  59 #define MC13XXX_IRQMASK0_CHGCURRM       MC13XXX_IRQSTAT0_CHGCURRI
  60 #define MC13XXX_IRQMASK0_BPONM          MC13XXX_IRQSTAT0_BPONI
  61 #define MC13XXX_IRQMASK0_LOBATLM        MC13XXX_IRQSTAT0_LOBATLI
  62 #define MC13XXX_IRQMASK0_LOBATHM        MC13XXX_IRQSTAT0_LOBATHI
  63 #define MC13783_IRQMASK0_UDPM           MC13783_IRQSTAT0_UDPI
  64 #define MC13783_IRQMASK0_USBM           MC13783_IRQSTAT0_USBI
  65 #define MC13783_IRQMASK0_IDM            MC13783_IRQSTAT0_IDI
  66 #define MC13783_IRQMASK0_SE1M           MC13783_IRQSTAT0_SE1I
  67 #define MC13783_IRQMASK0_CKDETM         MC13783_IRQSTAT0_CKDETI
  68 #define MC13783_IRQMASK0_UDMM           MC13783_IRQSTAT0_UDMI
  69
  70 #define MC13XXX_IRQSTAT1        3
  71 #define MC13XXX_IRQSTAT1_1HZI           (1 << 0)
  72 #define MC13XXX_IRQSTAT1_TODAI          (1 << 1)
  73 #define MC13783_IRQSTAT1_ONOFD1I        (1 << 3)
  74 #define MC13783_IRQSTAT1_ONOFD2I        (1 << 4)
  75 #define MC13783_IRQSTAT1_ONOFD3I        (1 << 5)
  76 #define MC13XXX_IRQSTAT1_SYSRSTI        (1 << 6)
  77 #define MC13XXX_IRQSTAT1_RTCRSTI        (1 << 7)
  78 #define MC13XXX_IRQSTAT1_PCI            (1 << 8)
  79 #define MC13XXX_IRQSTAT1_WARMI          (1 << 9)
  80 #define MC13XXX_IRQSTAT1_MEMHLDI        (1 << 10)
  81 #define MC13783_IRQSTAT1_PWRRDYI        (1 << 11)
  82 #define MC13XXX_IRQSTAT1_THWARNLI       (1 << 12)
  83 #define MC13XXX_IRQSTAT1_THWARNHI       (1 << 13)
  84 #define MC13XXX_IRQSTAT1_CLKI           (1 << 14)
  85 #define MC13783_IRQSTAT1_SEMAFI         (1 << 15)
  86 #define MC13783_IRQSTAT1_MC2BI          (1 << 17)
  87 #define MC13783_IRQSTAT1_HSDETI         (1 << 18)
  88 #define MC13783_IRQSTAT1_HSLI           (1 << 19)
  89 #define MC13783_IRQSTAT1_ALSPTHI        (1 << 20)
  90 #define MC13783_IRQSTAT1_AHSSHORTI      (1 << 21)
  91
  92 #define MC13XXX_IRQMASK1        4
  93 #define MC13XXX_IRQMASK1_1HZM           MC13XXX_IRQSTAT1_1HZI
  94 #define MC13XXX_IRQMASK1_TODAM          MC13XXX_IRQSTAT1_TODAI
  95 #define MC13783_IRQMASK1_ONOFD1M        MC13783_IRQSTAT1_ONOFD1I
  96 #define MC13783_IRQMASK1_ONOFD2M        MC13783_IRQSTAT1_ONOFD2I
  97 #define MC13783_IRQMASK1_ONOFD3M        MC13783_IRQSTAT1_ONOFD3I
  98 #define MC13XXX_IRQMASK1_SYSRSTM        MC13XXX_IRQSTAT1_SYSRSTI
  99 #define MC13XXX_IRQMASK1_RTCRSTM        MC13XXX_IRQSTAT1_RTCRSTI
 100 #define MC13XXX_IRQMASK1_PCM            MC13XXX_IRQSTAT1_PCI
 101 #define MC13XXX_IRQMASK1_WARMM          MC13XXX_IRQSTAT1_WARMI
 102 #define MC13XXX_IRQMASK1_MEMHLDM        MC13XXX_IRQSTAT1_MEMHLDI
 103 #define MC13783_IRQMASK1_PWRRDYM        MC13783_IRQSTAT1_PWRRDYI
 104 #define MC13XXX_IRQMASK1_THWARNLM       MC13XXX_IRQSTAT1_THWARNLI
 105 #define MC13XXX_IRQMASK1_THWARNHM       MC13XXX_IRQSTAT1_THWARNHI
 106 #define MC13XXX_IRQMASK1_CLKM           MC13XXX_IRQSTAT1_CLKI
 107 #define MC13783_IRQMASK1_SEMAFM         MC13783_IRQSTAT1_SEMAFI
 108 #define MC13783_IRQMASK1_MC2BM          MC13783_IRQSTAT1_MC2BI
 109 #define MC13783_IRQMASK1_HSDETM         MC13783_IRQSTAT1_HSDETI
 110 #define MC13783_IRQMASK1_HSLM           MC13783_IRQSTAT1_HSLI
 111 #define MC13783_IRQMASK1_ALSPTHM        MC13783_IRQSTAT1_ALSPTHI
 112 #define MC13783_IRQMASK1_AHSSHORTM      MC13783_IRQSTAT1_AHSSHORTI
 113
 114 #define MC13XXX_REVISION        7
 115 #define MC13XXX_REVISION_REVMETAL       (0x07 <<  0)
 116 #define MC13XXX_REVISION_REVFULL        (0x03 <<  3)
 117 #define MC13XXX_REVISION_ICID           (0x07 <<  6)
 118 #define MC13XXX_REVISION_FIN            (0x03 <<  9)
 119 #define MC13XXX_REVISION_FAB            (0x03 << 11)
 120 #define MC13XXX_REVISION_ICIDCODE       (0x3f << 13)
 121
 122 #define MC34708_REVISION_REVMETAL       (0x07 <<  0)
 123 #define MC34708_REVISION_REVFULL        (0x07 <<  3)
 124 #define MC34708_REVISION_FIN            (0x07 <<  6)
 125 #define MC34708_REVISION_FAB            (0x07 <<  9)
 126
 127 #define MC13XXX_ADC1            44
 128 #define MC13XXX_ADC1_ADEN               (1 << 0)
 129 #define MC13XXX_ADC1_RAND               (1 << 1)
 130 #define MC13XXX_ADC1_ADSEL              (1 << 3)
 131 #define MC13XXX_ADC1_ASC                (1 << 20)
 132 #define MC13XXX_ADC1_ADTRIGIGN          (1 << 21)
 133
 134 #define MC13XXX_ADC2            45
 135
 136 void mc13xxx_lock(struct mc13xxx *mc13xxx)
 137 {
 138         if (!mutex_trylock(&mc13xxx->lock)) {
 139                 dev_dbg(mc13xxx->dev, "wait for %s from %pf\n",
 140                                 __func__, __builtin_return_address(0));
 141
 142                 mutex_lock(&mc13xxx->lock);
 143         }
 144         dev_dbg(mc13xxx->dev, "%s from %pf\n",
 145                         __func__, __builtin_return_address(0));
 146 }
 147 EXPORT_SYMBOL(mc13xxx_lock);
 148
 149 void mc13xxx_unlock(struct mc13xxx *mc13xxx)
 150 {
 151         dev_dbg(mc13xxx->dev, "%s from %pf\n",
 152                         __func__, __builtin_return_address(0));
 153         mutex_unlock(&mc13xxx->lock);
 154 }
 155 EXPORT_SYMBOL(mc13xxx_unlock);
 156
 157 int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
 158 {
 159         int ret;
 160
 161         if (offset > MC13XXX_NUMREGS)
 162                 return -EINVAL;
 163
 164         ret = regmap_read(mc13xxx->regmap, offset, val);
 165         dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
 166
 167         return ret;
 168 }
 169 EXPORT_SYMBOL(mc13xxx_reg_read);
 170
 171 int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
 172 {
 173         dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
 174
 175         if (offset > MC13XXX_NUMREGS || val > 0xffffff)
 176                 return -EINVAL;
 177
 178         return regmap_write(mc13xxx->regmap, offset, val);
 179 }
 180 EXPORT_SYMBOL(mc13xxx_reg_write);
 181
 182 int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
 183                 u32 mask, u32 val)
 184 {
 185         BUG_ON(val & ~mask);
 186         dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x (mask: 0x%06x)\n",
 187                         offset, val, mask);
 188
 189         return regmap_update_bits(mc13xxx->regmap, offset, mask, val);
 190 }
 191 EXPORT_SYMBOL(mc13xxx_reg_rmw);
 192
 193 int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
 194 {
 195         int ret;
 196         unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 197         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 198         u32 mask;
 199
 200         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 201                 return -EINVAL;
 202
 203         ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 204         if (ret)
 205                 return ret;
 206
 207         if (mask & irqbit)
 208                 /* already masked */
 209                 return 0;
 210
 211         return mc13xxx_reg_write(mc13xxx, offmask, mask | irqbit);
 212 }
 213 EXPORT_SYMBOL(mc13xxx_irq_mask);
 214
 215 int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
 216 {
 217         int ret;
 218         unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 219         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 220         u32 mask;
 221
 222         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 223                 return -EINVAL;
 224
 225         ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 226         if (ret)
 227                 return ret;
 228
 229         if (!(mask & irqbit))
 230                 /* already unmasked */
 231                 return 0;
 232
 233         return mc13xxx_reg_write(mc13xxx, offmask, mask & ~irqbit);
 234 }
 235 EXPORT_SYMBOL(mc13xxx_irq_unmask);
 236
 237 int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
 238                 int *enabled, int *pending)
 239 {
 240         int ret;
 241         unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 242         unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
 243         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 244
 245         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 246                 return -EINVAL;
 247
 248         if (enabled) {
 249                 u32 mask;
 250
 251                 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 252                 if (ret)
 253                         return ret;
 254
 255                 *enabled = mask & irqbit;
 256         }
 257
 258         if (pending) {
 259                 u32 stat;
 260
 261                 ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
 262                 if (ret)
 263                         return ret;
 264
 265                 *pending = stat & irqbit;
 266         }
 267
 268         return 0;
 269 }
 270 EXPORT_SYMBOL(mc13xxx_irq_status);
 271
 272 int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq)
 273 {
 274         unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
 275         unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
 276
 277         BUG_ON(irq < 0 || irq >= MC13XXX_NUM_IRQ);
 278
 279         return mc13xxx_reg_write(mc13xxx, offstat, val);
 280 }
 281 EXPORT_SYMBOL(mc13xxx_irq_ack);
 282
 283 int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
 284                 irq_handler_t handler, const char *name, void *dev)
 285 {
 286         BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 287         BUG_ON(!handler);
 288
 289         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 290                 return -EINVAL;
 291
 292         if (mc13xxx->irqhandler[irq])
 293                 return -EBUSY;
 294
 295         mc13xxx->irqhandler[irq] = handler;
 296         mc13xxx->irqdata[irq] = dev;
 297
 298         return 0;
 299 }
 300 EXPORT_SYMBOL(mc13xxx_irq_request_nounmask);
 301
 302 int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
 303                 irq_handler_t handler, const char *name, void *dev)
 304 {
 305         int ret;
 306
 307         ret = mc13xxx_irq_request_nounmask(mc13xxx, irq, handler, name, dev);
 308         if (ret)
 309                 return ret;
 310
 311         ret = mc13xxx_irq_unmask(mc13xxx, irq);
 312         if (ret) {
 313                 mc13xxx->irqhandler[irq] = NULL;
 314                 mc13xxx->irqdata[irq] = NULL;
 315                 return ret;
 316         }
 317
 318         return 0;
 319 }
 320 EXPORT_SYMBOL(mc13xxx_irq_request);
 321
 322 int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
 323 {
 324         int ret;
 325         BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 326
 327         if (irq < 0 || irq >= MC13XXX_NUM_IRQ || !mc13xxx->irqhandler[irq] ||
 328                         mc13xxx->irqdata[irq] != dev)
 329                 return -EINVAL;
 330
 331         ret = mc13xxx_irq_mask(mc13xxx, irq);
 332         if (ret)
 333                 return ret;
 334
 335         mc13xxx->irqhandler[irq] = NULL;
 336         mc13xxx->irqdata[irq] = NULL;
 337
 338         return 0;
 339 }
 340 EXPORT_SYMBOL(mc13xxx_irq_free);
 341
 342 static inline irqreturn_t mc13xxx_irqhandler(struct mc13xxx *mc13xxx, int irq)
 343 {
 344         return mc13xxx->irqhandler[irq](irq, mc13xxx->irqdata[irq]);
 345 }
 346
 347 /*
 348  * returns: number of handled irqs or negative error
 349  * locking: holds mc13xxx->lock
 350  */
 351 static int mc13xxx_irq_handle(struct mc13xxx *mc13xxx,
 352                 unsigned int offstat, unsigned int offmask, int baseirq)
 353 {
 354         u32 stat, mask;
 355         int ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
 356         int num_handled = 0;
 357
 358         if (ret)
 359                 return ret;
 360
 361         ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 362         if (ret)
 363                 return ret;
 364
 365         while (stat & ~mask) {
 366                 int irq = __ffs(stat & ~mask);
 367
 368                 stat &= ~(1 << irq);
 369
 370                 if (likely(mc13xxx->irqhandler[baseirq + irq])) {
 371                         irqreturn_t handled;
 372
 373                         handled = mc13xxx_irqhandler(mc13xxx, baseirq + irq);
 374                         if (handled == IRQ_HANDLED)
 375                                 num_handled++;
 376                 } else {
 377                         dev_err(mc13xxx->dev,
 378                                         "BUG: irq %u but no handler\n",
 379                                         baseirq + irq);
 380
 381                         mask |= 1 << irq;
 382
 383                         ret = mc13xxx_reg_write(mc13xxx, offmask, mask);
 384                 }
 385         }
 386
 387         return num_handled;
 388 }
 389
 390 static irqreturn_t mc13xxx_irq_thread(int irq, void *data)
 391 {
 392         struct mc13xxx *mc13xxx = data;
 393         irqreturn_t ret;
 394         int handled = 0;
 395
 396         mc13xxx_lock(mc13xxx);
 397
 398         ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT0,
 399                         MC13XXX_IRQMASK0, 0);
 400         if (ret > 0)
 401                 handled = 1;
 402
 403         ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT1,
 404                         MC13XXX_IRQMASK1, 24);
 405         if (ret > 0)
 406                 handled = 1;
 407
 408         mc13xxx_unlock(mc13xxx);
 409
 410         return IRQ_RETVAL(handled);
 411 }
 412
 413 #define maskval(reg, mask)      (((reg) & (mask)) >> __ffs(mask))
 414 static void mc13xxx_print_revision(struct mc13xxx *mc13xxx, u32 revision)
 415 {
 416         dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
 417                         "fin: %d, fab: %d, icid: %d/%d\n",
 418                         mc13xxx->variant->name,
 419                         maskval(revision, MC13XXX_REVISION_REVFULL),
 420                         maskval(revision, MC13XXX_REVISION_REVMETAL),
 421                         maskval(revision, MC13XXX_REVISION_FIN),
 422                         maskval(revision, MC13XXX_REVISION_FAB),
 423                         maskval(revision, MC13XXX_REVISION_ICID),
 424                         maskval(revision, MC13XXX_REVISION_ICIDCODE));
 425 }
 426
 427 static void mc34708_print_revision(struct mc13xxx *mc13xxx, u32 revision)
 428 {
 429         dev_info(mc13xxx->dev, "%s: rev %d.%d, fin: %d, fab: %d\n",
 430                         mc13xxx->variant->name,
 431                         maskval(revision, MC34708_REVISION_REVFULL),
 432                         maskval(revision, MC34708_REVISION_REVMETAL),
 433                         maskval(revision, MC34708_REVISION_FIN),
 434                         maskval(revision, MC34708_REVISION_FAB));
 435 }
 436
 437 /* These are only exported for mc13xxx-i2c and mc13xxx-spi */
 438 struct mc13xxx_variant mc13xxx_variant_mc13783 = {
 439         .name = "mc13783",
 440         .print_revision = mc13xxx_print_revision,
 441 };
 442 EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13783);
 443
 444 struct mc13xxx_variant mc13xxx_variant_mc13892 = {
 445         .name = "mc13892",
 446         .print_revision = mc13xxx_print_revision,
 447 };
 448 EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13892);
 449
 450 struct mc13xxx_variant mc13xxx_variant_mc34708 = {
 451         .name = "mc34708",
 452         .print_revision = mc34708_print_revision,
 453 };
 454 EXPORT_SYMBOL_GPL(mc13xxx_variant_mc34708);
 455
 456 static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
 457 {
 458         return mc13xxx->variant->name;
 459 }
 460
 461 int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
 462 {
 463         return mc13xxx->flags;
 464 }
 465 EXPORT_SYMBOL(mc13xxx_get_flags);
 466
 467 #define MC13XXX_ADC1_CHAN0_SHIFT        5
 468 #define MC13XXX_ADC1_CHAN1_SHIFT        8
 469 #define MC13783_ADC1_ATO_SHIFT          11
 470 #define MC13783_ADC1_ATOX               (1 << 19)
 471
 472 struct mc13xxx_adcdone_data {
 473         struct mc13xxx *mc13xxx;
 474         struct completion done;
 475 };
 476
 477 static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
 478 {
 479         struct mc13xxx_adcdone_data *adcdone_data = data;
 480
 481         mc13xxx_irq_ack(adcdone_data->mc13xxx, irq);
 482
 483         complete_all(&adcdone_data->done);
 484
 485         return IRQ_HANDLED;
 486 }
 487
 488 #define MC13XXX_ADC_WORKING (1 << 0)
 489
 490 int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
 491                 unsigned int channel, u8 ato, bool atox,
 492                 unsigned int *sample)
 493 {
 494         u32 adc0, adc1, old_adc0;
 495         int i, ret;
 496         struct mc13xxx_adcdone_data adcdone_data = {
 497                 .mc13xxx = mc13xxx,
 498         };
 499         init_completion(&adcdone_data.done);
 500
 501         dev_dbg(mc13xxx->dev, "%s\n", __func__);
 502
 503         mc13xxx_lock(mc13xxx);
 504
 505         if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
 506                 ret = -EBUSY;
 507                 goto out;
 508         }
 509
 510         mc13xxx->adcflags |= MC13XXX_ADC_WORKING;
 511
 512         mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
 513
 514         adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2;
 515         adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
 516
 517         if (channel > 7)
 518                 adc1 |= MC13XXX_ADC1_ADSEL;
 519
 520         switch (mode) {
 521         case MC13XXX_ADC_MODE_TS:
 522                 adc0 |= MC13XXX_ADC0_ADREFEN | MC13XXX_ADC0_TSMOD0 |
 523                         MC13XXX_ADC0_TSMOD1;
 524                 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
 525                 break;
 526
 527         case MC13XXX_ADC_MODE_SINGLE_CHAN:
 528                 adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
 529                 adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
 530                 adc1 |= MC13XXX_ADC1_RAND;
 531                 break;
 532
 533         case MC13XXX_ADC_MODE_MULT_CHAN:
 534                 adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
 535                 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
 536                 break;
 537
 538         default:
 539                 mc13xxx_unlock(mc13xxx);
 540                 return -EINVAL;
 541         }
 542
 543         adc1 |= ato << MC13783_ADC1_ATO_SHIFT;
 544         if (atox)
 545                 adc1 |= MC13783_ADC1_ATOX;
 546
 547         dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
 548         mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
 549                         mc13xxx_handler_adcdone, __func__, &adcdone_data);
 550         mc13xxx_irq_ack(mc13xxx, MC13XXX_IRQ_ADCDONE);
 551
 552         mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
 553         mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);
 554
 555         mc13xxx_unlock(mc13xxx);
 556
 557         ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
 558
 559         if (!ret)
 560                 ret = -ETIMEDOUT;
 561
 562         mc13xxx_lock(mc13xxx);
 563
 564         mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);
 565
 566         if (ret > 0)
 567                 for (i = 0; i < 4; ++i) {
 568                         ret = mc13xxx_reg_read(mc13xxx,
 569                                         MC13XXX_ADC2, &sample[i]);
 570                         if (ret)
 571                                 break;
 572                 }
 573
 574         if (mode == MC13XXX_ADC_MODE_TS)
 575                 /* restore TSMOD */
 576                 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);
 577
 578         mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
 579 out:
 580         mc13xxx_unlock(mc13xxx);
 581
 582         return ret;
 583 }
 584 EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);
 585
 586 static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
 587                 const char *format, void *pdata, size_t pdata_size)
 588 {
 589         char buf[30];
 590         const char *name = mc13xxx_get_chipname(mc13xxx);
 591
 592         struct mfd_cell cell = {
 593                 .platform_data = pdata,
 594                 .pdata_size = pdata_size,
 595         };
 596
 597         /* there is no asnprintf in the kernel :-( */
 598         if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
 599                 return -E2BIG;
 600
 601         cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
 602         if (!cell.name)
 603                 return -ENOMEM;
 604
 605         return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0, NULL);
 606 }
 607
 608 static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
 609 {
 610         return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
 611 }
 612
 613 #ifdef CONFIG_OF
 614 static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 615 {
 616         struct device_node *np = mc13xxx->dev->of_node;
 617
 618         if (!np)
 619                 return -ENODEV;
 620
 621         if (of_get_property(np, "fsl,mc13xxx-uses-adc", NULL))
 622                 mc13xxx->flags |= MC13XXX_USE_ADC;
 623
 624         if (of_get_property(np, "fsl,mc13xxx-uses-codec", NULL))
 625                 mc13xxx->flags |= MC13XXX_USE_CODEC;
 626
 627         if (of_get_property(np, "fsl,mc13xxx-uses-rtc", NULL))
 628                 mc13xxx->flags |= MC13XXX_USE_RTC;
 629
 630         if (of_get_property(np, "fsl,mc13xxx-uses-touch", NULL))
 631                 mc13xxx->flags |= MC13XXX_USE_TOUCHSCREEN;
 632
 633         return 0;
 634 }
 635 #else
 636 static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 637 {
 638         return -ENODEV;
 639 }
 640 #endif
 641
 642 int mc13xxx_common_init(struct mc13xxx *mc13xxx,
 643                 struct mc13xxx_platform_data *pdata, int irq)
 644 {
 645         int ret;
 646         u32 revision;
 647
 648         mc13xxx_lock(mc13xxx);
 649
 650         ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
 651         if (ret)
 652                 goto err_revision;
 653
 654         mc13xxx->variant->print_revision(mc13xxx, revision);
 655
 656         /* mask all irqs */
 657         ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK0, 0x00ffffff);
 658         if (ret)
 659                 goto err_mask;
 660
 661         ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK1, 0x00ffffff);
 662         if (ret)
 663                 goto err_mask;
 664
 665         ret = request_threaded_irq(irq, NULL, mc13xxx_irq_thread,
 666                         IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx);
 667
 668         if (ret) {
 669 err_mask:
 670 err_revision:
 671                 mc13xxx_unlock(mc13xxx);
 672                 return ret;
 673         }
 674
 675         mc13xxx->irq = irq;
 676
 677         mc13xxx_unlock(mc13xxx);
 678
 679         if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
 680                 mc13xxx->flags = pdata->flags;
 681
 682         if (mc13xxx->flags & MC13XXX_USE_ADC)
 683                 mc13xxx_add_subdevice(mc13xxx, "%s-adc");
 684
 685         if (mc13xxx->flags & MC13XXX_USE_CODEC)
 686                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
 687                                         pdata->codec, sizeof(*pdata->codec));
 688
 689         if (mc13xxx->flags & MC13XXX_USE_RTC)
 690                 mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
 691
 692         if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
 693                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-ts",
 694                                 &pdata->touch, sizeof(pdata->touch));
 695
 696         if (pdata) {
 697                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
 698                         &pdata->regulators, sizeof(pdata->regulators));
 699                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
 700                                 pdata->leds, sizeof(*pdata->leds));
 701                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
 702                                 pdata->buttons, sizeof(*pdata->buttons));
 703         } else {
 704                 mc13xxx_add_subdevice(mc13xxx, "%s-regulator");
 705                 mc13xxx_add_subdevice(mc13xxx, "%s-led");
 706                 mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton");
 707         }
 708
 709         return 0;
 710 }
 711 EXPORT_SYMBOL_GPL(mc13xxx_common_init);
 712
 713 void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
 714 {
 715         free_irq(mc13xxx->irq, mc13xxx);
 716
 717         mfd_remove_devices(mc13xxx->dev);
 718 }
 719 EXPORT_SYMBOL_GPL(mc13xxx_common_cleanup);
 720
 721 MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
 722 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
 723 MODULE_LICENSE("GPL v2");