1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
22 #include <linux/pci.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/highmem.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/idr.h>
30 #include <linux/platform_device.h>
31 #include <linux/mfd/core.h>
32 #include <linux/mfd/rtsx_pci.h>
33 #include <asm/unaligned.h>
37 static bool msi_en
= true;
38 module_param(msi_en
, bool, S_IRUGO
| S_IWUSR
);
39 MODULE_PARM_DESC(msi_en
, "Enable MSI");
41 static DEFINE_IDR(rtsx_pci_idr
);
42 static DEFINE_SPINLOCK(rtsx_pci_lock
);
44 static struct mfd_cell rtsx_pcr_cells
[] = {
46 .name
= DRV_NAME_RTSX_PCI_SDMMC
,
49 .name
= DRV_NAME_RTSX_PCI_MS
,
53 static const struct pci_device_id rtsx_pci_ids
[] = {
54 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
55 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
57 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
58 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
59 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
60 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
64 MODULE_DEVICE_TABLE(pci
, rtsx_pci_ids
);
66 void rtsx_pci_start_run(struct rtsx_pcr
*pcr
)
68 /* If pci device removed, don't queue idle work any more */
72 if (pcr
->state
!= PDEV_STAT_RUN
) {
73 pcr
->state
= PDEV_STAT_RUN
;
74 if (pcr
->ops
->enable_auto_blink
)
75 pcr
->ops
->enable_auto_blink(pcr
);
78 rtsx_pci_write_config_byte(pcr
, LCTLR
, 0);
81 mod_delayed_work(system_wq
, &pcr
->idle_work
, msecs_to_jiffies(200));
83 EXPORT_SYMBOL_GPL(rtsx_pci_start_run
);
85 int rtsx_pci_write_register(struct rtsx_pcr
*pcr
, u16 addr
, u8 mask
, u8 data
)
88 u32 val
= HAIMR_WRITE_START
;
90 val
|= (u32
)(addr
& 0x3FFF) << 16;
91 val
|= (u32
)mask
<< 8;
94 rtsx_pci_writel(pcr
, RTSX_HAIMR
, val
);
96 for (i
= 0; i
< MAX_RW_REG_CNT
; i
++) {
97 val
= rtsx_pci_readl(pcr
, RTSX_HAIMR
);
98 if ((val
& HAIMR_TRANS_END
) == 0) {
107 EXPORT_SYMBOL_GPL(rtsx_pci_write_register
);
109 int rtsx_pci_read_register(struct rtsx_pcr
*pcr
, u16 addr
, u8
*data
)
111 u32 val
= HAIMR_READ_START
;
114 val
|= (u32
)(addr
& 0x3FFF) << 16;
115 rtsx_pci_writel(pcr
, RTSX_HAIMR
, val
);
117 for (i
= 0; i
< MAX_RW_REG_CNT
; i
++) {
118 val
= rtsx_pci_readl(pcr
, RTSX_HAIMR
);
119 if ((val
& HAIMR_TRANS_END
) == 0)
123 if (i
>= MAX_RW_REG_CNT
)
127 *data
= (u8
)(val
& 0xFF);
131 EXPORT_SYMBOL_GPL(rtsx_pci_read_register
);
133 int rtsx_pci_write_phy_register(struct rtsx_pcr
*pcr
, u8 addr
, u16 val
)
135 int err
, i
, finished
= 0;
138 rtsx_pci_init_cmd(pcr
);
140 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYDATA0
, 0xFF, (u8
)val
);
141 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYDATA1
, 0xFF, (u8
)(val
>> 8));
142 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYADDR
, 0xFF, addr
);
143 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYRWCTL
, 0xFF, 0x81);
145 err
= rtsx_pci_send_cmd(pcr
, 100);
149 for (i
= 0; i
< 100000; i
++) {
150 err
= rtsx_pci_read_register(pcr
, PHYRWCTL
, &tmp
);
165 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register
);
167 int rtsx_pci_read_phy_register(struct rtsx_pcr
*pcr
, u8 addr
, u16
*val
)
169 int err
, i
, finished
= 0;
173 rtsx_pci_init_cmd(pcr
);
175 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYADDR
, 0xFF, addr
);
176 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYRWCTL
, 0xFF, 0x80);
178 err
= rtsx_pci_send_cmd(pcr
, 100);
182 for (i
= 0; i
< 100000; i
++) {
183 err
= rtsx_pci_read_register(pcr
, PHYRWCTL
, &tmp
);
196 rtsx_pci_init_cmd(pcr
);
198 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, PHYDATA0
, 0, 0);
199 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, PHYDATA1
, 0, 0);
201 err
= rtsx_pci_send_cmd(pcr
, 100);
205 ptr
= rtsx_pci_get_cmd_data(pcr
);
206 data
= ((u16
)ptr
[1] << 8) | ptr
[0];
213 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register
);
215 void rtsx_pci_stop_cmd(struct rtsx_pcr
*pcr
)
217 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, STOP_CMD
);
218 rtsx_pci_writel(pcr
, RTSX_HDBCTLR
, STOP_DMA
);
220 rtsx_pci_write_register(pcr
, DMACTL
, 0x80, 0x80);
221 rtsx_pci_write_register(pcr
, RBCTL
, 0x80, 0x80);
223 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd
);
225 void rtsx_pci_add_cmd(struct rtsx_pcr
*pcr
,
226 u8 cmd_type
, u16 reg_addr
, u8 mask
, u8 data
)
230 u32
*ptr
= (u32
*)(pcr
->host_cmds_ptr
);
232 val
|= (u32
)(cmd_type
& 0x03) << 30;
233 val
|= (u32
)(reg_addr
& 0x3FFF) << 16;
234 val
|= (u32
)mask
<< 8;
237 spin_lock_irqsave(&pcr
->lock
, flags
);
239 if (pcr
->ci
< (HOST_CMDS_BUF_LEN
/ 4)) {
240 put_unaligned_le32(val
, ptr
);
244 spin_unlock_irqrestore(&pcr
->lock
, flags
);
246 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd
);
248 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr
*pcr
)
252 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
254 val
|= (u32
)(pcr
->ci
* 4) & 0x00FFFFFF;
255 /* Hardware Auto Response */
257 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, val
);
259 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait
);
261 int rtsx_pci_send_cmd(struct rtsx_pcr
*pcr
, int timeout
)
263 struct completion trans_done
;
269 spin_lock_irqsave(&pcr
->lock
, flags
);
271 /* set up data structures for the wakeup system */
272 pcr
->done
= &trans_done
;
273 pcr
->trans_result
= TRANS_NOT_READY
;
274 init_completion(&trans_done
);
276 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
278 val
|= (u32
)(pcr
->ci
* 4) & 0x00FFFFFF;
279 /* Hardware Auto Response */
281 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, val
);
283 spin_unlock_irqrestore(&pcr
->lock
, flags
);
285 /* Wait for TRANS_OK_INT */
286 timeleft
= wait_for_completion_interruptible_timeout(
287 &trans_done
, msecs_to_jiffies(timeout
));
289 dev_dbg(&(pcr
->pci
->dev
), "Timeout (%s %d)\n",
292 goto finish_send_cmd
;
295 spin_lock_irqsave(&pcr
->lock
, flags
);
296 if (pcr
->trans_result
== TRANS_RESULT_FAIL
)
298 else if (pcr
->trans_result
== TRANS_RESULT_OK
)
300 else if (pcr
->trans_result
== TRANS_NO_DEVICE
)
302 spin_unlock_irqrestore(&pcr
->lock
, flags
);
305 spin_lock_irqsave(&pcr
->lock
, flags
);
307 spin_unlock_irqrestore(&pcr
->lock
, flags
);
309 if ((err
< 0) && (err
!= -ENODEV
))
310 rtsx_pci_stop_cmd(pcr
);
313 complete(pcr
->finish_me
);
317 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd
);
319 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr
*pcr
,
320 dma_addr_t addr
, unsigned int len
, int end
)
322 u64
*ptr
= (u64
*)(pcr
->host_sg_tbl_ptr
) + pcr
->sgi
;
324 u8 option
= SG_VALID
| SG_TRANS_DATA
;
326 dev_dbg(&(pcr
->pci
->dev
), "DMA addr: 0x%x, Len: 0x%x\n",
327 (unsigned int)addr
, len
);
331 val
= ((u64
)addr
<< 32) | ((u64
)len
<< 12) | option
;
333 put_unaligned_le64(val
, ptr
);
337 int rtsx_pci_transfer_data(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
338 int num_sg
, bool read
, int timeout
)
342 dev_dbg(&(pcr
->pci
->dev
), "--> %s: num_sg = %d\n", __func__
, num_sg
);
343 count
= rtsx_pci_dma_map_sg(pcr
, sglist
, num_sg
, read
);
346 dev_dbg(&(pcr
->pci
->dev
), "DMA mapping count: %d\n", count
);
348 err
= rtsx_pci_dma_transfer(pcr
, sglist
, count
, read
, timeout
);
350 rtsx_pci_dma_unmap_sg(pcr
, sglist
, num_sg
, read
);
354 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data
);
356 int rtsx_pci_dma_map_sg(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
357 int num_sg
, bool read
)
359 enum dma_data_direction dir
= read
? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
364 if ((sglist
== NULL
) || (num_sg
<= 0))
367 return dma_map_sg(&(pcr
->pci
->dev
), sglist
, num_sg
, dir
);
369 EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg
);
371 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
372 int num_sg
, bool read
)
374 enum dma_data_direction dir
= read
? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
376 dma_unmap_sg(&(pcr
->pci
->dev
), sglist
, num_sg
, dir
);
378 EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg
);
380 int rtsx_pci_dma_transfer(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
381 int count
, bool read
, int timeout
)
383 struct completion trans_done
;
384 struct scatterlist
*sg
;
391 u8 dir
= read
? DEVICE_TO_HOST
: HOST_TO_DEVICE
;
396 if ((sglist
== NULL
) || (count
< 1))
399 val
= ((u32
)(dir
& 0x01) << 29) | TRIG_DMA
| ADMA_MODE
;
401 for_each_sg(sglist
, sg
, count
, i
) {
402 addr
= sg_dma_address(sg
);
403 len
= sg_dma_len(sg
);
404 rtsx_pci_add_sg_tbl(pcr
, addr
, len
, i
== count
- 1);
407 spin_lock_irqsave(&pcr
->lock
, flags
);
409 pcr
->done
= &trans_done
;
410 pcr
->trans_result
= TRANS_NOT_READY
;
411 init_completion(&trans_done
);
412 rtsx_pci_writel(pcr
, RTSX_HDBAR
, pcr
->host_sg_tbl_addr
);
413 rtsx_pci_writel(pcr
, RTSX_HDBCTLR
, val
);
415 spin_unlock_irqrestore(&pcr
->lock
, flags
);
417 timeleft
= wait_for_completion_interruptible_timeout(
418 &trans_done
, msecs_to_jiffies(timeout
));
420 dev_dbg(&(pcr
->pci
->dev
), "Timeout (%s %d)\n",
426 spin_lock_irqsave(&pcr
->lock
, flags
);
427 if (pcr
->trans_result
== TRANS_RESULT_FAIL
)
429 else if (pcr
->trans_result
== TRANS_NO_DEVICE
)
431 spin_unlock_irqrestore(&pcr
->lock
, flags
);
434 spin_lock_irqsave(&pcr
->lock
, flags
);
436 spin_unlock_irqrestore(&pcr
->lock
, flags
);
438 if ((err
< 0) && (err
!= -ENODEV
))
439 rtsx_pci_stop_cmd(pcr
);
442 complete(pcr
->finish_me
);
446 EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer
);
448 int rtsx_pci_read_ppbuf(struct rtsx_pcr
*pcr
, u8
*buf
, int buf_len
)
460 for (i
= 0; i
< buf_len
/ 256; i
++) {
461 rtsx_pci_init_cmd(pcr
);
463 for (j
= 0; j
< 256; j
++)
464 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, reg
++, 0, 0);
466 err
= rtsx_pci_send_cmd(pcr
, 250);
470 memcpy(ptr
, rtsx_pci_get_cmd_data(pcr
), 256);
475 rtsx_pci_init_cmd(pcr
);
477 for (j
= 0; j
< buf_len
% 256; j
++)
478 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, reg
++, 0, 0);
480 err
= rtsx_pci_send_cmd(pcr
, 250);
485 memcpy(ptr
, rtsx_pci_get_cmd_data(pcr
), buf_len
% 256);
489 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf
);
491 int rtsx_pci_write_ppbuf(struct rtsx_pcr
*pcr
, u8
*buf
, int buf_len
)
503 for (i
= 0; i
< buf_len
/ 256; i
++) {
504 rtsx_pci_init_cmd(pcr
);
506 for (j
= 0; j
< 256; j
++) {
507 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
512 err
= rtsx_pci_send_cmd(pcr
, 250);
518 rtsx_pci_init_cmd(pcr
);
520 for (j
= 0; j
< buf_len
% 256; j
++) {
521 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
526 err
= rtsx_pci_send_cmd(pcr
, 250);
533 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf
);
535 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr
*pcr
, const u32
*tbl
)
539 rtsx_pci_init_cmd(pcr
);
541 while (*tbl
& 0xFFFF0000) {
542 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
543 (u16
)(*tbl
>> 16), 0xFF, (u8
)(*tbl
));
547 err
= rtsx_pci_send_cmd(pcr
, 100);
554 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr
*pcr
, int card
)
558 if (card
== RTSX_SD_CARD
)
559 tbl
= pcr
->sd_pull_ctl_enable_tbl
;
560 else if (card
== RTSX_MS_CARD
)
561 tbl
= pcr
->ms_pull_ctl_enable_tbl
;
565 return rtsx_pci_set_pull_ctl(pcr
, tbl
);
567 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable
);
569 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr
*pcr
, int card
)
573 if (card
== RTSX_SD_CARD
)
574 tbl
= pcr
->sd_pull_ctl_disable_tbl
;
575 else if (card
== RTSX_MS_CARD
)
576 tbl
= pcr
->ms_pull_ctl_disable_tbl
;
581 return rtsx_pci_set_pull_ctl(pcr
, tbl
);
583 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable
);
585 static void rtsx_pci_enable_bus_int(struct rtsx_pcr
*pcr
)
587 pcr
->bier
= TRANS_OK_INT_EN
| TRANS_FAIL_INT_EN
| SD_INT_EN
;
589 if (pcr
->num_slots
> 1)
590 pcr
->bier
|= MS_INT_EN
;
592 /* Enable Bus Interrupt */
593 rtsx_pci_writel(pcr
, RTSX_BIER
, pcr
->bier
);
595 dev_dbg(&(pcr
->pci
->dev
), "RTSX_BIER: 0x%08x\n", pcr
->bier
);
598 static inline u8
double_ssc_depth(u8 depth
)
600 return ((depth
> 1) ? (depth
- 1) : depth
);
603 static u8
revise_ssc_depth(u8 ssc_depth
, u8 div
)
605 if (div
> CLK_DIV_1
) {
606 if (ssc_depth
> (div
- 1))
607 ssc_depth
-= (div
- 1);
609 ssc_depth
= SSC_DEPTH_4M
;
615 int rtsx_pci_switch_clock(struct rtsx_pcr
*pcr
, unsigned int card_clock
,
616 u8 ssc_depth
, bool initial_mode
, bool double_clk
, bool vpclk
)
619 u8 n
, clk_divider
, mcu_cnt
, div
;
621 [RTSX_SSC_DEPTH_4M
] = SSC_DEPTH_4M
,
622 [RTSX_SSC_DEPTH_2M
] = SSC_DEPTH_2M
,
623 [RTSX_SSC_DEPTH_1M
] = SSC_DEPTH_1M
,
624 [RTSX_SSC_DEPTH_500K
] = SSC_DEPTH_500K
,
625 [RTSX_SSC_DEPTH_250K
] = SSC_DEPTH_250K
,
629 /* We use 250k(around) here, in initial stage */
630 clk_divider
= SD_CLK_DIVIDE_128
;
631 card_clock
= 30000000;
633 clk_divider
= SD_CLK_DIVIDE_0
;
635 err
= rtsx_pci_write_register(pcr
, SD_CFG1
,
636 SD_CLK_DIVIDE_MASK
, clk_divider
);
640 card_clock
/= 1000000;
641 dev_dbg(&(pcr
->pci
->dev
), "Switch card clock to %dMHz\n", card_clock
);
644 if (!initial_mode
&& double_clk
)
645 clk
= card_clock
* 2;
646 dev_dbg(&(pcr
->pci
->dev
),
647 "Internal SSC clock: %dMHz (cur_clock = %d)\n",
648 clk
, pcr
->cur_clock
);
650 if (clk
== pcr
->cur_clock
)
653 if (pcr
->ops
->conv_clk_and_div_n
)
654 n
= (u8
)pcr
->ops
->conv_clk_and_div_n(clk
, CLK_TO_DIV_N
);
657 if ((clk
<= 2) || (n
> MAX_DIV_N_PCR
))
660 mcu_cnt
= (u8
)(125/clk
+ 3);
664 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
666 while ((n
< MIN_DIV_N_PCR
) && (div
< CLK_DIV_8
)) {
667 if (pcr
->ops
->conv_clk_and_div_n
) {
668 int dbl_clk
= pcr
->ops
->conv_clk_and_div_n(n
,
670 n
= (u8
)pcr
->ops
->conv_clk_and_div_n(dbl_clk
,
677 dev_dbg(&(pcr
->pci
->dev
), "n = %d, div = %d\n", n
, div
);
679 ssc_depth
= depth
[ssc_depth
];
681 ssc_depth
= double_ssc_depth(ssc_depth
);
683 ssc_depth
= revise_ssc_depth(ssc_depth
, div
);
684 dev_dbg(&(pcr
->pci
->dev
), "ssc_depth = %d\n", ssc_depth
);
686 rtsx_pci_init_cmd(pcr
);
687 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
,
688 CLK_LOW_FREQ
, CLK_LOW_FREQ
);
689 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_DIV
,
690 0xFF, (div
<< 4) | mcu_cnt
);
691 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
, SSC_RSTB
, 0);
692 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL2
,
693 SSC_DEPTH_MASK
, ssc_depth
);
694 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_DIV_N_0
, 0xFF, n
);
695 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
, SSC_RSTB
, SSC_RSTB
);
697 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
699 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
700 PHASE_NOT_RESET
, PHASE_NOT_RESET
);
703 err
= rtsx_pci_send_cmd(pcr
, 2000);
707 /* Wait SSC clock stable */
709 err
= rtsx_pci_write_register(pcr
, CLK_CTL
, CLK_LOW_FREQ
, 0);
713 pcr
->cur_clock
= clk
;
716 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock
);
718 int rtsx_pci_card_power_on(struct rtsx_pcr
*pcr
, int card
)
720 if (pcr
->ops
->card_power_on
)
721 return pcr
->ops
->card_power_on(pcr
, card
);
725 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on
);
727 int rtsx_pci_card_power_off(struct rtsx_pcr
*pcr
, int card
)
729 if (pcr
->ops
->card_power_off
)
730 return pcr
->ops
->card_power_off(pcr
, card
);
734 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off
);
736 int rtsx_pci_card_exclusive_check(struct rtsx_pcr
*pcr
, int card
)
738 unsigned int cd_mask
[] = {
739 [RTSX_SD_CARD
] = SD_EXIST
,
740 [RTSX_MS_CARD
] = MS_EXIST
743 if (!(pcr
->flags
& PCR_MS_PMOS
)) {
744 /* When using single PMOS, accessing card is not permitted
745 * if the existing card is not the designated one.
747 if (pcr
->card_exist
& (~cd_mask
[card
]))
753 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check
);
755 int rtsx_pci_switch_output_voltage(struct rtsx_pcr
*pcr
, u8 voltage
)
757 if (pcr
->ops
->switch_output_voltage
)
758 return pcr
->ops
->switch_output_voltage(pcr
, voltage
);
762 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage
);
764 unsigned int rtsx_pci_card_exist(struct rtsx_pcr
*pcr
)
768 val
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
769 if (pcr
->ops
->cd_deglitch
)
770 val
= pcr
->ops
->cd_deglitch(pcr
);
774 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist
);
776 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr
*pcr
)
778 struct completion finish
;
780 pcr
->finish_me
= &finish
;
781 init_completion(&finish
);
786 if (!pcr
->remove_pci
)
787 rtsx_pci_stop_cmd(pcr
);
789 wait_for_completion_interruptible_timeout(&finish
,
790 msecs_to_jiffies(2));
791 pcr
->finish_me
= NULL
;
793 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer
);
795 static void rtsx_pci_card_detect(struct work_struct
*work
)
797 struct delayed_work
*dwork
;
798 struct rtsx_pcr
*pcr
;
800 unsigned int card_detect
= 0, card_inserted
, card_removed
;
803 dwork
= to_delayed_work(work
);
804 pcr
= container_of(dwork
, struct rtsx_pcr
, carddet_work
);
806 dev_dbg(&(pcr
->pci
->dev
), "--> %s\n", __func__
);
808 mutex_lock(&pcr
->pcr_mutex
);
809 spin_lock_irqsave(&pcr
->lock
, flags
);
811 irq_status
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
812 dev_dbg(&(pcr
->pci
->dev
), "irq_status: 0x%08x\n", irq_status
);
814 irq_status
&= CARD_EXIST
;
815 card_inserted
= pcr
->card_inserted
& irq_status
;
816 card_removed
= pcr
->card_removed
;
817 pcr
->card_inserted
= 0;
818 pcr
->card_removed
= 0;
820 spin_unlock_irqrestore(&pcr
->lock
, flags
);
822 if (card_inserted
|| card_removed
) {
823 dev_dbg(&(pcr
->pci
->dev
),
824 "card_inserted: 0x%x, card_removed: 0x%x\n",
825 card_inserted
, card_removed
);
827 if (pcr
->ops
->cd_deglitch
)
828 card_inserted
= pcr
->ops
->cd_deglitch(pcr
);
830 card_detect
= card_inserted
| card_removed
;
832 pcr
->card_exist
|= card_inserted
;
833 pcr
->card_exist
&= ~card_removed
;
836 mutex_unlock(&pcr
->pcr_mutex
);
838 if ((card_detect
& SD_EXIST
) && pcr
->slots
[RTSX_SD_CARD
].card_event
)
839 pcr
->slots
[RTSX_SD_CARD
].card_event(
840 pcr
->slots
[RTSX_SD_CARD
].p_dev
);
841 if ((card_detect
& MS_EXIST
) && pcr
->slots
[RTSX_MS_CARD
].card_event
)
842 pcr
->slots
[RTSX_MS_CARD
].card_event(
843 pcr
->slots
[RTSX_MS_CARD
].p_dev
);
846 static irqreturn_t
rtsx_pci_isr(int irq
, void *dev_id
)
848 struct rtsx_pcr
*pcr
= dev_id
;
854 spin_lock(&pcr
->lock
);
856 int_reg
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
857 /* Clear interrupt flag */
858 rtsx_pci_writel(pcr
, RTSX_BIPR
, int_reg
);
859 if ((int_reg
& pcr
->bier
) == 0) {
860 spin_unlock(&pcr
->lock
);
863 if (int_reg
== 0xFFFFFFFF) {
864 spin_unlock(&pcr
->lock
);
868 int_reg
&= (pcr
->bier
| 0x7FFFFF);
870 if (int_reg
& SD_INT
) {
871 if (int_reg
& SD_EXIST
) {
872 pcr
->card_inserted
|= SD_EXIST
;
874 pcr
->card_removed
|= SD_EXIST
;
875 pcr
->card_inserted
&= ~SD_EXIST
;
879 if (int_reg
& MS_INT
) {
880 if (int_reg
& MS_EXIST
) {
881 pcr
->card_inserted
|= MS_EXIST
;
883 pcr
->card_removed
|= MS_EXIST
;
884 pcr
->card_inserted
&= ~MS_EXIST
;
888 if (int_reg
& (NEED_COMPLETE_INT
| DELINK_INT
)) {
889 if (int_reg
& (TRANS_FAIL_INT
| DELINK_INT
)) {
890 pcr
->trans_result
= TRANS_RESULT_FAIL
;
893 } else if (int_reg
& TRANS_OK_INT
) {
894 pcr
->trans_result
= TRANS_RESULT_OK
;
900 if (pcr
->card_inserted
|| pcr
->card_removed
)
901 schedule_delayed_work(&pcr
->carddet_work
,
902 msecs_to_jiffies(200));
904 spin_unlock(&pcr
->lock
);
908 static int rtsx_pci_acquire_irq(struct rtsx_pcr
*pcr
)
910 dev_info(&(pcr
->pci
->dev
), "%s: pcr->msi_en = %d, pci->irq = %d\n",
911 __func__
, pcr
->msi_en
, pcr
->pci
->irq
);
913 if (request_irq(pcr
->pci
->irq
, rtsx_pci_isr
,
914 pcr
->msi_en
? 0 : IRQF_SHARED
,
915 DRV_NAME_RTSX_PCI
, pcr
)) {
916 dev_err(&(pcr
->pci
->dev
),
917 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
922 pcr
->irq
= pcr
->pci
->irq
;
923 pci_intx(pcr
->pci
, !pcr
->msi_en
);
928 static void rtsx_pci_idle_work(struct work_struct
*work
)
930 struct delayed_work
*dwork
= to_delayed_work(work
);
931 struct rtsx_pcr
*pcr
= container_of(dwork
, struct rtsx_pcr
, idle_work
);
933 dev_dbg(&(pcr
->pci
->dev
), "--> %s\n", __func__
);
935 mutex_lock(&pcr
->pcr_mutex
);
937 pcr
->state
= PDEV_STAT_IDLE
;
939 if (pcr
->ops
->disable_auto_blink
)
940 pcr
->ops
->disable_auto_blink(pcr
);
941 if (pcr
->ops
->turn_off_led
)
942 pcr
->ops
->turn_off_led(pcr
);
945 rtsx_pci_write_config_byte(pcr
, LCTLR
, pcr
->aspm_en
);
947 mutex_unlock(&pcr
->pcr_mutex
);
950 static void rtsx_pci_power_off(struct rtsx_pcr
*pcr
, u8 pm_state
)
952 if (pcr
->ops
->turn_off_led
)
953 pcr
->ops
->turn_off_led(pcr
);
955 rtsx_pci_writel(pcr
, RTSX_BIER
, 0);
958 rtsx_pci_write_register(pcr
, PETXCFG
, 0x08, 0x08);
959 rtsx_pci_write_register(pcr
, HOST_SLEEP_STATE
, 0x03, pm_state
);
961 if (pcr
->ops
->force_power_down
)
962 pcr
->ops
->force_power_down(pcr
, pm_state
);
965 static int rtsx_pci_init_hw(struct rtsx_pcr
*pcr
)
969 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
971 rtsx_pci_enable_bus_int(pcr
);
974 err
= rtsx_pci_write_register(pcr
, FPDCTL
, SSC_POWER_DOWN
, 0);
978 /* Wait SSC power stable */
981 if (pcr
->ops
->optimize_phy
) {
982 err
= pcr
->ops
->optimize_phy(pcr
);
987 rtsx_pci_init_cmd(pcr
);
989 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
990 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_DIV
, 0x07, 0x07);
992 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, HOST_SLEEP_STATE
, 0x03, 0x00);
993 /* Disable card clock */
994 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_CLK_EN
, 0x1E, 0);
995 /* Reset delink mode */
996 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CHANGE_LINK_STATE
, 0x0A, 0);
997 /* Card driving select */
998 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_DRIVE_SEL
,
999 0xFF, pcr
->card_drive_sel
);
1000 /* Enable SSC Clock */
1001 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
,
1002 0xFF, SSC_8X_EN
| SSC_SEL_4M
);
1003 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL2
, 0xFF, 0x12);
1004 /* Disable cd_pwr_save */
1005 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CHANGE_LINK_STATE
, 0x16, 0x10);
1006 /* Clear Link Ready Interrupt */
1007 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, IRQSTAT0
,
1008 LINK_RDY_INT
, LINK_RDY_INT
);
1009 /* Enlarge the estimation window of PERST# glitch
1010 * to reduce the chance of invalid card interrupt
1012 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PERST_GLITCH_WIDTH
, 0xFF, 0x80);
1013 /* Update RC oscillator to 400k
1014 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
1017 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, RCCTL
, 0x01, 0x00);
1018 /* Set interrupt write clear
1019 * bit 1: U_elbi_if_rd_clr_en
1020 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1021 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1023 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, NFTS_TX_CTRL
, 0x02, 0);
1025 err
= rtsx_pci_send_cmd(pcr
, 100);
1029 rtsx_pci_write_config_byte(pcr
, LCTLR
, 0);
1031 /* Enable clk_request_n to enable clock power management */
1032 rtsx_pci_write_config_byte(pcr
, 0x81, 1);
1033 /* Enter L1 when host tx idle */
1034 rtsx_pci_write_config_byte(pcr
, 0x70F, 0x5B);
1036 if (pcr
->ops
->extra_init_hw
) {
1037 err
= pcr
->ops
->extra_init_hw(pcr
);
1042 /* No CD interrupt if probing driver with card inserted.
1043 * So we need to initialize pcr->card_exist here.
1045 if (pcr
->ops
->cd_deglitch
)
1046 pcr
->card_exist
= pcr
->ops
->cd_deglitch(pcr
);
1048 pcr
->card_exist
= rtsx_pci_readl(pcr
, RTSX_BIPR
) & CARD_EXIST
;
1053 static int rtsx_pci_init_chip(struct rtsx_pcr
*pcr
)
1057 spin_lock_init(&pcr
->lock
);
1058 mutex_init(&pcr
->pcr_mutex
);
1060 switch (PCI_PID(pcr
)) {
1063 rts5209_init_params(pcr
);
1067 rts5229_init_params(pcr
);
1071 rtl8411_init_params(pcr
);
1075 rts5227_init_params(pcr
);
1079 rts5249_init_params(pcr
);
1083 rtl8411b_init_params(pcr
);
1087 rtl8402_init_params(pcr
);
1091 dev_dbg(&(pcr
->pci
->dev
), "PID: 0x%04x, IC version: 0x%02x\n",
1092 PCI_PID(pcr
), pcr
->ic_version
);
1094 pcr
->slots
= kcalloc(pcr
->num_slots
, sizeof(struct rtsx_slot
),
1099 if (pcr
->ops
->fetch_vendor_settings
)
1100 pcr
->ops
->fetch_vendor_settings(pcr
);
1102 dev_dbg(&(pcr
->pci
->dev
), "pcr->aspm_en = 0x%x\n", pcr
->aspm_en
);
1103 dev_dbg(&(pcr
->pci
->dev
), "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1104 pcr
->sd30_drive_sel_1v8
);
1105 dev_dbg(&(pcr
->pci
->dev
), "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1106 pcr
->sd30_drive_sel_3v3
);
1107 dev_dbg(&(pcr
->pci
->dev
), "pcr->card_drive_sel = 0x%x\n",
1108 pcr
->card_drive_sel
);
1109 dev_dbg(&(pcr
->pci
->dev
), "pcr->flags = 0x%x\n", pcr
->flags
);
1111 pcr
->state
= PDEV_STAT_IDLE
;
1112 err
= rtsx_pci_init_hw(pcr
);
1121 static int rtsx_pci_probe(struct pci_dev
*pcidev
,
1122 const struct pci_device_id
*id
)
1124 struct rtsx_pcr
*pcr
;
1125 struct pcr_handle
*handle
;
1129 dev_dbg(&(pcidev
->dev
),
1130 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1131 pci_name(pcidev
), (int)pcidev
->vendor
, (int)pcidev
->device
,
1132 (int)pcidev
->revision
);
1134 ret
= pci_set_dma_mask(pcidev
, DMA_BIT_MASK(32));
1138 ret
= pci_enable_device(pcidev
);
1142 ret
= pci_request_regions(pcidev
, DRV_NAME_RTSX_PCI
);
1146 pcr
= kzalloc(sizeof(*pcr
), GFP_KERNEL
);
1152 handle
= kzalloc(sizeof(*handle
), GFP_KERNEL
);
1159 idr_preload(GFP_KERNEL
);
1160 spin_lock(&rtsx_pci_lock
);
1161 ret
= idr_alloc(&rtsx_pci_idr
, pcr
, 0, 0, GFP_NOWAIT
);
1164 spin_unlock(&rtsx_pci_lock
);
1170 dev_set_drvdata(&pcidev
->dev
, handle
);
1172 len
= pci_resource_len(pcidev
, 0);
1173 base
= pci_resource_start(pcidev
, 0);
1174 pcr
->remap_addr
= ioremap_nocache(base
, len
);
1175 if (!pcr
->remap_addr
) {
1180 pcr
->rtsx_resv_buf
= dma_alloc_coherent(&(pcidev
->dev
),
1181 RTSX_RESV_BUF_LEN
, &(pcr
->rtsx_resv_buf_addr
),
1183 if (pcr
->rtsx_resv_buf
== NULL
) {
1187 pcr
->host_cmds_ptr
= pcr
->rtsx_resv_buf
;
1188 pcr
->host_cmds_addr
= pcr
->rtsx_resv_buf_addr
;
1189 pcr
->host_sg_tbl_ptr
= pcr
->rtsx_resv_buf
+ HOST_CMDS_BUF_LEN
;
1190 pcr
->host_sg_tbl_addr
= pcr
->rtsx_resv_buf_addr
+ HOST_CMDS_BUF_LEN
;
1192 pcr
->card_inserted
= 0;
1193 pcr
->card_removed
= 0;
1194 INIT_DELAYED_WORK(&pcr
->carddet_work
, rtsx_pci_card_detect
);
1195 INIT_DELAYED_WORK(&pcr
->idle_work
, rtsx_pci_idle_work
);
1197 pcr
->msi_en
= msi_en
;
1199 ret
= pci_enable_msi(pcidev
);
1201 pcr
->msi_en
= false;
1204 ret
= rtsx_pci_acquire_irq(pcr
);
1208 pci_set_master(pcidev
);
1209 synchronize_irq(pcr
->irq
);
1211 ret
= rtsx_pci_init_chip(pcr
);
1215 for (i
= 0; i
< ARRAY_SIZE(rtsx_pcr_cells
); i
++) {
1216 rtsx_pcr_cells
[i
].platform_data
= handle
;
1217 rtsx_pcr_cells
[i
].pdata_size
= sizeof(*handle
);
1219 ret
= mfd_add_devices(&pcidev
->dev
, pcr
->id
, rtsx_pcr_cells
,
1220 ARRAY_SIZE(rtsx_pcr_cells
), NULL
, 0, NULL
);
1224 schedule_delayed_work(&pcr
->idle_work
, msecs_to_jiffies(200));
1229 free_irq(pcr
->irq
, (void *)pcr
);
1232 pci_disable_msi(pcr
->pci
);
1233 dma_free_coherent(&(pcr
->pci
->dev
), RTSX_RESV_BUF_LEN
,
1234 pcr
->rtsx_resv_buf
, pcr
->rtsx_resv_buf_addr
);
1236 iounmap(pcr
->remap_addr
);
1242 pci_release_regions(pcidev
);
1244 pci_disable_device(pcidev
);
1249 static void rtsx_pci_remove(struct pci_dev
*pcidev
)
1251 struct pcr_handle
*handle
= pci_get_drvdata(pcidev
);
1252 struct rtsx_pcr
*pcr
= handle
->pcr
;
1254 pcr
->remove_pci
= true;
1256 /* Disable interrupts at the pcr level */
1257 spin_lock_irq(&pcr
->lock
);
1258 rtsx_pci_writel(pcr
, RTSX_BIER
, 0);
1260 spin_unlock_irq(&pcr
->lock
);
1262 cancel_delayed_work_sync(&pcr
->carddet_work
);
1263 cancel_delayed_work_sync(&pcr
->idle_work
);
1265 mfd_remove_devices(&pcidev
->dev
);
1267 dma_free_coherent(&(pcr
->pci
->dev
), RTSX_RESV_BUF_LEN
,
1268 pcr
->rtsx_resv_buf
, pcr
->rtsx_resv_buf_addr
);
1269 free_irq(pcr
->irq
, (void *)pcr
);
1271 pci_disable_msi(pcr
->pci
);
1272 iounmap(pcr
->remap_addr
);
1274 pci_release_regions(pcidev
);
1275 pci_disable_device(pcidev
);
1277 spin_lock(&rtsx_pci_lock
);
1278 idr_remove(&rtsx_pci_idr
, pcr
->id
);
1279 spin_unlock(&rtsx_pci_lock
);
1285 dev_dbg(&(pcidev
->dev
),
1286 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1287 pci_name(pcidev
), (int)pcidev
->vendor
, (int)pcidev
->device
);
1292 static int rtsx_pci_suspend(struct pci_dev
*pcidev
, pm_message_t state
)
1294 struct pcr_handle
*handle
;
1295 struct rtsx_pcr
*pcr
;
1297 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1299 handle
= pci_get_drvdata(pcidev
);
1302 cancel_delayed_work(&pcr
->carddet_work
);
1303 cancel_delayed_work(&pcr
->idle_work
);
1305 mutex_lock(&pcr
->pcr_mutex
);
1307 rtsx_pci_power_off(pcr
, HOST_ENTER_S3
);
1309 pci_save_state(pcidev
);
1310 pci_enable_wake(pcidev
, pci_choose_state(pcidev
, state
), 0);
1311 pci_disable_device(pcidev
);
1312 pci_set_power_state(pcidev
, pci_choose_state(pcidev
, state
));
1314 mutex_unlock(&pcr
->pcr_mutex
);
1318 static int rtsx_pci_resume(struct pci_dev
*pcidev
)
1320 struct pcr_handle
*handle
;
1321 struct rtsx_pcr
*pcr
;
1324 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1326 handle
= pci_get_drvdata(pcidev
);
1329 mutex_lock(&pcr
->pcr_mutex
);
1331 pci_set_power_state(pcidev
, PCI_D0
);
1332 pci_restore_state(pcidev
);
1333 ret
= pci_enable_device(pcidev
);
1336 pci_set_master(pcidev
);
1338 ret
= rtsx_pci_write_register(pcr
, HOST_SLEEP_STATE
, 0x03, 0x00);
1342 ret
= rtsx_pci_init_hw(pcr
);
1346 schedule_delayed_work(&pcr
->idle_work
, msecs_to_jiffies(200));
1349 mutex_unlock(&pcr
->pcr_mutex
);
1353 static void rtsx_pci_shutdown(struct pci_dev
*pcidev
)
1355 struct pcr_handle
*handle
;
1356 struct rtsx_pcr
*pcr
;
1358 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1360 handle
= pci_get_drvdata(pcidev
);
1362 rtsx_pci_power_off(pcr
, HOST_ENTER_S1
);
1364 pci_disable_device(pcidev
);
1367 #else /* CONFIG_PM */
1369 #define rtsx_pci_suspend NULL
1370 #define rtsx_pci_resume NULL
1371 #define rtsx_pci_shutdown NULL
1373 #endif /* CONFIG_PM */
1375 static struct pci_driver rtsx_pci_driver
= {
1376 .name
= DRV_NAME_RTSX_PCI
,
1377 .id_table
= rtsx_pci_ids
,
1378 .probe
= rtsx_pci_probe
,
1379 .remove
= rtsx_pci_remove
,
1380 .suspend
= rtsx_pci_suspend
,
1381 .resume
= rtsx_pci_resume
,
1382 .shutdown
= rtsx_pci_shutdown
,
1384 module_pci_driver(rtsx_pci_driver
);
1386 MODULE_LICENSE("GPL");
1387 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1388 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");