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mfd: stmpe: Rework registers access
[deliverable/linux.git] / drivers / mfd / stmpe.c
1 /*
2 * ST Microelectronics MFD: stmpe's driver
3 *
4 * Copyright (C) ST-Ericsson SA 2010
5 *
6 * License Terms: GNU General Public License, version 2
7 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
8 */
9
10 #include <linux/err.h>
11 #include <linux/gpio.h>
12 #include <linux/export.h>
13 #include <linux/kernel.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/of.h>
18 #include <linux/of_gpio.h>
19 #include <linux/pm.h>
20 #include <linux/slab.h>
21 #include <linux/mfd/core.h>
22 #include <linux/delay.h>
23 #include <linux/regulator/consumer.h>
24 #include "stmpe.h"
25
26 /**
27 * struct stmpe_platform_data - STMPE platform data
28 * @id: device id to distinguish between multiple STMPEs on the same board
29 * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
30 * @irq_trigger: IRQ trigger to use for the interrupt to the host
31 * @autosleep: bool to enable/disable stmpe autosleep
32 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep
33 * @irq_over_gpio: true if gpio is used to get irq
34 * @irq_gpio: gpio number over which irq will be requested (significant only if
35 * irq_over_gpio is true)
36 */
37 struct stmpe_platform_data {
38 int id;
39 unsigned int blocks;
40 unsigned int irq_trigger;
41 bool autosleep;
42 bool irq_over_gpio;
43 int irq_gpio;
44 int autosleep_timeout;
45 };
46
47 static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
48 {
49 return stmpe->variant->enable(stmpe, blocks, true);
50 }
51
52 static int __stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
53 {
54 return stmpe->variant->enable(stmpe, blocks, false);
55 }
56
57 static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg)
58 {
59 int ret;
60
61 ret = stmpe->ci->read_byte(stmpe, reg);
62 if (ret < 0)
63 dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret);
64
65 dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret);
66
67 return ret;
68 }
69
70 static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
71 {
72 int ret;
73
74 dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val);
75
76 ret = stmpe->ci->write_byte(stmpe, reg, val);
77 if (ret < 0)
78 dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret);
79
80 return ret;
81 }
82
83 static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
84 {
85 int ret;
86
87 ret = __stmpe_reg_read(stmpe, reg);
88 if (ret < 0)
89 return ret;
90
91 ret &= ~mask;
92 ret |= val;
93
94 return __stmpe_reg_write(stmpe, reg, ret);
95 }
96
97 static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length,
98 u8 *values)
99 {
100 int ret;
101
102 ret = stmpe->ci->read_block(stmpe, reg, length, values);
103 if (ret < 0)
104 dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret);
105
106 dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret);
107 stmpe_dump_bytes("stmpe rd: ", values, length);
108
109 return ret;
110 }
111
112 static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
113 const u8 *values)
114 {
115 int ret;
116
117 dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length);
118 stmpe_dump_bytes("stmpe wr: ", values, length);
119
120 ret = stmpe->ci->write_block(stmpe, reg, length, values);
121 if (ret < 0)
122 dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret);
123
124 return ret;
125 }
126
127 /**
128 * stmpe_enable - enable blocks on an STMPE device
129 * @stmpe: Device to work on
130 * @blocks: Mask of blocks (enum stmpe_block values) to enable
131 */
132 int stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
133 {
134 int ret;
135
136 mutex_lock(&stmpe->lock);
137 ret = __stmpe_enable(stmpe, blocks);
138 mutex_unlock(&stmpe->lock);
139
140 return ret;
141 }
142 EXPORT_SYMBOL_GPL(stmpe_enable);
143
144 /**
145 * stmpe_disable - disable blocks on an STMPE device
146 * @stmpe: Device to work on
147 * @blocks: Mask of blocks (enum stmpe_block values) to enable
148 */
149 int stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
150 {
151 int ret;
152
153 mutex_lock(&stmpe->lock);
154 ret = __stmpe_disable(stmpe, blocks);
155 mutex_unlock(&stmpe->lock);
156
157 return ret;
158 }
159 EXPORT_SYMBOL_GPL(stmpe_disable);
160
161 /**
162 * stmpe_reg_read() - read a single STMPE register
163 * @stmpe: Device to read from
164 * @reg: Register to read
165 */
166 int stmpe_reg_read(struct stmpe *stmpe, u8 reg)
167 {
168 int ret;
169
170 mutex_lock(&stmpe->lock);
171 ret = __stmpe_reg_read(stmpe, reg);
172 mutex_unlock(&stmpe->lock);
173
174 return ret;
175 }
176 EXPORT_SYMBOL_GPL(stmpe_reg_read);
177
178 /**
179 * stmpe_reg_write() - write a single STMPE register
180 * @stmpe: Device to write to
181 * @reg: Register to write
182 * @val: Value to write
183 */
184 int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
185 {
186 int ret;
187
188 mutex_lock(&stmpe->lock);
189 ret = __stmpe_reg_write(stmpe, reg, val);
190 mutex_unlock(&stmpe->lock);
191
192 return ret;
193 }
194 EXPORT_SYMBOL_GPL(stmpe_reg_write);
195
196 /**
197 * stmpe_set_bits() - set the value of a bitfield in a STMPE register
198 * @stmpe: Device to write to
199 * @reg: Register to write
200 * @mask: Mask of bits to set
201 * @val: Value to set
202 */
203 int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
204 {
205 int ret;
206
207 mutex_lock(&stmpe->lock);
208 ret = __stmpe_set_bits(stmpe, reg, mask, val);
209 mutex_unlock(&stmpe->lock);
210
211 return ret;
212 }
213 EXPORT_SYMBOL_GPL(stmpe_set_bits);
214
215 /**
216 * stmpe_block_read() - read multiple STMPE registers
217 * @stmpe: Device to read from
218 * @reg: First register
219 * @length: Number of registers
220 * @values: Buffer to write to
221 */
222 int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values)
223 {
224 int ret;
225
226 mutex_lock(&stmpe->lock);
227 ret = __stmpe_block_read(stmpe, reg, length, values);
228 mutex_unlock(&stmpe->lock);
229
230 return ret;
231 }
232 EXPORT_SYMBOL_GPL(stmpe_block_read);
233
234 /**
235 * stmpe_block_write() - write multiple STMPE registers
236 * @stmpe: Device to write to
237 * @reg: First register
238 * @length: Number of registers
239 * @values: Values to write
240 */
241 int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
242 const u8 *values)
243 {
244 int ret;
245
246 mutex_lock(&stmpe->lock);
247 ret = __stmpe_block_write(stmpe, reg, length, values);
248 mutex_unlock(&stmpe->lock);
249
250 return ret;
251 }
252 EXPORT_SYMBOL_GPL(stmpe_block_write);
253
254 /**
255 * stmpe_set_altfunc()- set the alternate function for STMPE pins
256 * @stmpe: Device to configure
257 * @pins: Bitmask of pins to affect
258 * @block: block to enable alternate functions for
259 *
260 * @pins is assumed to have a bit set for each of the bits whose alternate
261 * function is to be changed, numbered according to the GPIOXY numbers.
262 *
263 * If the GPIO module is not enabled, this function automatically enables it in
264 * order to perform the change.
265 */
266 int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block)
267 {
268 struct stmpe_variant_info *variant = stmpe->variant;
269 u8 regaddr = stmpe->regs[STMPE_IDX_GPAFR_U_MSB];
270 int af_bits = variant->af_bits;
271 int numregs = DIV_ROUND_UP(stmpe->num_gpios * af_bits, 8);
272 int mask = (1 << af_bits) - 1;
273 u8 regs[8];
274 int af, afperreg, ret;
275
276 if (!variant->get_altfunc)
277 return 0;
278
279 afperreg = 8 / af_bits;
280 mutex_lock(&stmpe->lock);
281
282 ret = __stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
283 if (ret < 0)
284 goto out;
285
286 ret = __stmpe_block_read(stmpe, regaddr, numregs, regs);
287 if (ret < 0)
288 goto out;
289
290 af = variant->get_altfunc(stmpe, block);
291
292 while (pins) {
293 int pin = __ffs(pins);
294 int regoffset = numregs - (pin / afperreg) - 1;
295 int pos = (pin % afperreg) * (8 / afperreg);
296
297 regs[regoffset] &= ~(mask << pos);
298 regs[regoffset] |= af << pos;
299
300 pins &= ~(1 << pin);
301 }
302
303 ret = __stmpe_block_write(stmpe, regaddr, numregs, regs);
304
305 out:
306 mutex_unlock(&stmpe->lock);
307 return ret;
308 }
309 EXPORT_SYMBOL_GPL(stmpe_set_altfunc);
310
311 /*
312 * GPIO (all variants)
313 */
314
315 static struct resource stmpe_gpio_resources[] = {
316 /* Start and end filled dynamically */
317 {
318 .flags = IORESOURCE_IRQ,
319 },
320 };
321
322 static const struct mfd_cell stmpe_gpio_cell = {
323 .name = "stmpe-gpio",
324 .of_compatible = "st,stmpe-gpio",
325 .resources = stmpe_gpio_resources,
326 .num_resources = ARRAY_SIZE(stmpe_gpio_resources),
327 };
328
329 static const struct mfd_cell stmpe_gpio_cell_noirq = {
330 .name = "stmpe-gpio",
331 .of_compatible = "st,stmpe-gpio",
332 /* gpio cell resources consist of an irq only so no resources here */
333 };
334
335 /*
336 * Keypad (1601, 2401, 2403)
337 */
338
339 static struct resource stmpe_keypad_resources[] = {
340 {
341 .name = "KEYPAD",
342 .flags = IORESOURCE_IRQ,
343 },
344 {
345 .name = "KEYPAD_OVER",
346 .flags = IORESOURCE_IRQ,
347 },
348 };
349
350 static const struct mfd_cell stmpe_keypad_cell = {
351 .name = "stmpe-keypad",
352 .of_compatible = "st,stmpe-keypad",
353 .resources = stmpe_keypad_resources,
354 .num_resources = ARRAY_SIZE(stmpe_keypad_resources),
355 };
356
357 /*
358 * PWM (1601, 2401, 2403)
359 */
360 static struct resource stmpe_pwm_resources[] = {
361 {
362 .name = "PWM0",
363 .flags = IORESOURCE_IRQ,
364 },
365 {
366 .name = "PWM1",
367 .flags = IORESOURCE_IRQ,
368 },
369 {
370 .name = "PWM2",
371 .flags = IORESOURCE_IRQ,
372 },
373 };
374
375 static const struct mfd_cell stmpe_pwm_cell = {
376 .name = "stmpe-pwm",
377 .of_compatible = "st,stmpe-pwm",
378 .resources = stmpe_pwm_resources,
379 .num_resources = ARRAY_SIZE(stmpe_pwm_resources),
380 };
381
382 /*
383 * STMPE801
384 */
385 static const u8 stmpe801_regs[] = {
386 [STMPE_IDX_CHIP_ID] = STMPE801_REG_CHIP_ID,
387 [STMPE_IDX_ICR_LSB] = STMPE801_REG_SYS_CTRL,
388 [STMPE_IDX_GPMR_LSB] = STMPE801_REG_GPIO_MP_STA,
389 [STMPE_IDX_GPSR_LSB] = STMPE801_REG_GPIO_SET_PIN,
390 [STMPE_IDX_GPCR_LSB] = STMPE801_REG_GPIO_SET_PIN,
391 [STMPE_IDX_GPDR_LSB] = STMPE801_REG_GPIO_DIR,
392 [STMPE_IDX_IEGPIOR_LSB] = STMPE801_REG_GPIO_INT_EN,
393 [STMPE_IDX_ISGPIOR_MSB] = STMPE801_REG_GPIO_INT_STA,
394
395 };
396
397 static struct stmpe_variant_block stmpe801_blocks[] = {
398 {
399 .cell = &stmpe_gpio_cell,
400 .irq = 0,
401 .block = STMPE_BLOCK_GPIO,
402 },
403 };
404
405 static struct stmpe_variant_block stmpe801_blocks_noirq[] = {
406 {
407 .cell = &stmpe_gpio_cell_noirq,
408 .block = STMPE_BLOCK_GPIO,
409 },
410 };
411
412 static int stmpe801_enable(struct stmpe *stmpe, unsigned int blocks,
413 bool enable)
414 {
415 if (blocks & STMPE_BLOCK_GPIO)
416 return 0;
417 else
418 return -EINVAL;
419 }
420
421 static struct stmpe_variant_info stmpe801 = {
422 .name = "stmpe801",
423 .id_val = STMPE801_ID,
424 .id_mask = 0xffff,
425 .num_gpios = 8,
426 .regs = stmpe801_regs,
427 .blocks = stmpe801_blocks,
428 .num_blocks = ARRAY_SIZE(stmpe801_blocks),
429 .num_irqs = STMPE801_NR_INTERNAL_IRQS,
430 .enable = stmpe801_enable,
431 };
432
433 static struct stmpe_variant_info stmpe801_noirq = {
434 .name = "stmpe801",
435 .id_val = STMPE801_ID,
436 .id_mask = 0xffff,
437 .num_gpios = 8,
438 .regs = stmpe801_regs,
439 .blocks = stmpe801_blocks_noirq,
440 .num_blocks = ARRAY_SIZE(stmpe801_blocks_noirq),
441 .enable = stmpe801_enable,
442 };
443
444 /*
445 * Touchscreen (STMPE811 or STMPE610)
446 */
447
448 static struct resource stmpe_ts_resources[] = {
449 {
450 .name = "TOUCH_DET",
451 .flags = IORESOURCE_IRQ,
452 },
453 {
454 .name = "FIFO_TH",
455 .flags = IORESOURCE_IRQ,
456 },
457 };
458
459 static const struct mfd_cell stmpe_ts_cell = {
460 .name = "stmpe-ts",
461 .of_compatible = "st,stmpe-ts",
462 .resources = stmpe_ts_resources,
463 .num_resources = ARRAY_SIZE(stmpe_ts_resources),
464 };
465
466 /*
467 * STMPE811 or STMPE610
468 */
469
470 static const u8 stmpe811_regs[] = {
471 [STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID,
472 [STMPE_IDX_SYS_CTRL] = STMPE811_REG_SYS_CTRL,
473 [STMPE_IDX_SYS_CTRL2] = STMPE811_REG_SYS_CTRL2,
474 [STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL,
475 [STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN,
476 [STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA,
477 [STMPE_IDX_GPMR_LSB] = STMPE811_REG_GPIO_MP_STA,
478 [STMPE_IDX_GPSR_LSB] = STMPE811_REG_GPIO_SET_PIN,
479 [STMPE_IDX_GPCR_LSB] = STMPE811_REG_GPIO_CLR_PIN,
480 [STMPE_IDX_GPDR_LSB] = STMPE811_REG_GPIO_DIR,
481 [STMPE_IDX_GPRER_LSB] = STMPE811_REG_GPIO_RE,
482 [STMPE_IDX_GPFER_LSB] = STMPE811_REG_GPIO_FE,
483 [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF,
484 [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN,
485 [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA,
486 [STMPE_IDX_GPEDR_LSB] = STMPE811_REG_GPIO_ED,
487 };
488
489 static struct stmpe_variant_block stmpe811_blocks[] = {
490 {
491 .cell = &stmpe_gpio_cell,
492 .irq = STMPE811_IRQ_GPIOC,
493 .block = STMPE_BLOCK_GPIO,
494 },
495 {
496 .cell = &stmpe_ts_cell,
497 .irq = STMPE811_IRQ_TOUCH_DET,
498 .block = STMPE_BLOCK_TOUCHSCREEN,
499 },
500 };
501
502 static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks,
503 bool enable)
504 {
505 unsigned int mask = 0;
506
507 if (blocks & STMPE_BLOCK_GPIO)
508 mask |= STMPE811_SYS_CTRL2_GPIO_OFF;
509
510 if (blocks & STMPE_BLOCK_ADC)
511 mask |= STMPE811_SYS_CTRL2_ADC_OFF;
512
513 if (blocks & STMPE_BLOCK_TOUCHSCREEN)
514 mask |= STMPE811_SYS_CTRL2_TSC_OFF;
515
516 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask,
517 enable ? 0 : mask);
518 }
519
520 static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
521 {
522 /* 0 for touchscreen, 1 for GPIO */
523 return block != STMPE_BLOCK_TOUCHSCREEN;
524 }
525
526 static struct stmpe_variant_info stmpe811 = {
527 .name = "stmpe811",
528 .id_val = 0x0811,
529 .id_mask = 0xffff,
530 .num_gpios = 8,
531 .af_bits = 1,
532 .regs = stmpe811_regs,
533 .blocks = stmpe811_blocks,
534 .num_blocks = ARRAY_SIZE(stmpe811_blocks),
535 .num_irqs = STMPE811_NR_INTERNAL_IRQS,
536 .enable = stmpe811_enable,
537 .get_altfunc = stmpe811_get_altfunc,
538 };
539
540 /* Similar to 811, except number of gpios */
541 static struct stmpe_variant_info stmpe610 = {
542 .name = "stmpe610",
543 .id_val = 0x0811,
544 .id_mask = 0xffff,
545 .num_gpios = 6,
546 .af_bits = 1,
547 .regs = stmpe811_regs,
548 .blocks = stmpe811_blocks,
549 .num_blocks = ARRAY_SIZE(stmpe811_blocks),
550 .num_irqs = STMPE811_NR_INTERNAL_IRQS,
551 .enable = stmpe811_enable,
552 .get_altfunc = stmpe811_get_altfunc,
553 };
554
555 /*
556 * STMPE1601
557 */
558
559 static const u8 stmpe1601_regs[] = {
560 [STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID,
561 [STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL,
562 [STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2,
563 [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB,
564 [STMPE_IDX_IER_MSB] = STMPE1601_REG_IER_MSB,
565 [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB,
566 [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB,
567 [STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB,
568 [STMPE_IDX_GPMR_CSB] = STMPE1601_REG_GPIO_MP_MSB,
569 [STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB,
570 [STMPE_IDX_GPSR_CSB] = STMPE1601_REG_GPIO_SET_MSB,
571 [STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB,
572 [STMPE_IDX_GPCR_CSB] = STMPE1601_REG_GPIO_CLR_MSB,
573 [STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB,
574 [STMPE_IDX_GPDR_CSB] = STMPE1601_REG_GPIO_SET_DIR_MSB,
575 [STMPE_IDX_GPEDR_LSB] = STMPE1601_REG_GPIO_ED_LSB,
576 [STMPE_IDX_GPEDR_CSB] = STMPE1601_REG_GPIO_ED_MSB,
577 [STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB,
578 [STMPE_IDX_GPRER_CSB] = STMPE1601_REG_GPIO_RE_MSB,
579 [STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB,
580 [STMPE_IDX_GPFER_CSB] = STMPE1601_REG_GPIO_FE_MSB,
581 [STMPE_IDX_GPPUR_LSB] = STMPE1601_REG_GPIO_PU_LSB,
582 [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB,
583 [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB,
584 [STMPE_IDX_IEGPIOR_CSB] = STMPE1601_REG_INT_EN_GPIO_MASK_MSB,
585 [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB,
586 };
587
588 static struct stmpe_variant_block stmpe1601_blocks[] = {
589 {
590 .cell = &stmpe_gpio_cell,
591 .irq = STMPE1601_IRQ_GPIOC,
592 .block = STMPE_BLOCK_GPIO,
593 },
594 {
595 .cell = &stmpe_keypad_cell,
596 .irq = STMPE1601_IRQ_KEYPAD,
597 .block = STMPE_BLOCK_KEYPAD,
598 },
599 {
600 .cell = &stmpe_pwm_cell,
601 .irq = STMPE1601_IRQ_PWM0,
602 .block = STMPE_BLOCK_PWM,
603 },
604 };
605
606 /* supported autosleep timeout delay (in msecs) */
607 static const int stmpe_autosleep_delay[] = {
608 4, 16, 32, 64, 128, 256, 512, 1024,
609 };
610
611 static int stmpe_round_timeout(int timeout)
612 {
613 int i;
614
615 for (i = 0; i < ARRAY_SIZE(stmpe_autosleep_delay); i++) {
616 if (stmpe_autosleep_delay[i] >= timeout)
617 return i;
618 }
619
620 /*
621 * requests for delays longer than supported should not return the
622 * longest supported delay
623 */
624 return -EINVAL;
625 }
626
627 static int stmpe_autosleep(struct stmpe *stmpe, int autosleep_timeout)
628 {
629 int ret;
630
631 if (!stmpe->variant->enable_autosleep)
632 return -ENOSYS;
633
634 mutex_lock(&stmpe->lock);
635 ret = stmpe->variant->enable_autosleep(stmpe, autosleep_timeout);
636 mutex_unlock(&stmpe->lock);
637
638 return ret;
639 }
640
641 /*
642 * Both stmpe 1601/2403 support same layout for autosleep
643 */
644 static int stmpe1601_autosleep(struct stmpe *stmpe,
645 int autosleep_timeout)
646 {
647 int ret, timeout;
648
649 /* choose the best available timeout */
650 timeout = stmpe_round_timeout(autosleep_timeout);
651 if (timeout < 0) {
652 dev_err(stmpe->dev, "invalid timeout\n");
653 return timeout;
654 }
655
656 ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
657 STMPE1601_AUTOSLEEP_TIMEOUT_MASK,
658 timeout);
659 if (ret < 0)
660 return ret;
661
662 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
663 STPME1601_AUTOSLEEP_ENABLE,
664 STPME1601_AUTOSLEEP_ENABLE);
665 }
666
667 static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks,
668 bool enable)
669 {
670 unsigned int mask = 0;
671
672 if (blocks & STMPE_BLOCK_GPIO)
673 mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO;
674 else
675 mask &= ~STMPE1601_SYS_CTRL_ENABLE_GPIO;
676
677 if (blocks & STMPE_BLOCK_KEYPAD)
678 mask |= STMPE1601_SYS_CTRL_ENABLE_KPC;
679 else
680 mask &= ~STMPE1601_SYS_CTRL_ENABLE_KPC;
681
682 if (blocks & STMPE_BLOCK_PWM)
683 mask |= STMPE1601_SYS_CTRL_ENABLE_SPWM;
684 else
685 mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM;
686
687 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
688 enable ? mask : 0);
689 }
690
691 static int stmpe1601_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
692 {
693 switch (block) {
694 case STMPE_BLOCK_PWM:
695 return 2;
696
697 case STMPE_BLOCK_KEYPAD:
698 return 1;
699
700 case STMPE_BLOCK_GPIO:
701 default:
702 return 0;
703 }
704 }
705
706 static struct stmpe_variant_info stmpe1601 = {
707 .name = "stmpe1601",
708 .id_val = 0x0210,
709 .id_mask = 0xfff0, /* at least 0x0210 and 0x0212 */
710 .num_gpios = 16,
711 .af_bits = 2,
712 .regs = stmpe1601_regs,
713 .blocks = stmpe1601_blocks,
714 .num_blocks = ARRAY_SIZE(stmpe1601_blocks),
715 .num_irqs = STMPE1601_NR_INTERNAL_IRQS,
716 .enable = stmpe1601_enable,
717 .get_altfunc = stmpe1601_get_altfunc,
718 .enable_autosleep = stmpe1601_autosleep,
719 };
720
721 /*
722 * STMPE1801
723 */
724 static const u8 stmpe1801_regs[] = {
725 [STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID,
726 [STMPE_IDX_SYS_CTRL] = STMPE1801_REG_SYS_CTRL,
727 [STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW,
728 [STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW,
729 [STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW,
730 [STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW,
731 [STMPE_IDX_GPMR_CSB] = STMPE1801_REG_GPIO_MP_MID,
732 [STMPE_IDX_GPMR_MSB] = STMPE1801_REG_GPIO_MP_HIGH,
733 [STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW,
734 [STMPE_IDX_GPSR_CSB] = STMPE1801_REG_GPIO_SET_MID,
735 [STMPE_IDX_GPSR_MSB] = STMPE1801_REG_GPIO_SET_HIGH,
736 [STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW,
737 [STMPE_IDX_GPCR_CSB] = STMPE1801_REG_GPIO_CLR_MID,
738 [STMPE_IDX_GPCR_MSB] = STMPE1801_REG_GPIO_CLR_HIGH,
739 [STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW,
740 [STMPE_IDX_GPDR_CSB] = STMPE1801_REG_GPIO_SET_DIR_MID,
741 [STMPE_IDX_GPDR_MSB] = STMPE1801_REG_GPIO_SET_DIR_HIGH,
742 [STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW,
743 [STMPE_IDX_GPRER_CSB] = STMPE1801_REG_GPIO_RE_MID,
744 [STMPE_IDX_GPRER_MSB] = STMPE1801_REG_GPIO_RE_HIGH,
745 [STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW,
746 [STMPE_IDX_GPFER_CSB] = STMPE1801_REG_GPIO_FE_MID,
747 [STMPE_IDX_GPFER_MSB] = STMPE1801_REG_GPIO_FE_HIGH,
748 [STMPE_IDX_GPPUR_LSB] = STMPE1801_REG_GPIO_PULL_UP_LOW,
749 [STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW,
750 [STMPE_IDX_IEGPIOR_CSB] = STMPE1801_REG_INT_EN_GPIO_MASK_MID,
751 [STMPE_IDX_IEGPIOR_MSB] = STMPE1801_REG_INT_EN_GPIO_MASK_HIGH,
752 [STMPE_IDX_ISGPIOR_MSB] = STMPE1801_REG_INT_STA_GPIO_HIGH,
753 };
754
755 static struct stmpe_variant_block stmpe1801_blocks[] = {
756 {
757 .cell = &stmpe_gpio_cell,
758 .irq = STMPE1801_IRQ_GPIOC,
759 .block = STMPE_BLOCK_GPIO,
760 },
761 {
762 .cell = &stmpe_keypad_cell,
763 .irq = STMPE1801_IRQ_KEYPAD,
764 .block = STMPE_BLOCK_KEYPAD,
765 },
766 };
767
768 static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks,
769 bool enable)
770 {
771 unsigned int mask = 0;
772 if (blocks & STMPE_BLOCK_GPIO)
773 mask |= STMPE1801_MSK_INT_EN_GPIO;
774
775 if (blocks & STMPE_BLOCK_KEYPAD)
776 mask |= STMPE1801_MSK_INT_EN_KPC;
777
778 return __stmpe_set_bits(stmpe, STMPE1801_REG_INT_EN_MASK_LOW, mask,
779 enable ? mask : 0);
780 }
781
782 static int stmpe_reset(struct stmpe *stmpe)
783 {
784 u16 id_val = stmpe->variant->id_val;
785 unsigned long timeout;
786 int ret = 0;
787 u8 reset_bit;
788
789 if (id_val == STMPE811_ID)
790 /* STMPE801 and STMPE610 use bit 1 of SYS_CTRL register */
791 reset_bit = STMPE811_SYS_CTRL_RESET;
792 else
793 /* all other STMPE variant use bit 7 of SYS_CTRL register */
794 reset_bit = STMPE_SYS_CTRL_RESET;
795
796 ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL],
797 reset_bit, reset_bit);
798 if (ret < 0)
799 return ret;
800
801 timeout = jiffies + msecs_to_jiffies(100);
802 while (time_before(jiffies, timeout)) {
803 ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]);
804 if (ret < 0)
805 return ret;
806 if (!(ret & reset_bit))
807 return 0;
808 usleep_range(100, 200);
809 }
810 return -EIO;
811 }
812
813 static struct stmpe_variant_info stmpe1801 = {
814 .name = "stmpe1801",
815 .id_val = STMPE1801_ID,
816 .id_mask = 0xfff0,
817 .num_gpios = 18,
818 .af_bits = 0,
819 .regs = stmpe1801_regs,
820 .blocks = stmpe1801_blocks,
821 .num_blocks = ARRAY_SIZE(stmpe1801_blocks),
822 .num_irqs = STMPE1801_NR_INTERNAL_IRQS,
823 .enable = stmpe1801_enable,
824 /* stmpe1801 do not have any gpio alternate function */
825 .get_altfunc = NULL,
826 };
827
828 /*
829 * STMPE24XX
830 */
831
832 static const u8 stmpe24xx_regs[] = {
833 [STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID,
834 [STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL,
835 [STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2,
836 [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB,
837 [STMPE_IDX_IER_MSB] = STMPE24XX_REG_IER_MSB,
838 [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB,
839 [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB,
840 [STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB,
841 [STMPE_IDX_GPMR_CSB] = STMPE24XX_REG_GPMR_CSB,
842 [STMPE_IDX_GPMR_MSB] = STMPE24XX_REG_GPMR_MSB,
843 [STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB,
844 [STMPE_IDX_GPSR_CSB] = STMPE24XX_REG_GPSR_CSB,
845 [STMPE_IDX_GPSR_MSB] = STMPE24XX_REG_GPSR_MSB,
846 [STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB,
847 [STMPE_IDX_GPCR_CSB] = STMPE24XX_REG_GPCR_CSB,
848 [STMPE_IDX_GPCR_MSB] = STMPE24XX_REG_GPCR_MSB,
849 [STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB,
850 [STMPE_IDX_GPDR_CSB] = STMPE24XX_REG_GPDR_CSB,
851 [STMPE_IDX_GPDR_MSB] = STMPE24XX_REG_GPDR_MSB,
852 [STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB,
853 [STMPE_IDX_GPRER_CSB] = STMPE24XX_REG_GPRER_CSB,
854 [STMPE_IDX_GPRER_MSB] = STMPE24XX_REG_GPRER_MSB,
855 [STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB,
856 [STMPE_IDX_GPFER_CSB] = STMPE24XX_REG_GPFER_CSB,
857 [STMPE_IDX_GPFER_MSB] = STMPE24XX_REG_GPFER_MSB,
858 [STMPE_IDX_GPPUR_LSB] = STMPE24XX_REG_GPPUR_LSB,
859 [STMPE_IDX_GPPDR_LSB] = STMPE24XX_REG_GPPDR_LSB,
860 [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB,
861 [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB,
862 [STMPE_IDX_IEGPIOR_CSB] = STMPE24XX_REG_IEGPIOR_CSB,
863 [STMPE_IDX_IEGPIOR_MSB] = STMPE24XX_REG_IEGPIOR_MSB,
864 [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB,
865 [STMPE_IDX_GPEDR_LSB] = STMPE24XX_REG_GPEDR_LSB,
866 [STMPE_IDX_GPEDR_CSB] = STMPE24XX_REG_GPEDR_CSB,
867 [STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB,
868 };
869
870 static struct stmpe_variant_block stmpe24xx_blocks[] = {
871 {
872 .cell = &stmpe_gpio_cell,
873 .irq = STMPE24XX_IRQ_GPIOC,
874 .block = STMPE_BLOCK_GPIO,
875 },
876 {
877 .cell = &stmpe_keypad_cell,
878 .irq = STMPE24XX_IRQ_KEYPAD,
879 .block = STMPE_BLOCK_KEYPAD,
880 },
881 {
882 .cell = &stmpe_pwm_cell,
883 .irq = STMPE24XX_IRQ_PWM0,
884 .block = STMPE_BLOCK_PWM,
885 },
886 };
887
888 static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks,
889 bool enable)
890 {
891 unsigned int mask = 0;
892
893 if (blocks & STMPE_BLOCK_GPIO)
894 mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO;
895
896 if (blocks & STMPE_BLOCK_KEYPAD)
897 mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC;
898
899 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
900 enable ? mask : 0);
901 }
902
903 static int stmpe24xx_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
904 {
905 switch (block) {
906 case STMPE_BLOCK_ROTATOR:
907 return 2;
908
909 case STMPE_BLOCK_KEYPAD:
910 case STMPE_BLOCK_PWM:
911 return 1;
912
913 case STMPE_BLOCK_GPIO:
914 default:
915 return 0;
916 }
917 }
918
919 static struct stmpe_variant_info stmpe2401 = {
920 .name = "stmpe2401",
921 .id_val = 0x0101,
922 .id_mask = 0xffff,
923 .num_gpios = 24,
924 .af_bits = 2,
925 .regs = stmpe24xx_regs,
926 .blocks = stmpe24xx_blocks,
927 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks),
928 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS,
929 .enable = stmpe24xx_enable,
930 .get_altfunc = stmpe24xx_get_altfunc,
931 };
932
933 static struct stmpe_variant_info stmpe2403 = {
934 .name = "stmpe2403",
935 .id_val = 0x0120,
936 .id_mask = 0xffff,
937 .num_gpios = 24,
938 .af_bits = 2,
939 .regs = stmpe24xx_regs,
940 .blocks = stmpe24xx_blocks,
941 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks),
942 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS,
943 .enable = stmpe24xx_enable,
944 .get_altfunc = stmpe24xx_get_altfunc,
945 .enable_autosleep = stmpe1601_autosleep, /* same as stmpe1601 */
946 };
947
948 static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = {
949 [STMPE610] = &stmpe610,
950 [STMPE801] = &stmpe801,
951 [STMPE811] = &stmpe811,
952 [STMPE1601] = &stmpe1601,
953 [STMPE1801] = &stmpe1801,
954 [STMPE2401] = &stmpe2401,
955 [STMPE2403] = &stmpe2403,
956 };
957
958 /*
959 * These devices can be connected in a 'no-irq' configuration - the irq pin
960 * is not used and the device cannot interrupt the CPU. Here we only list
961 * devices which support this configuration - the driver will fail probing
962 * for any devices not listed here which are configured in this way.
963 */
964 static struct stmpe_variant_info *stmpe_noirq_variant_info[STMPE_NBR_PARTS] = {
965 [STMPE801] = &stmpe801_noirq,
966 };
967
968 static irqreturn_t stmpe_irq(int irq, void *data)
969 {
970 struct stmpe *stmpe = data;
971 struct stmpe_variant_info *variant = stmpe->variant;
972 int num = DIV_ROUND_UP(variant->num_irqs, 8);
973 u8 israddr;
974 u8 isr[3];
975 int ret;
976 int i;
977
978 if (variant->id_val == STMPE801_ID) {
979 int base = irq_create_mapping(stmpe->domain, 0);
980
981 handle_nested_irq(base);
982 return IRQ_HANDLED;
983 }
984
985 if (variant->id_val == STMPE1801_ID)
986 israddr = stmpe->regs[STMPE_IDX_ISR_LSB];
987 else
988 israddr = stmpe->regs[STMPE_IDX_ISR_MSB];
989
990 ret = stmpe_block_read(stmpe, israddr, num, isr);
991 if (ret < 0)
992 return IRQ_NONE;
993
994 for (i = 0; i < num; i++) {
995 int bank = num - i - 1;
996 u8 status = isr[i];
997 u8 clear;
998
999 status &= stmpe->ier[bank];
1000 if (!status)
1001 continue;
1002
1003 clear = status;
1004 while (status) {
1005 int bit = __ffs(status);
1006 int line = bank * 8 + bit;
1007 int nestedirq = irq_create_mapping(stmpe->domain, line);
1008
1009 handle_nested_irq(nestedirq);
1010 status &= ~(1 << bit);
1011 }
1012
1013 stmpe_reg_write(stmpe, israddr + i, clear);
1014 }
1015
1016 return IRQ_HANDLED;
1017 }
1018
1019 static void stmpe_irq_lock(struct irq_data *data)
1020 {
1021 struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
1022
1023 mutex_lock(&stmpe->irq_lock);
1024 }
1025
1026 static void stmpe_irq_sync_unlock(struct irq_data *data)
1027 {
1028 struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
1029 struct stmpe_variant_info *variant = stmpe->variant;
1030 int num = DIV_ROUND_UP(variant->num_irqs, 8);
1031 int i;
1032
1033 for (i = 0; i < num; i++) {
1034 u8 new = stmpe->ier[i];
1035 u8 old = stmpe->oldier[i];
1036
1037 if (new == old)
1038 continue;
1039
1040 stmpe->oldier[i] = new;
1041 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB + i], new);
1042 }
1043
1044 mutex_unlock(&stmpe->irq_lock);
1045 }
1046
1047 static void stmpe_irq_mask(struct irq_data *data)
1048 {
1049 struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
1050 int offset = data->hwirq;
1051 int regoffset = offset / 8;
1052 int mask = 1 << (offset % 8);
1053
1054 stmpe->ier[regoffset] &= ~mask;
1055 }
1056
1057 static void stmpe_irq_unmask(struct irq_data *data)
1058 {
1059 struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
1060 int offset = data->hwirq;
1061 int regoffset = offset / 8;
1062 int mask = 1 << (offset % 8);
1063
1064 stmpe->ier[regoffset] |= mask;
1065 }
1066
1067 static struct irq_chip stmpe_irq_chip = {
1068 .name = "stmpe",
1069 .irq_bus_lock = stmpe_irq_lock,
1070 .irq_bus_sync_unlock = stmpe_irq_sync_unlock,
1071 .irq_mask = stmpe_irq_mask,
1072 .irq_unmask = stmpe_irq_unmask,
1073 };
1074
1075 static int stmpe_irq_map(struct irq_domain *d, unsigned int virq,
1076 irq_hw_number_t hwirq)
1077 {
1078 struct stmpe *stmpe = d->host_data;
1079 struct irq_chip *chip = NULL;
1080
1081 if (stmpe->variant->id_val != STMPE801_ID)
1082 chip = &stmpe_irq_chip;
1083
1084 irq_set_chip_data(virq, stmpe);
1085 irq_set_chip_and_handler(virq, chip, handle_edge_irq);
1086 irq_set_nested_thread(virq, 1);
1087 irq_set_noprobe(virq);
1088
1089 return 0;
1090 }
1091
1092 static void stmpe_irq_unmap(struct irq_domain *d, unsigned int virq)
1093 {
1094 irq_set_chip_and_handler(virq, NULL, NULL);
1095 irq_set_chip_data(virq, NULL);
1096 }
1097
1098 static const struct irq_domain_ops stmpe_irq_ops = {
1099 .map = stmpe_irq_map,
1100 .unmap = stmpe_irq_unmap,
1101 .xlate = irq_domain_xlate_twocell,
1102 };
1103
1104 static int stmpe_irq_init(struct stmpe *stmpe, struct device_node *np)
1105 {
1106 int base = 0;
1107 int num_irqs = stmpe->variant->num_irqs;
1108
1109 stmpe->domain = irq_domain_add_simple(np, num_irqs, base,
1110 &stmpe_irq_ops, stmpe);
1111 if (!stmpe->domain) {
1112 dev_err(stmpe->dev, "Failed to create irqdomain\n");
1113 return -ENOSYS;
1114 }
1115
1116 return 0;
1117 }
1118
1119 static int stmpe_chip_init(struct stmpe *stmpe)
1120 {
1121 unsigned int irq_trigger = stmpe->pdata->irq_trigger;
1122 int autosleep_timeout = stmpe->pdata->autosleep_timeout;
1123 struct stmpe_variant_info *variant = stmpe->variant;
1124 u8 icr = 0;
1125 unsigned int id;
1126 u8 data[2];
1127 int ret;
1128
1129 ret = stmpe_block_read(stmpe, stmpe->regs[STMPE_IDX_CHIP_ID],
1130 ARRAY_SIZE(data), data);
1131 if (ret < 0)
1132 return ret;
1133
1134 id = (data[0] << 8) | data[1];
1135 if ((id & variant->id_mask) != variant->id_val) {
1136 dev_err(stmpe->dev, "unknown chip id: %#x\n", id);
1137 return -EINVAL;
1138 }
1139
1140 dev_info(stmpe->dev, "%s detected, chip id: %#x\n", variant->name, id);
1141
1142 /* Disable all modules -- subdrivers should enable what they need. */
1143 ret = stmpe_disable(stmpe, ~0);
1144 if (ret)
1145 return ret;
1146
1147 ret = stmpe_reset(stmpe);
1148 if (ret < 0)
1149 return ret;
1150
1151 if (stmpe->irq >= 0) {
1152 if (id == STMPE801_ID)
1153 icr = STMPE_SYS_CTRL_INT_EN;
1154 else
1155 icr = STMPE_ICR_LSB_GIM;
1156
1157 /* STMPE801 doesn't support Edge interrupts */
1158 if (id != STMPE801_ID) {
1159 if (irq_trigger == IRQF_TRIGGER_FALLING ||
1160 irq_trigger == IRQF_TRIGGER_RISING)
1161 icr |= STMPE_ICR_LSB_EDGE;
1162 }
1163
1164 if (irq_trigger == IRQF_TRIGGER_RISING ||
1165 irq_trigger == IRQF_TRIGGER_HIGH) {
1166 if (id == STMPE801_ID)
1167 icr |= STMPE_SYS_CTRL_INT_HI;
1168 else
1169 icr |= STMPE_ICR_LSB_HIGH;
1170 }
1171 }
1172
1173 if (stmpe->pdata->autosleep) {
1174 ret = stmpe_autosleep(stmpe, autosleep_timeout);
1175 if (ret)
1176 return ret;
1177 }
1178
1179 return stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_ICR_LSB], icr);
1180 }
1181
1182 static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell)
1183 {
1184 return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1,
1185 NULL, 0, stmpe->domain);
1186 }
1187
1188 static int stmpe_devices_init(struct stmpe *stmpe)
1189 {
1190 struct stmpe_variant_info *variant = stmpe->variant;
1191 unsigned int platform_blocks = stmpe->pdata->blocks;
1192 int ret = -EINVAL;
1193 int i, j;
1194
1195 for (i = 0; i < variant->num_blocks; i++) {
1196 struct stmpe_variant_block *block = &variant->blocks[i];
1197
1198 if (!(platform_blocks & block->block))
1199 continue;
1200
1201 for (j = 0; j < block->cell->num_resources; j++) {
1202 struct resource *res =
1203 (struct resource *) &block->cell->resources[j];
1204
1205 /* Dynamically fill in a variant's IRQ. */
1206 if (res->flags & IORESOURCE_IRQ)
1207 res->start = res->end = block->irq + j;
1208 }
1209
1210 platform_blocks &= ~block->block;
1211 ret = stmpe_add_device(stmpe, block->cell);
1212 if (ret)
1213 return ret;
1214 }
1215
1216 if (platform_blocks)
1217 dev_warn(stmpe->dev,
1218 "platform wants blocks (%#x) not present on variant",
1219 platform_blocks);
1220
1221 return ret;
1222 }
1223
1224 static void stmpe_of_probe(struct stmpe_platform_data *pdata,
1225 struct device_node *np)
1226 {
1227 struct device_node *child;
1228
1229 pdata->id = of_alias_get_id(np, "stmpe-i2c");
1230 if (pdata->id < 0)
1231 pdata->id = -1;
1232
1233 pdata->irq_gpio = of_get_named_gpio_flags(np, "irq-gpio", 0,
1234 &pdata->irq_trigger);
1235 if (gpio_is_valid(pdata->irq_gpio))
1236 pdata->irq_over_gpio = 1;
1237 else
1238 pdata->irq_trigger = IRQF_TRIGGER_NONE;
1239
1240 of_property_read_u32(np, "st,autosleep-timeout",
1241 &pdata->autosleep_timeout);
1242
1243 pdata->autosleep = (pdata->autosleep_timeout) ? true : false;
1244
1245 for_each_child_of_node(np, child) {
1246 if (!strcmp(child->name, "stmpe_gpio")) {
1247 pdata->blocks |= STMPE_BLOCK_GPIO;
1248 } else if (!strcmp(child->name, "stmpe_keypad")) {
1249 pdata->blocks |= STMPE_BLOCK_KEYPAD;
1250 } else if (!strcmp(child->name, "stmpe_touchscreen")) {
1251 pdata->blocks |= STMPE_BLOCK_TOUCHSCREEN;
1252 } else if (!strcmp(child->name, "stmpe_adc")) {
1253 pdata->blocks |= STMPE_BLOCK_ADC;
1254 } else if (!strcmp(child->name, "stmpe_pwm")) {
1255 pdata->blocks |= STMPE_BLOCK_PWM;
1256 } else if (!strcmp(child->name, "stmpe_rotator")) {
1257 pdata->blocks |= STMPE_BLOCK_ROTATOR;
1258 }
1259 }
1260 }
1261
1262 /* Called from client specific probe routines */
1263 int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum)
1264 {
1265 struct stmpe_platform_data *pdata;
1266 struct device_node *np = ci->dev->of_node;
1267 struct stmpe *stmpe;
1268 int ret;
1269
1270 pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL);
1271 if (!pdata)
1272 return -ENOMEM;
1273
1274 stmpe_of_probe(pdata, np);
1275
1276 if (of_find_property(np, "interrupts", NULL) == NULL)
1277 ci->irq = -1;
1278
1279 stmpe = devm_kzalloc(ci->dev, sizeof(struct stmpe), GFP_KERNEL);
1280 if (!stmpe)
1281 return -ENOMEM;
1282
1283 mutex_init(&stmpe->irq_lock);
1284 mutex_init(&stmpe->lock);
1285
1286 stmpe->dev = ci->dev;
1287 stmpe->client = ci->client;
1288 stmpe->pdata = pdata;
1289 stmpe->ci = ci;
1290 stmpe->partnum = partnum;
1291 stmpe->variant = stmpe_variant_info[partnum];
1292 stmpe->regs = stmpe->variant->regs;
1293 stmpe->num_gpios = stmpe->variant->num_gpios;
1294 stmpe->vcc = devm_regulator_get_optional(ci->dev, "vcc");
1295 if (!IS_ERR(stmpe->vcc)) {
1296 ret = regulator_enable(stmpe->vcc);
1297 if (ret)
1298 dev_warn(ci->dev, "failed to enable VCC supply\n");
1299 }
1300 stmpe->vio = devm_regulator_get_optional(ci->dev, "vio");
1301 if (!IS_ERR(stmpe->vio)) {
1302 ret = regulator_enable(stmpe->vio);
1303 if (ret)
1304 dev_warn(ci->dev, "failed to enable VIO supply\n");
1305 }
1306 dev_set_drvdata(stmpe->dev, stmpe);
1307
1308 if (ci->init)
1309 ci->init(stmpe);
1310
1311 if (pdata->irq_over_gpio) {
1312 ret = devm_gpio_request_one(ci->dev, pdata->irq_gpio,
1313 GPIOF_DIR_IN, "stmpe");
1314 if (ret) {
1315 dev_err(stmpe->dev, "failed to request IRQ GPIO: %d\n",
1316 ret);
1317 return ret;
1318 }
1319
1320 stmpe->irq = gpio_to_irq(pdata->irq_gpio);
1321 } else {
1322 stmpe->irq = ci->irq;
1323 }
1324
1325 if (stmpe->irq < 0) {
1326 /* use alternate variant info for no-irq mode, if supported */
1327 dev_info(stmpe->dev,
1328 "%s configured in no-irq mode by platform data\n",
1329 stmpe->variant->name);
1330 if (!stmpe_noirq_variant_info[stmpe->partnum]) {
1331 dev_err(stmpe->dev,
1332 "%s does not support no-irq mode!\n",
1333 stmpe->variant->name);
1334 return -ENODEV;
1335 }
1336 stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum];
1337 } else if (pdata->irq_trigger == IRQF_TRIGGER_NONE) {
1338 pdata->irq_trigger = irq_get_trigger_type(stmpe->irq);
1339 }
1340
1341 ret = stmpe_chip_init(stmpe);
1342 if (ret)
1343 return ret;
1344
1345 if (stmpe->irq >= 0) {
1346 ret = stmpe_irq_init(stmpe, np);
1347 if (ret)
1348 return ret;
1349
1350 ret = devm_request_threaded_irq(ci->dev, stmpe->irq, NULL,
1351 stmpe_irq, pdata->irq_trigger | IRQF_ONESHOT,
1352 "stmpe", stmpe);
1353 if (ret) {
1354 dev_err(stmpe->dev, "failed to request IRQ: %d\n",
1355 ret);
1356 return ret;
1357 }
1358 }
1359
1360 ret = stmpe_devices_init(stmpe);
1361 if (!ret)
1362 return 0;
1363
1364 dev_err(stmpe->dev, "failed to add children\n");
1365 mfd_remove_devices(stmpe->dev);
1366
1367 return ret;
1368 }
1369
1370 int stmpe_remove(struct stmpe *stmpe)
1371 {
1372 if (!IS_ERR(stmpe->vio))
1373 regulator_disable(stmpe->vio);
1374 if (!IS_ERR(stmpe->vcc))
1375 regulator_disable(stmpe->vcc);
1376
1377 mfd_remove_devices(stmpe->dev);
1378
1379 return 0;
1380 }
1381
1382 #ifdef CONFIG_PM
1383 static int stmpe_suspend(struct device *dev)
1384 {
1385 struct stmpe *stmpe = dev_get_drvdata(dev);
1386
1387 if (stmpe->irq >= 0 && device_may_wakeup(dev))
1388 enable_irq_wake(stmpe->irq);
1389
1390 return 0;
1391 }
1392
1393 static int stmpe_resume(struct device *dev)
1394 {
1395 struct stmpe *stmpe = dev_get_drvdata(dev);
1396
1397 if (stmpe->irq >= 0 && device_may_wakeup(dev))
1398 disable_irq_wake(stmpe->irq);
1399
1400 return 0;
1401 }
1402
1403 const struct dev_pm_ops stmpe_dev_pm_ops = {
1404 .suspend = stmpe_suspend,
1405 .resume = stmpe_resume,
1406 };
1407 #endif
Linux kernel - Deliverables
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