drivers/misc/mei/hw-txe.c

   1 /*
   2  *
   3  * Intel Management Engine Interface (Intel MEI) Linux driver
   4  * Copyright (c) 2013-2014, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13  * more details.
  14  *
  15  */
  16
  17 #include <linux/pci.h>
  18 #include <linux/jiffies.h>
  19 #include <linux/ktime.h>
  20 #include <linux/delay.h>
  21 #include <linux/kthread.h>
  22 #include <linux/irqreturn.h>
  23
  24 #include <linux/mei.h>
  25
  26 #include "mei_dev.h"
  27 #include "hw-txe.h"
  28 #include "client.h"
  29 #include "hbm.h"
  30
  31 /**
  32  * mei_txe_reg_read - Reads 32bit data from the txe device
  33  *
  34  * @base_addr: registers base address
  35  * @offset: register offset
  36  *
  37  * Return: register value
  38  */
  39 static inline u32 mei_txe_reg_read(void __iomem *base_addr,
  40                                         unsigned long offset)
  41 {
  42         return ioread32(base_addr + offset);
  43 }
  44
  45 /**
  46  * mei_txe_reg_write - Writes 32bit data to the txe device
  47  *
  48  * @base_addr: registers base address
  49  * @offset: register offset
  50  * @value: the value to write
  51  */
  52 static inline void mei_txe_reg_write(void __iomem *base_addr,
  53                                 unsigned long offset, u32 value)
  54 {
  55         iowrite32(value, base_addr + offset);
  56 }
  57
  58 /**
  59  * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR
  60  *
  61  * @hw: the txe hardware structure
  62  * @offset: register offset
  63  *
  64  * Doesn't check for aliveness while Reads 32bit data from the SeC BAR
  65  *
  66  * Return: register value
  67  */
  68 static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw,
  69                                 unsigned long offset)
  70 {
  71         return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset);
  72 }
  73
  74 /**
  75  * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR
  76  *
  77  * @hw: the txe hardware structure
  78  * @offset: register offset
  79  *
  80  * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set
  81  *
  82  * Return: register value
  83  */
  84 static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw,
  85                                 unsigned long offset)
  86 {
  87         WARN(!hw->aliveness, "sec read: aliveness not asserted\n");
  88         return mei_txe_sec_reg_read_silent(hw, offset);
  89 }
  90 /**
  91  * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR
  92  *   doesn't check for aliveness
  93  *
  94  * @hw: the txe hardware structure
  95  * @offset: register offset
  96  * @value: value to write
  97  *
  98  * Doesn't check for aliveness while writes 32bit data from to the SeC BAR
  99  */
 100 static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw,
 101                                 unsigned long offset, u32 value)
 102 {
 103         mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value);
 104 }
 105
 106 /**
 107  * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR
 108  *
 109  * @hw: the txe hardware structure
 110  * @offset: register offset
 111  * @value: value to write
 112  *
 113  * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set
 114  */
 115 static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw,
 116                                 unsigned long offset, u32 value)
 117 {
 118         WARN(!hw->aliveness, "sec write: aliveness not asserted\n");
 119         mei_txe_sec_reg_write_silent(hw, offset, value);
 120 }
 121 /**
 122  * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR
 123  *
 124  * @hw: the txe hardware structure
 125  * @offset: offset from which to read the data
 126  *
 127  * Return: the byte read.
 128  */
 129 static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw,
 130                                 unsigned long offset)
 131 {
 132         return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset);
 133 }
 134
 135 /**
 136  * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR
 137  *
 138  * @hw: the txe hardware structure
 139  * @offset: offset from which to write the data
 140  * @value: the byte to write
 141  */
 142 static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw,
 143                                 unsigned long offset, u32 value)
 144 {
 145         mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value);
 146 }
 147
 148 /**
 149  * mei_txe_aliveness_set - request for aliveness change
 150  *
 151  * @dev: the device structure
 152  * @req: requested aliveness value
 153  *
 154  * Request for aliveness change and returns true if the change is
 155  *   really needed and false if aliveness is already
 156  *   in the requested state
 157  *
 158  * Locking: called under "dev->device_lock" lock
 159  *
 160  * Return: true if request was send
 161  */
 162 static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req)
 163 {
 164
 165         struct mei_txe_hw *hw = to_txe_hw(dev);
 166         bool do_req = hw->aliveness != req;
 167
 168         dev_dbg(dev->dev, "Aliveness current=%d request=%d\n",
 169                                 hw->aliveness, req);
 170         if (do_req) {
 171                 dev->pg_event = MEI_PG_EVENT_WAIT;
 172                 mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req);
 173         }
 174         return do_req;
 175 }
 176
 177
 178 /**
 179  * mei_txe_aliveness_req_get - get aliveness requested register value
 180  *
 181  * @dev: the device structure
 182  *
 183  * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from
 184  * from HICR_HOST_ALIVENESS_REQ register value
 185  *
 186  * Return: SICR_HOST_ALIVENESS_REQ_REQUESTED bit value
 187  */
 188 static u32 mei_txe_aliveness_req_get(struct mei_device *dev)
 189 {
 190         struct mei_txe_hw *hw = to_txe_hw(dev);
 191         u32 reg;
 192
 193         reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG);
 194         return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED;
 195 }
 196
 197 /**
 198  * mei_txe_aliveness_get - get aliveness response register value
 199  *
 200  * @dev: the device structure
 201  *
 202  * Return: HICR_HOST_ALIVENESS_RESP_ACK bit from HICR_HOST_ALIVENESS_RESP
 203  *         register
 204  */
 205 static u32 mei_txe_aliveness_get(struct mei_device *dev)
 206 {
 207         struct mei_txe_hw *hw = to_txe_hw(dev);
 208         u32 reg;
 209
 210         reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG);
 211         return reg & HICR_HOST_ALIVENESS_RESP_ACK;
 212 }
 213
 214 /**
 215  * mei_txe_aliveness_poll - waits for aliveness to settle
 216  *
 217  * @dev: the device structure
 218  * @expected: expected aliveness value
 219  *
 220  * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
 221  *
 222  * Return: 0 if the expected value was received, -ETIME otherwise
 223  */
 224 static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected)
 225 {
 226         struct mei_txe_hw *hw = to_txe_hw(dev);
 227         ktime_t stop, start;
 228
 229         start = ktime_get();
 230         stop = ktime_add(start, ms_to_ktime(SEC_ALIVENESS_WAIT_TIMEOUT));
 231         do {
 232                 hw->aliveness = mei_txe_aliveness_get(dev);
 233                 if (hw->aliveness == expected) {
 234                         dev->pg_event = MEI_PG_EVENT_IDLE;
 235                         dev_dbg(dev->dev, "aliveness settled after %lld usecs\n",
 236                                 ktime_to_us(ktime_sub(ktime_get(), start)));
 237                         return 0;
 238                 }
 239                 usleep_range(20, 50);
 240         } while (ktime_before(ktime_get(), stop));
 241
 242         dev->pg_event = MEI_PG_EVENT_IDLE;
 243         dev_err(dev->dev, "aliveness timed out\n");
 244         return -ETIME;
 245 }
 246
 247 /**
 248  * mei_txe_aliveness_wait - waits for aliveness to settle
 249  *
 250  * @dev: the device structure
 251  * @expected: expected aliveness value
 252  *
 253  * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
 254  *
 255  * Return: 0 on success and < 0 otherwise
 256  */
 257 static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected)
 258 {
 259         struct mei_txe_hw *hw = to_txe_hw(dev);
 260         const unsigned long timeout =
 261                         msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT);
 262         long err;
 263         int ret;
 264
 265         hw->aliveness = mei_txe_aliveness_get(dev);
 266         if (hw->aliveness == expected)
 267                 return 0;
 268
 269         mutex_unlock(&dev->device_lock);
 270         err = wait_event_timeout(hw->wait_aliveness_resp,
 271                         dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
 272         mutex_lock(&dev->device_lock);
 273
 274         hw->aliveness = mei_txe_aliveness_get(dev);
 275         ret = hw->aliveness == expected ? 0 : -ETIME;
 276
 277         if (ret)
 278                 dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n",
 279                         err, hw->aliveness, dev->pg_event);
 280         else
 281                 dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n",
 282                         jiffies_to_msecs(timeout - err),
 283                         hw->aliveness, dev->pg_event);
 284
 285         dev->pg_event = MEI_PG_EVENT_IDLE;
 286         return ret;
 287 }
 288
 289 /**
 290  * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete
 291  *
 292  * @dev: the device structure
 293  * @req: requested aliveness value
 294  *
 295  * Return: 0 on success and < 0 otherwise
 296  */
 297 int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req)
 298 {
 299         if (mei_txe_aliveness_set(dev, req))
 300                 return mei_txe_aliveness_wait(dev, req);
 301         return 0;
 302 }
 303
 304 /**
 305  * mei_txe_pg_in_transition - is device now in pg transition
 306  *
 307  * @dev: the device structure
 308  *
 309  * Return: true if in pg transition, false otherwise
 310  */
 311 static bool mei_txe_pg_in_transition(struct mei_device *dev)
 312 {
 313         return dev->pg_event == MEI_PG_EVENT_WAIT;
 314 }
 315
 316 /**
 317  * mei_txe_pg_is_enabled - detect if PG is supported by HW
 318  *
 319  * @dev: the device structure
 320  *
 321  * Return: true is pg supported, false otherwise
 322  */
 323 static bool mei_txe_pg_is_enabled(struct mei_device *dev)
 324 {
 325         return true;
 326 }
 327
 328 /**
 329  * mei_txe_pg_state  - translate aliveness register value
 330  *   to the mei power gating state
 331  *
 332  * @dev: the device structure
 333  *
 334  * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
 335  */
 336 static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev)
 337 {
 338         struct mei_txe_hw *hw = to_txe_hw(dev);
 339
 340         return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON;
 341 }
 342
 343 /**
 344  * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt
 345  *
 346  * @dev: the device structure
 347  */
 348 static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev)
 349 {
 350         struct mei_txe_hw *hw = to_txe_hw(dev);
 351         u32 hintmsk;
 352         /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */
 353         hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG);
 354         hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY;
 355         mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk);
 356 }
 357
 358 /**
 359  * mei_txe_input_doorbell_set - sets bit 0 in
 360  *    SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL.
 361  *
 362  * @hw: the txe hardware structure
 363  */
 364 static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw)
 365 {
 366         /* Clear the interrupt cause */
 367         clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause);
 368         mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1);
 369 }
 370
 371 /**
 372  * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1
 373  *
 374  * @hw: the txe hardware structure
 375  */
 376 static void mei_txe_output_ready_set(struct mei_txe_hw *hw)
 377 {
 378         mei_txe_br_reg_write(hw,
 379                         SICR_SEC_IPC_OUTPUT_STATUS_REG,
 380                         SEC_IPC_OUTPUT_STATUS_RDY);
 381 }
 382
 383 /**
 384  * mei_txe_is_input_ready - check if TXE is ready for receiving data
 385  *
 386  * @dev: the device structure
 387  *
 388  * Return: true if INPUT STATUS READY bit is set
 389  */
 390 static bool mei_txe_is_input_ready(struct mei_device *dev)
 391 {
 392         struct mei_txe_hw *hw = to_txe_hw(dev);
 393         u32 status;
 394
 395         status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG);
 396         return !!(SEC_IPC_INPUT_STATUS_RDY & status);
 397 }
 398
 399 /**
 400  * mei_txe_intr_clear - clear all interrupts
 401  *
 402  * @dev: the device structure
 403  */
 404 static inline void mei_txe_intr_clear(struct mei_device *dev)
 405 {
 406         struct mei_txe_hw *hw = to_txe_hw(dev);
 407
 408         mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG,
 409                 SEC_IPC_HOST_INT_STATUS_PENDING);
 410         mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK);
 411         mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK);
 412 }
 413
 414 /**
 415  * mei_txe_intr_disable - disable all interrupts
 416  *
 417  * @dev: the device structure
 418  */
 419 static void mei_txe_intr_disable(struct mei_device *dev)
 420 {
 421         struct mei_txe_hw *hw = to_txe_hw(dev);
 422
 423         mei_txe_br_reg_write(hw, HHIER_REG, 0);
 424         mei_txe_br_reg_write(hw, HIER_REG, 0);
 425 }
 426 /**
 427  * mei_txe_intr_enable - enable all interrupts
 428  *
 429  * @dev: the device structure
 430  */
 431 static void mei_txe_intr_enable(struct mei_device *dev)
 432 {
 433         struct mei_txe_hw *hw = to_txe_hw(dev);
 434
 435         mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK);
 436         mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK);
 437 }
 438
 439 /**
 440  * mei_txe_pending_interrupts - check if there are pending interrupts
 441  *      only Aliveness, Input ready, and output doorbell are of relevance
 442  *
 443  * @dev: the device structure
 444  *
 445  * Checks if there are pending interrupts
 446  * only Aliveness, Readiness, Input ready, and Output doorbell are relevant
 447  *
 448  * Return: true if there are pending interrupts
 449  */
 450 static bool mei_txe_pending_interrupts(struct mei_device *dev)
 451 {
 452
 453         struct mei_txe_hw *hw = to_txe_hw(dev);
 454         bool ret = (hw->intr_cause & (TXE_INTR_READINESS |
 455                                       TXE_INTR_ALIVENESS |
 456                                       TXE_INTR_IN_READY  |
 457                                       TXE_INTR_OUT_DB));
 458
 459         if (ret) {
 460                 dev_dbg(dev->dev,
 461                         "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n",
 462                         !!(hw->intr_cause & TXE_INTR_IN_READY),
 463                         !!(hw->intr_cause & TXE_INTR_READINESS),
 464                         !!(hw->intr_cause & TXE_INTR_ALIVENESS),
 465                         !!(hw->intr_cause & TXE_INTR_OUT_DB));
 466         }
 467         return ret;
 468 }
 469
 470 /**
 471  * mei_txe_input_payload_write - write a dword to the host buffer
 472  *      at offset idx
 473  *
 474  * @dev: the device structure
 475  * @idx: index in the host buffer
 476  * @value: value
 477  */
 478 static void mei_txe_input_payload_write(struct mei_device *dev,
 479                         unsigned long idx, u32 value)
 480 {
 481         struct mei_txe_hw *hw = to_txe_hw(dev);
 482
 483         mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG +
 484                         (idx * sizeof(u32)), value);
 485 }
 486
 487 /**
 488  * mei_txe_out_data_read - read dword from the device buffer
 489  *      at offset idx
 490  *
 491  * @dev: the device structure
 492  * @idx: index in the device buffer
 493  *
 494  * Return: register value at index
 495  */
 496 static u32 mei_txe_out_data_read(const struct mei_device *dev,
 497                                         unsigned long idx)
 498 {
 499         struct mei_txe_hw *hw = to_txe_hw(dev);
 500
 501         return mei_txe_br_reg_read(hw,
 502                 BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32)));
 503 }
 504
 505 /* Readiness */
 506
 507 /**
 508  * mei_txe_readiness_set_host_rdy - set host readiness bit
 509  *
 510  * @dev: the device structure
 511  */
 512 static void mei_txe_readiness_set_host_rdy(struct mei_device *dev)
 513 {
 514         struct mei_txe_hw *hw = to_txe_hw(dev);
 515
 516         mei_txe_br_reg_write(hw,
 517                 SICR_HOST_IPC_READINESS_REQ_REG,
 518                 SICR_HOST_IPC_READINESS_HOST_RDY);
 519 }
 520
 521 /**
 522  * mei_txe_readiness_clear - clear host readiness bit
 523  *
 524  * @dev: the device structure
 525  */
 526 static void mei_txe_readiness_clear(struct mei_device *dev)
 527 {
 528         struct mei_txe_hw *hw = to_txe_hw(dev);
 529
 530         mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG,
 531                                 SICR_HOST_IPC_READINESS_RDY_CLR);
 532 }
 533 /**
 534  * mei_txe_readiness_get - Reads and returns
 535  *      the HICR_SEC_IPC_READINESS register value
 536  *
 537  * @dev: the device structure
 538  *
 539  * Return: the HICR_SEC_IPC_READINESS register value
 540  */
 541 static u32 mei_txe_readiness_get(struct mei_device *dev)
 542 {
 543         struct mei_txe_hw *hw = to_txe_hw(dev);
 544
 545         return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
 546 }
 547
 548
 549 /**
 550  * mei_txe_readiness_is_sec_rdy - check readiness
 551  *  for HICR_SEC_IPC_READINESS_SEC_RDY
 552  *
 553  * @readiness: cached readiness state
 554  *
 555  * Return: true if readiness bit is set
 556  */
 557 static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness)
 558 {
 559         return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY);
 560 }
 561
 562 /**
 563  * mei_txe_hw_is_ready - check if the hw is ready
 564  *
 565  * @dev: the device structure
 566  *
 567  * Return: true if sec is ready
 568  */
 569 static bool mei_txe_hw_is_ready(struct mei_device *dev)
 570 {
 571         u32 readiness =  mei_txe_readiness_get(dev);
 572
 573         return mei_txe_readiness_is_sec_rdy(readiness);
 574 }
 575
 576 /**
 577  * mei_txe_host_is_ready - check if the host is ready
 578  *
 579  * @dev: the device structure
 580  *
 581  * Return: true if host is ready
 582  */
 583 static inline bool mei_txe_host_is_ready(struct mei_device *dev)
 584 {
 585         struct mei_txe_hw *hw = to_txe_hw(dev);
 586         u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
 587
 588         return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY);
 589 }
 590
 591 /**
 592  * mei_txe_readiness_wait - wait till readiness settles
 593  *
 594  * @dev: the device structure
 595  *
 596  * Return: 0 on success and -ETIME on timeout
 597  */
 598 static int mei_txe_readiness_wait(struct mei_device *dev)
 599 {
 600         if (mei_txe_hw_is_ready(dev))
 601                 return 0;
 602
 603         mutex_unlock(&dev->device_lock);
 604         wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready,
 605                         msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT));
 606         mutex_lock(&dev->device_lock);
 607         if (!dev->recvd_hw_ready) {
 608                 dev_err(dev->dev, "wait for readiness failed\n");
 609                 return -ETIME;
 610         }
 611
 612         dev->recvd_hw_ready = false;
 613         return 0;
 614 }
 615
 616 static const struct mei_fw_status mei_txe_fw_sts = {
 617         .count = 2,
 618         .status[0] = PCI_CFG_TXE_FW_STS0,
 619         .status[1] = PCI_CFG_TXE_FW_STS1
 620 };
 621
 622 /**
 623  * mei_txe_fw_status - read fw status register from pci config space
 624  *
 625  * @dev: mei device
 626  * @fw_status: fw status register values
 627  *
 628  * Return: 0 on success, error otherwise
 629  */
 630 static int mei_txe_fw_status(struct mei_device *dev,
 631                              struct mei_fw_status *fw_status)
 632 {
 633         const struct mei_fw_status *fw_src = &mei_txe_fw_sts;
 634         struct pci_dev *pdev = to_pci_dev(dev->dev);
 635         int ret;
 636         int i;
 637
 638         if (!fw_status)
 639                 return -EINVAL;
 640
 641         fw_status->count = fw_src->count;
 642         for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
 643                 ret = pci_read_config_dword(pdev,
 644                         fw_src->status[i], &fw_status->status[i]);
 645                 if (ret)
 646                         return ret;
 647         }
 648
 649         return 0;
 650 }
 651
 652 /**
 653  *  mei_txe_hw_config - configure hardware at the start of the devices
 654  *
 655  * @dev: the device structure
 656  *
 657  * Configure hardware at the start of the device should be done only
 658  *   once at the device probe time
 659  */
 660 static void mei_txe_hw_config(struct mei_device *dev)
 661 {
 662
 663         struct mei_txe_hw *hw = to_txe_hw(dev);
 664
 665         /* Doesn't change in runtime */
 666         dev->hbuf_depth = PAYLOAD_SIZE / 4;
 667
 668         hw->aliveness = mei_txe_aliveness_get(dev);
 669         hw->readiness = mei_txe_readiness_get(dev);
 670
 671         dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n",
 672                 hw->aliveness, hw->readiness);
 673 }
 674
 675
 676 /**
 677  * mei_txe_write - writes a message to device.
 678  *
 679  * @dev: the device structure
 680  * @header: header of message
 681  * @buf: message buffer will be written
 682  *
 683  * Return: 0 if success, <0 - otherwise.
 684  */
 685
 686 static int mei_txe_write(struct mei_device *dev,
 687                 struct mei_msg_hdr *header, unsigned char *buf)
 688 {
 689         struct mei_txe_hw *hw = to_txe_hw(dev);
 690         unsigned long rem;
 691         unsigned long length;
 692         int slots = dev->hbuf_depth;
 693         u32 *reg_buf = (u32 *)buf;
 694         u32 dw_cnt;
 695         int i;
 696
 697         if (WARN_ON(!header || !buf))
 698                 return -EINVAL;
 699
 700         length = header->length;
 701
 702         dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
 703
 704         dw_cnt = mei_data2slots(length);
 705         if (dw_cnt > slots)
 706                 return -EMSGSIZE;
 707
 708         if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n"))
 709                 return -EAGAIN;
 710
 711         /* Enable Input Ready Interrupt. */
 712         mei_txe_input_ready_interrupt_enable(dev);
 713
 714         if (!mei_txe_is_input_ready(dev)) {
 715                 char fw_sts_str[MEI_FW_STATUS_STR_SZ];
 716
 717                 mei_fw_status_str(dev, fw_sts_str, MEI_FW_STATUS_STR_SZ);
 718                 dev_err(dev->dev, "Input is not ready %s\n", fw_sts_str);
 719                 return -EAGAIN;
 720         }
 721
 722         mei_txe_input_payload_write(dev, 0, *((u32 *)header));
 723
 724         for (i = 0; i < length / 4; i++)
 725                 mei_txe_input_payload_write(dev, i + 1, reg_buf[i]);
 726
 727         rem = length & 0x3;
 728         if (rem > 0) {
 729                 u32 reg = 0;
 730
 731                 memcpy(&reg, &buf[length - rem], rem);
 732                 mei_txe_input_payload_write(dev, i + 1, reg);
 733         }
 734
 735         /* after each write the whole buffer is consumed */
 736         hw->slots = 0;
 737
 738         /* Set Input-Doorbell */
 739         mei_txe_input_doorbell_set(hw);
 740
 741         return 0;
 742 }
 743
 744 /**
 745  * mei_txe_hbuf_max_len - mimics the me hbuf circular buffer
 746  *
 747  * @dev: the device structure
 748  *
 749  * Return: the PAYLOAD_SIZE - 4
 750  */
 751 static size_t mei_txe_hbuf_max_len(const struct mei_device *dev)
 752 {
 753         return PAYLOAD_SIZE - sizeof(struct mei_msg_hdr);
 754 }
 755
 756 /**
 757  * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer
 758  *
 759  * @dev: the device structure
 760  *
 761  * Return: always hbuf_depth
 762  */
 763 static int mei_txe_hbuf_empty_slots(struct mei_device *dev)
 764 {
 765         struct mei_txe_hw *hw = to_txe_hw(dev);
 766
 767         return hw->slots;
 768 }
 769
 770 /**
 771  * mei_txe_count_full_read_slots - mimics the me device circular buffer
 772  *
 773  * @dev: the device structure
 774  *
 775  * Return: always buffer size in dwords count
 776  */
 777 static int mei_txe_count_full_read_slots(struct mei_device *dev)
 778 {
 779         /* read buffers has static size */
 780         return  PAYLOAD_SIZE / 4;
 781 }
 782
 783 /**
 784  * mei_txe_read_hdr - read message header which is always in 4 first bytes
 785  *
 786  * @dev: the device structure
 787  *
 788  * Return: mei message header
 789  */
 790
 791 static u32 mei_txe_read_hdr(const struct mei_device *dev)
 792 {
 793         return mei_txe_out_data_read(dev, 0);
 794 }
 795 /**
 796  * mei_txe_read - reads a message from the txe device.
 797  *
 798  * @dev: the device structure
 799  * @buf: message buffer will be written
 800  * @len: message size will be read
 801  *
 802  * Return: -EINVAL on error wrong argument and 0 on success
 803  */
 804 static int mei_txe_read(struct mei_device *dev,
 805                 unsigned char *buf, unsigned long len)
 806 {
 807
 808         struct mei_txe_hw *hw = to_txe_hw(dev);
 809         u32 *reg_buf, reg;
 810         u32 rem;
 811         u32 i;
 812
 813         if (WARN_ON(!buf || !len))
 814                 return -EINVAL;
 815
 816         reg_buf = (u32 *)buf;
 817         rem = len & 0x3;
 818
 819         dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n",
 820                 len, mei_txe_out_data_read(dev, 0));
 821
 822         for (i = 0; i < len / 4; i++) {
 823                 /* skip header: index starts from 1 */
 824                 reg = mei_txe_out_data_read(dev, i + 1);
 825                 dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg);
 826                 *reg_buf++ = reg;
 827         }
 828
 829         if (rem) {
 830                 reg = mei_txe_out_data_read(dev, i + 1);
 831                 memcpy(reg_buf, &reg, rem);
 832         }
 833
 834         mei_txe_output_ready_set(hw);
 835         return 0;
 836 }
 837
 838 /**
 839  * mei_txe_hw_reset - resets host and fw.
 840  *
 841  * @dev: the device structure
 842  * @intr_enable: if interrupt should be enabled after reset.
 843  *
 844  * Return: 0 on success and < 0 in case of error
 845  */
 846 static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable)
 847 {
 848         struct mei_txe_hw *hw = to_txe_hw(dev);
 849
 850         u32 aliveness_req;
 851         /*
 852          * read input doorbell to ensure consistency between  Bridge and SeC
 853          * return value might be garbage return
 854          */
 855         (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG);
 856
 857         aliveness_req = mei_txe_aliveness_req_get(dev);
 858         hw->aliveness = mei_txe_aliveness_get(dev);
 859
 860         /* Disable interrupts in this stage we will poll */
 861         mei_txe_intr_disable(dev);
 862
 863         /*
 864          * If Aliveness Request and Aliveness Response are not equal then
 865          * wait for them to be equal
 866          * Since we might have interrupts disabled - poll for it
 867          */
 868         if (aliveness_req != hw->aliveness)
 869                 if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) {
 870                         dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n");
 871                         return -EIO;
 872                 }
 873
 874         /*
 875          * If Aliveness Request and Aliveness Response are set then clear them
 876          */
 877         if (aliveness_req) {
 878                 mei_txe_aliveness_set(dev, 0);
 879                 if (mei_txe_aliveness_poll(dev, 0) < 0) {
 880                         dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
 881                         return -EIO;
 882                 }
 883         }
 884
 885         /*
 886          * Set readiness RDY_CLR bit
 887          */
 888         mei_txe_readiness_clear(dev);
 889
 890         return 0;
 891 }
 892
 893 /**
 894  * mei_txe_hw_start - start the hardware after reset
 895  *
 896  * @dev: the device structure
 897  *
 898  * Return: 0 on success an error code otherwise
 899  */
 900 static int mei_txe_hw_start(struct mei_device *dev)
 901 {
 902         struct mei_txe_hw *hw = to_txe_hw(dev);
 903         int ret;
 904
 905         u32 hisr;
 906
 907         /* bring back interrupts */
 908         mei_txe_intr_enable(dev);
 909
 910         ret = mei_txe_readiness_wait(dev);
 911         if (ret < 0) {
 912                 dev_err(dev->dev, "waiting for readiness failed\n");
 913                 return ret;
 914         }
 915
 916         /*
 917          * If HISR.INT2_STS interrupt status bit is set then clear it.
 918          */
 919         hisr = mei_txe_br_reg_read(hw, HISR_REG);
 920         if (hisr & HISR_INT_2_STS)
 921                 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS);
 922
 923         /* Clear the interrupt cause of OutputDoorbell */
 924         clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause);
 925
 926         ret = mei_txe_aliveness_set_sync(dev, 1);
 927         if (ret < 0) {
 928                 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
 929                 return ret;
 930         }
 931
 932         /* enable input ready interrupts:
 933          * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK
 934          */
 935         mei_txe_input_ready_interrupt_enable(dev);
 936
 937
 938         /*  Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */
 939         mei_txe_output_ready_set(hw);
 940
 941         /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY
 942          */
 943         mei_txe_readiness_set_host_rdy(dev);
 944
 945         return 0;
 946 }
 947
 948 /**
 949  * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into
 950  *  single bit mask and acknowledge the interrupts
 951  *
 952  * @dev: the device structure
 953  * @do_ack: acknowledge interrupts
 954  *
 955  * Return: true if found interrupts to process.
 956  */
 957 static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack)
 958 {
 959         struct mei_txe_hw *hw = to_txe_hw(dev);
 960         u32 hisr;
 961         u32 hhisr;
 962         u32 ipc_isr;
 963         u32 aliveness;
 964         bool generated;
 965
 966         /* read interrupt registers */
 967         hhisr = mei_txe_br_reg_read(hw, HHISR_REG);
 968         generated = (hhisr & IPC_HHIER_MSK);
 969         if (!generated)
 970                 goto out;
 971
 972         hisr = mei_txe_br_reg_read(hw, HISR_REG);
 973
 974         aliveness = mei_txe_aliveness_get(dev);
 975         if (hhisr & IPC_HHIER_SEC && aliveness)
 976                 ipc_isr = mei_txe_sec_reg_read_silent(hw,
 977                                 SEC_IPC_HOST_INT_STATUS_REG);
 978         else
 979                 ipc_isr = 0;
 980
 981         generated = generated ||
 982                 (hisr & HISR_INT_STS_MSK) ||
 983                 (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING);
 984
 985         if (generated && do_ack) {
 986                 /* Save the interrupt causes */
 987                 hw->intr_cause |= hisr & HISR_INT_STS_MSK;
 988                 if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY)
 989                         hw->intr_cause |= TXE_INTR_IN_READY;
 990
 991
 992                 mei_txe_intr_disable(dev);
 993                 /* Clear the interrupts in hierarchy:
 994                  * IPC and Bridge, than the High Level */
 995                 mei_txe_sec_reg_write_silent(hw,
 996                         SEC_IPC_HOST_INT_STATUS_REG, ipc_isr);
 997                 mei_txe_br_reg_write(hw, HISR_REG, hisr);
 998                 mei_txe_br_reg_write(hw, HHISR_REG, hhisr);
 999         }
1000
1001 out:
1002         return generated;
1003 }
1004
1005 /**
1006  * mei_txe_irq_quick_handler - The ISR of the MEI device
1007  *
1008  * @irq: The irq number
1009  * @dev_id: pointer to the device structure
1010  *
1011  * Return: IRQ_WAKE_THREAD if interrupt is designed for the device
1012  *         IRQ_NONE otherwise
1013  */
1014 irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id)
1015 {
1016         struct mei_device *dev = dev_id;
1017
1018         if (mei_txe_check_and_ack_intrs(dev, true))
1019                 return IRQ_WAKE_THREAD;
1020         return IRQ_NONE;
1021 }
1022
1023
1024 /**
1025  * mei_txe_irq_thread_handler - txe interrupt thread
1026  *
1027  * @irq: The irq number
1028  * @dev_id: pointer to the device structure
1029  *
1030  * Return: IRQ_HANDLED
1031  */
1032 irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id)
1033 {
1034         struct mei_device *dev = (struct mei_device *) dev_id;
1035         struct mei_txe_hw *hw = to_txe_hw(dev);
1036         struct mei_cl_cb complete_list;
1037         s32 slots;
1038         int rets = 0;
1039
1040         dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n",
1041                 mei_txe_br_reg_read(hw, HHISR_REG),
1042                 mei_txe_br_reg_read(hw, HISR_REG),
1043                 mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG));
1044
1045
1046         /* initialize our complete list */
1047         mutex_lock(&dev->device_lock);
1048         mei_io_list_init(&complete_list);
1049
1050         if (pci_dev_msi_enabled(to_pci_dev(dev->dev)))
1051                 mei_txe_check_and_ack_intrs(dev, true);
1052
1053         /* show irq events */
1054         mei_txe_pending_interrupts(dev);
1055
1056         hw->aliveness = mei_txe_aliveness_get(dev);
1057         hw->readiness = mei_txe_readiness_get(dev);
1058
1059         /* Readiness:
1060          * Detection of TXE driver going through reset
1061          * or TXE driver resetting the HECI interface.
1062          */
1063         if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) {
1064                 dev_dbg(dev->dev, "Readiness Interrupt was received...\n");
1065
1066                 /* Check if SeC is going through reset */
1067                 if (mei_txe_readiness_is_sec_rdy(hw->readiness)) {
1068                         dev_dbg(dev->dev, "we need to start the dev.\n");
1069                         dev->recvd_hw_ready = true;
1070                 } else {
1071                         dev->recvd_hw_ready = false;
1072                         if (dev->dev_state != MEI_DEV_RESETTING) {
1073
1074                                 dev_warn(dev->dev, "FW not ready: resetting.\n");
1075                                 schedule_work(&dev->reset_work);
1076                                 goto end;
1077
1078                         }
1079                 }
1080                 wake_up(&dev->wait_hw_ready);
1081         }
1082
1083         /************************************************************/
1084         /* Check interrupt cause:
1085          * Aliveness: Detection of SeC acknowledge of host request that
1086          * it remain alive or host cancellation of that request.
1087          */
1088
1089         if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) {
1090                 /* Clear the interrupt cause */
1091                 dev_dbg(dev->dev,
1092                         "Aliveness Interrupt: Status: %d\n", hw->aliveness);
1093                 dev->pg_event = MEI_PG_EVENT_RECEIVED;
1094                 if (waitqueue_active(&hw->wait_aliveness_resp))
1095                         wake_up(&hw->wait_aliveness_resp);
1096         }
1097
1098
1099         /* Output Doorbell:
1100          * Detection of SeC having sent output to host
1101          */
1102         slots = mei_count_full_read_slots(dev);
1103         if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) {
1104                 /* Read from TXE */
1105                 rets = mei_irq_read_handler(dev, &complete_list, &slots);
1106                 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
1107                         dev_err(dev->dev,
1108                                 "mei_irq_read_handler ret = %d.\n", rets);
1109
1110                         schedule_work(&dev->reset_work);
1111                         goto end;
1112                 }
1113         }
1114         /* Input Ready: Detection if host can write to SeC */
1115         if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) {
1116                 dev->hbuf_is_ready = true;
1117                 hw->slots = dev->hbuf_depth;
1118         }
1119
1120         if (hw->aliveness && dev->hbuf_is_ready) {
1121                 /* get the real register value */
1122                 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1123                 rets = mei_irq_write_handler(dev, &complete_list);
1124                 if (rets && rets != -EMSGSIZE)
1125                         dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n",
1126                                 rets);
1127                 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1128         }
1129
1130         mei_irq_compl_handler(dev, &complete_list);
1131
1132 end:
1133         dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
1134
1135         mutex_unlock(&dev->device_lock);
1136
1137         mei_enable_interrupts(dev);
1138         return IRQ_HANDLED;
1139 }
1140
1141 static const struct mei_hw_ops mei_txe_hw_ops = {
1142
1143         .host_is_ready = mei_txe_host_is_ready,
1144
1145         .fw_status = mei_txe_fw_status,
1146         .pg_state = mei_txe_pg_state,
1147
1148         .hw_is_ready = mei_txe_hw_is_ready,
1149         .hw_reset = mei_txe_hw_reset,
1150         .hw_config = mei_txe_hw_config,
1151         .hw_start = mei_txe_hw_start,
1152
1153         .pg_in_transition = mei_txe_pg_in_transition,
1154         .pg_is_enabled = mei_txe_pg_is_enabled,
1155
1156         .intr_clear = mei_txe_intr_clear,
1157         .intr_enable = mei_txe_intr_enable,
1158         .intr_disable = mei_txe_intr_disable,
1159
1160         .hbuf_free_slots = mei_txe_hbuf_empty_slots,
1161         .hbuf_is_ready = mei_txe_is_input_ready,
1162         .hbuf_max_len = mei_txe_hbuf_max_len,
1163
1164         .write = mei_txe_write,
1165
1166         .rdbuf_full_slots = mei_txe_count_full_read_slots,
1167         .read_hdr = mei_txe_read_hdr,
1168
1169         .read = mei_txe_read,
1170
1171 };
1172
1173 /**
1174  * mei_txe_dev_init - allocates and initializes txe hardware specific structure
1175  *
1176  * @pdev: pci device
1177  *
1178  * Return: struct mei_device * on success or NULL
1179  */
1180 struct mei_device *mei_txe_dev_init(struct pci_dev *pdev)
1181 {
1182         struct mei_device *dev;
1183         struct mei_txe_hw *hw;
1184
1185         dev = kzalloc(sizeof(struct mei_device) +
1186                          sizeof(struct mei_txe_hw), GFP_KERNEL);
1187         if (!dev)
1188                 return NULL;
1189
1190         mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops);
1191
1192         hw = to_txe_hw(dev);
1193
1194         init_waitqueue_head(&hw->wait_aliveness_resp);
1195
1196         return dev;
1197 }
1198
1199 /**
1200  * mei_txe_setup_satt2 - SATT2 configuration for DMA support.
1201  *
1202  * @dev:   the device structure
1203  * @addr:  physical address start of the range
1204  * @range: physical range size
1205  *
1206  * Return: 0 on success an error code otherwise
1207  */
1208 int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range)
1209 {
1210         struct mei_txe_hw *hw = to_txe_hw(dev);
1211
1212         u32 lo32 = lower_32_bits(addr);
1213         u32 hi32 = upper_32_bits(addr);
1214         u32 ctrl;
1215
1216         /* SATT is limited to 36 Bits */
1217         if (hi32 & ~0xF)
1218                 return -EINVAL;
1219
1220         /* SATT has to be 16Byte aligned */
1221         if (lo32 & 0xF)
1222                 return -EINVAL;
1223
1224         /* SATT range has to be 4Bytes aligned */
1225         if (range & 0x4)
1226                 return -EINVAL;
1227
1228         /* SATT is limited to 32 MB range*/
1229         if (range > SATT_RANGE_MAX)
1230                 return -EINVAL;
1231
1232         ctrl = SATT2_CTRL_VALID_MSK;
1233         ctrl |= hi32  << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT;
1234
1235         mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range);
1236         mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32);
1237         mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl);
1238         dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n",
1239                 range, lo32, ctrl);
1240
1241         return 0;
1242 }