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mmc: replace printk with appropriate display macro
[deliverable/linux.git] / drivers / mmc / host / dw_mmc.c
1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/scatterlist.h>
26 #include <linux/seq_file.h>
27 #include <linux/slab.h>
28 #include <linux/stat.h>
29 #include <linux/delay.h>
30 #include <linux/irq.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/dw_mmc.h>
34 #include <linux/bitops.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/workqueue.h>
37
38 #include "dw_mmc.h"
39
40 /* Common flag combinations */
41 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
42 SDMMC_INT_HTO | SDMMC_INT_SBE | \
43 SDMMC_INT_EBE)
44 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
45 SDMMC_INT_RESP_ERR)
46 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
47 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
48 #define DW_MCI_SEND_STATUS 1
49 #define DW_MCI_RECV_STATUS 2
50 #define DW_MCI_DMA_THRESHOLD 16
51
52 #ifdef CONFIG_MMC_DW_IDMAC
53 struct idmac_desc {
54 u32 des0; /* Control Descriptor */
55 #define IDMAC_DES0_DIC BIT(1)
56 #define IDMAC_DES0_LD BIT(2)
57 #define IDMAC_DES0_FD BIT(3)
58 #define IDMAC_DES0_CH BIT(4)
59 #define IDMAC_DES0_ER BIT(5)
60 #define IDMAC_DES0_CES BIT(30)
61 #define IDMAC_DES0_OWN BIT(31)
62
63 u32 des1; /* Buffer sizes */
64 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
65 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
66
67 u32 des2; /* buffer 1 physical address */
68
69 u32 des3; /* buffer 2 physical address */
70 };
71 #endif /* CONFIG_MMC_DW_IDMAC */
72
73 /**
74 * struct dw_mci_slot - MMC slot state
75 * @mmc: The mmc_host representing this slot.
76 * @host: The MMC controller this slot is using.
77 * @ctype: Card type for this slot.
78 * @mrq: mmc_request currently being processed or waiting to be
79 * processed, or NULL when the slot is idle.
80 * @queue_node: List node for placing this node in the @queue list of
81 * &struct dw_mci.
82 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
83 * @flags: Random state bits associated with the slot.
84 * @id: Number of this slot.
85 * @last_detect_state: Most recently observed card detect state.
86 */
87 struct dw_mci_slot {
88 struct mmc_host *mmc;
89 struct dw_mci *host;
90
91 u32 ctype;
92
93 struct mmc_request *mrq;
94 struct list_head queue_node;
95
96 unsigned int clock;
97 unsigned long flags;
98 #define DW_MMC_CARD_PRESENT 0
99 #define DW_MMC_CARD_NEED_INIT 1
100 int id;
101 int last_detect_state;
102 };
103
104 static struct workqueue_struct *dw_mci_card_workqueue;
105
106 #if defined(CONFIG_DEBUG_FS)
107 static int dw_mci_req_show(struct seq_file *s, void *v)
108 {
109 struct dw_mci_slot *slot = s->private;
110 struct mmc_request *mrq;
111 struct mmc_command *cmd;
112 struct mmc_command *stop;
113 struct mmc_data *data;
114
115 /* Make sure we get a consistent snapshot */
116 spin_lock_bh(&slot->host->lock);
117 mrq = slot->mrq;
118
119 if (mrq) {
120 cmd = mrq->cmd;
121 data = mrq->data;
122 stop = mrq->stop;
123
124 if (cmd)
125 seq_printf(s,
126 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
127 cmd->opcode, cmd->arg, cmd->flags,
128 cmd->resp[0], cmd->resp[1], cmd->resp[2],
129 cmd->resp[2], cmd->error);
130 if (data)
131 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
132 data->bytes_xfered, data->blocks,
133 data->blksz, data->flags, data->error);
134 if (stop)
135 seq_printf(s,
136 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
137 stop->opcode, stop->arg, stop->flags,
138 stop->resp[0], stop->resp[1], stop->resp[2],
139 stop->resp[2], stop->error);
140 }
141
142 spin_unlock_bh(&slot->host->lock);
143
144 return 0;
145 }
146
147 static int dw_mci_req_open(struct inode *inode, struct file *file)
148 {
149 return single_open(file, dw_mci_req_show, inode->i_private);
150 }
151
152 static const struct file_operations dw_mci_req_fops = {
153 .owner = THIS_MODULE,
154 .open = dw_mci_req_open,
155 .read = seq_read,
156 .llseek = seq_lseek,
157 .release = single_release,
158 };
159
160 static int dw_mci_regs_show(struct seq_file *s, void *v)
161 {
162 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
163 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
164 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
165 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
166 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
167 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
168
169 return 0;
170 }
171
172 static int dw_mci_regs_open(struct inode *inode, struct file *file)
173 {
174 return single_open(file, dw_mci_regs_show, inode->i_private);
175 }
176
177 static const struct file_operations dw_mci_regs_fops = {
178 .owner = THIS_MODULE,
179 .open = dw_mci_regs_open,
180 .read = seq_read,
181 .llseek = seq_lseek,
182 .release = single_release,
183 };
184
185 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
186 {
187 struct mmc_host *mmc = slot->mmc;
188 struct dw_mci *host = slot->host;
189 struct dentry *root;
190 struct dentry *node;
191
192 root = mmc->debugfs_root;
193 if (!root)
194 return;
195
196 node = debugfs_create_file("regs", S_IRUSR, root, host,
197 &dw_mci_regs_fops);
198 if (!node)
199 goto err;
200
201 node = debugfs_create_file("req", S_IRUSR, root, slot,
202 &dw_mci_req_fops);
203 if (!node)
204 goto err;
205
206 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
207 if (!node)
208 goto err;
209
210 node = debugfs_create_x32("pending_events", S_IRUSR, root,
211 (u32 *)&host->pending_events);
212 if (!node)
213 goto err;
214
215 node = debugfs_create_x32("completed_events", S_IRUSR, root,
216 (u32 *)&host->completed_events);
217 if (!node)
218 goto err;
219
220 return;
221
222 err:
223 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
224 }
225 #endif /* defined(CONFIG_DEBUG_FS) */
226
227 static void dw_mci_set_timeout(struct dw_mci *host)
228 {
229 /* timeout (maximum) */
230 mci_writel(host, TMOUT, 0xffffffff);
231 }
232
233 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
234 {
235 struct mmc_data *data;
236 u32 cmdr;
237 cmd->error = -EINPROGRESS;
238
239 cmdr = cmd->opcode;
240
241 if (cmdr == MMC_STOP_TRANSMISSION)
242 cmdr |= SDMMC_CMD_STOP;
243 else
244 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
245
246 if (cmd->flags & MMC_RSP_PRESENT) {
247 /* We expect a response, so set this bit */
248 cmdr |= SDMMC_CMD_RESP_EXP;
249 if (cmd->flags & MMC_RSP_136)
250 cmdr |= SDMMC_CMD_RESP_LONG;
251 }
252
253 if (cmd->flags & MMC_RSP_CRC)
254 cmdr |= SDMMC_CMD_RESP_CRC;
255
256 data = cmd->data;
257 if (data) {
258 cmdr |= SDMMC_CMD_DAT_EXP;
259 if (data->flags & MMC_DATA_STREAM)
260 cmdr |= SDMMC_CMD_STRM_MODE;
261 if (data->flags & MMC_DATA_WRITE)
262 cmdr |= SDMMC_CMD_DAT_WR;
263 }
264
265 return cmdr;
266 }
267
268 static void dw_mci_start_command(struct dw_mci *host,
269 struct mmc_command *cmd, u32 cmd_flags)
270 {
271 host->cmd = cmd;
272 dev_vdbg(&host->pdev->dev,
273 "start command: ARGR=0x%08x CMDR=0x%08x\n",
274 cmd->arg, cmd_flags);
275
276 mci_writel(host, CMDARG, cmd->arg);
277 wmb();
278
279 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
280 }
281
282 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
283 {
284 dw_mci_start_command(host, data->stop, host->stop_cmdr);
285 }
286
287 /* DMA interface functions */
288 static void dw_mci_stop_dma(struct dw_mci *host)
289 {
290 if (host->using_dma) {
291 host->dma_ops->stop(host);
292 host->dma_ops->cleanup(host);
293 } else {
294 /* Data transfer was stopped by the interrupt handler */
295 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
296 }
297 }
298
299 #ifdef CONFIG_MMC_DW_IDMAC
300 static void dw_mci_dma_cleanup(struct dw_mci *host)
301 {
302 struct mmc_data *data = host->data;
303
304 if (data)
305 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
306 ((data->flags & MMC_DATA_WRITE)
307 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
308 }
309
310 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
311 {
312 u32 temp;
313
314 /* Disable and reset the IDMAC interface */
315 temp = mci_readl(host, CTRL);
316 temp &= ~SDMMC_CTRL_USE_IDMAC;
317 temp |= SDMMC_CTRL_DMA_RESET;
318 mci_writel(host, CTRL, temp);
319
320 /* Stop the IDMAC running */
321 temp = mci_readl(host, BMOD);
322 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
323 mci_writel(host, BMOD, temp);
324 }
325
326 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
327 {
328 struct mmc_data *data = host->data;
329
330 dev_vdbg(&host->pdev->dev, "DMA complete\n");
331
332 host->dma_ops->cleanup(host);
333
334 /*
335 * If the card was removed, data will be NULL. No point in trying to
336 * send the stop command or waiting for NBUSY in this case.
337 */
338 if (data) {
339 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
340 tasklet_schedule(&host->tasklet);
341 }
342 }
343
344 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
345 unsigned int sg_len)
346 {
347 int i;
348 struct idmac_desc *desc = host->sg_cpu;
349
350 for (i = 0; i < sg_len; i++, desc++) {
351 unsigned int length = sg_dma_len(&data->sg[i]);
352 u32 mem_addr = sg_dma_address(&data->sg[i]);
353
354 /* Set the OWN bit and disable interrupts for this descriptor */
355 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
356
357 /* Buffer length */
358 IDMAC_SET_BUFFER1_SIZE(desc, length);
359
360 /* Physical address to DMA to/from */
361 desc->des2 = mem_addr;
362 }
363
364 /* Set first descriptor */
365 desc = host->sg_cpu;
366 desc->des0 |= IDMAC_DES0_FD;
367
368 /* Set last descriptor */
369 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
370 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
371 desc->des0 |= IDMAC_DES0_LD;
372
373 wmb();
374 }
375
376 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
377 {
378 u32 temp;
379
380 dw_mci_translate_sglist(host, host->data, sg_len);
381
382 /* Select IDMAC interface */
383 temp = mci_readl(host, CTRL);
384 temp |= SDMMC_CTRL_USE_IDMAC;
385 mci_writel(host, CTRL, temp);
386
387 wmb();
388
389 /* Enable the IDMAC */
390 temp = mci_readl(host, BMOD);
391 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
392 mci_writel(host, BMOD, temp);
393
394 /* Start it running */
395 mci_writel(host, PLDMND, 1);
396 }
397
398 static int dw_mci_idmac_init(struct dw_mci *host)
399 {
400 struct idmac_desc *p;
401 int i;
402
403 /* Number of descriptors in the ring buffer */
404 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
405
406 /* Forward link the descriptor list */
407 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
408 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
409
410 /* Set the last descriptor as the end-of-ring descriptor */
411 p->des3 = host->sg_dma;
412 p->des0 = IDMAC_DES0_ER;
413
414 /* Mask out interrupts - get Tx & Rx complete only */
415 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
416 SDMMC_IDMAC_INT_TI);
417
418 /* Set the descriptor base address */
419 mci_writel(host, DBADDR, host->sg_dma);
420 return 0;
421 }
422
423 static struct dw_mci_dma_ops dw_mci_idmac_ops = {
424 .init = dw_mci_idmac_init,
425 .start = dw_mci_idmac_start_dma,
426 .stop = dw_mci_idmac_stop_dma,
427 .complete = dw_mci_idmac_complete_dma,
428 .cleanup = dw_mci_dma_cleanup,
429 };
430 #endif /* CONFIG_MMC_DW_IDMAC */
431
432 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
433 {
434 struct scatterlist *sg;
435 unsigned int i, direction, sg_len;
436 u32 temp;
437
438 host->using_dma = 0;
439
440 /* If we don't have a channel, we can't do DMA */
441 if (!host->use_dma)
442 return -ENODEV;
443
444 /*
445 * We don't do DMA on "complex" transfers, i.e. with
446 * non-word-aligned buffers or lengths. Also, we don't bother
447 * with all the DMA setup overhead for short transfers.
448 */
449 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
450 return -EINVAL;
451 if (data->blksz & 3)
452 return -EINVAL;
453
454 for_each_sg(data->sg, sg, data->sg_len, i) {
455 if (sg->offset & 3 || sg->length & 3)
456 return -EINVAL;
457 }
458
459 host->using_dma = 1;
460
461 if (data->flags & MMC_DATA_READ)
462 direction = DMA_FROM_DEVICE;
463 else
464 direction = DMA_TO_DEVICE;
465
466 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
467 direction);
468
469 dev_vdbg(&host->pdev->dev,
470 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
471 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
472 sg_len);
473
474 /* Enable the DMA interface */
475 temp = mci_readl(host, CTRL);
476 temp |= SDMMC_CTRL_DMA_ENABLE;
477 mci_writel(host, CTRL, temp);
478
479 /* Disable RX/TX IRQs, let DMA handle it */
480 temp = mci_readl(host, INTMASK);
481 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
482 mci_writel(host, INTMASK, temp);
483
484 host->dma_ops->start(host, sg_len);
485
486 return 0;
487 }
488
489 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
490 {
491 u32 temp;
492
493 data->error = -EINPROGRESS;
494
495 WARN_ON(host->data);
496 host->sg = NULL;
497 host->data = data;
498
499 if (data->flags & MMC_DATA_READ)
500 host->dir_status = DW_MCI_RECV_STATUS;
501 else
502 host->dir_status = DW_MCI_SEND_STATUS;
503
504 if (dw_mci_submit_data_dma(host, data)) {
505 host->sg = data->sg;
506 host->pio_offset = 0;
507 host->part_buf_start = 0;
508 host->part_buf_count = 0;
509
510 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
511 temp = mci_readl(host, INTMASK);
512 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
513 mci_writel(host, INTMASK, temp);
514
515 temp = mci_readl(host, CTRL);
516 temp &= ~SDMMC_CTRL_DMA_ENABLE;
517 mci_writel(host, CTRL, temp);
518 }
519 }
520
521 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
522 {
523 struct dw_mci *host = slot->host;
524 unsigned long timeout = jiffies + msecs_to_jiffies(500);
525 unsigned int cmd_status = 0;
526
527 mci_writel(host, CMDARG, arg);
528 wmb();
529 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
530
531 while (time_before(jiffies, timeout)) {
532 cmd_status = mci_readl(host, CMD);
533 if (!(cmd_status & SDMMC_CMD_START))
534 return;
535 }
536 dev_err(&slot->mmc->class_dev,
537 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
538 cmd, arg, cmd_status);
539 }
540
541 static void dw_mci_setup_bus(struct dw_mci_slot *slot)
542 {
543 struct dw_mci *host = slot->host;
544 u32 div;
545
546 if (slot->clock != host->current_speed) {
547 if (host->bus_hz % slot->clock)
548 /*
549 * move the + 1 after the divide to prevent
550 * over-clocking the card.
551 */
552 div = ((host->bus_hz / slot->clock) >> 1) + 1;
553 else
554 div = (host->bus_hz / slot->clock) >> 1;
555
556 dev_info(&slot->mmc->class_dev,
557 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
558 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
559 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
560
561 /* disable clock */
562 mci_writel(host, CLKENA, 0);
563 mci_writel(host, CLKSRC, 0);
564
565 /* inform CIU */
566 mci_send_cmd(slot,
567 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
568
569 /* set clock to desired speed */
570 mci_writel(host, CLKDIV, div);
571
572 /* inform CIU */
573 mci_send_cmd(slot,
574 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
575
576 /* enable clock */
577 mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE |
578 SDMMC_CLKEN_LOW_PWR);
579
580 /* inform CIU */
581 mci_send_cmd(slot,
582 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
583
584 host->current_speed = slot->clock;
585 }
586
587 /* Set the current slot bus width */
588 mci_writel(host, CTYPE, (slot->ctype << slot->id));
589 }
590
591 static void dw_mci_start_request(struct dw_mci *host,
592 struct dw_mci_slot *slot)
593 {
594 struct mmc_request *mrq;
595 struct mmc_command *cmd;
596 struct mmc_data *data;
597 u32 cmdflags;
598
599 mrq = slot->mrq;
600 if (host->pdata->select_slot)
601 host->pdata->select_slot(slot->id);
602
603 /* Slot specific timing and width adjustment */
604 dw_mci_setup_bus(slot);
605
606 host->cur_slot = slot;
607 host->mrq = mrq;
608
609 host->pending_events = 0;
610 host->completed_events = 0;
611 host->data_status = 0;
612
613 data = mrq->data;
614 if (data) {
615 dw_mci_set_timeout(host);
616 mci_writel(host, BYTCNT, data->blksz*data->blocks);
617 mci_writel(host, BLKSIZ, data->blksz);
618 }
619
620 cmd = mrq->cmd;
621 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
622
623 /* this is the first command, send the initialization clock */
624 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
625 cmdflags |= SDMMC_CMD_INIT;
626
627 if (data) {
628 dw_mci_submit_data(host, data);
629 wmb();
630 }
631
632 dw_mci_start_command(host, cmd, cmdflags);
633
634 if (mrq->stop)
635 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
636 }
637
638 /* must be called with host->lock held */
639 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
640 struct mmc_request *mrq)
641 {
642 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
643 host->state);
644
645 slot->mrq = mrq;
646
647 if (host->state == STATE_IDLE) {
648 host->state = STATE_SENDING_CMD;
649 dw_mci_start_request(host, slot);
650 } else {
651 list_add_tail(&slot->queue_node, &host->queue);
652 }
653 }
654
655 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
656 {
657 struct dw_mci_slot *slot = mmc_priv(mmc);
658 struct dw_mci *host = slot->host;
659
660 WARN_ON(slot->mrq);
661
662 /*
663 * The check for card presence and queueing of the request must be
664 * atomic, otherwise the card could be removed in between and the
665 * request wouldn't fail until another card was inserted.
666 */
667 spin_lock_bh(&host->lock);
668
669 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
670 spin_unlock_bh(&host->lock);
671 mrq->cmd->error = -ENOMEDIUM;
672 mmc_request_done(mmc, mrq);
673 return;
674 }
675
676 dw_mci_queue_request(host, slot, mrq);
677
678 spin_unlock_bh(&host->lock);
679 }
680
681 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
682 {
683 struct dw_mci_slot *slot = mmc_priv(mmc);
684 u32 regs;
685
686 /* set default 1 bit mode */
687 slot->ctype = SDMMC_CTYPE_1BIT;
688
689 switch (ios->bus_width) {
690 case MMC_BUS_WIDTH_1:
691 slot->ctype = SDMMC_CTYPE_1BIT;
692 break;
693 case MMC_BUS_WIDTH_4:
694 slot->ctype = SDMMC_CTYPE_4BIT;
695 break;
696 case MMC_BUS_WIDTH_8:
697 slot->ctype = SDMMC_CTYPE_8BIT;
698 break;
699 }
700
701 /* DDR mode set */
702 if (ios->timing == MMC_TIMING_UHS_DDR50) {
703 regs = mci_readl(slot->host, UHS_REG);
704 regs |= (0x1 << slot->id) << 16;
705 mci_writel(slot->host, UHS_REG, regs);
706 }
707
708 if (ios->clock) {
709 /*
710 * Use mirror of ios->clock to prevent race with mmc
711 * core ios update when finding the minimum.
712 */
713 slot->clock = ios->clock;
714 }
715
716 switch (ios->power_mode) {
717 case MMC_POWER_UP:
718 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
719 break;
720 default:
721 break;
722 }
723 }
724
725 static int dw_mci_get_ro(struct mmc_host *mmc)
726 {
727 int read_only;
728 struct dw_mci_slot *slot = mmc_priv(mmc);
729 struct dw_mci_board *brd = slot->host->pdata;
730
731 /* Use platform get_ro function, else try on board write protect */
732 if (brd->get_ro)
733 read_only = brd->get_ro(slot->id);
734 else
735 read_only =
736 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
737
738 dev_dbg(&mmc->class_dev, "card is %s\n",
739 read_only ? "read-only" : "read-write");
740
741 return read_only;
742 }
743
744 static int dw_mci_get_cd(struct mmc_host *mmc)
745 {
746 int present;
747 struct dw_mci_slot *slot = mmc_priv(mmc);
748 struct dw_mci_board *brd = slot->host->pdata;
749
750 /* Use platform get_cd function, else try onboard card detect */
751 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
752 present = 1;
753 else if (brd->get_cd)
754 present = !brd->get_cd(slot->id);
755 else
756 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
757 == 0 ? 1 : 0;
758
759 if (present)
760 dev_dbg(&mmc->class_dev, "card is present\n");
761 else
762 dev_dbg(&mmc->class_dev, "card is not present\n");
763
764 return present;
765 }
766
767 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
768 {
769 struct dw_mci_slot *slot = mmc_priv(mmc);
770 struct dw_mci *host = slot->host;
771 u32 int_mask;
772
773 /* Enable/disable Slot Specific SDIO interrupt */
774 int_mask = mci_readl(host, INTMASK);
775 if (enb) {
776 mci_writel(host, INTMASK,
777 (int_mask | (1 << SDMMC_INT_SDIO(slot->id))));
778 } else {
779 mci_writel(host, INTMASK,
780 (int_mask & ~(1 << SDMMC_INT_SDIO(slot->id))));
781 }
782 }
783
784 static const struct mmc_host_ops dw_mci_ops = {
785 .request = dw_mci_request,
786 .set_ios = dw_mci_set_ios,
787 .get_ro = dw_mci_get_ro,
788 .get_cd = dw_mci_get_cd,
789 .enable_sdio_irq = dw_mci_enable_sdio_irq,
790 };
791
792 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
793 __releases(&host->lock)
794 __acquires(&host->lock)
795 {
796 struct dw_mci_slot *slot;
797 struct mmc_host *prev_mmc = host->cur_slot->mmc;
798
799 WARN_ON(host->cmd || host->data);
800
801 host->cur_slot->mrq = NULL;
802 host->mrq = NULL;
803 if (!list_empty(&host->queue)) {
804 slot = list_entry(host->queue.next,
805 struct dw_mci_slot, queue_node);
806 list_del(&slot->queue_node);
807 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
808 mmc_hostname(slot->mmc));
809 host->state = STATE_SENDING_CMD;
810 dw_mci_start_request(host, slot);
811 } else {
812 dev_vdbg(&host->pdev->dev, "list empty\n");
813 host->state = STATE_IDLE;
814 }
815
816 spin_unlock(&host->lock);
817 mmc_request_done(prev_mmc, mrq);
818 spin_lock(&host->lock);
819 }
820
821 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
822 {
823 u32 status = host->cmd_status;
824
825 host->cmd_status = 0;
826
827 /* Read the response from the card (up to 16 bytes) */
828 if (cmd->flags & MMC_RSP_PRESENT) {
829 if (cmd->flags & MMC_RSP_136) {
830 cmd->resp[3] = mci_readl(host, RESP0);
831 cmd->resp[2] = mci_readl(host, RESP1);
832 cmd->resp[1] = mci_readl(host, RESP2);
833 cmd->resp[0] = mci_readl(host, RESP3);
834 } else {
835 cmd->resp[0] = mci_readl(host, RESP0);
836 cmd->resp[1] = 0;
837 cmd->resp[2] = 0;
838 cmd->resp[3] = 0;
839 }
840 }
841
842 if (status & SDMMC_INT_RTO)
843 cmd->error = -ETIMEDOUT;
844 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
845 cmd->error = -EILSEQ;
846 else if (status & SDMMC_INT_RESP_ERR)
847 cmd->error = -EIO;
848 else
849 cmd->error = 0;
850
851 if (cmd->error) {
852 /* newer ip versions need a delay between retries */
853 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
854 mdelay(20);
855
856 if (cmd->data) {
857 host->data = NULL;
858 dw_mci_stop_dma(host);
859 }
860 }
861 }
862
863 static void dw_mci_tasklet_func(unsigned long priv)
864 {
865 struct dw_mci *host = (struct dw_mci *)priv;
866 struct mmc_data *data;
867 struct mmc_command *cmd;
868 enum dw_mci_state state;
869 enum dw_mci_state prev_state;
870 u32 status, ctrl;
871
872 spin_lock(&host->lock);
873
874 state = host->state;
875 data = host->data;
876
877 do {
878 prev_state = state;
879
880 switch (state) {
881 case STATE_IDLE:
882 break;
883
884 case STATE_SENDING_CMD:
885 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
886 &host->pending_events))
887 break;
888
889 cmd = host->cmd;
890 host->cmd = NULL;
891 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
892 dw_mci_command_complete(host, host->mrq->cmd);
893 if (!host->mrq->data || cmd->error) {
894 dw_mci_request_end(host, host->mrq);
895 goto unlock;
896 }
897
898 prev_state = state = STATE_SENDING_DATA;
899 /* fall through */
900
901 case STATE_SENDING_DATA:
902 if (test_and_clear_bit(EVENT_DATA_ERROR,
903 &host->pending_events)) {
904 dw_mci_stop_dma(host);
905 if (data->stop)
906 send_stop_cmd(host, data);
907 state = STATE_DATA_ERROR;
908 break;
909 }
910
911 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
912 &host->pending_events))
913 break;
914
915 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
916 prev_state = state = STATE_DATA_BUSY;
917 /* fall through */
918
919 case STATE_DATA_BUSY:
920 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
921 &host->pending_events))
922 break;
923
924 host->data = NULL;
925 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
926 status = host->data_status;
927
928 if (status & DW_MCI_DATA_ERROR_FLAGS) {
929 if (status & SDMMC_INT_DTO) {
930 data->error = -ETIMEDOUT;
931 } else if (status & SDMMC_INT_DCRC) {
932 data->error = -EILSEQ;
933 } else if (status & SDMMC_INT_EBE &&
934 host->dir_status ==
935 DW_MCI_SEND_STATUS) {
936 /*
937 * No data CRC status was returned.
938 * The number of bytes transferred will
939 * be exaggerated in PIO mode.
940 */
941 data->bytes_xfered = 0;
942 data->error = -ETIMEDOUT;
943 } else {
944 dev_err(&host->pdev->dev,
945 "data FIFO error "
946 "(status=%08x)\n",
947 status);
948 data->error = -EIO;
949 }
950 /*
951 * After an error, there may be data lingering
952 * in the FIFO, so reset it - doing so
953 * generates a block interrupt, hence setting
954 * the scatter-gather pointer to NULL.
955 */
956 host->sg = NULL;
957 ctrl = mci_readl(host, CTRL);
958 ctrl |= SDMMC_CTRL_FIFO_RESET;
959 mci_writel(host, CTRL, ctrl);
960 } else {
961 data->bytes_xfered = data->blocks * data->blksz;
962 data->error = 0;
963 }
964
965 if (!data->stop) {
966 dw_mci_request_end(host, host->mrq);
967 goto unlock;
968 }
969
970 prev_state = state = STATE_SENDING_STOP;
971 if (!data->error)
972 send_stop_cmd(host, data);
973 /* fall through */
974
975 case STATE_SENDING_STOP:
976 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
977 &host->pending_events))
978 break;
979
980 host->cmd = NULL;
981 dw_mci_command_complete(host, host->mrq->stop);
982 dw_mci_request_end(host, host->mrq);
983 goto unlock;
984
985 case STATE_DATA_ERROR:
986 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
987 &host->pending_events))
988 break;
989
990 state = STATE_DATA_BUSY;
991 break;
992 }
993 } while (state != prev_state);
994
995 host->state = state;
996 unlock:
997 spin_unlock(&host->lock);
998
999 }
1000
1001 /* push final bytes to part_buf, only use during push */
1002 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1003 {
1004 memcpy((void *)&host->part_buf, buf, cnt);
1005 host->part_buf_count = cnt;
1006 }
1007
1008 /* append bytes to part_buf, only use during push */
1009 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1010 {
1011 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1012 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1013 host->part_buf_count += cnt;
1014 return cnt;
1015 }
1016
1017 /* pull first bytes from part_buf, only use during pull */
1018 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1019 {
1020 cnt = min(cnt, (int)host->part_buf_count);
1021 if (cnt) {
1022 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1023 cnt);
1024 host->part_buf_count -= cnt;
1025 host->part_buf_start += cnt;
1026 }
1027 return cnt;
1028 }
1029
1030 /* pull final bytes from the part_buf, assuming it's just been filled */
1031 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1032 {
1033 memcpy(buf, &host->part_buf, cnt);
1034 host->part_buf_start = cnt;
1035 host->part_buf_count = (1 << host->data_shift) - cnt;
1036 }
1037
1038 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1039 {
1040 /* try and push anything in the part_buf */
1041 if (unlikely(host->part_buf_count)) {
1042 int len = dw_mci_push_part_bytes(host, buf, cnt);
1043 buf += len;
1044 cnt -= len;
1045 if (!sg_next(host->sg) || host->part_buf_count == 2) {
1046 mci_writew(host, DATA, host->part_buf16);
1047 host->part_buf_count = 0;
1048 }
1049 }
1050 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1051 if (unlikely((unsigned long)buf & 0x1)) {
1052 while (cnt >= 2) {
1053 u16 aligned_buf[64];
1054 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1055 int items = len >> 1;
1056 int i;
1057 /* memcpy from input buffer into aligned buffer */
1058 memcpy(aligned_buf, buf, len);
1059 buf += len;
1060 cnt -= len;
1061 /* push data from aligned buffer into fifo */
1062 for (i = 0; i < items; ++i)
1063 mci_writew(host, DATA, aligned_buf[i]);
1064 }
1065 } else
1066 #endif
1067 {
1068 u16 *pdata = buf;
1069 for (; cnt >= 2; cnt -= 2)
1070 mci_writew(host, DATA, *pdata++);
1071 buf = pdata;
1072 }
1073 /* put anything remaining in the part_buf */
1074 if (cnt) {
1075 dw_mci_set_part_bytes(host, buf, cnt);
1076 if (!sg_next(host->sg))
1077 mci_writew(host, DATA, host->part_buf16);
1078 }
1079 }
1080
1081 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1082 {
1083 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1084 if (unlikely((unsigned long)buf & 0x1)) {
1085 while (cnt >= 2) {
1086 /* pull data from fifo into aligned buffer */
1087 u16 aligned_buf[64];
1088 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1089 int items = len >> 1;
1090 int i;
1091 for (i = 0; i < items; ++i)
1092 aligned_buf[i] = mci_readw(host, DATA);
1093 /* memcpy from aligned buffer into output buffer */
1094 memcpy(buf, aligned_buf, len);
1095 buf += len;
1096 cnt -= len;
1097 }
1098 } else
1099 #endif
1100 {
1101 u16 *pdata = buf;
1102 for (; cnt >= 2; cnt -= 2)
1103 *pdata++ = mci_readw(host, DATA);
1104 buf = pdata;
1105 }
1106 if (cnt) {
1107 host->part_buf16 = mci_readw(host, DATA);
1108 dw_mci_pull_final_bytes(host, buf, cnt);
1109 }
1110 }
1111
1112 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1113 {
1114 /* try and push anything in the part_buf */
1115 if (unlikely(host->part_buf_count)) {
1116 int len = dw_mci_push_part_bytes(host, buf, cnt);
1117 buf += len;
1118 cnt -= len;
1119 if (!sg_next(host->sg) || host->part_buf_count == 4) {
1120 mci_writel(host, DATA, host->part_buf32);
1121 host->part_buf_count = 0;
1122 }
1123 }
1124 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1125 if (unlikely((unsigned long)buf & 0x3)) {
1126 while (cnt >= 4) {
1127 u32 aligned_buf[32];
1128 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1129 int items = len >> 2;
1130 int i;
1131 /* memcpy from input buffer into aligned buffer */
1132 memcpy(aligned_buf, buf, len);
1133 buf += len;
1134 cnt -= len;
1135 /* push data from aligned buffer into fifo */
1136 for (i = 0; i < items; ++i)
1137 mci_writel(host, DATA, aligned_buf[i]);
1138 }
1139 } else
1140 #endif
1141 {
1142 u32 *pdata = buf;
1143 for (; cnt >= 4; cnt -= 4)
1144 mci_writel(host, DATA, *pdata++);
1145 buf = pdata;
1146 }
1147 /* put anything remaining in the part_buf */
1148 if (cnt) {
1149 dw_mci_set_part_bytes(host, buf, cnt);
1150 if (!sg_next(host->sg))
1151 mci_writel(host, DATA, host->part_buf32);
1152 }
1153 }
1154
1155 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1156 {
1157 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1158 if (unlikely((unsigned long)buf & 0x3)) {
1159 while (cnt >= 4) {
1160 /* pull data from fifo into aligned buffer */
1161 u32 aligned_buf[32];
1162 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1163 int items = len >> 2;
1164 int i;
1165 for (i = 0; i < items; ++i)
1166 aligned_buf[i] = mci_readl(host, DATA);
1167 /* memcpy from aligned buffer into output buffer */
1168 memcpy(buf, aligned_buf, len);
1169 buf += len;
1170 cnt -= len;
1171 }
1172 } else
1173 #endif
1174 {
1175 u32 *pdata = buf;
1176 for (; cnt >= 4; cnt -= 4)
1177 *pdata++ = mci_readl(host, DATA);
1178 buf = pdata;
1179 }
1180 if (cnt) {
1181 host->part_buf32 = mci_readl(host, DATA);
1182 dw_mci_pull_final_bytes(host, buf, cnt);
1183 }
1184 }
1185
1186 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1187 {
1188 /* try and push anything in the part_buf */
1189 if (unlikely(host->part_buf_count)) {
1190 int len = dw_mci_push_part_bytes(host, buf, cnt);
1191 buf += len;
1192 cnt -= len;
1193 if (!sg_next(host->sg) || host->part_buf_count == 8) {
1194 mci_writew(host, DATA, host->part_buf);
1195 host->part_buf_count = 0;
1196 }
1197 }
1198 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1199 if (unlikely((unsigned long)buf & 0x7)) {
1200 while (cnt >= 8) {
1201 u64 aligned_buf[16];
1202 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1203 int items = len >> 3;
1204 int i;
1205 /* memcpy from input buffer into aligned buffer */
1206 memcpy(aligned_buf, buf, len);
1207 buf += len;
1208 cnt -= len;
1209 /* push data from aligned buffer into fifo */
1210 for (i = 0; i < items; ++i)
1211 mci_writeq(host, DATA, aligned_buf[i]);
1212 }
1213 } else
1214 #endif
1215 {
1216 u64 *pdata = buf;
1217 for (; cnt >= 8; cnt -= 8)
1218 mci_writeq(host, DATA, *pdata++);
1219 buf = pdata;
1220 }
1221 /* put anything remaining in the part_buf */
1222 if (cnt) {
1223 dw_mci_set_part_bytes(host, buf, cnt);
1224 if (!sg_next(host->sg))
1225 mci_writeq(host, DATA, host->part_buf);
1226 }
1227 }
1228
1229 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1230 {
1231 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1232 if (unlikely((unsigned long)buf & 0x7)) {
1233 while (cnt >= 8) {
1234 /* pull data from fifo into aligned buffer */
1235 u64 aligned_buf[16];
1236 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1237 int items = len >> 3;
1238 int i;
1239 for (i = 0; i < items; ++i)
1240 aligned_buf[i] = mci_readq(host, DATA);
1241 /* memcpy from aligned buffer into output buffer */
1242 memcpy(buf, aligned_buf, len);
1243 buf += len;
1244 cnt -= len;
1245 }
1246 } else
1247 #endif
1248 {
1249 u64 *pdata = buf;
1250 for (; cnt >= 8; cnt -= 8)
1251 *pdata++ = mci_readq(host, DATA);
1252 buf = pdata;
1253 }
1254 if (cnt) {
1255 host->part_buf = mci_readq(host, DATA);
1256 dw_mci_pull_final_bytes(host, buf, cnt);
1257 }
1258 }
1259
1260 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1261 {
1262 int len;
1263
1264 /* get remaining partial bytes */
1265 len = dw_mci_pull_part_bytes(host, buf, cnt);
1266 if (unlikely(len == cnt))
1267 return;
1268 buf += len;
1269 cnt -= len;
1270
1271 /* get the rest of the data */
1272 host->pull_data(host, buf, cnt);
1273 }
1274
1275 static void dw_mci_read_data_pio(struct dw_mci *host)
1276 {
1277 struct scatterlist *sg = host->sg;
1278 void *buf = sg_virt(sg);
1279 unsigned int offset = host->pio_offset;
1280 struct mmc_data *data = host->data;
1281 int shift = host->data_shift;
1282 u32 status;
1283 unsigned int nbytes = 0, len;
1284
1285 do {
1286 len = host->part_buf_count +
1287 (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift);
1288 if (offset + len <= sg->length) {
1289 dw_mci_pull_data(host, (void *)(buf + offset), len);
1290
1291 offset += len;
1292 nbytes += len;
1293
1294 if (offset == sg->length) {
1295 flush_dcache_page(sg_page(sg));
1296 host->sg = sg = sg_next(sg);
1297 if (!sg)
1298 goto done;
1299
1300 offset = 0;
1301 buf = sg_virt(sg);
1302 }
1303 } else {
1304 unsigned int remaining = sg->length - offset;
1305 dw_mci_pull_data(host, (void *)(buf + offset),
1306 remaining);
1307 nbytes += remaining;
1308
1309 flush_dcache_page(sg_page(sg));
1310 host->sg = sg = sg_next(sg);
1311 if (!sg)
1312 goto done;
1313
1314 offset = len - remaining;
1315 buf = sg_virt(sg);
1316 dw_mci_pull_data(host, buf, offset);
1317 nbytes += offset;
1318 }
1319
1320 status = mci_readl(host, MINTSTS);
1321 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1322 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1323 host->data_status = status;
1324 data->bytes_xfered += nbytes;
1325 smp_wmb();
1326
1327 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1328
1329 tasklet_schedule(&host->tasklet);
1330 return;
1331 }
1332 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
1333 host->pio_offset = offset;
1334 data->bytes_xfered += nbytes;
1335 return;
1336
1337 done:
1338 data->bytes_xfered += nbytes;
1339 smp_wmb();
1340 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1341 }
1342
1343 static void dw_mci_write_data_pio(struct dw_mci *host)
1344 {
1345 struct scatterlist *sg = host->sg;
1346 void *buf = sg_virt(sg);
1347 unsigned int offset = host->pio_offset;
1348 struct mmc_data *data = host->data;
1349 int shift = host->data_shift;
1350 u32 status;
1351 unsigned int nbytes = 0, len;
1352
1353 do {
1354 len = ((host->fifo_depth -
1355 SDMMC_GET_FCNT(mci_readl(host, STATUS))) << shift)
1356 - host->part_buf_count;
1357 if (offset + len <= sg->length) {
1358 host->push_data(host, (void *)(buf + offset), len);
1359
1360 offset += len;
1361 nbytes += len;
1362 if (offset == sg->length) {
1363 host->sg = sg = sg_next(sg);
1364 if (!sg)
1365 goto done;
1366
1367 offset = 0;
1368 buf = sg_virt(sg);
1369 }
1370 } else {
1371 unsigned int remaining = sg->length - offset;
1372
1373 host->push_data(host, (void *)(buf + offset),
1374 remaining);
1375 nbytes += remaining;
1376
1377 host->sg = sg = sg_next(sg);
1378 if (!sg)
1379 goto done;
1380
1381 offset = len - remaining;
1382 buf = sg_virt(sg);
1383 host->push_data(host, (void *)buf, offset);
1384 nbytes += offset;
1385 }
1386
1387 status = mci_readl(host, MINTSTS);
1388 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1389 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1390 host->data_status = status;
1391 data->bytes_xfered += nbytes;
1392
1393 smp_wmb();
1394
1395 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1396
1397 tasklet_schedule(&host->tasklet);
1398 return;
1399 }
1400 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1401 host->pio_offset = offset;
1402 data->bytes_xfered += nbytes;
1403 return;
1404
1405 done:
1406 data->bytes_xfered += nbytes;
1407 smp_wmb();
1408 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1409 }
1410
1411 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1412 {
1413 if (!host->cmd_status)
1414 host->cmd_status = status;
1415
1416 smp_wmb();
1417
1418 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1419 tasklet_schedule(&host->tasklet);
1420 }
1421
1422 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1423 {
1424 struct dw_mci *host = dev_id;
1425 u32 status, pending;
1426 unsigned int pass_count = 0;
1427 int i;
1428
1429 do {
1430 status = mci_readl(host, RINTSTS);
1431 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1432
1433 /*
1434 * DTO fix - version 2.10a and below, and only if internal DMA
1435 * is configured.
1436 */
1437 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1438 if (!pending &&
1439 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1440 pending |= SDMMC_INT_DATA_OVER;
1441 }
1442
1443 if (!pending)
1444 break;
1445
1446 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1447 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1448 host->cmd_status = status;
1449 smp_wmb();
1450 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1451 }
1452
1453 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1454 /* if there is an error report DATA_ERROR */
1455 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1456 host->data_status = status;
1457 smp_wmb();
1458 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1459 if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC |
1460 SDMMC_INT_SBE | SDMMC_INT_EBE)))
1461 tasklet_schedule(&host->tasklet);
1462 }
1463
1464 if (pending & SDMMC_INT_DATA_OVER) {
1465 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1466 if (!host->data_status)
1467 host->data_status = status;
1468 smp_wmb();
1469 if (host->dir_status == DW_MCI_RECV_STATUS) {
1470 if (host->sg != NULL)
1471 dw_mci_read_data_pio(host);
1472 }
1473 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1474 tasklet_schedule(&host->tasklet);
1475 }
1476
1477 if (pending & SDMMC_INT_RXDR) {
1478 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1479 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
1480 dw_mci_read_data_pio(host);
1481 }
1482
1483 if (pending & SDMMC_INT_TXDR) {
1484 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1485 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
1486 dw_mci_write_data_pio(host);
1487 }
1488
1489 if (pending & SDMMC_INT_CMD_DONE) {
1490 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1491 dw_mci_cmd_interrupt(host, status);
1492 }
1493
1494 if (pending & SDMMC_INT_CD) {
1495 mci_writel(host, RINTSTS, SDMMC_INT_CD);
1496 queue_work(dw_mci_card_workqueue, &host->card_work);
1497 }
1498
1499 /* Handle SDIO Interrupts */
1500 for (i = 0; i < host->num_slots; i++) {
1501 struct dw_mci_slot *slot = host->slot[i];
1502 if (pending & SDMMC_INT_SDIO(i)) {
1503 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1504 mmc_signal_sdio_irq(slot->mmc);
1505 }
1506 }
1507
1508 } while (pass_count++ < 5);
1509
1510 #ifdef CONFIG_MMC_DW_IDMAC
1511 /* Handle DMA interrupts */
1512 pending = mci_readl(host, IDSTS);
1513 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1514 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1515 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1516 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1517 host->dma_ops->complete(host);
1518 }
1519 #endif
1520
1521 return IRQ_HANDLED;
1522 }
1523
1524 static void dw_mci_work_routine_card(struct work_struct *work)
1525 {
1526 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
1527 int i;
1528
1529 for (i = 0; i < host->num_slots; i++) {
1530 struct dw_mci_slot *slot = host->slot[i];
1531 struct mmc_host *mmc = slot->mmc;
1532 struct mmc_request *mrq;
1533 int present;
1534 u32 ctrl;
1535
1536 present = dw_mci_get_cd(mmc);
1537 while (present != slot->last_detect_state) {
1538 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1539 present ? "inserted" : "removed");
1540
1541 /* Power up slot (before spin_lock, may sleep) */
1542 if (present != 0 && host->pdata->setpower)
1543 host->pdata->setpower(slot->id, mmc->ocr_avail);
1544
1545 spin_lock_bh(&host->lock);
1546
1547 /* Card change detected */
1548 slot->last_detect_state = present;
1549
1550 /* Mark card as present if applicable */
1551 if (present != 0)
1552 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1553
1554 /* Clean up queue if present */
1555 mrq = slot->mrq;
1556 if (mrq) {
1557 if (mrq == host->mrq) {
1558 host->data = NULL;
1559 host->cmd = NULL;
1560
1561 switch (host->state) {
1562 case STATE_IDLE:
1563 break;
1564 case STATE_SENDING_CMD:
1565 mrq->cmd->error = -ENOMEDIUM;
1566 if (!mrq->data)
1567 break;
1568 /* fall through */
1569 case STATE_SENDING_DATA:
1570 mrq->data->error = -ENOMEDIUM;
1571 dw_mci_stop_dma(host);
1572 break;
1573 case STATE_DATA_BUSY:
1574 case STATE_DATA_ERROR:
1575 if (mrq->data->error == -EINPROGRESS)
1576 mrq->data->error = -ENOMEDIUM;
1577 if (!mrq->stop)
1578 break;
1579 /* fall through */
1580 case STATE_SENDING_STOP:
1581 mrq->stop->error = -ENOMEDIUM;
1582 break;
1583 }
1584
1585 dw_mci_request_end(host, mrq);
1586 } else {
1587 list_del(&slot->queue_node);
1588 mrq->cmd->error = -ENOMEDIUM;
1589 if (mrq->data)
1590 mrq->data->error = -ENOMEDIUM;
1591 if (mrq->stop)
1592 mrq->stop->error = -ENOMEDIUM;
1593
1594 spin_unlock(&host->lock);
1595 mmc_request_done(slot->mmc, mrq);
1596 spin_lock(&host->lock);
1597 }
1598 }
1599
1600 /* Power down slot */
1601 if (present == 0) {
1602 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1603
1604 /*
1605 * Clear down the FIFO - doing so generates a
1606 * block interrupt, hence setting the
1607 * scatter-gather pointer to NULL.
1608 */
1609 host->sg = NULL;
1610
1611 ctrl = mci_readl(host, CTRL);
1612 ctrl |= SDMMC_CTRL_FIFO_RESET;
1613 mci_writel(host, CTRL, ctrl);
1614
1615 #ifdef CONFIG_MMC_DW_IDMAC
1616 ctrl = mci_readl(host, BMOD);
1617 ctrl |= 0x01; /* Software reset of DMA */
1618 mci_writel(host, BMOD, ctrl);
1619 #endif
1620
1621 }
1622
1623 spin_unlock_bh(&host->lock);
1624
1625 /* Power down slot (after spin_unlock, may sleep) */
1626 if (present == 0 && host->pdata->setpower)
1627 host->pdata->setpower(slot->id, 0);
1628
1629 present = dw_mci_get_cd(mmc);
1630 }
1631
1632 mmc_detect_change(slot->mmc,
1633 msecs_to_jiffies(host->pdata->detect_delay_ms));
1634 }
1635 }
1636
1637 static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1638 {
1639 struct mmc_host *mmc;
1640 struct dw_mci_slot *slot;
1641
1642 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev);
1643 if (!mmc)
1644 return -ENOMEM;
1645
1646 slot = mmc_priv(mmc);
1647 slot->id = id;
1648 slot->mmc = mmc;
1649 slot->host = host;
1650
1651 mmc->ops = &dw_mci_ops;
1652 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1653 mmc->f_max = host->bus_hz;
1654
1655 if (host->pdata->get_ocr)
1656 mmc->ocr_avail = host->pdata->get_ocr(id);
1657 else
1658 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1659
1660 /*
1661 * Start with slot power disabled, it will be enabled when a card
1662 * is detected.
1663 */
1664 if (host->pdata->setpower)
1665 host->pdata->setpower(id, 0);
1666
1667 if (host->pdata->caps)
1668 mmc->caps = host->pdata->caps;
1669 else
1670 mmc->caps = 0;
1671
1672 if (host->pdata->get_bus_wd)
1673 if (host->pdata->get_bus_wd(slot->id) >= 4)
1674 mmc->caps |= MMC_CAP_4_BIT_DATA;
1675
1676 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1677 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
1678
1679 #ifdef CONFIG_MMC_DW_IDMAC
1680 mmc->max_segs = host->ring_size;
1681 mmc->max_blk_size = 65536;
1682 mmc->max_blk_count = host->ring_size;
1683 mmc->max_seg_size = 0x1000;
1684 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1685 #else
1686 if (host->pdata->blk_settings) {
1687 mmc->max_segs = host->pdata->blk_settings->max_segs;
1688 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1689 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1690 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1691 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1692 } else {
1693 /* Useful defaults if platform data is unset. */
1694 mmc->max_segs = 64;
1695 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1696 mmc->max_blk_count = 512;
1697 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1698 mmc->max_seg_size = mmc->max_req_size;
1699 }
1700 #endif /* CONFIG_MMC_DW_IDMAC */
1701
1702 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1703 if (IS_ERR(host->vmmc)) {
1704 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
1705 host->vmmc = NULL;
1706 } else
1707 regulator_enable(host->vmmc);
1708
1709 if (dw_mci_get_cd(mmc))
1710 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1711 else
1712 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1713
1714 host->slot[id] = slot;
1715 mmc_add_host(mmc);
1716
1717 #if defined(CONFIG_DEBUG_FS)
1718 dw_mci_init_debugfs(slot);
1719 #endif
1720
1721 /* Card initially undetected */
1722 slot->last_detect_state = 0;
1723
1724 /*
1725 * Card may have been plugged in prior to boot so we
1726 * need to run the detect tasklet
1727 */
1728 queue_work(dw_mci_card_workqueue, &host->card_work);
1729
1730 return 0;
1731 }
1732
1733 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1734 {
1735 /* Shutdown detect IRQ */
1736 if (slot->host->pdata->exit)
1737 slot->host->pdata->exit(id);
1738
1739 /* Debugfs stuff is cleaned up by mmc core */
1740 mmc_remove_host(slot->mmc);
1741 slot->host->slot[id] = NULL;
1742 mmc_free_host(slot->mmc);
1743 }
1744
1745 static void dw_mci_init_dma(struct dw_mci *host)
1746 {
1747 /* Alloc memory for sg translation */
1748 host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE,
1749 &host->sg_dma, GFP_KERNEL);
1750 if (!host->sg_cpu) {
1751 dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n",
1752 __func__);
1753 goto no_dma;
1754 }
1755
1756 /* Determine which DMA interface to use */
1757 #ifdef CONFIG_MMC_DW_IDMAC
1758 host->dma_ops = &dw_mci_idmac_ops;
1759 dev_info(&host->pdev->dev, "Using internal DMA controller.\n");
1760 #endif
1761
1762 if (!host->dma_ops)
1763 goto no_dma;
1764
1765 if (host->dma_ops->init) {
1766 if (host->dma_ops->init(host)) {
1767 dev_err(&host->pdev->dev, "%s: Unable to initialize "
1768 "DMA Controller.\n", __func__);
1769 goto no_dma;
1770 }
1771 } else {
1772 dev_err(&host->pdev->dev, "DMA initialization not found.\n");
1773 goto no_dma;
1774 }
1775
1776 host->use_dma = 1;
1777 return;
1778
1779 no_dma:
1780 dev_info(&host->pdev->dev, "Using PIO mode.\n");
1781 host->use_dma = 0;
1782 return;
1783 }
1784
1785 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1786 {
1787 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1788 unsigned int ctrl;
1789
1790 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1791 SDMMC_CTRL_DMA_RESET));
1792
1793 /* wait till resets clear */
1794 do {
1795 ctrl = mci_readl(host, CTRL);
1796 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1797 SDMMC_CTRL_DMA_RESET)))
1798 return true;
1799 } while (time_before(jiffies, timeout));
1800
1801 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1802
1803 return false;
1804 }
1805
1806 static int dw_mci_probe(struct platform_device *pdev)
1807 {
1808 struct dw_mci *host;
1809 struct resource *regs;
1810 struct dw_mci_board *pdata;
1811 int irq, ret, i, width;
1812 u32 fifo_size;
1813
1814 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1815 if (!regs)
1816 return -ENXIO;
1817
1818 irq = platform_get_irq(pdev, 0);
1819 if (irq < 0)
1820 return irq;
1821
1822 host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL);
1823 if (!host)
1824 return -ENOMEM;
1825
1826 host->pdev = pdev;
1827 host->pdata = pdata = pdev->dev.platform_data;
1828 if (!pdata || !pdata->init) {
1829 dev_err(&pdev->dev,
1830 "Platform data must supply init function\n");
1831 ret = -ENODEV;
1832 goto err_freehost;
1833 }
1834
1835 if (!pdata->select_slot && pdata->num_slots > 1) {
1836 dev_err(&pdev->dev,
1837 "Platform data must supply select_slot function\n");
1838 ret = -ENODEV;
1839 goto err_freehost;
1840 }
1841
1842 if (!pdata->bus_hz) {
1843 dev_err(&pdev->dev,
1844 "Platform data must supply bus speed\n");
1845 ret = -ENODEV;
1846 goto err_freehost;
1847 }
1848
1849 host->bus_hz = pdata->bus_hz;
1850 host->quirks = pdata->quirks;
1851
1852 spin_lock_init(&host->lock);
1853 INIT_LIST_HEAD(&host->queue);
1854
1855 ret = -ENOMEM;
1856 host->regs = ioremap(regs->start, resource_size(regs));
1857 if (!host->regs)
1858 goto err_freehost;
1859
1860 host->dma_ops = pdata->dma_ops;
1861 dw_mci_init_dma(host);
1862
1863 /*
1864 * Get the host data width - this assumes that HCON has been set with
1865 * the correct values.
1866 */
1867 i = (mci_readl(host, HCON) >> 7) & 0x7;
1868 if (!i) {
1869 host->push_data = dw_mci_push_data16;
1870 host->pull_data = dw_mci_pull_data16;
1871 width = 16;
1872 host->data_shift = 1;
1873 } else if (i == 2) {
1874 host->push_data = dw_mci_push_data64;
1875 host->pull_data = dw_mci_pull_data64;
1876 width = 64;
1877 host->data_shift = 3;
1878 } else {
1879 /* Check for a reserved value, and warn if it is */
1880 WARN((i != 1),
1881 "HCON reports a reserved host data width!\n"
1882 "Defaulting to 32-bit access.\n");
1883 host->push_data = dw_mci_push_data32;
1884 host->pull_data = dw_mci_pull_data32;
1885 width = 32;
1886 host->data_shift = 2;
1887 }
1888
1889 /* Reset all blocks */
1890 if (!mci_wait_reset(&pdev->dev, host)) {
1891 ret = -ENODEV;
1892 goto err_dmaunmap;
1893 }
1894
1895 /* Clear the interrupts for the host controller */
1896 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1897 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1898
1899 /* Put in max timeout */
1900 mci_writel(host, TMOUT, 0xFFFFFFFF);
1901
1902 /*
1903 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
1904 * Tx Mark = fifo_size / 2 DMA Size = 8
1905 */
1906 if (!host->pdata->fifo_depth) {
1907 /*
1908 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
1909 * have been overwritten by the bootloader, just like we're
1910 * about to do, so if you know the value for your hardware, you
1911 * should put it in the platform data.
1912 */
1913 fifo_size = mci_readl(host, FIFOTH);
1914 fifo_size = 1 + ((fifo_size >> 16) & 0x7ff);
1915 } else {
1916 fifo_size = host->pdata->fifo_depth;
1917 }
1918 host->fifo_depth = fifo_size;
1919 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
1920 ((fifo_size/2) << 0));
1921 mci_writel(host, FIFOTH, host->fifoth_val);
1922
1923 /* disable clock to CIU */
1924 mci_writel(host, CLKENA, 0);
1925 mci_writel(host, CLKSRC, 0);
1926
1927 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
1928 dw_mci_card_workqueue = alloc_workqueue("dw-mci-card",
1929 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
1930 if (!dw_mci_card_workqueue)
1931 goto err_dmaunmap;
1932 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
1933
1934 ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host);
1935 if (ret)
1936 goto err_workqueue;
1937
1938 platform_set_drvdata(pdev, host);
1939
1940 if (host->pdata->num_slots)
1941 host->num_slots = host->pdata->num_slots;
1942 else
1943 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
1944
1945 /* We need at least one slot to succeed */
1946 for (i = 0; i < host->num_slots; i++) {
1947 ret = dw_mci_init_slot(host, i);
1948 if (ret) {
1949 ret = -ENODEV;
1950 goto err_init_slot;
1951 }
1952 }
1953
1954 /*
1955 * Enable interrupts for command done, data over, data empty, card det,
1956 * receive ready and error such as transmit, receive timeout, crc error
1957 */
1958 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1959 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
1960 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
1961 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
1962 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
1963
1964 dev_info(&pdev->dev, "DW MMC controller at irq %d, "
1965 "%d bit host data width, "
1966 "%u deep fifo\n",
1967 irq, width, fifo_size);
1968 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
1969 dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n");
1970
1971 return 0;
1972
1973 err_init_slot:
1974 /* De-init any initialized slots */
1975 while (i > 0) {
1976 if (host->slot[i])
1977 dw_mci_cleanup_slot(host->slot[i], i);
1978 i--;
1979 }
1980 free_irq(irq, host);
1981
1982 err_workqueue:
1983 destroy_workqueue(dw_mci_card_workqueue);
1984
1985 err_dmaunmap:
1986 if (host->use_dma && host->dma_ops->exit)
1987 host->dma_ops->exit(host);
1988 dma_free_coherent(&host->pdev->dev, PAGE_SIZE,
1989 host->sg_cpu, host->sg_dma);
1990 iounmap(host->regs);
1991
1992 if (host->vmmc) {
1993 regulator_disable(host->vmmc);
1994 regulator_put(host->vmmc);
1995 }
1996
1997
1998 err_freehost:
1999 kfree(host);
2000 return ret;
2001 }
2002
2003 static int __exit dw_mci_remove(struct platform_device *pdev)
2004 {
2005 struct dw_mci *host = platform_get_drvdata(pdev);
2006 int i;
2007
2008 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2009 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2010
2011 platform_set_drvdata(pdev, NULL);
2012
2013 for (i = 0; i < host->num_slots; i++) {
2014 dev_dbg(&pdev->dev, "remove slot %d\n", i);
2015 if (host->slot[i])
2016 dw_mci_cleanup_slot(host->slot[i], i);
2017 }
2018
2019 /* disable clock to CIU */
2020 mci_writel(host, CLKENA, 0);
2021 mci_writel(host, CLKSRC, 0);
2022
2023 free_irq(platform_get_irq(pdev, 0), host);
2024 destroy_workqueue(dw_mci_card_workqueue);
2025 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
2026
2027 if (host->use_dma && host->dma_ops->exit)
2028 host->dma_ops->exit(host);
2029
2030 if (host->vmmc) {
2031 regulator_disable(host->vmmc);
2032 regulator_put(host->vmmc);
2033 }
2034
2035 iounmap(host->regs);
2036
2037 kfree(host);
2038 return 0;
2039 }
2040
2041 #ifdef CONFIG_PM
2042 /*
2043 * TODO: we should probably disable the clock to the card in the suspend path.
2044 */
2045 static int dw_mci_suspend(struct platform_device *pdev, pm_message_t mesg)
2046 {
2047 int i, ret;
2048 struct dw_mci *host = platform_get_drvdata(pdev);
2049
2050 for (i = 0; i < host->num_slots; i++) {
2051 struct dw_mci_slot *slot = host->slot[i];
2052 if (!slot)
2053 continue;
2054 ret = mmc_suspend_host(slot->mmc);
2055 if (ret < 0) {
2056 while (--i >= 0) {
2057 slot = host->slot[i];
2058 if (slot)
2059 mmc_resume_host(host->slot[i]->mmc);
2060 }
2061 return ret;
2062 }
2063 }
2064
2065 if (host->vmmc)
2066 regulator_disable(host->vmmc);
2067
2068 return 0;
2069 }
2070
2071 static int dw_mci_resume(struct platform_device *pdev)
2072 {
2073 int i, ret;
2074 struct dw_mci *host = platform_get_drvdata(pdev);
2075
2076 if (host->vmmc)
2077 regulator_enable(host->vmmc);
2078
2079 if (host->dma_ops->init)
2080 host->dma_ops->init(host);
2081
2082 if (!mci_wait_reset(&pdev->dev, host)) {
2083 ret = -ENODEV;
2084 return ret;
2085 }
2086
2087 /* Restore the old value at FIFOTH register */
2088 mci_writel(host, FIFOTH, host->fifoth_val);
2089
2090 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2091 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2092 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2093 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2094 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2095
2096 for (i = 0; i < host->num_slots; i++) {
2097 struct dw_mci_slot *slot = host->slot[i];
2098 if (!slot)
2099 continue;
2100 ret = mmc_resume_host(host->slot[i]->mmc);
2101 if (ret < 0)
2102 return ret;
2103 }
2104
2105 return 0;
2106 }
2107 #else
2108 #define dw_mci_suspend NULL
2109 #define dw_mci_resume NULL
2110 #endif /* CONFIG_PM */
2111
2112 static struct platform_driver dw_mci_driver = {
2113 .remove = __exit_p(dw_mci_remove),
2114 .suspend = dw_mci_suspend,
2115 .resume = dw_mci_resume,
2116 .driver = {
2117 .name = "dw_mmc",
2118 },
2119 };
2120
2121 static int __init dw_mci_init(void)
2122 {
2123 return platform_driver_probe(&dw_mci_driver, dw_mci_probe);
2124 }
2125
2126 static void __exit dw_mci_exit(void)
2127 {
2128 platform_driver_unregister(&dw_mci_driver);
2129 }
2130
2131 module_init(dw_mci_init);
2132 module_exit(dw_mci_exit);
2133
2134 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2135 MODULE_AUTHOR("NXP Semiconductor VietNam");
2136 MODULE_AUTHOR("Imagination Technologies Ltd");
2137 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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