2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/dw_mmc.h>
33 #include <linux/bitops.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/workqueue.h>
40 /* Common flag combinations */
41 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
42 SDMMC_INT_HTO | SDMMC_INT_SBE | \
44 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
46 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
47 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
48 #define DW_MCI_SEND_STATUS 1
49 #define DW_MCI_RECV_STATUS 2
50 #define DW_MCI_DMA_THRESHOLD 16
52 #ifdef CONFIG_MMC_DW_IDMAC
54 u32 des0
; /* Control Descriptor */
55 #define IDMAC_DES0_DIC BIT(1)
56 #define IDMAC_DES0_LD BIT(2)
57 #define IDMAC_DES0_FD BIT(3)
58 #define IDMAC_DES0_CH BIT(4)
59 #define IDMAC_DES0_ER BIT(5)
60 #define IDMAC_DES0_CES BIT(30)
61 #define IDMAC_DES0_OWN BIT(31)
63 u32 des1
; /* Buffer sizes */
64 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
65 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
67 u32 des2
; /* buffer 1 physical address */
69 u32 des3
; /* buffer 2 physical address */
71 #endif /* CONFIG_MMC_DW_IDMAC */
74 * struct dw_mci_slot - MMC slot state
75 * @mmc: The mmc_host representing this slot.
76 * @host: The MMC controller this slot is using.
77 * @ctype: Card type for this slot.
78 * @mrq: mmc_request currently being processed or waiting to be
79 * processed, or NULL when the slot is idle.
80 * @queue_node: List node for placing this node in the @queue list of
82 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
83 * @flags: Random state bits associated with the slot.
84 * @id: Number of this slot.
85 * @last_detect_state: Most recently observed card detect state.
93 struct mmc_request
*mrq
;
94 struct list_head queue_node
;
98 #define DW_MMC_CARD_PRESENT 0
99 #define DW_MMC_CARD_NEED_INIT 1
101 int last_detect_state
;
104 #if defined(CONFIG_DEBUG_FS)
105 static int dw_mci_req_show(struct seq_file
*s
, void *v
)
107 struct dw_mci_slot
*slot
= s
->private;
108 struct mmc_request
*mrq
;
109 struct mmc_command
*cmd
;
110 struct mmc_command
*stop
;
111 struct mmc_data
*data
;
113 /* Make sure we get a consistent snapshot */
114 spin_lock_bh(&slot
->host
->lock
);
124 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
125 cmd
->opcode
, cmd
->arg
, cmd
->flags
,
126 cmd
->resp
[0], cmd
->resp
[1], cmd
->resp
[2],
127 cmd
->resp
[2], cmd
->error
);
129 seq_printf(s
, "DATA %u / %u * %u flg %x err %d\n",
130 data
->bytes_xfered
, data
->blocks
,
131 data
->blksz
, data
->flags
, data
->error
);
134 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
135 stop
->opcode
, stop
->arg
, stop
->flags
,
136 stop
->resp
[0], stop
->resp
[1], stop
->resp
[2],
137 stop
->resp
[2], stop
->error
);
140 spin_unlock_bh(&slot
->host
->lock
);
145 static int dw_mci_req_open(struct inode
*inode
, struct file
*file
)
147 return single_open(file
, dw_mci_req_show
, inode
->i_private
);
150 static const struct file_operations dw_mci_req_fops
= {
151 .owner
= THIS_MODULE
,
152 .open
= dw_mci_req_open
,
155 .release
= single_release
,
158 static int dw_mci_regs_show(struct seq_file
*s
, void *v
)
160 seq_printf(s
, "STATUS:\t0x%08x\n", SDMMC_STATUS
);
161 seq_printf(s
, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS
);
162 seq_printf(s
, "CMD:\t0x%08x\n", SDMMC_CMD
);
163 seq_printf(s
, "CTRL:\t0x%08x\n", SDMMC_CTRL
);
164 seq_printf(s
, "INTMASK:\t0x%08x\n", SDMMC_INTMASK
);
165 seq_printf(s
, "CLKENA:\t0x%08x\n", SDMMC_CLKENA
);
170 static int dw_mci_regs_open(struct inode
*inode
, struct file
*file
)
172 return single_open(file
, dw_mci_regs_show
, inode
->i_private
);
175 static const struct file_operations dw_mci_regs_fops
= {
176 .owner
= THIS_MODULE
,
177 .open
= dw_mci_regs_open
,
180 .release
= single_release
,
183 static void dw_mci_init_debugfs(struct dw_mci_slot
*slot
)
185 struct mmc_host
*mmc
= slot
->mmc
;
186 struct dw_mci
*host
= slot
->host
;
190 root
= mmc
->debugfs_root
;
194 node
= debugfs_create_file("regs", S_IRUSR
, root
, host
,
199 node
= debugfs_create_file("req", S_IRUSR
, root
, slot
,
204 node
= debugfs_create_u32("state", S_IRUSR
, root
, (u32
*)&host
->state
);
208 node
= debugfs_create_x32("pending_events", S_IRUSR
, root
,
209 (u32
*)&host
->pending_events
);
213 node
= debugfs_create_x32("completed_events", S_IRUSR
, root
,
214 (u32
*)&host
->completed_events
);
221 dev_err(&mmc
->class_dev
, "failed to initialize debugfs for slot\n");
223 #endif /* defined(CONFIG_DEBUG_FS) */
225 static void dw_mci_set_timeout(struct dw_mci
*host
)
227 /* timeout (maximum) */
228 mci_writel(host
, TMOUT
, 0xffffffff);
231 static u32
dw_mci_prepare_command(struct mmc_host
*mmc
, struct mmc_command
*cmd
)
233 struct mmc_data
*data
;
234 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
235 const struct dw_mci_drv_data
*drv_data
= slot
->host
->drv_data
;
237 cmd
->error
= -EINPROGRESS
;
241 if (cmdr
== MMC_STOP_TRANSMISSION
)
242 cmdr
|= SDMMC_CMD_STOP
;
244 cmdr
|= SDMMC_CMD_PRV_DAT_WAIT
;
246 if (cmd
->flags
& MMC_RSP_PRESENT
) {
247 /* We expect a response, so set this bit */
248 cmdr
|= SDMMC_CMD_RESP_EXP
;
249 if (cmd
->flags
& MMC_RSP_136
)
250 cmdr
|= SDMMC_CMD_RESP_LONG
;
253 if (cmd
->flags
& MMC_RSP_CRC
)
254 cmdr
|= SDMMC_CMD_RESP_CRC
;
258 cmdr
|= SDMMC_CMD_DAT_EXP
;
259 if (data
->flags
& MMC_DATA_STREAM
)
260 cmdr
|= SDMMC_CMD_STRM_MODE
;
261 if (data
->flags
& MMC_DATA_WRITE
)
262 cmdr
|= SDMMC_CMD_DAT_WR
;
265 if (drv_data
&& drv_data
->prepare_command
)
266 drv_data
->prepare_command(slot
->host
, &cmdr
);
271 static void dw_mci_start_command(struct dw_mci
*host
,
272 struct mmc_command
*cmd
, u32 cmd_flags
)
276 "start command: ARGR=0x%08x CMDR=0x%08x\n",
277 cmd
->arg
, cmd_flags
);
279 mci_writel(host
, CMDARG
, cmd
->arg
);
282 mci_writel(host
, CMD
, cmd_flags
| SDMMC_CMD_START
);
285 static void send_stop_cmd(struct dw_mci
*host
, struct mmc_data
*data
)
287 dw_mci_start_command(host
, data
->stop
, host
->stop_cmdr
);
290 /* DMA interface functions */
291 static void dw_mci_stop_dma(struct dw_mci
*host
)
293 if (host
->using_dma
) {
294 host
->dma_ops
->stop(host
);
295 host
->dma_ops
->cleanup(host
);
297 /* Data transfer was stopped by the interrupt handler */
298 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
302 static int dw_mci_get_dma_dir(struct mmc_data
*data
)
304 if (data
->flags
& MMC_DATA_WRITE
)
305 return DMA_TO_DEVICE
;
307 return DMA_FROM_DEVICE
;
310 #ifdef CONFIG_MMC_DW_IDMAC
311 static void dw_mci_dma_cleanup(struct dw_mci
*host
)
313 struct mmc_data
*data
= host
->data
;
316 if (!data
->host_cookie
)
317 dma_unmap_sg(host
->dev
,
320 dw_mci_get_dma_dir(data
));
323 static void dw_mci_idmac_stop_dma(struct dw_mci
*host
)
327 /* Disable and reset the IDMAC interface */
328 temp
= mci_readl(host
, CTRL
);
329 temp
&= ~SDMMC_CTRL_USE_IDMAC
;
330 temp
|= SDMMC_CTRL_DMA_RESET
;
331 mci_writel(host
, CTRL
, temp
);
333 /* Stop the IDMAC running */
334 temp
= mci_readl(host
, BMOD
);
335 temp
&= ~(SDMMC_IDMAC_ENABLE
| SDMMC_IDMAC_FB
);
336 mci_writel(host
, BMOD
, temp
);
339 static void dw_mci_idmac_complete_dma(struct dw_mci
*host
)
341 struct mmc_data
*data
= host
->data
;
343 dev_vdbg(host
->dev
, "DMA complete\n");
345 host
->dma_ops
->cleanup(host
);
348 * If the card was removed, data will be NULL. No point in trying to
349 * send the stop command or waiting for NBUSY in this case.
352 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
353 tasklet_schedule(&host
->tasklet
);
357 static void dw_mci_translate_sglist(struct dw_mci
*host
, struct mmc_data
*data
,
361 struct idmac_desc
*desc
= host
->sg_cpu
;
363 for (i
= 0; i
< sg_len
; i
++, desc
++) {
364 unsigned int length
= sg_dma_len(&data
->sg
[i
]);
365 u32 mem_addr
= sg_dma_address(&data
->sg
[i
]);
367 /* Set the OWN bit and disable interrupts for this descriptor */
368 desc
->des0
= IDMAC_DES0_OWN
| IDMAC_DES0_DIC
| IDMAC_DES0_CH
;
371 IDMAC_SET_BUFFER1_SIZE(desc
, length
);
373 /* Physical address to DMA to/from */
374 desc
->des2
= mem_addr
;
377 /* Set first descriptor */
379 desc
->des0
|= IDMAC_DES0_FD
;
381 /* Set last descriptor */
382 desc
= host
->sg_cpu
+ (i
- 1) * sizeof(struct idmac_desc
);
383 desc
->des0
&= ~(IDMAC_DES0_CH
| IDMAC_DES0_DIC
);
384 desc
->des0
|= IDMAC_DES0_LD
;
389 static void dw_mci_idmac_start_dma(struct dw_mci
*host
, unsigned int sg_len
)
393 dw_mci_translate_sglist(host
, host
->data
, sg_len
);
395 /* Select IDMAC interface */
396 temp
= mci_readl(host
, CTRL
);
397 temp
|= SDMMC_CTRL_USE_IDMAC
;
398 mci_writel(host
, CTRL
, temp
);
402 /* Enable the IDMAC */
403 temp
= mci_readl(host
, BMOD
);
404 temp
|= SDMMC_IDMAC_ENABLE
| SDMMC_IDMAC_FB
;
405 mci_writel(host
, BMOD
, temp
);
407 /* Start it running */
408 mci_writel(host
, PLDMND
, 1);
411 static int dw_mci_idmac_init(struct dw_mci
*host
)
413 struct idmac_desc
*p
;
416 /* Number of descriptors in the ring buffer */
417 host
->ring_size
= PAGE_SIZE
/ sizeof(struct idmac_desc
);
419 /* Forward link the descriptor list */
420 for (i
= 0, p
= host
->sg_cpu
; i
< host
->ring_size
- 1; i
++, p
++)
421 p
->des3
= host
->sg_dma
+ (sizeof(struct idmac_desc
) * (i
+ 1));
423 /* Set the last descriptor as the end-of-ring descriptor */
424 p
->des3
= host
->sg_dma
;
425 p
->des0
= IDMAC_DES0_ER
;
427 mci_writel(host
, BMOD
, SDMMC_IDMAC_SWRESET
);
429 /* Mask out interrupts - get Tx & Rx complete only */
430 mci_writel(host
, IDINTEN
, SDMMC_IDMAC_INT_NI
| SDMMC_IDMAC_INT_RI
|
433 /* Set the descriptor base address */
434 mci_writel(host
, DBADDR
, host
->sg_dma
);
438 static const struct dw_mci_dma_ops dw_mci_idmac_ops
= {
439 .init
= dw_mci_idmac_init
,
440 .start
= dw_mci_idmac_start_dma
,
441 .stop
= dw_mci_idmac_stop_dma
,
442 .complete
= dw_mci_idmac_complete_dma
,
443 .cleanup
= dw_mci_dma_cleanup
,
445 #endif /* CONFIG_MMC_DW_IDMAC */
447 static int dw_mci_pre_dma_transfer(struct dw_mci
*host
,
448 struct mmc_data
*data
,
451 struct scatterlist
*sg
;
452 unsigned int i
, sg_len
;
454 if (!next
&& data
->host_cookie
)
455 return data
->host_cookie
;
458 * We don't do DMA on "complex" transfers, i.e. with
459 * non-word-aligned buffers or lengths. Also, we don't bother
460 * with all the DMA setup overhead for short transfers.
462 if (data
->blocks
* data
->blksz
< DW_MCI_DMA_THRESHOLD
)
468 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
469 if (sg
->offset
& 3 || sg
->length
& 3)
473 sg_len
= dma_map_sg(host
->dev
,
476 dw_mci_get_dma_dir(data
));
481 data
->host_cookie
= sg_len
;
486 static void dw_mci_pre_req(struct mmc_host
*mmc
,
487 struct mmc_request
*mrq
,
490 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
491 struct mmc_data
*data
= mrq
->data
;
493 if (!slot
->host
->use_dma
|| !data
)
496 if (data
->host_cookie
) {
497 data
->host_cookie
= 0;
501 if (dw_mci_pre_dma_transfer(slot
->host
, mrq
->data
, 1) < 0)
502 data
->host_cookie
= 0;
505 static void dw_mci_post_req(struct mmc_host
*mmc
,
506 struct mmc_request
*mrq
,
509 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
510 struct mmc_data
*data
= mrq
->data
;
512 if (!slot
->host
->use_dma
|| !data
)
515 if (data
->host_cookie
)
516 dma_unmap_sg(slot
->host
->dev
,
519 dw_mci_get_dma_dir(data
));
520 data
->host_cookie
= 0;
523 static int dw_mci_submit_data_dma(struct dw_mci
*host
, struct mmc_data
*data
)
530 /* If we don't have a channel, we can't do DMA */
534 sg_len
= dw_mci_pre_dma_transfer(host
, data
, 0);
536 host
->dma_ops
->stop(host
);
543 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
544 (unsigned long)host
->sg_cpu
, (unsigned long)host
->sg_dma
,
547 /* Enable the DMA interface */
548 temp
= mci_readl(host
, CTRL
);
549 temp
|= SDMMC_CTRL_DMA_ENABLE
;
550 mci_writel(host
, CTRL
, temp
);
552 /* Disable RX/TX IRQs, let DMA handle it */
553 temp
= mci_readl(host
, INTMASK
);
554 temp
&= ~(SDMMC_INT_RXDR
| SDMMC_INT_TXDR
);
555 mci_writel(host
, INTMASK
, temp
);
557 host
->dma_ops
->start(host
, sg_len
);
562 static void dw_mci_submit_data(struct dw_mci
*host
, struct mmc_data
*data
)
566 data
->error
= -EINPROGRESS
;
572 if (data
->flags
& MMC_DATA_READ
)
573 host
->dir_status
= DW_MCI_RECV_STATUS
;
575 host
->dir_status
= DW_MCI_SEND_STATUS
;
577 if (dw_mci_submit_data_dma(host
, data
)) {
578 int flags
= SG_MITER_ATOMIC
;
579 if (host
->data
->flags
& MMC_DATA_READ
)
580 flags
|= SG_MITER_TO_SG
;
582 flags
|= SG_MITER_FROM_SG
;
584 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
586 host
->part_buf_start
= 0;
587 host
->part_buf_count
= 0;
589 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
| SDMMC_INT_RXDR
);
590 temp
= mci_readl(host
, INTMASK
);
591 temp
|= SDMMC_INT_TXDR
| SDMMC_INT_RXDR
;
592 mci_writel(host
, INTMASK
, temp
);
594 temp
= mci_readl(host
, CTRL
);
595 temp
&= ~SDMMC_CTRL_DMA_ENABLE
;
596 mci_writel(host
, CTRL
, temp
);
600 static void mci_send_cmd(struct dw_mci_slot
*slot
, u32 cmd
, u32 arg
)
602 struct dw_mci
*host
= slot
->host
;
603 unsigned long timeout
= jiffies
+ msecs_to_jiffies(500);
604 unsigned int cmd_status
= 0;
606 mci_writel(host
, CMDARG
, arg
);
608 mci_writel(host
, CMD
, SDMMC_CMD_START
| cmd
);
610 while (time_before(jiffies
, timeout
)) {
611 cmd_status
= mci_readl(host
, CMD
);
612 if (!(cmd_status
& SDMMC_CMD_START
))
615 dev_err(&slot
->mmc
->class_dev
,
616 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
617 cmd
, arg
, cmd_status
);
620 static void dw_mci_setup_bus(struct dw_mci_slot
*slot
, bool force_clkinit
)
622 struct dw_mci
*host
= slot
->host
;
626 if (slot
->clock
!= host
->current_speed
|| force_clkinit
) {
627 div
= host
->bus_hz
/ slot
->clock
;
628 if (host
->bus_hz
% slot
->clock
&& host
->bus_hz
> slot
->clock
)
630 * move the + 1 after the divide to prevent
631 * over-clocking the card.
635 div
= (host
->bus_hz
!= slot
->clock
) ? DIV_ROUND_UP(div
, 2) : 0;
637 dev_info(&slot
->mmc
->class_dev
,
638 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
639 " div = %d)\n", slot
->id
, host
->bus_hz
, slot
->clock
,
640 div
? ((host
->bus_hz
/ div
) >> 1) : host
->bus_hz
, div
);
643 mci_writel(host
, CLKENA
, 0);
644 mci_writel(host
, CLKSRC
, 0);
648 SDMMC_CMD_UPD_CLK
| SDMMC_CMD_PRV_DAT_WAIT
, 0);
650 /* set clock to desired speed */
651 mci_writel(host
, CLKDIV
, div
);
655 SDMMC_CMD_UPD_CLK
| SDMMC_CMD_PRV_DAT_WAIT
, 0);
657 /* enable clock; only low power if no SDIO */
658 clk_en_a
= SDMMC_CLKEN_ENABLE
<< slot
->id
;
659 if (!(mci_readl(host
, INTMASK
) & SDMMC_INT_SDIO(slot
->id
)))
660 clk_en_a
|= SDMMC_CLKEN_LOW_PWR
<< slot
->id
;
661 mci_writel(host
, CLKENA
, clk_en_a
);
665 SDMMC_CMD_UPD_CLK
| SDMMC_CMD_PRV_DAT_WAIT
, 0);
667 host
->current_speed
= slot
->clock
;
670 /* Set the current slot bus width */
671 mci_writel(host
, CTYPE
, (slot
->ctype
<< slot
->id
));
674 static void __dw_mci_start_request(struct dw_mci
*host
,
675 struct dw_mci_slot
*slot
,
676 struct mmc_command
*cmd
)
678 struct mmc_request
*mrq
;
679 struct mmc_data
*data
;
683 if (host
->pdata
->select_slot
)
684 host
->pdata
->select_slot(slot
->id
);
686 host
->cur_slot
= slot
;
689 host
->pending_events
= 0;
690 host
->completed_events
= 0;
691 host
->data_status
= 0;
695 dw_mci_set_timeout(host
);
696 mci_writel(host
, BYTCNT
, data
->blksz
*data
->blocks
);
697 mci_writel(host
, BLKSIZ
, data
->blksz
);
700 cmdflags
= dw_mci_prepare_command(slot
->mmc
, cmd
);
702 /* this is the first command, send the initialization clock */
703 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT
, &slot
->flags
))
704 cmdflags
|= SDMMC_CMD_INIT
;
707 dw_mci_submit_data(host
, data
);
711 dw_mci_start_command(host
, cmd
, cmdflags
);
714 host
->stop_cmdr
= dw_mci_prepare_command(slot
->mmc
, mrq
->stop
);
717 static void dw_mci_start_request(struct dw_mci
*host
,
718 struct dw_mci_slot
*slot
)
720 struct mmc_request
*mrq
= slot
->mrq
;
721 struct mmc_command
*cmd
;
723 cmd
= mrq
->sbc
? mrq
->sbc
: mrq
->cmd
;
724 __dw_mci_start_request(host
, slot
, cmd
);
727 /* must be called with host->lock held */
728 static void dw_mci_queue_request(struct dw_mci
*host
, struct dw_mci_slot
*slot
,
729 struct mmc_request
*mrq
)
731 dev_vdbg(&slot
->mmc
->class_dev
, "queue request: state=%d\n",
736 if (host
->state
== STATE_IDLE
) {
737 host
->state
= STATE_SENDING_CMD
;
738 dw_mci_start_request(host
, slot
);
740 list_add_tail(&slot
->queue_node
, &host
->queue
);
744 static void dw_mci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
746 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
747 struct dw_mci
*host
= slot
->host
;
752 * The check for card presence and queueing of the request must be
753 * atomic, otherwise the card could be removed in between and the
754 * request wouldn't fail until another card was inserted.
756 spin_lock_bh(&host
->lock
);
758 if (!test_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
)) {
759 spin_unlock_bh(&host
->lock
);
760 mrq
->cmd
->error
= -ENOMEDIUM
;
761 mmc_request_done(mmc
, mrq
);
765 dw_mci_queue_request(host
, slot
, mrq
);
767 spin_unlock_bh(&host
->lock
);
770 static void dw_mci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
772 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
773 const struct dw_mci_drv_data
*drv_data
= slot
->host
->drv_data
;
776 /* set default 1 bit mode */
777 slot
->ctype
= SDMMC_CTYPE_1BIT
;
779 switch (ios
->bus_width
) {
780 case MMC_BUS_WIDTH_1
:
781 slot
->ctype
= SDMMC_CTYPE_1BIT
;
783 case MMC_BUS_WIDTH_4
:
784 slot
->ctype
= SDMMC_CTYPE_4BIT
;
786 case MMC_BUS_WIDTH_8
:
787 slot
->ctype
= SDMMC_CTYPE_8BIT
;
791 regs
= mci_readl(slot
->host
, UHS_REG
);
794 if (ios
->timing
== MMC_TIMING_UHS_DDR50
)
795 regs
|= (0x1 << slot
->id
) << 16;
797 regs
&= ~(0x1 << slot
->id
) << 16;
799 mci_writel(slot
->host
, UHS_REG
, regs
);
803 * Use mirror of ios->clock to prevent race with mmc
804 * core ios update when finding the minimum.
806 slot
->clock
= ios
->clock
;
809 if (drv_data
&& drv_data
->set_ios
)
810 drv_data
->set_ios(slot
->host
, ios
);
812 /* Slot specific timing and width adjustment */
813 dw_mci_setup_bus(slot
, false);
815 switch (ios
->power_mode
) {
817 set_bit(DW_MMC_CARD_NEED_INIT
, &slot
->flags
);
824 static int dw_mci_get_ro(struct mmc_host
*mmc
)
827 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
828 struct dw_mci_board
*brd
= slot
->host
->pdata
;
830 /* Use platform get_ro function, else try on board write protect */
831 if (brd
->quirks
& DW_MCI_QUIRK_NO_WRITE_PROTECT
)
833 else if (brd
->get_ro
)
834 read_only
= brd
->get_ro(slot
->id
);
837 mci_readl(slot
->host
, WRTPRT
) & (1 << slot
->id
) ? 1 : 0;
839 dev_dbg(&mmc
->class_dev
, "card is %s\n",
840 read_only
? "read-only" : "read-write");
845 static int dw_mci_get_cd(struct mmc_host
*mmc
)
848 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
849 struct dw_mci_board
*brd
= slot
->host
->pdata
;
851 /* Use platform get_cd function, else try onboard card detect */
852 if (brd
->quirks
& DW_MCI_QUIRK_BROKEN_CARD_DETECTION
)
854 else if (brd
->get_cd
)
855 present
= !brd
->get_cd(slot
->id
);
857 present
= (mci_readl(slot
->host
, CDETECT
) & (1 << slot
->id
))
861 dev_dbg(&mmc
->class_dev
, "card is present\n");
863 dev_dbg(&mmc
->class_dev
, "card is not present\n");
869 * Disable lower power mode.
871 * Low power mode will stop the card clock when idle. According to the
872 * description of the CLKENA register we should disable low power mode
873 * for SDIO cards if we need SDIO interrupts to work.
875 * This function is fast if low power mode is already disabled.
877 static void dw_mci_disable_low_power(struct dw_mci_slot
*slot
)
879 struct dw_mci
*host
= slot
->host
;
881 const u32 clken_low_pwr
= SDMMC_CLKEN_LOW_PWR
<< slot
->id
;
883 clk_en_a
= mci_readl(host
, CLKENA
);
885 if (clk_en_a
& clken_low_pwr
) {
886 mci_writel(host
, CLKENA
, clk_en_a
& ~clken_low_pwr
);
887 mci_send_cmd(slot
, SDMMC_CMD_UPD_CLK
|
888 SDMMC_CMD_PRV_DAT_WAIT
, 0);
892 static void dw_mci_enable_sdio_irq(struct mmc_host
*mmc
, int enb
)
894 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
895 struct dw_mci
*host
= slot
->host
;
898 /* Enable/disable Slot Specific SDIO interrupt */
899 int_mask
= mci_readl(host
, INTMASK
);
902 * Turn off low power mode if it was enabled. This is a bit of
903 * a heavy operation and we disable / enable IRQs a lot, so
904 * we'll leave low power mode disabled and it will get
905 * re-enabled again in dw_mci_setup_bus().
907 dw_mci_disable_low_power(slot
);
909 mci_writel(host
, INTMASK
,
910 (int_mask
| SDMMC_INT_SDIO(slot
->id
)));
912 mci_writel(host
, INTMASK
,
913 (int_mask
& ~SDMMC_INT_SDIO(slot
->id
)));
917 static const struct mmc_host_ops dw_mci_ops
= {
918 .request
= dw_mci_request
,
919 .pre_req
= dw_mci_pre_req
,
920 .post_req
= dw_mci_post_req
,
921 .set_ios
= dw_mci_set_ios
,
922 .get_ro
= dw_mci_get_ro
,
923 .get_cd
= dw_mci_get_cd
,
924 .enable_sdio_irq
= dw_mci_enable_sdio_irq
,
927 static void dw_mci_request_end(struct dw_mci
*host
, struct mmc_request
*mrq
)
928 __releases(&host
->lock
)
929 __acquires(&host
->lock
)
931 struct dw_mci_slot
*slot
;
932 struct mmc_host
*prev_mmc
= host
->cur_slot
->mmc
;
934 WARN_ON(host
->cmd
|| host
->data
);
936 host
->cur_slot
->mrq
= NULL
;
938 if (!list_empty(&host
->queue
)) {
939 slot
= list_entry(host
->queue
.next
,
940 struct dw_mci_slot
, queue_node
);
941 list_del(&slot
->queue_node
);
942 dev_vdbg(host
->dev
, "list not empty: %s is next\n",
943 mmc_hostname(slot
->mmc
));
944 host
->state
= STATE_SENDING_CMD
;
945 dw_mci_start_request(host
, slot
);
947 dev_vdbg(host
->dev
, "list empty\n");
948 host
->state
= STATE_IDLE
;
951 spin_unlock(&host
->lock
);
952 mmc_request_done(prev_mmc
, mrq
);
953 spin_lock(&host
->lock
);
956 static void dw_mci_command_complete(struct dw_mci
*host
, struct mmc_command
*cmd
)
958 u32 status
= host
->cmd_status
;
960 host
->cmd_status
= 0;
962 /* Read the response from the card (up to 16 bytes) */
963 if (cmd
->flags
& MMC_RSP_PRESENT
) {
964 if (cmd
->flags
& MMC_RSP_136
) {
965 cmd
->resp
[3] = mci_readl(host
, RESP0
);
966 cmd
->resp
[2] = mci_readl(host
, RESP1
);
967 cmd
->resp
[1] = mci_readl(host
, RESP2
);
968 cmd
->resp
[0] = mci_readl(host
, RESP3
);
970 cmd
->resp
[0] = mci_readl(host
, RESP0
);
977 if (status
& SDMMC_INT_RTO
)
978 cmd
->error
= -ETIMEDOUT
;
979 else if ((cmd
->flags
& MMC_RSP_CRC
) && (status
& SDMMC_INT_RCRC
))
980 cmd
->error
= -EILSEQ
;
981 else if (status
& SDMMC_INT_RESP_ERR
)
987 /* newer ip versions need a delay between retries */
988 if (host
->quirks
& DW_MCI_QUIRK_RETRY_DELAY
)
992 dw_mci_stop_dma(host
);
998 static void dw_mci_tasklet_func(unsigned long priv
)
1000 struct dw_mci
*host
= (struct dw_mci
*)priv
;
1001 struct mmc_data
*data
;
1002 struct mmc_command
*cmd
;
1003 enum dw_mci_state state
;
1004 enum dw_mci_state prev_state
;
1007 spin_lock(&host
->lock
);
1009 state
= host
->state
;
1019 case STATE_SENDING_CMD
:
1020 if (!test_and_clear_bit(EVENT_CMD_COMPLETE
,
1021 &host
->pending_events
))
1026 set_bit(EVENT_CMD_COMPLETE
, &host
->completed_events
);
1027 dw_mci_command_complete(host
, cmd
);
1028 if (cmd
== host
->mrq
->sbc
&& !cmd
->error
) {
1029 prev_state
= state
= STATE_SENDING_CMD
;
1030 __dw_mci_start_request(host
, host
->cur_slot
,
1035 if (!host
->mrq
->data
|| cmd
->error
) {
1036 dw_mci_request_end(host
, host
->mrq
);
1040 prev_state
= state
= STATE_SENDING_DATA
;
1043 case STATE_SENDING_DATA
:
1044 if (test_and_clear_bit(EVENT_DATA_ERROR
,
1045 &host
->pending_events
)) {
1046 dw_mci_stop_dma(host
);
1048 send_stop_cmd(host
, data
);
1049 state
= STATE_DATA_ERROR
;
1053 if (!test_and_clear_bit(EVENT_XFER_COMPLETE
,
1054 &host
->pending_events
))
1057 set_bit(EVENT_XFER_COMPLETE
, &host
->completed_events
);
1058 prev_state
= state
= STATE_DATA_BUSY
;
1061 case STATE_DATA_BUSY
:
1062 if (!test_and_clear_bit(EVENT_DATA_COMPLETE
,
1063 &host
->pending_events
))
1067 set_bit(EVENT_DATA_COMPLETE
, &host
->completed_events
);
1068 status
= host
->data_status
;
1070 if (status
& DW_MCI_DATA_ERROR_FLAGS
) {
1071 if (status
& SDMMC_INT_DTO
) {
1072 data
->error
= -ETIMEDOUT
;
1073 } else if (status
& SDMMC_INT_DCRC
) {
1074 data
->error
= -EILSEQ
;
1075 } else if (status
& SDMMC_INT_EBE
&&
1077 DW_MCI_SEND_STATUS
) {
1079 * No data CRC status was returned.
1080 * The number of bytes transferred will
1081 * be exaggerated in PIO mode.
1083 data
->bytes_xfered
= 0;
1084 data
->error
= -ETIMEDOUT
;
1093 * After an error, there may be data lingering
1094 * in the FIFO, so reset it - doing so
1095 * generates a block interrupt, hence setting
1096 * the scatter-gather pointer to NULL.
1098 sg_miter_stop(&host
->sg_miter
);
1100 ctrl
= mci_readl(host
, CTRL
);
1101 ctrl
|= SDMMC_CTRL_FIFO_RESET
;
1102 mci_writel(host
, CTRL
, ctrl
);
1104 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
1109 dw_mci_request_end(host
, host
->mrq
);
1113 if (host
->mrq
->sbc
&& !data
->error
) {
1114 data
->stop
->error
= 0;
1115 dw_mci_request_end(host
, host
->mrq
);
1119 prev_state
= state
= STATE_SENDING_STOP
;
1121 send_stop_cmd(host
, data
);
1124 case STATE_SENDING_STOP
:
1125 if (!test_and_clear_bit(EVENT_CMD_COMPLETE
,
1126 &host
->pending_events
))
1130 dw_mci_command_complete(host
, host
->mrq
->stop
);
1131 dw_mci_request_end(host
, host
->mrq
);
1134 case STATE_DATA_ERROR
:
1135 if (!test_and_clear_bit(EVENT_XFER_COMPLETE
,
1136 &host
->pending_events
))
1139 state
= STATE_DATA_BUSY
;
1142 } while (state
!= prev_state
);
1144 host
->state
= state
;
1146 spin_unlock(&host
->lock
);
1150 /* push final bytes to part_buf, only use during push */
1151 static void dw_mci_set_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
1153 memcpy((void *)&host
->part_buf
, buf
, cnt
);
1154 host
->part_buf_count
= cnt
;
1157 /* append bytes to part_buf, only use during push */
1158 static int dw_mci_push_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
1160 cnt
= min(cnt
, (1 << host
->data_shift
) - host
->part_buf_count
);
1161 memcpy((void *)&host
->part_buf
+ host
->part_buf_count
, buf
, cnt
);
1162 host
->part_buf_count
+= cnt
;
1166 /* pull first bytes from part_buf, only use during pull */
1167 static int dw_mci_pull_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
1169 cnt
= min(cnt
, (int)host
->part_buf_count
);
1171 memcpy(buf
, (void *)&host
->part_buf
+ host
->part_buf_start
,
1173 host
->part_buf_count
-= cnt
;
1174 host
->part_buf_start
+= cnt
;
1179 /* pull final bytes from the part_buf, assuming it's just been filled */
1180 static void dw_mci_pull_final_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
1182 memcpy(buf
, &host
->part_buf
, cnt
);
1183 host
->part_buf_start
= cnt
;
1184 host
->part_buf_count
= (1 << host
->data_shift
) - cnt
;
1187 static void dw_mci_push_data16(struct dw_mci
*host
, void *buf
, int cnt
)
1189 /* try and push anything in the part_buf */
1190 if (unlikely(host
->part_buf_count
)) {
1191 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
1194 if (!sg_next(host
->sg
) || host
->part_buf_count
== 2) {
1195 mci_writew(host
, DATA(host
->data_offset
),
1197 host
->part_buf_count
= 0;
1200 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1201 if (unlikely((unsigned long)buf
& 0x1)) {
1203 u16 aligned_buf
[64];
1204 int len
= min(cnt
& -2, (int)sizeof(aligned_buf
));
1205 int items
= len
>> 1;
1207 /* memcpy from input buffer into aligned buffer */
1208 memcpy(aligned_buf
, buf
, len
);
1211 /* push data from aligned buffer into fifo */
1212 for (i
= 0; i
< items
; ++i
)
1213 mci_writew(host
, DATA(host
->data_offset
),
1220 for (; cnt
>= 2; cnt
-= 2)
1221 mci_writew(host
, DATA(host
->data_offset
), *pdata
++);
1224 /* put anything remaining in the part_buf */
1226 dw_mci_set_part_bytes(host
, buf
, cnt
);
1227 if (!sg_next(host
->sg
))
1228 mci_writew(host
, DATA(host
->data_offset
),
1233 static void dw_mci_pull_data16(struct dw_mci
*host
, void *buf
, int cnt
)
1235 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1236 if (unlikely((unsigned long)buf
& 0x1)) {
1238 /* pull data from fifo into aligned buffer */
1239 u16 aligned_buf
[64];
1240 int len
= min(cnt
& -2, (int)sizeof(aligned_buf
));
1241 int items
= len
>> 1;
1243 for (i
= 0; i
< items
; ++i
)
1244 aligned_buf
[i
] = mci_readw(host
,
1245 DATA(host
->data_offset
));
1246 /* memcpy from aligned buffer into output buffer */
1247 memcpy(buf
, aligned_buf
, len
);
1255 for (; cnt
>= 2; cnt
-= 2)
1256 *pdata
++ = mci_readw(host
, DATA(host
->data_offset
));
1260 host
->part_buf16
= mci_readw(host
, DATA(host
->data_offset
));
1261 dw_mci_pull_final_bytes(host
, buf
, cnt
);
1265 static void dw_mci_push_data32(struct dw_mci
*host
, void *buf
, int cnt
)
1267 /* try and push anything in the part_buf */
1268 if (unlikely(host
->part_buf_count
)) {
1269 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
1272 if (!sg_next(host
->sg
) || host
->part_buf_count
== 4) {
1273 mci_writel(host
, DATA(host
->data_offset
),
1275 host
->part_buf_count
= 0;
1278 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1279 if (unlikely((unsigned long)buf
& 0x3)) {
1281 u32 aligned_buf
[32];
1282 int len
= min(cnt
& -4, (int)sizeof(aligned_buf
));
1283 int items
= len
>> 2;
1285 /* memcpy from input buffer into aligned buffer */
1286 memcpy(aligned_buf
, buf
, len
);
1289 /* push data from aligned buffer into fifo */
1290 for (i
= 0; i
< items
; ++i
)
1291 mci_writel(host
, DATA(host
->data_offset
),
1298 for (; cnt
>= 4; cnt
-= 4)
1299 mci_writel(host
, DATA(host
->data_offset
), *pdata
++);
1302 /* put anything remaining in the part_buf */
1304 dw_mci_set_part_bytes(host
, buf
, cnt
);
1305 if (!sg_next(host
->sg
))
1306 mci_writel(host
, DATA(host
->data_offset
),
1311 static void dw_mci_pull_data32(struct dw_mci
*host
, void *buf
, int cnt
)
1313 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1314 if (unlikely((unsigned long)buf
& 0x3)) {
1316 /* pull data from fifo into aligned buffer */
1317 u32 aligned_buf
[32];
1318 int len
= min(cnt
& -4, (int)sizeof(aligned_buf
));
1319 int items
= len
>> 2;
1321 for (i
= 0; i
< items
; ++i
)
1322 aligned_buf
[i
] = mci_readl(host
,
1323 DATA(host
->data_offset
));
1324 /* memcpy from aligned buffer into output buffer */
1325 memcpy(buf
, aligned_buf
, len
);
1333 for (; cnt
>= 4; cnt
-= 4)
1334 *pdata
++ = mci_readl(host
, DATA(host
->data_offset
));
1338 host
->part_buf32
= mci_readl(host
, DATA(host
->data_offset
));
1339 dw_mci_pull_final_bytes(host
, buf
, cnt
);
1343 static void dw_mci_push_data64(struct dw_mci
*host
, void *buf
, int cnt
)
1345 /* try and push anything in the part_buf */
1346 if (unlikely(host
->part_buf_count
)) {
1347 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
1350 if (!sg_next(host
->sg
) || host
->part_buf_count
== 8) {
1351 mci_writew(host
, DATA(host
->data_offset
),
1353 host
->part_buf_count
= 0;
1356 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1357 if (unlikely((unsigned long)buf
& 0x7)) {
1359 u64 aligned_buf
[16];
1360 int len
= min(cnt
& -8, (int)sizeof(aligned_buf
));
1361 int items
= len
>> 3;
1363 /* memcpy from input buffer into aligned buffer */
1364 memcpy(aligned_buf
, buf
, len
);
1367 /* push data from aligned buffer into fifo */
1368 for (i
= 0; i
< items
; ++i
)
1369 mci_writeq(host
, DATA(host
->data_offset
),
1376 for (; cnt
>= 8; cnt
-= 8)
1377 mci_writeq(host
, DATA(host
->data_offset
), *pdata
++);
1380 /* put anything remaining in the part_buf */
1382 dw_mci_set_part_bytes(host
, buf
, cnt
);
1383 if (!sg_next(host
->sg
))
1384 mci_writeq(host
, DATA(host
->data_offset
),
1389 static void dw_mci_pull_data64(struct dw_mci
*host
, void *buf
, int cnt
)
1391 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1392 if (unlikely((unsigned long)buf
& 0x7)) {
1394 /* pull data from fifo into aligned buffer */
1395 u64 aligned_buf
[16];
1396 int len
= min(cnt
& -8, (int)sizeof(aligned_buf
));
1397 int items
= len
>> 3;
1399 for (i
= 0; i
< items
; ++i
)
1400 aligned_buf
[i
] = mci_readq(host
,
1401 DATA(host
->data_offset
));
1402 /* memcpy from aligned buffer into output buffer */
1403 memcpy(buf
, aligned_buf
, len
);
1411 for (; cnt
>= 8; cnt
-= 8)
1412 *pdata
++ = mci_readq(host
, DATA(host
->data_offset
));
1416 host
->part_buf
= mci_readq(host
, DATA(host
->data_offset
));
1417 dw_mci_pull_final_bytes(host
, buf
, cnt
);
1421 static void dw_mci_pull_data(struct dw_mci
*host
, void *buf
, int cnt
)
1425 /* get remaining partial bytes */
1426 len
= dw_mci_pull_part_bytes(host
, buf
, cnt
);
1427 if (unlikely(len
== cnt
))
1432 /* get the rest of the data */
1433 host
->pull_data(host
, buf
, cnt
);
1436 static void dw_mci_read_data_pio(struct dw_mci
*host
)
1438 struct sg_mapping_iter
*sg_miter
= &host
->sg_miter
;
1440 unsigned int offset
;
1441 struct mmc_data
*data
= host
->data
;
1442 int shift
= host
->data_shift
;
1444 unsigned int nbytes
= 0, len
;
1445 unsigned int remain
, fcnt
;
1448 if (!sg_miter_next(sg_miter
))
1451 host
->sg
= sg_miter
->__sg
;
1452 buf
= sg_miter
->addr
;
1453 remain
= sg_miter
->length
;
1457 fcnt
= (SDMMC_GET_FCNT(mci_readl(host
, STATUS
))
1458 << shift
) + host
->part_buf_count
;
1459 len
= min(remain
, fcnt
);
1462 dw_mci_pull_data(host
, (void *)(buf
+ offset
), len
);
1468 sg_miter
->consumed
= offset
;
1469 status
= mci_readl(host
, MINTSTS
);
1470 mci_writel(host
, RINTSTS
, SDMMC_INT_RXDR
);
1471 } while (status
& SDMMC_INT_RXDR
); /*if the RXDR is ready read again*/
1472 data
->bytes_xfered
+= nbytes
;
1475 if (!sg_miter_next(sg_miter
))
1477 sg_miter
->consumed
= 0;
1479 sg_miter_stop(sg_miter
);
1483 data
->bytes_xfered
+= nbytes
;
1484 sg_miter_stop(sg_miter
);
1487 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
1490 static void dw_mci_write_data_pio(struct dw_mci
*host
)
1492 struct sg_mapping_iter
*sg_miter
= &host
->sg_miter
;
1494 unsigned int offset
;
1495 struct mmc_data
*data
= host
->data
;
1496 int shift
= host
->data_shift
;
1498 unsigned int nbytes
= 0, len
;
1499 unsigned int fifo_depth
= host
->fifo_depth
;
1500 unsigned int remain
, fcnt
;
1503 if (!sg_miter_next(sg_miter
))
1506 host
->sg
= sg_miter
->__sg
;
1507 buf
= sg_miter
->addr
;
1508 remain
= sg_miter
->length
;
1512 fcnt
= ((fifo_depth
-
1513 SDMMC_GET_FCNT(mci_readl(host
, STATUS
)))
1514 << shift
) - host
->part_buf_count
;
1515 len
= min(remain
, fcnt
);
1518 host
->push_data(host
, (void *)(buf
+ offset
), len
);
1524 sg_miter
->consumed
= offset
;
1525 status
= mci_readl(host
, MINTSTS
);
1526 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
);
1527 } while (status
& SDMMC_INT_TXDR
); /* if TXDR write again */
1528 data
->bytes_xfered
+= nbytes
;
1531 if (!sg_miter_next(sg_miter
))
1533 sg_miter
->consumed
= 0;
1535 sg_miter_stop(sg_miter
);
1539 data
->bytes_xfered
+= nbytes
;
1540 sg_miter_stop(sg_miter
);
1543 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
1546 static void dw_mci_cmd_interrupt(struct dw_mci
*host
, u32 status
)
1548 if (!host
->cmd_status
)
1549 host
->cmd_status
= status
;
1553 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
1554 tasklet_schedule(&host
->tasklet
);
1557 static irqreturn_t
dw_mci_interrupt(int irq
, void *dev_id
)
1559 struct dw_mci
*host
= dev_id
;
1561 unsigned int pass_count
= 0;
1565 pending
= mci_readl(host
, MINTSTS
); /* read-only mask reg */
1568 * DTO fix - version 2.10a and below, and only if internal DMA
1571 if (host
->quirks
& DW_MCI_QUIRK_IDMAC_DTO
) {
1573 ((mci_readl(host
, STATUS
) >> 17) & 0x1fff))
1574 pending
|= SDMMC_INT_DATA_OVER
;
1580 if (pending
& DW_MCI_CMD_ERROR_FLAGS
) {
1581 mci_writel(host
, RINTSTS
, DW_MCI_CMD_ERROR_FLAGS
);
1582 host
->cmd_status
= pending
;
1584 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
1587 if (pending
& DW_MCI_DATA_ERROR_FLAGS
) {
1588 /* if there is an error report DATA_ERROR */
1589 mci_writel(host
, RINTSTS
, DW_MCI_DATA_ERROR_FLAGS
);
1590 host
->data_status
= pending
;
1592 set_bit(EVENT_DATA_ERROR
, &host
->pending_events
);
1593 tasklet_schedule(&host
->tasklet
);
1596 if (pending
& SDMMC_INT_DATA_OVER
) {
1597 mci_writel(host
, RINTSTS
, SDMMC_INT_DATA_OVER
);
1598 if (!host
->data_status
)
1599 host
->data_status
= pending
;
1601 if (host
->dir_status
== DW_MCI_RECV_STATUS
) {
1602 if (host
->sg
!= NULL
)
1603 dw_mci_read_data_pio(host
);
1605 set_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
);
1606 tasklet_schedule(&host
->tasklet
);
1609 if (pending
& SDMMC_INT_RXDR
) {
1610 mci_writel(host
, RINTSTS
, SDMMC_INT_RXDR
);
1611 if (host
->dir_status
== DW_MCI_RECV_STATUS
&& host
->sg
)
1612 dw_mci_read_data_pio(host
);
1615 if (pending
& SDMMC_INT_TXDR
) {
1616 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
);
1617 if (host
->dir_status
== DW_MCI_SEND_STATUS
&& host
->sg
)
1618 dw_mci_write_data_pio(host
);
1621 if (pending
& SDMMC_INT_CMD_DONE
) {
1622 mci_writel(host
, RINTSTS
, SDMMC_INT_CMD_DONE
);
1623 dw_mci_cmd_interrupt(host
, pending
);
1626 if (pending
& SDMMC_INT_CD
) {
1627 mci_writel(host
, RINTSTS
, SDMMC_INT_CD
);
1628 queue_work(host
->card_workqueue
, &host
->card_work
);
1631 /* Handle SDIO Interrupts */
1632 for (i
= 0; i
< host
->num_slots
; i
++) {
1633 struct dw_mci_slot
*slot
= host
->slot
[i
];
1634 if (pending
& SDMMC_INT_SDIO(i
)) {
1635 mci_writel(host
, RINTSTS
, SDMMC_INT_SDIO(i
));
1636 mmc_signal_sdio_irq(slot
->mmc
);
1640 } while (pass_count
++ < 5);
1642 #ifdef CONFIG_MMC_DW_IDMAC
1643 /* Handle DMA interrupts */
1644 pending
= mci_readl(host
, IDSTS
);
1645 if (pending
& (SDMMC_IDMAC_INT_TI
| SDMMC_IDMAC_INT_RI
)) {
1646 mci_writel(host
, IDSTS
, SDMMC_IDMAC_INT_TI
| SDMMC_IDMAC_INT_RI
);
1647 mci_writel(host
, IDSTS
, SDMMC_IDMAC_INT_NI
);
1648 host
->dma_ops
->complete(host
);
1655 static void dw_mci_work_routine_card(struct work_struct
*work
)
1657 struct dw_mci
*host
= container_of(work
, struct dw_mci
, card_work
);
1660 for (i
= 0; i
< host
->num_slots
; i
++) {
1661 struct dw_mci_slot
*slot
= host
->slot
[i
];
1662 struct mmc_host
*mmc
= slot
->mmc
;
1663 struct mmc_request
*mrq
;
1667 present
= dw_mci_get_cd(mmc
);
1668 while (present
!= slot
->last_detect_state
) {
1669 dev_dbg(&slot
->mmc
->class_dev
, "card %s\n",
1670 present
? "inserted" : "removed");
1672 /* Power up slot (before spin_lock, may sleep) */
1673 if (present
!= 0 && host
->pdata
->setpower
)
1674 host
->pdata
->setpower(slot
->id
, mmc
->ocr_avail
);
1676 spin_lock_bh(&host
->lock
);
1678 /* Card change detected */
1679 slot
->last_detect_state
= present
;
1681 /* Mark card as present if applicable */
1683 set_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
);
1685 /* Clean up queue if present */
1688 if (mrq
== host
->mrq
) {
1692 switch (host
->state
) {
1695 case STATE_SENDING_CMD
:
1696 mrq
->cmd
->error
= -ENOMEDIUM
;
1700 case STATE_SENDING_DATA
:
1701 mrq
->data
->error
= -ENOMEDIUM
;
1702 dw_mci_stop_dma(host
);
1704 case STATE_DATA_BUSY
:
1705 case STATE_DATA_ERROR
:
1706 if (mrq
->data
->error
== -EINPROGRESS
)
1707 mrq
->data
->error
= -ENOMEDIUM
;
1711 case STATE_SENDING_STOP
:
1712 mrq
->stop
->error
= -ENOMEDIUM
;
1716 dw_mci_request_end(host
, mrq
);
1718 list_del(&slot
->queue_node
);
1719 mrq
->cmd
->error
= -ENOMEDIUM
;
1721 mrq
->data
->error
= -ENOMEDIUM
;
1723 mrq
->stop
->error
= -ENOMEDIUM
;
1725 spin_unlock(&host
->lock
);
1726 mmc_request_done(slot
->mmc
, mrq
);
1727 spin_lock(&host
->lock
);
1731 /* Power down slot */
1733 clear_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
);
1736 * Clear down the FIFO - doing so generates a
1737 * block interrupt, hence setting the
1738 * scatter-gather pointer to NULL.
1740 sg_miter_stop(&host
->sg_miter
);
1743 ctrl
= mci_readl(host
, CTRL
);
1744 ctrl
|= SDMMC_CTRL_FIFO_RESET
;
1745 mci_writel(host
, CTRL
, ctrl
);
1747 #ifdef CONFIG_MMC_DW_IDMAC
1748 ctrl
= mci_readl(host
, BMOD
);
1749 /* Software reset of DMA */
1750 ctrl
|= SDMMC_IDMAC_SWRESET
;
1751 mci_writel(host
, BMOD
, ctrl
);
1756 spin_unlock_bh(&host
->lock
);
1758 /* Power down slot (after spin_unlock, may sleep) */
1759 if (present
== 0 && host
->pdata
->setpower
)
1760 host
->pdata
->setpower(slot
->id
, 0);
1762 present
= dw_mci_get_cd(mmc
);
1765 mmc_detect_change(slot
->mmc
,
1766 msecs_to_jiffies(host
->pdata
->detect_delay_ms
));
1771 /* given a slot id, find out the device node representing that slot */
1772 static struct device_node
*dw_mci_of_find_slot_node(struct device
*dev
, u8 slot
)
1774 struct device_node
*np
;
1778 if (!dev
|| !dev
->of_node
)
1781 for_each_child_of_node(dev
->of_node
, np
) {
1782 addr
= of_get_property(np
, "reg", &len
);
1783 if (!addr
|| (len
< sizeof(int)))
1785 if (be32_to_cpup(addr
) == slot
)
1791 /* find out bus-width for a given slot */
1792 static u32
dw_mci_of_get_bus_wd(struct device
*dev
, u8 slot
)
1794 struct device_node
*np
= dw_mci_of_find_slot_node(dev
, slot
);
1800 if (of_property_read_u32(np
, "bus-width", &bus_wd
))
1801 dev_err(dev
, "bus-width property not found, assuming width"
1805 #else /* CONFIG_OF */
1806 static u32
dw_mci_of_get_bus_wd(struct device
*dev
, u8 slot
)
1810 static struct device_node
*dw_mci_of_find_slot_node(struct device
*dev
, u8 slot
)
1814 #endif /* CONFIG_OF */
1816 static int dw_mci_init_slot(struct dw_mci
*host
, unsigned int id
)
1818 struct mmc_host
*mmc
;
1819 struct dw_mci_slot
*slot
;
1820 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
1824 mmc
= mmc_alloc_host(sizeof(struct dw_mci_slot
), host
->dev
);
1828 slot
= mmc_priv(mmc
);
1832 host
->slot
[id
] = slot
;
1834 mmc
->ops
= &dw_mci_ops
;
1835 mmc
->f_min
= DIV_ROUND_UP(host
->bus_hz
, 510);
1836 mmc
->f_max
= host
->bus_hz
;
1838 if (host
->pdata
->get_ocr
)
1839 mmc
->ocr_avail
= host
->pdata
->get_ocr(id
);
1841 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
;
1844 * Start with slot power disabled, it will be enabled when a card
1847 if (host
->pdata
->setpower
)
1848 host
->pdata
->setpower(id
, 0);
1850 if (host
->pdata
->caps
)
1851 mmc
->caps
= host
->pdata
->caps
;
1853 if (host
->pdata
->pm_caps
)
1854 mmc
->pm_caps
= host
->pdata
->pm_caps
;
1856 if (host
->dev
->of_node
) {
1857 ctrl_id
= of_alias_get_id(host
->dev
->of_node
, "mshc");
1861 ctrl_id
= to_platform_device(host
->dev
)->id
;
1863 if (drv_data
&& drv_data
->caps
)
1864 mmc
->caps
|= drv_data
->caps
[ctrl_id
];
1866 if (host
->pdata
->caps2
)
1867 mmc
->caps2
= host
->pdata
->caps2
;
1869 if (host
->pdata
->get_bus_wd
)
1870 bus_width
= host
->pdata
->get_bus_wd(slot
->id
);
1871 else if (host
->dev
->of_node
)
1872 bus_width
= dw_mci_of_get_bus_wd(host
->dev
, slot
->id
);
1876 if (drv_data
&& drv_data
->setup_bus
) {
1877 struct device_node
*slot_np
;
1878 slot_np
= dw_mci_of_find_slot_node(host
->dev
, slot
->id
);
1879 ret
= drv_data
->setup_bus(host
, slot_np
, bus_width
);
1884 switch (bus_width
) {
1886 mmc
->caps
|= MMC_CAP_8_BIT_DATA
;
1888 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
1891 if (host
->pdata
->quirks
& DW_MCI_QUIRK_HIGHSPEED
)
1892 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
| MMC_CAP_MMC_HIGHSPEED
;
1894 if (host
->pdata
->blk_settings
) {
1895 mmc
->max_segs
= host
->pdata
->blk_settings
->max_segs
;
1896 mmc
->max_blk_size
= host
->pdata
->blk_settings
->max_blk_size
;
1897 mmc
->max_blk_count
= host
->pdata
->blk_settings
->max_blk_count
;
1898 mmc
->max_req_size
= host
->pdata
->blk_settings
->max_req_size
;
1899 mmc
->max_seg_size
= host
->pdata
->blk_settings
->max_seg_size
;
1901 /* Useful defaults if platform data is unset. */
1902 #ifdef CONFIG_MMC_DW_IDMAC
1903 mmc
->max_segs
= host
->ring_size
;
1904 mmc
->max_blk_size
= 65536;
1905 mmc
->max_blk_count
= host
->ring_size
;
1906 mmc
->max_seg_size
= 0x1000;
1907 mmc
->max_req_size
= mmc
->max_seg_size
* mmc
->max_blk_count
;
1910 mmc
->max_blk_size
= 65536; /* BLKSIZ is 16 bits */
1911 mmc
->max_blk_count
= 512;
1912 mmc
->max_req_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
1913 mmc
->max_seg_size
= mmc
->max_req_size
;
1914 #endif /* CONFIG_MMC_DW_IDMAC */
1917 host
->vmmc
= devm_regulator_get(mmc_dev(mmc
), "vmmc");
1918 if (IS_ERR(host
->vmmc
)) {
1919 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc
));
1922 regulator_enable(host
->vmmc
);
1924 if (dw_mci_get_cd(mmc
))
1925 set_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
);
1927 clear_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
);
1931 #if defined(CONFIG_DEBUG_FS)
1932 dw_mci_init_debugfs(slot
);
1935 /* Card initially undetected */
1936 slot
->last_detect_state
= 0;
1939 * Card may have been plugged in prior to boot so we
1940 * need to run the detect tasklet
1942 queue_work(host
->card_workqueue
, &host
->card_work
);
1951 static void dw_mci_cleanup_slot(struct dw_mci_slot
*slot
, unsigned int id
)
1953 /* Shutdown detect IRQ */
1954 if (slot
->host
->pdata
->exit
)
1955 slot
->host
->pdata
->exit(id
);
1957 /* Debugfs stuff is cleaned up by mmc core */
1958 mmc_remove_host(slot
->mmc
);
1959 slot
->host
->slot
[id
] = NULL
;
1960 mmc_free_host(slot
->mmc
);
1963 static void dw_mci_init_dma(struct dw_mci
*host
)
1965 /* Alloc memory for sg translation */
1966 host
->sg_cpu
= dmam_alloc_coherent(host
->dev
, PAGE_SIZE
,
1967 &host
->sg_dma
, GFP_KERNEL
);
1968 if (!host
->sg_cpu
) {
1969 dev_err(host
->dev
, "%s: could not alloc DMA memory\n",
1974 /* Determine which DMA interface to use */
1975 #ifdef CONFIG_MMC_DW_IDMAC
1976 host
->dma_ops
= &dw_mci_idmac_ops
;
1977 dev_info(host
->dev
, "Using internal DMA controller.\n");
1983 if (host
->dma_ops
->init
&& host
->dma_ops
->start
&&
1984 host
->dma_ops
->stop
&& host
->dma_ops
->cleanup
) {
1985 if (host
->dma_ops
->init(host
)) {
1986 dev_err(host
->dev
, "%s: Unable to initialize "
1987 "DMA Controller.\n", __func__
);
1991 dev_err(host
->dev
, "DMA initialization not found.\n");
1999 dev_info(host
->dev
, "Using PIO mode.\n");
2004 static bool mci_wait_reset(struct device
*dev
, struct dw_mci
*host
)
2006 unsigned long timeout
= jiffies
+ msecs_to_jiffies(500);
2009 mci_writel(host
, CTRL
, (SDMMC_CTRL_RESET
| SDMMC_CTRL_FIFO_RESET
|
2010 SDMMC_CTRL_DMA_RESET
));
2012 /* wait till resets clear */
2014 ctrl
= mci_readl(host
, CTRL
);
2015 if (!(ctrl
& (SDMMC_CTRL_RESET
| SDMMC_CTRL_FIFO_RESET
|
2016 SDMMC_CTRL_DMA_RESET
)))
2018 } while (time_before(jiffies
, timeout
));
2020 dev_err(dev
, "Timeout resetting block (ctrl %#x)\n", ctrl
);
2026 static struct dw_mci_of_quirks
{
2031 .quirk
= "supports-highspeed",
2032 .id
= DW_MCI_QUIRK_HIGHSPEED
,
2034 .quirk
= "broken-cd",
2035 .id
= DW_MCI_QUIRK_BROKEN_CARD_DETECTION
,
2039 static struct dw_mci_board
*dw_mci_parse_dt(struct dw_mci
*host
)
2041 struct dw_mci_board
*pdata
;
2042 struct device
*dev
= host
->dev
;
2043 struct device_node
*np
= dev
->of_node
;
2044 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
2047 pdata
= devm_kzalloc(dev
, sizeof(*pdata
), GFP_KERNEL
);
2049 dev_err(dev
, "could not allocate memory for pdata\n");
2050 return ERR_PTR(-ENOMEM
);
2053 /* find out number of slots supported */
2054 if (of_property_read_u32(dev
->of_node
, "num-slots",
2055 &pdata
->num_slots
)) {
2056 dev_info(dev
, "num-slots property not found, "
2057 "assuming 1 slot is available\n");
2058 pdata
->num_slots
= 1;
2062 for (idx
= 0; idx
< ARRAY_SIZE(of_quirks
); idx
++)
2063 if (of_get_property(np
, of_quirks
[idx
].quirk
, NULL
))
2064 pdata
->quirks
|= of_quirks
[idx
].id
;
2066 if (of_property_read_u32(np
, "fifo-depth", &pdata
->fifo_depth
))
2067 dev_info(dev
, "fifo-depth property not found, using "
2068 "value of FIFOTH register as default\n");
2070 of_property_read_u32(np
, "card-detect-delay", &pdata
->detect_delay_ms
);
2072 if (drv_data
&& drv_data
->parse_dt
) {
2073 ret
= drv_data
->parse_dt(host
);
2075 return ERR_PTR(ret
);
2078 if (of_find_property(np
, "keep-power-in-suspend", NULL
))
2079 pdata
->pm_caps
|= MMC_PM_KEEP_POWER
;
2081 if (of_find_property(np
, "enable-sdio-wakeup", NULL
))
2082 pdata
->pm_caps
|= MMC_PM_WAKE_SDIO_IRQ
;
2087 #else /* CONFIG_OF */
2088 static struct dw_mci_board
*dw_mci_parse_dt(struct dw_mci
*host
)
2090 return ERR_PTR(-EINVAL
);
2092 #endif /* CONFIG_OF */
2094 int dw_mci_probe(struct dw_mci
*host
)
2096 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
2097 int width
, i
, ret
= 0;
2102 host
->pdata
= dw_mci_parse_dt(host
);
2103 if (IS_ERR(host
->pdata
)) {
2104 dev_err(host
->dev
, "platform data not available\n");
2109 if (!host
->pdata
->select_slot
&& host
->pdata
->num_slots
> 1) {
2111 "Platform data must supply select_slot function\n");
2115 host
->biu_clk
= devm_clk_get(host
->dev
, "biu");
2116 if (IS_ERR(host
->biu_clk
)) {
2117 dev_dbg(host
->dev
, "biu clock not available\n");
2119 ret
= clk_prepare_enable(host
->biu_clk
);
2121 dev_err(host
->dev
, "failed to enable biu clock\n");
2126 host
->ciu_clk
= devm_clk_get(host
->dev
, "ciu");
2127 if (IS_ERR(host
->ciu_clk
)) {
2128 dev_dbg(host
->dev
, "ciu clock not available\n");
2130 ret
= clk_prepare_enable(host
->ciu_clk
);
2132 dev_err(host
->dev
, "failed to enable ciu clock\n");
2137 if (IS_ERR(host
->ciu_clk
))
2138 host
->bus_hz
= host
->pdata
->bus_hz
;
2140 host
->bus_hz
= clk_get_rate(host
->ciu_clk
);
2142 if (drv_data
&& drv_data
->setup_clock
) {
2143 ret
= drv_data
->setup_clock(host
);
2146 "implementation specific clock setup failed\n");
2151 if (!host
->bus_hz
) {
2153 "Platform data must supply bus speed\n");
2158 host
->quirks
= host
->pdata
->quirks
;
2160 spin_lock_init(&host
->lock
);
2161 INIT_LIST_HEAD(&host
->queue
);
2164 * Get the host data width - this assumes that HCON has been set with
2165 * the correct values.
2167 i
= (mci_readl(host
, HCON
) >> 7) & 0x7;
2169 host
->push_data
= dw_mci_push_data16
;
2170 host
->pull_data
= dw_mci_pull_data16
;
2172 host
->data_shift
= 1;
2173 } else if (i
== 2) {
2174 host
->push_data
= dw_mci_push_data64
;
2175 host
->pull_data
= dw_mci_pull_data64
;
2177 host
->data_shift
= 3;
2179 /* Check for a reserved value, and warn if it is */
2181 "HCON reports a reserved host data width!\n"
2182 "Defaulting to 32-bit access.\n");
2183 host
->push_data
= dw_mci_push_data32
;
2184 host
->pull_data
= dw_mci_pull_data32
;
2186 host
->data_shift
= 2;
2189 /* Reset all blocks */
2190 if (!mci_wait_reset(host
->dev
, host
))
2193 host
->dma_ops
= host
->pdata
->dma_ops
;
2194 dw_mci_init_dma(host
);
2196 /* Clear the interrupts for the host controller */
2197 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
2198 mci_writel(host
, INTMASK
, 0); /* disable all mmc interrupt first */
2200 /* Put in max timeout */
2201 mci_writel(host
, TMOUT
, 0xFFFFFFFF);
2204 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
2205 * Tx Mark = fifo_size / 2 DMA Size = 8
2207 if (!host
->pdata
->fifo_depth
) {
2209 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2210 * have been overwritten by the bootloader, just like we're
2211 * about to do, so if you know the value for your hardware, you
2212 * should put it in the platform data.
2214 fifo_size
= mci_readl(host
, FIFOTH
);
2215 fifo_size
= 1 + ((fifo_size
>> 16) & 0xfff);
2217 fifo_size
= host
->pdata
->fifo_depth
;
2219 host
->fifo_depth
= fifo_size
;
2220 host
->fifoth_val
= ((0x2 << 28) | ((fifo_size
/2 - 1) << 16) |
2221 ((fifo_size
/2) << 0));
2222 mci_writel(host
, FIFOTH
, host
->fifoth_val
);
2224 /* disable clock to CIU */
2225 mci_writel(host
, CLKENA
, 0);
2226 mci_writel(host
, CLKSRC
, 0);
2228 tasklet_init(&host
->tasklet
, dw_mci_tasklet_func
, (unsigned long)host
);
2229 host
->card_workqueue
= alloc_workqueue("dw-mci-card",
2230 WQ_MEM_RECLAIM
| WQ_NON_REENTRANT
, 1);
2231 if (!host
->card_workqueue
)
2233 INIT_WORK(&host
->card_work
, dw_mci_work_routine_card
);
2234 ret
= devm_request_irq(host
->dev
, host
->irq
, dw_mci_interrupt
,
2235 host
->irq_flags
, "dw-mci", host
);
2239 if (host
->pdata
->num_slots
)
2240 host
->num_slots
= host
->pdata
->num_slots
;
2242 host
->num_slots
= ((mci_readl(host
, HCON
) >> 1) & 0x1F) + 1;
2245 * Enable interrupts for command done, data over, data empty, card det,
2246 * receive ready and error such as transmit, receive timeout, crc error
2248 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
2249 mci_writel(host
, INTMASK
, SDMMC_INT_CMD_DONE
| SDMMC_INT_DATA_OVER
|
2250 SDMMC_INT_TXDR
| SDMMC_INT_RXDR
|
2251 DW_MCI_ERROR_FLAGS
| SDMMC_INT_CD
);
2252 mci_writel(host
, CTRL
, SDMMC_CTRL_INT_ENABLE
); /* Enable mci interrupt */
2254 dev_info(host
->dev
, "DW MMC controller at irq %d, "
2255 "%d bit host data width, "
2257 host
->irq
, width
, fifo_size
);
2259 /* We need at least one slot to succeed */
2260 for (i
= 0; i
< host
->num_slots
; i
++) {
2261 ret
= dw_mci_init_slot(host
, i
);
2263 dev_dbg(host
->dev
, "slot %d init failed\n", i
);
2269 dev_info(host
->dev
, "%d slots initialized\n", init_slots
);
2271 dev_dbg(host
->dev
, "attempted to initialize %d slots, "
2272 "but failed on all\n", host
->num_slots
);
2277 * In 2.40a spec, Data offset is changed.
2278 * Need to check the version-id and set data-offset for DATA register.
2280 host
->verid
= SDMMC_GET_VERID(mci_readl(host
, VERID
));
2281 dev_info(host
->dev
, "Version ID is %04x\n", host
->verid
);
2283 if (host
->verid
< DW_MMC_240A
)
2284 host
->data_offset
= DATA_OFFSET
;
2286 host
->data_offset
= DATA_240A_OFFSET
;
2288 if (host
->quirks
& DW_MCI_QUIRK_IDMAC_DTO
)
2289 dev_info(host
->dev
, "Internal DMAC interrupt fix enabled.\n");
2294 destroy_workqueue(host
->card_workqueue
);
2297 if (host
->use_dma
&& host
->dma_ops
->exit
)
2298 host
->dma_ops
->exit(host
);
2301 regulator_disable(host
->vmmc
);
2304 if (!IS_ERR(host
->ciu_clk
))
2305 clk_disable_unprepare(host
->ciu_clk
);
2308 if (!IS_ERR(host
->biu_clk
))
2309 clk_disable_unprepare(host
->biu_clk
);
2313 EXPORT_SYMBOL(dw_mci_probe
);
2315 void dw_mci_remove(struct dw_mci
*host
)
2319 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
2320 mci_writel(host
, INTMASK
, 0); /* disable all mmc interrupt first */
2322 for (i
= 0; i
< host
->num_slots
; i
++) {
2323 dev_dbg(host
->dev
, "remove slot %d\n", i
);
2325 dw_mci_cleanup_slot(host
->slot
[i
], i
);
2328 /* disable clock to CIU */
2329 mci_writel(host
, CLKENA
, 0);
2330 mci_writel(host
, CLKSRC
, 0);
2332 destroy_workqueue(host
->card_workqueue
);
2334 if (host
->use_dma
&& host
->dma_ops
->exit
)
2335 host
->dma_ops
->exit(host
);
2338 regulator_disable(host
->vmmc
);
2340 if (!IS_ERR(host
->ciu_clk
))
2341 clk_disable_unprepare(host
->ciu_clk
);
2343 if (!IS_ERR(host
->biu_clk
))
2344 clk_disable_unprepare(host
->biu_clk
);
2346 EXPORT_SYMBOL(dw_mci_remove
);
2350 #ifdef CONFIG_PM_SLEEP
2352 * TODO: we should probably disable the clock to the card in the suspend path.
2354 int dw_mci_suspend(struct dw_mci
*host
)
2358 for (i
= 0; i
< host
->num_slots
; i
++) {
2359 struct dw_mci_slot
*slot
= host
->slot
[i
];
2362 ret
= mmc_suspend_host(slot
->mmc
);
2365 slot
= host
->slot
[i
];
2367 mmc_resume_host(host
->slot
[i
]->mmc
);
2374 regulator_disable(host
->vmmc
);
2378 EXPORT_SYMBOL(dw_mci_suspend
);
2380 int dw_mci_resume(struct dw_mci
*host
)
2385 regulator_enable(host
->vmmc
);
2387 if (!mci_wait_reset(host
->dev
, host
)) {
2392 if (host
->use_dma
&& host
->dma_ops
->init
)
2393 host
->dma_ops
->init(host
);
2395 /* Restore the old value at FIFOTH register */
2396 mci_writel(host
, FIFOTH
, host
->fifoth_val
);
2398 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
2399 mci_writel(host
, INTMASK
, SDMMC_INT_CMD_DONE
| SDMMC_INT_DATA_OVER
|
2400 SDMMC_INT_TXDR
| SDMMC_INT_RXDR
|
2401 DW_MCI_ERROR_FLAGS
| SDMMC_INT_CD
);
2402 mci_writel(host
, CTRL
, SDMMC_CTRL_INT_ENABLE
);
2404 for (i
= 0; i
< host
->num_slots
; i
++) {
2405 struct dw_mci_slot
*slot
= host
->slot
[i
];
2408 if (slot
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
) {
2409 dw_mci_set_ios(slot
->mmc
, &slot
->mmc
->ios
);
2410 dw_mci_setup_bus(slot
, true);
2413 ret
= mmc_resume_host(host
->slot
[i
]->mmc
);
2419 EXPORT_SYMBOL(dw_mci_resume
);
2420 #endif /* CONFIG_PM_SLEEP */
2422 static int __init
dw_mci_init(void)
2424 printk(KERN_INFO
"Synopsys Designware Multimedia Card Interface Driver");
2428 static void __exit
dw_mci_exit(void)
2432 module_init(dw_mci_init
);
2433 module_exit(dw_mci_exit
);
2435 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2436 MODULE_AUTHOR("NXP Semiconductor VietNam");
2437 MODULE_AUTHOR("Imagination Technologies Ltd");
2438 MODULE_LICENSE("GPL v2");