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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux...
[deliverable/linux.git] / drivers / mmc / host / mvsdio.c
1 /*
2 * Marvell MMC/SD/SDIO driver
3 *
4 * Authors: Maen Suleiman, Nicolas Pitre
5 * Copyright (C) 2008-2009 Marvell Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/platform_device.h>
16 #include <linux/mbus.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
21 #include <linux/irq.h>
22 #include <linux/clk.h>
23 #include <linux/gpio.h>
24 #include <linux/of_gpio.h>
25 #include <linux/of_irq.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/pinctrl/consumer.h>
29
30 #include <asm/sizes.h>
31 #include <asm/unaligned.h>
32 #include <linux/platform_data/mmc-mvsdio.h>
33
34 #include "mvsdio.h"
35
36 #define DRIVER_NAME "mvsdio"
37
38 static int maxfreq;
39 static int nodma;
40
41 struct mvsd_host {
42 void __iomem *base;
43 struct mmc_request *mrq;
44 spinlock_t lock;
45 unsigned int xfer_mode;
46 unsigned int intr_en;
47 unsigned int ctrl;
48 unsigned int pio_size;
49 void *pio_ptr;
50 unsigned int sg_frags;
51 unsigned int ns_per_clk;
52 unsigned int clock;
53 unsigned int base_clock;
54 struct timer_list timer;
55 struct mmc_host *mmc;
56 struct device *dev;
57 struct clk *clk;
58 };
59
60 #define mvsd_write(offs, val) writel(val, iobase + (offs))
61 #define mvsd_read(offs) readl(iobase + (offs))
62
63 static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
64 {
65 void __iomem *iobase = host->base;
66 unsigned int tmout;
67 int tmout_index;
68
69 /*
70 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
71 * register is sometimes not set before a while when some
72 * "unusual" data block sizes are used (such as with the SWITCH
73 * command), even despite the fact that the XFER_DONE interrupt
74 * was raised. And if another data transfer starts before
75 * this bit comes to good sense (which eventually happens by
76 * itself) then the new transfer simply fails with a timeout.
77 */
78 if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) {
79 unsigned long t = jiffies + HZ;
80 unsigned int hw_state, count = 0;
81 do {
82 hw_state = mvsd_read(MVSD_HW_STATE);
83 if (time_after(jiffies, t)) {
84 dev_warn(host->dev, "FIFO_EMPTY bit missing\n");
85 break;
86 }
87 count++;
88 } while (!(hw_state & (1 << 13)));
89 dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit "
90 "(hw=0x%04x, count=%d, jiffies=%ld)\n",
91 hw_state, count, jiffies - (t - HZ));
92 }
93
94 /* If timeout=0 then maximum timeout index is used. */
95 tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
96 tmout += data->timeout_clks;
97 tmout_index = fls(tmout - 1) - 12;
98 if (tmout_index < 0)
99 tmout_index = 0;
100 if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
101 tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
102
103 dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
104 (data->flags & MMC_DATA_READ) ? "read" : "write",
105 (u32)sg_virt(data->sg), data->blocks, data->blksz,
106 tmout, tmout_index);
107
108 host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
109 host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
110 mvsd_write(MVSD_HOST_CTRL, host->ctrl);
111 mvsd_write(MVSD_BLK_COUNT, data->blocks);
112 mvsd_write(MVSD_BLK_SIZE, data->blksz);
113
114 if (nodma || (data->blksz | data->sg->offset) & 3 ||
115 ((!(data->flags & MMC_DATA_READ) && data->sg->offset & 0x3f))) {
116 /*
117 * We cannot do DMA on a buffer which offset or size
118 * is not aligned on a 4-byte boundary.
119 *
120 * It also appears the host to card DMA can corrupt
121 * data when the buffer is not aligned on a 64 byte
122 * boundary.
123 */
124 host->pio_size = data->blocks * data->blksz;
125 host->pio_ptr = sg_virt(data->sg);
126 if (!nodma)
127 dev_dbg(host->dev, "fallback to PIO for data at 0x%p size %d\n",
128 host->pio_ptr, host->pio_size);
129 return 1;
130 } else {
131 dma_addr_t phys_addr;
132 int dma_dir = (data->flags & MMC_DATA_READ) ?
133 DMA_FROM_DEVICE : DMA_TO_DEVICE;
134 host->sg_frags = dma_map_sg(mmc_dev(host->mmc), data->sg,
135 data->sg_len, dma_dir);
136 phys_addr = sg_dma_address(data->sg);
137 mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
138 mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16);
139 return 0;
140 }
141 }
142
143 static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
144 {
145 struct mvsd_host *host = mmc_priv(mmc);
146 void __iomem *iobase = host->base;
147 struct mmc_command *cmd = mrq->cmd;
148 u32 cmdreg = 0, xfer = 0, intr = 0;
149 unsigned long flags;
150
151 BUG_ON(host->mrq != NULL);
152 host->mrq = mrq;
153
154 dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
155 cmd->opcode, mvsd_read(MVSD_HW_STATE));
156
157 cmdreg = MVSD_CMD_INDEX(cmd->opcode);
158
159 if (cmd->flags & MMC_RSP_BUSY)
160 cmdreg |= MVSD_CMD_RSP_48BUSY;
161 else if (cmd->flags & MMC_RSP_136)
162 cmdreg |= MVSD_CMD_RSP_136;
163 else if (cmd->flags & MMC_RSP_PRESENT)
164 cmdreg |= MVSD_CMD_RSP_48;
165 else
166 cmdreg |= MVSD_CMD_RSP_NONE;
167
168 if (cmd->flags & MMC_RSP_CRC)
169 cmdreg |= MVSD_CMD_CHECK_CMDCRC;
170
171 if (cmd->flags & MMC_RSP_OPCODE)
172 cmdreg |= MVSD_CMD_INDX_CHECK;
173
174 if (cmd->flags & MMC_RSP_PRESENT) {
175 cmdreg |= MVSD_UNEXPECTED_RESP;
176 intr |= MVSD_NOR_UNEXP_RSP;
177 }
178
179 if (mrq->data) {
180 struct mmc_data *data = mrq->data;
181 int pio;
182
183 cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
184 xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
185 if (data->flags & MMC_DATA_READ)
186 xfer |= MVSD_XFER_MODE_TO_HOST;
187
188 pio = mvsd_setup_data(host, data);
189 if (pio) {
190 xfer |= MVSD_XFER_MODE_PIO;
191 /* PIO section of mvsd_irq has comments on those bits */
192 if (data->flags & MMC_DATA_WRITE)
193 intr |= MVSD_NOR_TX_AVAIL;
194 else if (host->pio_size > 32)
195 intr |= MVSD_NOR_RX_FIFO_8W;
196 else
197 intr |= MVSD_NOR_RX_READY;
198 }
199
200 if (data->stop) {
201 struct mmc_command *stop = data->stop;
202 u32 cmd12reg = 0;
203
204 mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
205 mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16);
206
207 if (stop->flags & MMC_RSP_BUSY)
208 cmd12reg |= MVSD_AUTOCMD12_BUSY;
209 if (stop->flags & MMC_RSP_OPCODE)
210 cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
211 cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
212 mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
213
214 xfer |= MVSD_XFER_MODE_AUTO_CMD12;
215 intr |= MVSD_NOR_AUTOCMD12_DONE;
216 } else {
217 intr |= MVSD_NOR_XFER_DONE;
218 }
219 } else {
220 intr |= MVSD_NOR_CMD_DONE;
221 }
222
223 mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
224 mvsd_write(MVSD_ARG_HI, cmd->arg >> 16);
225
226 spin_lock_irqsave(&host->lock, flags);
227
228 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
229 host->xfer_mode |= xfer;
230 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
231
232 mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
233 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
234 mvsd_write(MVSD_CMD, cmdreg);
235
236 host->intr_en &= MVSD_NOR_CARD_INT;
237 host->intr_en |= intr | MVSD_NOR_ERROR;
238 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
239 mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
240
241 mod_timer(&host->timer, jiffies + 5 * HZ);
242
243 spin_unlock_irqrestore(&host->lock, flags);
244 }
245
246 static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
247 u32 err_status)
248 {
249 void __iomem *iobase = host->base;
250
251 if (cmd->flags & MMC_RSP_136) {
252 unsigned int response[8], i;
253 for (i = 0; i < 8; i++)
254 response[i] = mvsd_read(MVSD_RSP(i));
255 cmd->resp[0] = ((response[0] & 0x03ff) << 22) |
256 ((response[1] & 0xffff) << 6) |
257 ((response[2] & 0xfc00) >> 10);
258 cmd->resp[1] = ((response[2] & 0x03ff) << 22) |
259 ((response[3] & 0xffff) << 6) |
260 ((response[4] & 0xfc00) >> 10);
261 cmd->resp[2] = ((response[4] & 0x03ff) << 22) |
262 ((response[5] & 0xffff) << 6) |
263 ((response[6] & 0xfc00) >> 10);
264 cmd->resp[3] = ((response[6] & 0x03ff) << 22) |
265 ((response[7] & 0x3fff) << 8);
266 } else if (cmd->flags & MMC_RSP_PRESENT) {
267 unsigned int response[3], i;
268 for (i = 0; i < 3; i++)
269 response[i] = mvsd_read(MVSD_RSP(i));
270 cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
271 ((response[1] & 0xffff) << (14 - 8)) |
272 ((response[0] & 0x03ff) << (30 - 8));
273 cmd->resp[1] = ((response[0] & 0xfc00) >> 10);
274 cmd->resp[2] = 0;
275 cmd->resp[3] = 0;
276 }
277
278 if (err_status & MVSD_ERR_CMD_TIMEOUT) {
279 cmd->error = -ETIMEDOUT;
280 } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
281 MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
282 cmd->error = -EILSEQ;
283 }
284 err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
285 MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
286 MVSD_ERR_CMD_STARTBIT);
287
288 return err_status;
289 }
290
291 static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
292 u32 err_status)
293 {
294 void __iomem *iobase = host->base;
295
296 if (host->pio_ptr) {
297 host->pio_ptr = NULL;
298 host->pio_size = 0;
299 } else {
300 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
301 (data->flags & MMC_DATA_READ) ?
302 DMA_FROM_DEVICE : DMA_TO_DEVICE);
303 }
304
305 if (err_status & MVSD_ERR_DATA_TIMEOUT)
306 data->error = -ETIMEDOUT;
307 else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
308 data->error = -EILSEQ;
309 else if (err_status & MVSD_ERR_XFER_SIZE)
310 data->error = -EBADE;
311 err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
312 MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
313
314 dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
315 mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
316 data->bytes_xfered =
317 (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
318 /* We can't be sure about the last block when errors are detected */
319 if (data->bytes_xfered && data->error)
320 data->bytes_xfered -= data->blksz;
321
322 /* Handle Auto cmd 12 response */
323 if (data->stop) {
324 unsigned int response[3], i;
325 for (i = 0; i < 3; i++)
326 response[i] = mvsd_read(MVSD_AUTO_RSP(i));
327 data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
328 ((response[1] & 0xffff) << (14 - 8)) |
329 ((response[0] & 0x03ff) << (30 - 8));
330 data->stop->resp[1] = ((response[0] & 0xfc00) >> 10);
331 data->stop->resp[2] = 0;
332 data->stop->resp[3] = 0;
333
334 if (err_status & MVSD_ERR_AUTOCMD12) {
335 u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
336 dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
337 if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
338 data->stop->error = -ENOEXEC;
339 else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
340 data->stop->error = -ETIMEDOUT;
341 else if (err_cmd12)
342 data->stop->error = -EILSEQ;
343 err_status &= ~MVSD_ERR_AUTOCMD12;
344 }
345 }
346
347 return err_status;
348 }
349
350 static irqreturn_t mvsd_irq(int irq, void *dev)
351 {
352 struct mvsd_host *host = dev;
353 void __iomem *iobase = host->base;
354 u32 intr_status, intr_done_mask;
355 int irq_handled = 0;
356
357 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
358 dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
359 intr_status, mvsd_read(MVSD_NOR_INTR_EN),
360 mvsd_read(MVSD_HW_STATE));
361
362 /*
363 * It looks like, SDIO IP can issue one late, spurious irq
364 * although all irqs should be disabled. To work around this,
365 * bail out early, if we didn't expect any irqs to occur.
366 */
367 if (!mvsd_read(MVSD_NOR_INTR_EN) && !mvsd_read(MVSD_ERR_INTR_EN)) {
368 dev_dbg(host->dev, "spurious irq detected intr 0x%04x intr_en 0x%04x erri 0x%04x erri_en 0x%04x\n",
369 mvsd_read(MVSD_NOR_INTR_STATUS),
370 mvsd_read(MVSD_NOR_INTR_EN),
371 mvsd_read(MVSD_ERR_INTR_STATUS),
372 mvsd_read(MVSD_ERR_INTR_EN));
373 return IRQ_HANDLED;
374 }
375
376 spin_lock(&host->lock);
377
378 /* PIO handling, if needed. Messy business... */
379 if (host->pio_size &&
380 (intr_status & host->intr_en &
381 (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
382 u16 *p = host->pio_ptr;
383 int s = host->pio_size;
384 while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
385 readsw(iobase + MVSD_FIFO, p, 16);
386 p += 16;
387 s -= 32;
388 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
389 }
390 /*
391 * Normally we'd use < 32 here, but the RX_FIFO_8W bit
392 * doesn't appear to assert when there is exactly 32 bytes
393 * (8 words) left to fetch in a transfer.
394 */
395 if (s <= 32) {
396 while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
397 put_unaligned(mvsd_read(MVSD_FIFO), p++);
398 put_unaligned(mvsd_read(MVSD_FIFO), p++);
399 s -= 4;
400 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
401 }
402 if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
403 u16 val[2] = {0, 0};
404 val[0] = mvsd_read(MVSD_FIFO);
405 val[1] = mvsd_read(MVSD_FIFO);
406 memcpy(p, ((void *)&val) + 4 - s, s);
407 s = 0;
408 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
409 }
410 if (s == 0) {
411 host->intr_en &=
412 ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
413 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
414 } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
415 host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
416 host->intr_en |= MVSD_NOR_RX_READY;
417 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
418 }
419 }
420 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
421 s, intr_status, mvsd_read(MVSD_HW_STATE));
422 host->pio_ptr = p;
423 host->pio_size = s;
424 irq_handled = 1;
425 } else if (host->pio_size &&
426 (intr_status & host->intr_en &
427 (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
428 u16 *p = host->pio_ptr;
429 int s = host->pio_size;
430 /*
431 * The TX_FIFO_8W bit is unreliable. When set, bursting
432 * 16 halfwords all at once in the FIFO drops data. Actually
433 * TX_AVAIL does go off after only one word is pushed even if
434 * TX_FIFO_8W remains set.
435 */
436 while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
437 mvsd_write(MVSD_FIFO, get_unaligned(p++));
438 mvsd_write(MVSD_FIFO, get_unaligned(p++));
439 s -= 4;
440 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
441 }
442 if (s < 4) {
443 if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
444 u16 val[2] = {0, 0};
445 memcpy(((void *)&val) + 4 - s, p, s);
446 mvsd_write(MVSD_FIFO, val[0]);
447 mvsd_write(MVSD_FIFO, val[1]);
448 s = 0;
449 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
450 }
451 if (s == 0) {
452 host->intr_en &=
453 ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
454 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
455 }
456 }
457 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
458 s, intr_status, mvsd_read(MVSD_HW_STATE));
459 host->pio_ptr = p;
460 host->pio_size = s;
461 irq_handled = 1;
462 }
463
464 mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
465
466 intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
467 MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
468 if (intr_status & host->intr_en & ~intr_done_mask) {
469 struct mmc_request *mrq = host->mrq;
470 struct mmc_command *cmd = mrq->cmd;
471 u32 err_status = 0;
472
473 del_timer(&host->timer);
474 host->mrq = NULL;
475
476 host->intr_en &= MVSD_NOR_CARD_INT;
477 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
478 mvsd_write(MVSD_ERR_INTR_EN, 0);
479
480 spin_unlock(&host->lock);
481
482 if (intr_status & MVSD_NOR_UNEXP_RSP) {
483 cmd->error = -EPROTO;
484 } else if (intr_status & MVSD_NOR_ERROR) {
485 err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
486 dev_dbg(host->dev, "err 0x%04x\n", err_status);
487 }
488
489 err_status = mvsd_finish_cmd(host, cmd, err_status);
490 if (mrq->data)
491 err_status = mvsd_finish_data(host, mrq->data, err_status);
492 if (err_status) {
493 dev_err(host->dev, "unhandled error status %#04x\n",
494 err_status);
495 cmd->error = -ENOMSG;
496 }
497
498 mmc_request_done(host->mmc, mrq);
499 irq_handled = 1;
500 } else
501 spin_unlock(&host->lock);
502
503 if (intr_status & MVSD_NOR_CARD_INT) {
504 mmc_signal_sdio_irq(host->mmc);
505 irq_handled = 1;
506 }
507
508 if (irq_handled)
509 return IRQ_HANDLED;
510
511 dev_err(host->dev, "unhandled interrupt status=0x%04x en=0x%04x pio=%d\n",
512 intr_status, host->intr_en, host->pio_size);
513 return IRQ_NONE;
514 }
515
516 static void mvsd_timeout_timer(unsigned long data)
517 {
518 struct mvsd_host *host = (struct mvsd_host *)data;
519 void __iomem *iobase = host->base;
520 struct mmc_request *mrq;
521 unsigned long flags;
522
523 spin_lock_irqsave(&host->lock, flags);
524 mrq = host->mrq;
525 if (mrq) {
526 dev_err(host->dev, "Timeout waiting for hardware interrupt.\n");
527 dev_err(host->dev, "hw_state=0x%04x, intr_status=0x%04x intr_en=0x%04x\n",
528 mvsd_read(MVSD_HW_STATE),
529 mvsd_read(MVSD_NOR_INTR_STATUS),
530 mvsd_read(MVSD_NOR_INTR_EN));
531
532 host->mrq = NULL;
533
534 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
535
536 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
537 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
538
539 host->intr_en &= MVSD_NOR_CARD_INT;
540 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
541 mvsd_write(MVSD_ERR_INTR_EN, 0);
542 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
543
544 mrq->cmd->error = -ETIMEDOUT;
545 mvsd_finish_cmd(host, mrq->cmd, 0);
546 if (mrq->data) {
547 mrq->data->error = -ETIMEDOUT;
548 mvsd_finish_data(host, mrq->data, 0);
549 }
550 }
551 spin_unlock_irqrestore(&host->lock, flags);
552
553 if (mrq)
554 mmc_request_done(host->mmc, mrq);
555 }
556
557 static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
558 {
559 struct mvsd_host *host = mmc_priv(mmc);
560 void __iomem *iobase = host->base;
561 unsigned long flags;
562
563 spin_lock_irqsave(&host->lock, flags);
564 if (enable) {
565 host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
566 host->intr_en |= MVSD_NOR_CARD_INT;
567 } else {
568 host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
569 host->intr_en &= ~MVSD_NOR_CARD_INT;
570 }
571 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
572 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
573 spin_unlock_irqrestore(&host->lock, flags);
574 }
575
576 static void mvsd_power_up(struct mvsd_host *host)
577 {
578 void __iomem *iobase = host->base;
579 dev_dbg(host->dev, "power up\n");
580 mvsd_write(MVSD_NOR_INTR_EN, 0);
581 mvsd_write(MVSD_ERR_INTR_EN, 0);
582 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
583 mvsd_write(MVSD_XFER_MODE, 0);
584 mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
585 mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
586 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
587 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
588 }
589
590 static void mvsd_power_down(struct mvsd_host *host)
591 {
592 void __iomem *iobase = host->base;
593 dev_dbg(host->dev, "power down\n");
594 mvsd_write(MVSD_NOR_INTR_EN, 0);
595 mvsd_write(MVSD_ERR_INTR_EN, 0);
596 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
597 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
598 mvsd_write(MVSD_NOR_STATUS_EN, 0);
599 mvsd_write(MVSD_ERR_STATUS_EN, 0);
600 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
601 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
602 }
603
604 static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
605 {
606 struct mvsd_host *host = mmc_priv(mmc);
607 void __iomem *iobase = host->base;
608 u32 ctrl_reg = 0;
609
610 if (ios->power_mode == MMC_POWER_UP)
611 mvsd_power_up(host);
612
613 if (ios->clock == 0) {
614 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
615 mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
616 host->clock = 0;
617 dev_dbg(host->dev, "clock off\n");
618 } else if (ios->clock != host->clock) {
619 u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
620 if (m > MVSD_BASE_DIV_MAX)
621 m = MVSD_BASE_DIV_MAX;
622 mvsd_write(MVSD_CLK_DIV, m);
623 host->clock = ios->clock;
624 host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
625 dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
626 ios->clock, host->base_clock / (m+1), m);
627 }
628
629 /* default transfer mode */
630 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
631 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
632
633 /* default to maximum timeout */
634 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
635 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
636
637 if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
638 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
639
640 if (ios->bus_width == MMC_BUS_WIDTH_4)
641 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
642
643 /*
644 * The HI_SPEED_EN bit is causing trouble with many (but not all)
645 * high speed SD, SDHC and SDIO cards. Not enabling that bit
646 * makes all cards work. So let's just ignore that bit for now
647 * and revisit this issue if problems for not enabling this bit
648 * are ever reported.
649 */
650 #if 0
651 if (ios->timing == MMC_TIMING_MMC_HS ||
652 ios->timing == MMC_TIMING_SD_HS)
653 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
654 #endif
655
656 host->ctrl = ctrl_reg;
657 mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
658 dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
659 (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
660 "push-pull" : "open-drain",
661 (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
662 "4bit-width" : "1bit-width",
663 (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
664 "high-speed" : "");
665
666 if (ios->power_mode == MMC_POWER_OFF)
667 mvsd_power_down(host);
668 }
669
670 static const struct mmc_host_ops mvsd_ops = {
671 .request = mvsd_request,
672 .get_ro = mmc_gpio_get_ro,
673 .set_ios = mvsd_set_ios,
674 .enable_sdio_irq = mvsd_enable_sdio_irq,
675 };
676
677 static void
678 mv_conf_mbus_windows(struct mvsd_host *host,
679 const struct mbus_dram_target_info *dram)
680 {
681 void __iomem *iobase = host->base;
682 int i;
683
684 for (i = 0; i < 4; i++) {
685 writel(0, iobase + MVSD_WINDOW_CTRL(i));
686 writel(0, iobase + MVSD_WINDOW_BASE(i));
687 }
688
689 for (i = 0; i < dram->num_cs; i++) {
690 const struct mbus_dram_window *cs = dram->cs + i;
691 writel(((cs->size - 1) & 0xffff0000) |
692 (cs->mbus_attr << 8) |
693 (dram->mbus_dram_target_id << 4) | 1,
694 iobase + MVSD_WINDOW_CTRL(i));
695 writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
696 }
697 }
698
699 static int mvsd_probe(struct platform_device *pdev)
700 {
701 struct device_node *np = pdev->dev.of_node;
702 struct mmc_host *mmc = NULL;
703 struct mvsd_host *host = NULL;
704 const struct mbus_dram_target_info *dram;
705 struct resource *r;
706 int ret, irq;
707 struct pinctrl *pinctrl;
708
709 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
710 irq = platform_get_irq(pdev, 0);
711 if (!r || irq < 0)
712 return -ENXIO;
713
714 mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
715 if (!mmc) {
716 ret = -ENOMEM;
717 goto out;
718 }
719
720 host = mmc_priv(mmc);
721 host->mmc = mmc;
722 host->dev = &pdev->dev;
723
724 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
725 if (IS_ERR(pinctrl))
726 dev_warn(&pdev->dev, "no pins associated\n");
727
728 /*
729 * Some non-DT platforms do not pass a clock, and the clock
730 * frequency is passed through platform_data. On DT platforms,
731 * a clock must always be passed, even if there is no gatable
732 * clock associated to the SDIO interface (it can simply be a
733 * fixed rate clock).
734 */
735 host->clk = devm_clk_get(&pdev->dev, NULL);
736 if (!IS_ERR(host->clk))
737 clk_prepare_enable(host->clk);
738
739 mmc->ops = &mvsd_ops;
740
741 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
742
743 mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
744 mmc->f_max = MVSD_CLOCKRATE_MAX;
745
746 mmc->max_blk_size = 2048;
747 mmc->max_blk_count = 65535;
748
749 mmc->max_segs = 1;
750 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
751 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
752
753 if (np) {
754 if (IS_ERR(host->clk)) {
755 dev_err(&pdev->dev, "DT platforms must have a clock associated\n");
756 ret = -EINVAL;
757 goto out;
758 }
759
760 host->base_clock = clk_get_rate(host->clk) / 2;
761 ret = mmc_of_parse(mmc);
762 if (ret < 0)
763 goto out;
764 } else {
765 const struct mvsdio_platform_data *mvsd_data;
766
767 mvsd_data = pdev->dev.platform_data;
768 if (!mvsd_data) {
769 ret = -ENXIO;
770 goto out;
771 }
772 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
773 MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
774 host->base_clock = mvsd_data->clock / 2;
775 /* GPIO 0 regarded as invalid for backward compatibility */
776 if (mvsd_data->gpio_card_detect &&
777 gpio_is_valid(mvsd_data->gpio_card_detect)) {
778 ret = mmc_gpio_request_cd(mmc,
779 mvsd_data->gpio_card_detect,
780 0);
781 if (ret)
782 goto out;
783 } else {
784 mmc->caps |= MMC_CAP_NEEDS_POLL;
785 }
786
787 if (mvsd_data->gpio_write_protect &&
788 gpio_is_valid(mvsd_data->gpio_write_protect))
789 mmc_gpio_request_ro(mmc, mvsd_data->gpio_write_protect);
790 }
791
792 if (maxfreq)
793 mmc->f_max = maxfreq;
794
795 spin_lock_init(&host->lock);
796
797 host->base = devm_ioremap_resource(&pdev->dev, r);
798 if (IS_ERR(host->base)) {
799 ret = PTR_ERR(host->base);
800 goto out;
801 }
802
803 /* (Re-)program MBUS remapping windows if we are asked to. */
804 dram = mv_mbus_dram_info();
805 if (dram)
806 mv_conf_mbus_windows(host, dram);
807
808 mvsd_power_down(host);
809
810 ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host);
811 if (ret) {
812 dev_err(&pdev->dev, "cannot assign irq %d\n", irq);
813 goto out;
814 }
815
816 setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host);
817 platform_set_drvdata(pdev, mmc);
818 ret = mmc_add_host(mmc);
819 if (ret)
820 goto out;
821
822 if (!(mmc->caps & MMC_CAP_NEEDS_POLL))
823 dev_dbg(&pdev->dev, "using GPIO for card detection\n");
824 else
825 dev_dbg(&pdev->dev, "lacking card detect (fall back to polling)\n");
826
827 return 0;
828
829 out:
830 if (mmc) {
831 mmc_gpio_free_cd(mmc);
832 mmc_gpio_free_ro(mmc);
833 if (!IS_ERR(host->clk))
834 clk_disable_unprepare(host->clk);
835 mmc_free_host(mmc);
836 }
837
838 return ret;
839 }
840
841 static int mvsd_remove(struct platform_device *pdev)
842 {
843 struct mmc_host *mmc = platform_get_drvdata(pdev);
844
845 struct mvsd_host *host = mmc_priv(mmc);
846
847 mmc_gpio_free_cd(mmc);
848 mmc_gpio_free_ro(mmc);
849 mmc_remove_host(mmc);
850 del_timer_sync(&host->timer);
851 mvsd_power_down(host);
852
853 if (!IS_ERR(host->clk))
854 clk_disable_unprepare(host->clk);
855 mmc_free_host(mmc);
856
857 return 0;
858 }
859
860 static const struct of_device_id mvsdio_dt_ids[] = {
861 { .compatible = "marvell,orion-sdio" },
862 { /* sentinel */ }
863 };
864 MODULE_DEVICE_TABLE(of, mvsdio_dt_ids);
865
866 static struct platform_driver mvsd_driver = {
867 .probe = mvsd_probe,
868 .remove = mvsd_remove,
869 .driver = {
870 .name = DRIVER_NAME,
871 .of_match_table = mvsdio_dt_ids,
872 },
873 };
874
875 module_platform_driver(mvsd_driver);
876
877 /* maximum card clock frequency (default 50MHz) */
878 module_param(maxfreq, int, 0);
879
880 /* force PIO transfers all the time */
881 module_param(nodma, int, 0);
882
883 MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
884 MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
885 MODULE_LICENSE("GPL");
886 MODULE_ALIAS("platform:mvsdio");
Linux kernel - Deliverables
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